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Fix hardware accelerated video to video copy on Cirrus VGA (Brian Kress)
[qemu-kvm/fedora.git] / hw / cirrus_vga.c
blob866954dc09ca9fad6a5180eb75234a6a18821547
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "kvm.h"
35 #include "qemu-kvm.h"
36
37 /*
38 * TODO:
39 * - destination write mask support not complete (bits 5..7)
40 * - optimize linear mappings
41 * - optimize bitblt functions
42 */
43
44 //#define DEBUG_CIRRUS
45 //#define DEBUG_BITBLT
46
47 /***************************************
48 *
49 * definitions
50 *
51 ***************************************/
52
53 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
54
55 // ID
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64
65 // sequencer 0x07
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75
76 // sequencer 0x0f
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81
82 // sequencer 0x12
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86
87 // sequencer 0x17
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95
96 // control 0x0b
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99
100 // control 0x30
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112
113 // control 0x31
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
119
120 // control 0x32
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
140
141 // control 0x33
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145
146 // memory-mapped IO
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176
177 // PCI 0x02: device
178 #define PCI_DEVICE_CLGD5462 0x00d0
179 #define PCI_DEVICE_CLGD5465 0x00d6
180
181 // PCI 0x04: command(word), 0x06(word): status
182 #define PCI_COMMAND_IOACCESS 0x0001
183 #define PCI_COMMAND_MEMACCESS 0x0002
184 #define PCI_COMMAND_BUSMASTER 0x0004
185 #define PCI_COMMAND_SPECIALCYCLE 0x0008
186 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
187 #define PCI_COMMAND_PALETTESNOOPING 0x0020
188 #define PCI_COMMAND_PARITYDETECTION 0x0040
189 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
190 #define PCI_COMMAND_SERR 0x0100
191 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
192 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
193 #define PCI_CLASS_BASE_DISPLAY 0x03
194 // PCI 0x08, 0x00ff0000
195 #define PCI_CLASS_SUB_VGA 0x00
196 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
197 #define PCI_CLASS_HEADERTYPE_00h 0x00
198 // 0x10-0x3f (headertype 00h)
199 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
200 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
201 #define PCI_MAP_MEM 0x0
202 #define PCI_MAP_IO 0x1
203 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
204 #define PCI_MAP_IO_ADDR_MASK (~0x3)
205 #define PCI_MAP_MEMFLAGS_32BIT 0x0
206 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
207 #define PCI_MAP_MEMFLAGS_64BIT 0x4
208 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
209 // PCI 0x28: cardbus CIS pointer
210 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
211 // PCI 0x30: expansion ROM base address
212 #define PCI_ROMBIOS_ENABLED 0x1
213 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
214 // PCI 0x38: reserved
215 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
216
217 #define CIRRUS_PNPMMIO_SIZE 0x1000
218
219
220 /* I/O and memory hook */
221 #define CIRRUS_HOOK_NOT_HANDLED 0
222 #define CIRRUS_HOOK_HANDLED 1
223
224 #define ABS(a) ((signed)(a) > 0 ? a : -a)
225
226 #define BLTUNSAFE(s) \
227 ( \
228 ( /* check dst is within bounds */ \
229 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
230 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
231 (s)->vram_size \
232 ) || \
233 ( /* check src is within bounds */ \
234 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
235 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
236 (s)->vram_size \
237 ) \
238 )
239
240 struct CirrusVGAState;
241 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
242 uint8_t * dst, const uint8_t * src,
243 int dstpitch, int srcpitch,
244 int bltwidth, int bltheight);
245 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
246 uint8_t *dst, int dst_pitch, int width, int height);
247
248 typedef struct CirrusVGAState {
249 VGA_STATE_COMMON
250
251 int cirrus_linear_io_addr;
252 int cirrus_linear_bitblt_io_addr;
253 int cirrus_mmio_io_addr;
254 uint32_t cirrus_addr_mask;
255 uint32_t linear_mmio_mask;
256 uint8_t cirrus_shadow_gr0;
257 uint8_t cirrus_shadow_gr1;
258 uint8_t cirrus_hidden_dac_lockindex;
259 uint8_t cirrus_hidden_dac_data;
260 uint32_t cirrus_bank_base[2];
261 uint32_t cirrus_bank_limit[2];
262 uint8_t cirrus_hidden_palette[48];
263 uint32_t hw_cursor_x;
264 uint32_t hw_cursor_y;
265 int cirrus_blt_pixelwidth;
266 int cirrus_blt_width;
267 int cirrus_blt_height;
268 int cirrus_blt_dstpitch;
269 int cirrus_blt_srcpitch;
270 uint32_t cirrus_blt_fgcol;
271 uint32_t cirrus_blt_bgcol;
272 uint32_t cirrus_blt_dstaddr;
273 uint32_t cirrus_blt_srcaddr;
274 uint8_t cirrus_blt_mode;
275 uint8_t cirrus_blt_modeext;
276 cirrus_bitblt_rop_t cirrus_rop;
277 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
278 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
279 uint8_t *cirrus_srcptr;
280 uint8_t *cirrus_srcptr_end;
281 uint32_t cirrus_srccounter;
282 /* hwcursor display state */
283 int last_hw_cursor_size;
284 int last_hw_cursor_x;
285 int last_hw_cursor_y;
286 int last_hw_cursor_y_start;
287 int last_hw_cursor_y_end;
288 int real_vram_size; /* XXX: suppress that */
289 CPUWriteMemoryFunc **cirrus_linear_write;
290 int device_id;
291 int bustype;
292 } CirrusVGAState;
293
294 typedef struct PCICirrusVGAState {
295 PCIDevice dev;
296 CirrusVGAState cirrus_vga;
297 } PCICirrusVGAState;
298
299 static uint8_t rop_to_index[256];
300
301 /***************************************
302 *
303 * prototypes.
304 *
305 ***************************************/
306
307
308 static void cirrus_bitblt_reset(CirrusVGAState *s);
309 static void cirrus_update_memory_access(CirrusVGAState *s);
310
311 /***************************************
312 *
313 * raster operations
314 *
315 ***************************************/
316
317 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
318 uint8_t *dst,const uint8_t *src,
319 int dstpitch,int srcpitch,
320 int bltwidth,int bltheight)
321 {
322 }
323
324 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
325 uint8_t *dst,
326 int dstpitch, int bltwidth,int bltheight)
327 {
328 }
329
330 #define ROP_NAME 0
331 #define ROP_OP(d, s) d = 0
332 #include "cirrus_vga_rop.h"
333
334 #define ROP_NAME src_and_dst
335 #define ROP_OP(d, s) d = (s) & (d)
336 #include "cirrus_vga_rop.h"
337
338 #define ROP_NAME src_and_notdst
339 #define ROP_OP(d, s) d = (s) & (~(d))
340 #include "cirrus_vga_rop.h"
341
342 #define ROP_NAME notdst
343 #define ROP_OP(d, s) d = ~(d)
344 #include "cirrus_vga_rop.h"
345
346 #define ROP_NAME src
347 #define ROP_OP(d, s) d = s
348 #include "cirrus_vga_rop.h"
349
350 #define ROP_NAME 1
351 #define ROP_OP(d, s) d = ~0
352 #include "cirrus_vga_rop.h"
353
354 #define ROP_NAME notsrc_and_dst
355 #define ROP_OP(d, s) d = (~(s)) & (d)
356 #include "cirrus_vga_rop.h"
357
358 #define ROP_NAME src_xor_dst
359 #define ROP_OP(d, s) d = (s) ^ (d)
360 #include "cirrus_vga_rop.h"
361
362 #define ROP_NAME src_or_dst
363 #define ROP_OP(d, s) d = (s) | (d)
364 #include "cirrus_vga_rop.h"
365
366 #define ROP_NAME notsrc_or_notdst
367 #define ROP_OP(d, s) d = (~(s)) | (~(d))
368 #include "cirrus_vga_rop.h"
369
370 #define ROP_NAME src_notxor_dst
371 #define ROP_OP(d, s) d = ~((s) ^ (d))
372 #include "cirrus_vga_rop.h"
373
374 #define ROP_NAME src_or_notdst
375 #define ROP_OP(d, s) d = (s) | (~(d))
376 #include "cirrus_vga_rop.h"
377
378 #define ROP_NAME notsrc
379 #define ROP_OP(d, s) d = (~(s))
380 #include "cirrus_vga_rop.h"
381
382 #define ROP_NAME notsrc_or_dst
383 #define ROP_OP(d, s) d = (~(s)) | (d)
384 #include "cirrus_vga_rop.h"
385
386 #define ROP_NAME notsrc_and_notdst
387 #define ROP_OP(d, s) d = (~(s)) & (~(d))
388 #include "cirrus_vga_rop.h"
389
390 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
391 cirrus_bitblt_rop_fwd_0,
392 cirrus_bitblt_rop_fwd_src_and_dst,
393 cirrus_bitblt_rop_nop,
394 cirrus_bitblt_rop_fwd_src_and_notdst,
395 cirrus_bitblt_rop_fwd_notdst,
396 cirrus_bitblt_rop_fwd_src,
397 cirrus_bitblt_rop_fwd_1,
398 cirrus_bitblt_rop_fwd_notsrc_and_dst,
399 cirrus_bitblt_rop_fwd_src_xor_dst,
400 cirrus_bitblt_rop_fwd_src_or_dst,
401 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
402 cirrus_bitblt_rop_fwd_src_notxor_dst,
403 cirrus_bitblt_rop_fwd_src_or_notdst,
404 cirrus_bitblt_rop_fwd_notsrc,
405 cirrus_bitblt_rop_fwd_notsrc_or_dst,
406 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
407 };
408
409 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
410 cirrus_bitblt_rop_bkwd_0,
411 cirrus_bitblt_rop_bkwd_src_and_dst,
412 cirrus_bitblt_rop_nop,
413 cirrus_bitblt_rop_bkwd_src_and_notdst,
414 cirrus_bitblt_rop_bkwd_notdst,
415 cirrus_bitblt_rop_bkwd_src,
416 cirrus_bitblt_rop_bkwd_1,
417 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
418 cirrus_bitblt_rop_bkwd_src_xor_dst,
419 cirrus_bitblt_rop_bkwd_src_or_dst,
420 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
421 cirrus_bitblt_rop_bkwd_src_notxor_dst,
422 cirrus_bitblt_rop_bkwd_src_or_notdst,
423 cirrus_bitblt_rop_bkwd_notsrc,
424 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
425 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
426 };
427
428 #define TRANSP_ROP(name) {\
429 name ## _8,\
430 name ## _16,\
431 }
432 #define TRANSP_NOP(func) {\
433 func,\
434 func,\
435 }
436
437 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
440 TRANSP_NOP(cirrus_bitblt_rop_nop),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
454 };
455
456 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
459 TRANSP_NOP(cirrus_bitblt_rop_nop),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
473 };
474
475 #define ROP2(name) {\
476 name ## _8,\
477 name ## _16,\
478 name ## _24,\
479 name ## _32,\
480 }
481
482 #define ROP_NOP2(func) {\
483 func,\
484 func,\
485 func,\
486 func,\
487 }
488
489 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
490 ROP2(cirrus_patternfill_0),
491 ROP2(cirrus_patternfill_src_and_dst),
492 ROP_NOP2(cirrus_bitblt_rop_nop),
493 ROP2(cirrus_patternfill_src_and_notdst),
494 ROP2(cirrus_patternfill_notdst),
495 ROP2(cirrus_patternfill_src),
496 ROP2(cirrus_patternfill_1),
497 ROP2(cirrus_patternfill_notsrc_and_dst),
498 ROP2(cirrus_patternfill_src_xor_dst),
499 ROP2(cirrus_patternfill_src_or_dst),
500 ROP2(cirrus_patternfill_notsrc_or_notdst),
501 ROP2(cirrus_patternfill_src_notxor_dst),
502 ROP2(cirrus_patternfill_src_or_notdst),
503 ROP2(cirrus_patternfill_notsrc),
504 ROP2(cirrus_patternfill_notsrc_or_dst),
505 ROP2(cirrus_patternfill_notsrc_and_notdst),
506 };
507
508 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
509 ROP2(cirrus_colorexpand_transp_0),
510 ROP2(cirrus_colorexpand_transp_src_and_dst),
511 ROP_NOP2(cirrus_bitblt_rop_nop),
512 ROP2(cirrus_colorexpand_transp_src_and_notdst),
513 ROP2(cirrus_colorexpand_transp_notdst),
514 ROP2(cirrus_colorexpand_transp_src),
515 ROP2(cirrus_colorexpand_transp_1),
516 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
517 ROP2(cirrus_colorexpand_transp_src_xor_dst),
518 ROP2(cirrus_colorexpand_transp_src_or_dst),
519 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
520 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
521 ROP2(cirrus_colorexpand_transp_src_or_notdst),
522 ROP2(cirrus_colorexpand_transp_notsrc),
523 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
524 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
525 };
526
527 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
528 ROP2(cirrus_colorexpand_0),
529 ROP2(cirrus_colorexpand_src_and_dst),
530 ROP_NOP2(cirrus_bitblt_rop_nop),
531 ROP2(cirrus_colorexpand_src_and_notdst),
532 ROP2(cirrus_colorexpand_notdst),
533 ROP2(cirrus_colorexpand_src),
534 ROP2(cirrus_colorexpand_1),
535 ROP2(cirrus_colorexpand_notsrc_and_dst),
536 ROP2(cirrus_colorexpand_src_xor_dst),
537 ROP2(cirrus_colorexpand_src_or_dst),
538 ROP2(cirrus_colorexpand_notsrc_or_notdst),
539 ROP2(cirrus_colorexpand_src_notxor_dst),
540 ROP2(cirrus_colorexpand_src_or_notdst),
541 ROP2(cirrus_colorexpand_notsrc),
542 ROP2(cirrus_colorexpand_notsrc_or_dst),
543 ROP2(cirrus_colorexpand_notsrc_and_notdst),
544 };
545
546 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
547 ROP2(cirrus_colorexpand_pattern_transp_0),
548 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
549 ROP_NOP2(cirrus_bitblt_rop_nop),
550 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
551 ROP2(cirrus_colorexpand_pattern_transp_notdst),
552 ROP2(cirrus_colorexpand_pattern_transp_src),
553 ROP2(cirrus_colorexpand_pattern_transp_1),
554 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
555 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
556 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
557 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
558 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
559 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
560 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
561 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
563 };
564
565 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
566 ROP2(cirrus_colorexpand_pattern_0),
567 ROP2(cirrus_colorexpand_pattern_src_and_dst),
568 ROP_NOP2(cirrus_bitblt_rop_nop),
569 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
570 ROP2(cirrus_colorexpand_pattern_notdst),
571 ROP2(cirrus_colorexpand_pattern_src),
572 ROP2(cirrus_colorexpand_pattern_1),
573 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
574 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
575 ROP2(cirrus_colorexpand_pattern_src_or_dst),
576 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
577 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
578 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
579 ROP2(cirrus_colorexpand_pattern_notsrc),
580 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
581 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
582 };
583
584 static const cirrus_fill_t cirrus_fill[16][4] = {
585 ROP2(cirrus_fill_0),
586 ROP2(cirrus_fill_src_and_dst),
587 ROP_NOP2(cirrus_bitblt_fill_nop),
588 ROP2(cirrus_fill_src_and_notdst),
589 ROP2(cirrus_fill_notdst),
590 ROP2(cirrus_fill_src),
591 ROP2(cirrus_fill_1),
592 ROP2(cirrus_fill_notsrc_and_dst),
593 ROP2(cirrus_fill_src_xor_dst),
594 ROP2(cirrus_fill_src_or_dst),
595 ROP2(cirrus_fill_notsrc_or_notdst),
596 ROP2(cirrus_fill_src_notxor_dst),
597 ROP2(cirrus_fill_src_or_notdst),
598 ROP2(cirrus_fill_notsrc),
599 ROP2(cirrus_fill_notsrc_or_dst),
600 ROP2(cirrus_fill_notsrc_and_notdst),
601 };
602
603 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
604 {
605 unsigned int color;
606 switch (s->cirrus_blt_pixelwidth) {
607 case 1:
608 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
609 break;
610 case 2:
611 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
612 s->cirrus_blt_fgcol = le16_to_cpu(color);
613 break;
614 case 3:
615 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
616 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
617 break;
618 default:
619 case 4:
620 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
621 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
622 s->cirrus_blt_fgcol = le32_to_cpu(color);
623 break;
624 }
625 }
626
627 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
628 {
629 unsigned int color;
630 switch (s->cirrus_blt_pixelwidth) {
631 case 1:
632 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
633 break;
634 case 2:
635 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
636 s->cirrus_blt_bgcol = le16_to_cpu(color);
637 break;
638 case 3:
639 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
640 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
641 break;
642 default:
643 case 4:
644 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
645 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
646 s->cirrus_blt_bgcol = le32_to_cpu(color);
647 break;
648 }
649 }
650
651 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
652 int off_pitch, int bytesperline,
653 int lines)
654 {
655 int y;
656 int off_cur;
657 int off_cur_end;
658
659 for (y = 0; y < lines; y++) {
660 off_cur = off_begin;
661 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
662 off_cur &= TARGET_PAGE_MASK;
663 while (off_cur < off_cur_end) {
664 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
665 off_cur += TARGET_PAGE_SIZE;
666 }
667 off_begin += off_pitch;
668 }
669 }
670
671 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
672 const uint8_t * src)
673 {
674 uint8_t *dst;
675
676 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
677
678 if (BLTUNSAFE(s))
679 return 0;
680
681 (*s->cirrus_rop) (s, dst, src,
682 s->cirrus_blt_dstpitch, 0,
683 s->cirrus_blt_width, s->cirrus_blt_height);
684 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
685 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
686 s->cirrus_blt_height);
687 return 1;
688 }
689
690 /* fill */
691
692 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
693 {
694 cirrus_fill_t rop_func;
695
696 if (BLTUNSAFE(s))
697 return 0;
698 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
699 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
700 s->cirrus_blt_dstpitch,
701 s->cirrus_blt_width, s->cirrus_blt_height);
702 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
703 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
704 s->cirrus_blt_height);
705 cirrus_bitblt_reset(s);
706 return 1;
707 }
708
709 /***************************************
710 *
711 * bitblt (video-to-video)
712 *
713 ***************************************/
714
715 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
716 {
717 return cirrus_bitblt_common_patterncopy(s,
718 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
719 s->cirrus_addr_mask));
720 }
721
722 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
723 {
724 int sx, sy;
725 int dx, dy;
726 int width, height;
727 int depth;
728 int notify = 0;
729
730 depth = s->get_bpp((VGAState *)s) / 8;
731 s->get_resolution((VGAState *)s, &width, &height);
732
733 /* extra x, y */
734 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
735 sy = (src / ABS(s->cirrus_blt_srcpitch));
736 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
737 dy = (dst / ABS(s->cirrus_blt_dstpitch));
738
739 /* normalize width */
740 w /= depth;
741
742 /* if we're doing a backward copy, we have to adjust
743 our x/y to be the upper left corner (instead of the lower
744 right corner) */
745 if (s->cirrus_blt_dstpitch < 0) {
746 sx -= (s->cirrus_blt_width / depth) - 1;
747 dx -= (s->cirrus_blt_width / depth) - 1;
748 sy -= s->cirrus_blt_height - 1;
749 dy -= s->cirrus_blt_height - 1;
750 }
751
752 /* are we in the visible portion of memory? */
753 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
754 (sx + w) <= width && (sy + h) <= height &&
755 (dx + w) <= width && (dy + h) <= height) {
756 notify = 1;
757 }
758
759 /* make to sure only copy if it's a plain copy ROP */
760 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
761 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
762 notify = 0;
763
764 /* we have to flush all pending changes so that the copy
765 is generated at the appropriate moment in time */
766 if (notify)
767 vga_hw_update();
768
769 (*s->cirrus_rop) (s, s->vram_ptr +
770 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
771 s->vram_ptr +
772 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
773 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
774 s->cirrus_blt_width, s->cirrus_blt_height);
775
776 if (notify)
777 qemu_console_copy(s->ds,
778 sx, sy, dx, dy,
779 s->cirrus_blt_width / depth,
780 s->cirrus_blt_height);
781
782 /* we don't have to notify the display that this portion has
783 changed since qemu_console_copy implies this */
784
785 if (!notify)
786 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
787 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
788 s->cirrus_blt_height);
789 }
790
791 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
792 {
793 if (BLTUNSAFE(s))
794 return 0;
795
796 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
797 s->cirrus_blt_srcaddr - s->start_addr,
798 s->cirrus_blt_width, s->cirrus_blt_height);
799
800 return 1;
801 }
802
803 /***************************************
804 *
805 * bitblt (cpu-to-video)
806 *
807 ***************************************/
808
809 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
810 {
811 int copy_count;
812 uint8_t *end_ptr;
813
814 if (s->cirrus_srccounter > 0) {
815 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
816 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
817 the_end:
818 s->cirrus_srccounter = 0;
819 cirrus_bitblt_reset(s);
820 } else {
821 /* at least one scan line */
822 do {
823 (*s->cirrus_rop)(s, s->vram_ptr +
824 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
825 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
826 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
827 s->cirrus_blt_width, 1);
828 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
829 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
830 if (s->cirrus_srccounter <= 0)
831 goto the_end;
832 /* more bytes than needed can be transfered because of
833 word alignment, so we keep them for the next line */
834 /* XXX: keep alignment to speed up transfer */
835 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
836 copy_count = s->cirrus_srcptr_end - end_ptr;
837 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
838 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
839 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
840 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
841 }
842 }
843 }
844
845 /***************************************
846 *
847 * bitblt wrapper
848 *
849 ***************************************/
850
851 static void cirrus_bitblt_reset(CirrusVGAState * s)
852 {
853 int need_update;
854
855 s->gr[0x31] &=
856 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
857 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
858 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
859 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
860 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
861 s->cirrus_srccounter = 0;
862 if (!need_update)
863 return;
864 cirrus_update_memory_access(s);
865 }
866
867 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
868 {
869 int w;
870
871 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
872 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
873 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
874
875 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
876 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
877 s->cirrus_blt_srcpitch = 8;
878 } else {
879 /* XXX: check for 24 bpp */
880 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
881 }
882 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
883 } else {
884 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
885 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
886 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
887 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
888 else
889 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
890 } else {
891 /* always align input size to 32 bits */
892 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
893 }
894 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
895 }
896 s->cirrus_srcptr = s->cirrus_bltbuf;
897 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
898 cirrus_update_memory_access(s);
899 return 1;
900 }
901
902 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
903 {
904 /* XXX */
905 #ifdef DEBUG_BITBLT
906 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
907 #endif
908 return 0;
909 }
910
911 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
912 {
913 int ret;
914
915 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
916 ret = cirrus_bitblt_videotovideo_patterncopy(s);
917 } else {
918 ret = cirrus_bitblt_videotovideo_copy(s);
919 }
920 if (ret)
921 cirrus_bitblt_reset(s);
922 return ret;
923 }
924
925 static void cirrus_bitblt_start(CirrusVGAState * s)
926 {
927 uint8_t blt_rop;
928
929 s->gr[0x31] |= CIRRUS_BLT_BUSY;
930
931 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
932 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
933 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
934 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
935 s->cirrus_blt_dstaddr =
936 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
937 s->cirrus_blt_srcaddr =
938 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
939 s->cirrus_blt_mode = s->gr[0x30];
940 s->cirrus_blt_modeext = s->gr[0x33];
941 blt_rop = s->gr[0x32];
942
943 #ifdef DEBUG_BITBLT
944 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
945 blt_rop,
946 s->cirrus_blt_mode,
947 s->cirrus_blt_modeext,
948 s->cirrus_blt_width,
949 s->cirrus_blt_height,
950 s->cirrus_blt_dstpitch,
951 s->cirrus_blt_srcpitch,
952 s->cirrus_blt_dstaddr,
953 s->cirrus_blt_srcaddr,
954 s->gr[0x2f]);
955 #endif
956
957 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
958 case CIRRUS_BLTMODE_PIXELWIDTH8:
959 s->cirrus_blt_pixelwidth = 1;
960 break;
961 case CIRRUS_BLTMODE_PIXELWIDTH16:
962 s->cirrus_blt_pixelwidth = 2;
963 break;
964 case CIRRUS_BLTMODE_PIXELWIDTH24:
965 s->cirrus_blt_pixelwidth = 3;
966 break;
967 case CIRRUS_BLTMODE_PIXELWIDTH32:
968 s->cirrus_blt_pixelwidth = 4;
969 break;
970 default:
971 #ifdef DEBUG_BITBLT
972 printf("cirrus: bitblt - pixel width is unknown\n");
973 #endif
974 goto bitblt_ignore;
975 }
976 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
977
978 if ((s->
979 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
980 CIRRUS_BLTMODE_MEMSYSDEST))
981 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
982 #ifdef DEBUG_BITBLT
983 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
984 #endif
985 goto bitblt_ignore;
986 }
987
988 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
989 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
990 CIRRUS_BLTMODE_TRANSPARENTCOMP |
991 CIRRUS_BLTMODE_PATTERNCOPY |
992 CIRRUS_BLTMODE_COLOREXPAND)) ==
993 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
994 cirrus_bitblt_fgcol(s);
995 cirrus_bitblt_solidfill(s, blt_rop);
996 } else {
997 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
998 CIRRUS_BLTMODE_PATTERNCOPY)) ==
999 CIRRUS_BLTMODE_COLOREXPAND) {
1000
1001 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1002 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1003 cirrus_bitblt_bgcol(s);
1004 else
1005 cirrus_bitblt_fgcol(s);
1006 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1007 } else {
1008 cirrus_bitblt_fgcol(s);
1009 cirrus_bitblt_bgcol(s);
1010 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1011 }
1012 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1013 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1014 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1015 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1016 cirrus_bitblt_bgcol(s);
1017 else
1018 cirrus_bitblt_fgcol(s);
1019 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1020 } else {
1021 cirrus_bitblt_fgcol(s);
1022 cirrus_bitblt_bgcol(s);
1023 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1024 }
1025 } else {
1026 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1027 }
1028 } else {
1029 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1030 if (s->cirrus_blt_pixelwidth > 2) {
1031 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1032 goto bitblt_ignore;
1033 }
1034 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1035 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1036 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1037 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1038 } else {
1039 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1040 }
1041 } else {
1042 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1043 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1044 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1045 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1046 } else {
1047 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1048 }
1049 }
1050 }
1051 // setup bitblt engine.
1052 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1053 if (!cirrus_bitblt_cputovideo(s))
1054 goto bitblt_ignore;
1055 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1056 if (!cirrus_bitblt_videotocpu(s))
1057 goto bitblt_ignore;
1058 } else {
1059 if (!cirrus_bitblt_videotovideo(s))
1060 goto bitblt_ignore;
1061 }
1062 }
1063 return;
1064 bitblt_ignore:;
1065 cirrus_bitblt_reset(s);
1066 }
1067
1068 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1069 {
1070 unsigned old_value;
1071
1072 old_value = s->gr[0x31];
1073 s->gr[0x31] = reg_value;
1074
1075 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1076 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1077 cirrus_bitblt_reset(s);
1078 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1079 ((reg_value & CIRRUS_BLT_START) != 0)) {
1080 cirrus_bitblt_start(s);
1081 }
1082 }
1083
1084
1085 /***************************************
1086 *
1087 * basic parameters
1088 *
1089 ***************************************/
1090
1091 static void cirrus_get_offsets(VGAState *s1,
1092 uint32_t *pline_offset,
1093 uint32_t *pstart_addr,
1094 uint32_t *pline_compare)
1095 {
1096 CirrusVGAState * s = (CirrusVGAState *)s1;
1097 uint32_t start_addr, line_offset, line_compare;
1098
1099 line_offset = s->cr[0x13]
1100 | ((s->cr[0x1b] & 0x10) << 4);
1101 line_offset <<= 3;
1102 *pline_offset = line_offset;
1103
1104 start_addr = (s->cr[0x0c] << 8)
1105 | s->cr[0x0d]
1106 | ((s->cr[0x1b] & 0x01) << 16)
1107 | ((s->cr[0x1b] & 0x0c) << 15)
1108 | ((s->cr[0x1d] & 0x80) << 12);
1109 *pstart_addr = start_addr;
1110
1111 line_compare = s->cr[0x18] |
1112 ((s->cr[0x07] & 0x10) << 4) |
1113 ((s->cr[0x09] & 0x40) << 3);
1114 *pline_compare = line_compare;
1115 }
1116
1117 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1118 {
1119 uint32_t ret = 16;
1120
1121 switch (s->cirrus_hidden_dac_data & 0xf) {
1122 case 0:
1123 ret = 15;
1124 break; /* Sierra HiColor */
1125 case 1:
1126 ret = 16;
1127 break; /* XGA HiColor */
1128 default:
1129 #ifdef DEBUG_CIRRUS
1130 printf("cirrus: invalid DAC value %x in 16bpp\n",
1131 (s->cirrus_hidden_dac_data & 0xf));
1132 #endif
1133 ret = 15; /* XXX */
1134 break;
1135 }
1136 return ret;
1137 }
1138
1139 static int cirrus_get_bpp(VGAState *s1)
1140 {
1141 CirrusVGAState * s = (CirrusVGAState *)s1;
1142 uint32_t ret = 8;
1143
1144 if ((s->sr[0x07] & 0x01) != 0) {
1145 /* Cirrus SVGA */
1146 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1147 case CIRRUS_SR7_BPP_8:
1148 ret = 8;
1149 break;
1150 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1151 ret = cirrus_get_bpp16_depth(s);
1152 break;
1153 case CIRRUS_SR7_BPP_24:
1154 ret = 24;
1155 break;
1156 case CIRRUS_SR7_BPP_16:
1157 ret = cirrus_get_bpp16_depth(s);
1158 break;
1159 case CIRRUS_SR7_BPP_32:
1160 ret = 32;
1161 break;
1162 default:
1163 #ifdef DEBUG_CIRRUS
1164 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1165 #endif
1166 ret = 8;
1167 break;
1168 }
1169 } else {
1170 /* VGA */
1171 ret = 0;
1172 }
1173
1174 return ret;
1175 }
1176
1177 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1178 {
1179 int width, height;
1180
1181 width = (s->cr[0x01] + 1) * 8;
1182 height = s->cr[0x12] |
1183 ((s->cr[0x07] & 0x02) << 7) |
1184 ((s->cr[0x07] & 0x40) << 3);
1185 height = (height + 1);
1186 /* interlace support */
1187 if (s->cr[0x1a] & 0x01)
1188 height = height * 2;
1189 *pwidth = width;
1190 *pheight = height;
1191 }
1192
1193 /***************************************
1194 *
1195 * bank memory
1196 *
1197 ***************************************/
1198
1199 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1200 {
1201 unsigned offset;
1202 unsigned limit;
1203
1204 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1205 offset = s->gr[0x09 + bank_index];
1206 else /* single bank */
1207 offset = s->gr[0x09];
1208
1209 if ((s->gr[0x0b] & 0x20) != 0)
1210 offset <<= 14;
1211 else
1212 offset <<= 12;
1213
1214 if (s->real_vram_size <= offset)
1215 limit = 0;
1216 else
1217 limit = s->real_vram_size - offset;
1218
1219 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1220 if (limit > 0x8000) {
1221 offset += 0x8000;
1222 limit -= 0x8000;
1223 } else {
1224 limit = 0;
1225 }
1226 }
1227
1228 if (limit > 0) {
1229 /* Thinking about changing bank base? First, drop the dirty bitmap information
1230 * on the current location, otherwise we lose this pointer forever */
1231 if (s->lfb_vram_mapped) {
1232 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1233 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1234 }
1235 s->cirrus_bank_base[bank_index] = offset;
1236 s->cirrus_bank_limit[bank_index] = limit;
1237 } else {
1238 s->cirrus_bank_base[bank_index] = 0;
1239 s->cirrus_bank_limit[bank_index] = 0;
1240 }
1241 }
1242
1243 /***************************************
1244 *
1245 * I/O access between 0x3c4-0x3c5
1246 *
1247 ***************************************/
1248
1249 static int
1250 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1251 {
1252 switch (reg_index) {
1253 case 0x00: // Standard VGA
1254 case 0x01: // Standard VGA
1255 case 0x02: // Standard VGA
1256 case 0x03: // Standard VGA
1257 case 0x04: // Standard VGA
1258 return CIRRUS_HOOK_NOT_HANDLED;
1259 case 0x06: // Unlock Cirrus extensions
1260 *reg_value = s->sr[reg_index];
1261 break;
1262 case 0x10:
1263 case 0x30:
1264 case 0x50:
1265 case 0x70: // Graphics Cursor X
1266 case 0x90:
1267 case 0xb0:
1268 case 0xd0:
1269 case 0xf0: // Graphics Cursor X
1270 *reg_value = s->sr[0x10];
1271 break;
1272 case 0x11:
1273 case 0x31:
1274 case 0x51:
1275 case 0x71: // Graphics Cursor Y
1276 case 0x91:
1277 case 0xb1:
1278 case 0xd1:
1279 case 0xf1: // Graphics Cursor Y
1280 *reg_value = s->sr[0x11];
1281 break;
1282 case 0x05: // ???
1283 case 0x07: // Extended Sequencer Mode
1284 case 0x08: // EEPROM Control
1285 case 0x09: // Scratch Register 0
1286 case 0x0a: // Scratch Register 1
1287 case 0x0b: // VCLK 0
1288 case 0x0c: // VCLK 1
1289 case 0x0d: // VCLK 2
1290 case 0x0e: // VCLK 3
1291 case 0x0f: // DRAM Control
1292 case 0x12: // Graphics Cursor Attribute
1293 case 0x13: // Graphics Cursor Pattern Address
1294 case 0x14: // Scratch Register 2
1295 case 0x15: // Scratch Register 3
1296 case 0x16: // Performance Tuning Register
1297 case 0x17: // Configuration Readback and Extended Control
1298 case 0x18: // Signature Generator Control
1299 case 0x19: // Signal Generator Result
1300 case 0x1a: // Signal Generator Result
1301 case 0x1b: // VCLK 0 Denominator & Post
1302 case 0x1c: // VCLK 1 Denominator & Post
1303 case 0x1d: // VCLK 2 Denominator & Post
1304 case 0x1e: // VCLK 3 Denominator & Post
1305 case 0x1f: // BIOS Write Enable and MCLK select
1306 #ifdef DEBUG_CIRRUS
1307 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1308 #endif
1309 *reg_value = s->sr[reg_index];
1310 break;
1311 default:
1312 #ifdef DEBUG_CIRRUS
1313 printf("cirrus: inport sr_index %02x\n", reg_index);
1314 #endif
1315 *reg_value = 0xff;
1316 break;
1317 }
1318
1319 return CIRRUS_HOOK_HANDLED;
1320 }
1321
1322 static int
1323 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1324 {
1325 switch (reg_index) {
1326 case 0x00: // Standard VGA
1327 case 0x01: // Standard VGA
1328 case 0x02: // Standard VGA
1329 case 0x03: // Standard VGA
1330 case 0x04: // Standard VGA
1331 return CIRRUS_HOOK_NOT_HANDLED;
1332 case 0x06: // Unlock Cirrus extensions
1333 reg_value &= 0x17;
1334 if (reg_value == 0x12) {
1335 s->sr[reg_index] = 0x12;
1336 } else {
1337 s->sr[reg_index] = 0x0f;
1338 }
1339 break;
1340 case 0x10:
1341 case 0x30:
1342 case 0x50:
1343 case 0x70: // Graphics Cursor X
1344 case 0x90:
1345 case 0xb0:
1346 case 0xd0:
1347 case 0xf0: // Graphics Cursor X
1348 s->sr[0x10] = reg_value;
1349 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1350 break;
1351 case 0x11:
1352 case 0x31:
1353 case 0x51:
1354 case 0x71: // Graphics Cursor Y
1355 case 0x91:
1356 case 0xb1:
1357 case 0xd1:
1358 case 0xf1: // Graphics Cursor Y
1359 s->sr[0x11] = reg_value;
1360 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1361 break;
1362 case 0x07: // Extended Sequencer Mode
1363 cirrus_update_memory_access(s);
1364 case 0x08: // EEPROM Control
1365 case 0x09: // Scratch Register 0
1366 case 0x0a: // Scratch Register 1
1367 case 0x0b: // VCLK 0
1368 case 0x0c: // VCLK 1
1369 case 0x0d: // VCLK 2
1370 case 0x0e: // VCLK 3
1371 case 0x0f: // DRAM Control
1372 case 0x12: // Graphics Cursor Attribute
1373 case 0x13: // Graphics Cursor Pattern Address
1374 case 0x14: // Scratch Register 2
1375 case 0x15: // Scratch Register 3
1376 case 0x16: // Performance Tuning Register
1377 case 0x18: // Signature Generator Control
1378 case 0x19: // Signature Generator Result
1379 case 0x1a: // Signature Generator Result
1380 case 0x1b: // VCLK 0 Denominator & Post
1381 case 0x1c: // VCLK 1 Denominator & Post
1382 case 0x1d: // VCLK 2 Denominator & Post
1383 case 0x1e: // VCLK 3 Denominator & Post
1384 case 0x1f: // BIOS Write Enable and MCLK select
1385 s->sr[reg_index] = reg_value;
1386 #ifdef DEBUG_CIRRUS
1387 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1388 reg_index, reg_value);
1389 #endif
1390 break;
1391 case 0x17: // Configuration Readback and Extended Control
1392 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1393 cirrus_update_memory_access(s);
1394 break;
1395 default:
1396 #ifdef DEBUG_CIRRUS
1397 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1398 reg_value);
1399 #endif
1400 break;
1401 }
1402
1403 return CIRRUS_HOOK_HANDLED;
1404 }
1405
1406 /***************************************
1407 *
1408 * I/O access at 0x3c6
1409 *
1410 ***************************************/
1411
1412 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1413 {
1414 *reg_value = 0xff;
1415 if (++s->cirrus_hidden_dac_lockindex == 5) {
1416 *reg_value = s->cirrus_hidden_dac_data;
1417 s->cirrus_hidden_dac_lockindex = 0;
1418 }
1419 }
1420
1421 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1422 {
1423 if (s->cirrus_hidden_dac_lockindex == 4) {
1424 s->cirrus_hidden_dac_data = reg_value;
1425 #if defined(DEBUG_CIRRUS)
1426 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1427 #endif
1428 }
1429 s->cirrus_hidden_dac_lockindex = 0;
1430 }
1431
1432 /***************************************
1433 *
1434 * I/O access at 0x3c9
1435 *
1436 ***************************************/
1437
1438 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1439 {
1440 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1441 return CIRRUS_HOOK_NOT_HANDLED;
1442 *reg_value =
1443 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1444 s->dac_sub_index];
1445 if (++s->dac_sub_index == 3) {
1446 s->dac_sub_index = 0;
1447 s->dac_read_index++;
1448 }
1449 return CIRRUS_HOOK_HANDLED;
1450 }
1451
1452 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1453 {
1454 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1455 return CIRRUS_HOOK_NOT_HANDLED;
1456 s->dac_cache[s->dac_sub_index] = reg_value;
1457 if (++s->dac_sub_index == 3) {
1458 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1459 s->dac_cache, 3);
1460 /* XXX update cursor */
1461 s->dac_sub_index = 0;
1462 s->dac_write_index++;
1463 }
1464 return CIRRUS_HOOK_HANDLED;
1465 }
1466
1467 /***************************************
1468 *
1469 * I/O access between 0x3ce-0x3cf
1470 *
1471 ***************************************/
1472
1473 static int
1474 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1475 {
1476 switch (reg_index) {
1477 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1478 *reg_value = s->cirrus_shadow_gr0;
1479 return CIRRUS_HOOK_HANDLED;
1480 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1481 *reg_value = s->cirrus_shadow_gr1;
1482 return CIRRUS_HOOK_HANDLED;
1483 case 0x02: // Standard VGA
1484 case 0x03: // Standard VGA
1485 case 0x04: // Standard VGA
1486 case 0x06: // Standard VGA
1487 case 0x07: // Standard VGA
1488 case 0x08: // Standard VGA
1489 return CIRRUS_HOOK_NOT_HANDLED;
1490 case 0x05: // Standard VGA, Cirrus extended mode
1491 default:
1492 break;
1493 }
1494
1495 if (reg_index < 0x3a) {
1496 *reg_value = s->gr[reg_index];
1497 } else {
1498 #ifdef DEBUG_CIRRUS
1499 printf("cirrus: inport gr_index %02x\n", reg_index);
1500 #endif
1501 *reg_value = 0xff;
1502 }
1503
1504 return CIRRUS_HOOK_HANDLED;
1505 }
1506
1507 static int
1508 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1509 {
1510 #if defined(DEBUG_BITBLT) && 0
1511 printf("gr%02x: %02x\n", reg_index, reg_value);
1512 #endif
1513 switch (reg_index) {
1514 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1515 s->cirrus_shadow_gr0 = reg_value;
1516 return CIRRUS_HOOK_NOT_HANDLED;
1517 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1518 s->cirrus_shadow_gr1 = reg_value;
1519 return CIRRUS_HOOK_NOT_HANDLED;
1520 case 0x02: // Standard VGA
1521 case 0x03: // Standard VGA
1522 case 0x04: // Standard VGA
1523 case 0x06: // Standard VGA
1524 case 0x07: // Standard VGA
1525 case 0x08: // Standard VGA
1526 return CIRRUS_HOOK_NOT_HANDLED;
1527 case 0x05: // Standard VGA, Cirrus extended mode
1528 s->gr[reg_index] = reg_value & 0x7f;
1529 cirrus_update_memory_access(s);
1530 break;
1531 case 0x09: // bank offset #0
1532 case 0x0A: // bank offset #1
1533 s->gr[reg_index] = reg_value;
1534 cirrus_update_bank_ptr(s, 0);
1535 cirrus_update_bank_ptr(s, 1);
1536 cirrus_update_memory_access(s);
1537 break;
1538 case 0x0B:
1539 s->gr[reg_index] = reg_value;
1540 cirrus_update_bank_ptr(s, 0);
1541 cirrus_update_bank_ptr(s, 1);
1542 cirrus_update_memory_access(s);
1543 break;
1544 case 0x10: // BGCOLOR 0x0000ff00
1545 case 0x11: // FGCOLOR 0x0000ff00
1546 case 0x12: // BGCOLOR 0x00ff0000
1547 case 0x13: // FGCOLOR 0x00ff0000
1548 case 0x14: // BGCOLOR 0xff000000
1549 case 0x15: // FGCOLOR 0xff000000
1550 case 0x20: // BLT WIDTH 0x0000ff
1551 case 0x22: // BLT HEIGHT 0x0000ff
1552 case 0x24: // BLT DEST PITCH 0x0000ff
1553 case 0x26: // BLT SRC PITCH 0x0000ff
1554 case 0x28: // BLT DEST ADDR 0x0000ff
1555 case 0x29: // BLT DEST ADDR 0x00ff00
1556 case 0x2c: // BLT SRC ADDR 0x0000ff
1557 case 0x2d: // BLT SRC ADDR 0x00ff00
1558 case 0x2f: // BLT WRITEMASK
1559 case 0x30: // BLT MODE
1560 case 0x32: // RASTER OP
1561 case 0x33: // BLT MODEEXT
1562 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1563 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1564 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1565 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1566 s->gr[reg_index] = reg_value;
1567 break;
1568 case 0x21: // BLT WIDTH 0x001f00
1569 case 0x23: // BLT HEIGHT 0x001f00
1570 case 0x25: // BLT DEST PITCH 0x001f00
1571 case 0x27: // BLT SRC PITCH 0x001f00
1572 s->gr[reg_index] = reg_value & 0x1f;
1573 break;
1574 case 0x2a: // BLT DEST ADDR 0x3f0000
1575 s->gr[reg_index] = reg_value & 0x3f;
1576 /* if auto start mode, starts bit blt now */
1577 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1578 cirrus_bitblt_start(s);
1579 }
1580 break;
1581 case 0x2e: // BLT SRC ADDR 0x3f0000
1582 s->gr[reg_index] = reg_value & 0x3f;
1583 break;
1584 case 0x31: // BLT STATUS/START
1585 cirrus_write_bitblt(s, reg_value);
1586 break;
1587 default:
1588 #ifdef DEBUG_CIRRUS
1589 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1590 reg_value);
1591 #endif
1592 break;
1593 }
1594
1595 return CIRRUS_HOOK_HANDLED;
1596 }
1597
1598 /***************************************
1599 *
1600 * I/O access between 0x3d4-0x3d5
1601 *
1602 ***************************************/
1603
1604 static int
1605 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1606 {
1607 switch (reg_index) {
1608 case 0x00: // Standard VGA
1609 case 0x01: // Standard VGA
1610 case 0x02: // Standard VGA
1611 case 0x03: // Standard VGA
1612 case 0x04: // Standard VGA
1613 case 0x05: // Standard VGA
1614 case 0x06: // Standard VGA
1615 case 0x07: // Standard VGA
1616 case 0x08: // Standard VGA
1617 case 0x09: // Standard VGA
1618 case 0x0a: // Standard VGA
1619 case 0x0b: // Standard VGA
1620 case 0x0c: // Standard VGA
1621 case 0x0d: // Standard VGA
1622 case 0x0e: // Standard VGA
1623 case 0x0f: // Standard VGA
1624 case 0x10: // Standard VGA
1625 case 0x11: // Standard VGA
1626 case 0x12: // Standard VGA
1627 case 0x13: // Standard VGA
1628 case 0x14: // Standard VGA
1629 case 0x15: // Standard VGA
1630 case 0x16: // Standard VGA
1631 case 0x17: // Standard VGA
1632 case 0x18: // Standard VGA
1633 return CIRRUS_HOOK_NOT_HANDLED;
1634 case 0x24: // Attribute Controller Toggle Readback (R)
1635 *reg_value = (s->ar_flip_flop << 7);
1636 break;
1637 case 0x19: // Interlace End
1638 case 0x1a: // Miscellaneous Control
1639 case 0x1b: // Extended Display Control
1640 case 0x1c: // Sync Adjust and Genlock
1641 case 0x1d: // Overlay Extended Control
1642 case 0x22: // Graphics Data Latches Readback (R)
1643 case 0x25: // Part Status
1644 case 0x27: // Part ID (R)
1645 *reg_value = s->cr[reg_index];
1646 break;
1647 case 0x26: // Attribute Controller Index Readback (R)
1648 *reg_value = s->ar_index & 0x3f;
1649 break;
1650 default:
1651 #ifdef DEBUG_CIRRUS
1652 printf("cirrus: inport cr_index %02x\n", reg_index);
1653 *reg_value = 0xff;
1654 #endif
1655 break;
1656 }
1657
1658 return CIRRUS_HOOK_HANDLED;
1659 }
1660
1661 static int
1662 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1663 {
1664 switch (reg_index) {
1665 case 0x00: // Standard VGA
1666 case 0x01: // Standard VGA
1667 case 0x02: // Standard VGA
1668 case 0x03: // Standard VGA
1669 case 0x04: // Standard VGA
1670 case 0x05: // Standard VGA
1671 case 0x06: // Standard VGA
1672 case 0x07: // Standard VGA
1673 case 0x08: // Standard VGA
1674 case 0x09: // Standard VGA
1675 case 0x0a: // Standard VGA
1676 case 0x0b: // Standard VGA
1677 case 0x0c: // Standard VGA
1678 case 0x0d: // Standard VGA
1679 case 0x0e: // Standard VGA
1680 case 0x0f: // Standard VGA
1681 case 0x10: // Standard VGA
1682 case 0x11: // Standard VGA
1683 case 0x12: // Standard VGA
1684 case 0x13: // Standard VGA
1685 case 0x14: // Standard VGA
1686 case 0x15: // Standard VGA
1687 case 0x16: // Standard VGA
1688 case 0x17: // Standard VGA
1689 case 0x18: // Standard VGA
1690 return CIRRUS_HOOK_NOT_HANDLED;
1691 case 0x19: // Interlace End
1692 case 0x1a: // Miscellaneous Control
1693 case 0x1b: // Extended Display Control
1694 case 0x1c: // Sync Adjust and Genlock
1695 case 0x1d: // Overlay Extended Control
1696 s->cr[reg_index] = reg_value;
1697 #ifdef DEBUG_CIRRUS
1698 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1699 reg_index, reg_value);
1700 #endif
1701 break;
1702 case 0x22: // Graphics Data Latches Readback (R)
1703 case 0x24: // Attribute Controller Toggle Readback (R)
1704 case 0x26: // Attribute Controller Index Readback (R)
1705 case 0x27: // Part ID (R)
1706 break;
1707 case 0x25: // Part Status
1708 default:
1709 #ifdef DEBUG_CIRRUS
1710 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1711 reg_value);
1712 #endif
1713 break;
1714 }
1715
1716 return CIRRUS_HOOK_HANDLED;
1717 }
1718
1719 /***************************************
1720 *
1721 * memory-mapped I/O (bitblt)
1722 *
1723 ***************************************/
1724
1725 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1726 {
1727 int value = 0xff;
1728
1729 switch (address) {
1730 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1731 cirrus_hook_read_gr(s, 0x00, &value);
1732 break;
1733 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1734 cirrus_hook_read_gr(s, 0x10, &value);
1735 break;
1736 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1737 cirrus_hook_read_gr(s, 0x12, &value);
1738 break;
1739 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1740 cirrus_hook_read_gr(s, 0x14, &value);
1741 break;
1742 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1743 cirrus_hook_read_gr(s, 0x01, &value);
1744 break;
1745 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1746 cirrus_hook_read_gr(s, 0x11, &value);
1747 break;
1748 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1749 cirrus_hook_read_gr(s, 0x13, &value);
1750 break;
1751 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1752 cirrus_hook_read_gr(s, 0x15, &value);
1753 break;
1754 case (CIRRUS_MMIO_BLTWIDTH + 0):
1755 cirrus_hook_read_gr(s, 0x20, &value);
1756 break;
1757 case (CIRRUS_MMIO_BLTWIDTH + 1):
1758 cirrus_hook_read_gr(s, 0x21, &value);
1759 break;
1760 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1761 cirrus_hook_read_gr(s, 0x22, &value);
1762 break;
1763 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1764 cirrus_hook_read_gr(s, 0x23, &value);
1765 break;
1766 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1767 cirrus_hook_read_gr(s, 0x24, &value);
1768 break;
1769 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1770 cirrus_hook_read_gr(s, 0x25, &value);
1771 break;
1772 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1773 cirrus_hook_read_gr(s, 0x26, &value);
1774 break;
1775 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1776 cirrus_hook_read_gr(s, 0x27, &value);
1777 break;
1778 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1779 cirrus_hook_read_gr(s, 0x28, &value);
1780 break;
1781 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1782 cirrus_hook_read_gr(s, 0x29, &value);
1783 break;
1784 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1785 cirrus_hook_read_gr(s, 0x2a, &value);
1786 break;
1787 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1788 cirrus_hook_read_gr(s, 0x2c, &value);
1789 break;
1790 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1791 cirrus_hook_read_gr(s, 0x2d, &value);
1792 break;
1793 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1794 cirrus_hook_read_gr(s, 0x2e, &value);
1795 break;
1796 case CIRRUS_MMIO_BLTWRITEMASK:
1797 cirrus_hook_read_gr(s, 0x2f, &value);
1798 break;
1799 case CIRRUS_MMIO_BLTMODE:
1800 cirrus_hook_read_gr(s, 0x30, &value);
1801 break;
1802 case CIRRUS_MMIO_BLTROP:
1803 cirrus_hook_read_gr(s, 0x32, &value);
1804 break;
1805 case CIRRUS_MMIO_BLTMODEEXT:
1806 cirrus_hook_read_gr(s, 0x33, &value);
1807 break;
1808 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1809 cirrus_hook_read_gr(s, 0x34, &value);
1810 break;
1811 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1812 cirrus_hook_read_gr(s, 0x35, &value);
1813 break;
1814 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1815 cirrus_hook_read_gr(s, 0x38, &value);
1816 break;
1817 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1818 cirrus_hook_read_gr(s, 0x39, &value);
1819 break;
1820 case CIRRUS_MMIO_BLTSTATUS:
1821 cirrus_hook_read_gr(s, 0x31, &value);
1822 break;
1823 default:
1824 #ifdef DEBUG_CIRRUS
1825 printf("cirrus: mmio read - address 0x%04x\n", address);
1826 #endif
1827 break;
1828 }
1829
1830 return (uint8_t) value;
1831 }
1832
1833 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1834 uint8_t value)
1835 {
1836 switch (address) {
1837 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1838 cirrus_hook_write_gr(s, 0x00, value);
1839 break;
1840 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1841 cirrus_hook_write_gr(s, 0x10, value);
1842 break;
1843 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1844 cirrus_hook_write_gr(s, 0x12, value);
1845 break;
1846 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1847 cirrus_hook_write_gr(s, 0x14, value);
1848 break;
1849 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1850 cirrus_hook_write_gr(s, 0x01, value);
1851 break;
1852 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1853 cirrus_hook_write_gr(s, 0x11, value);
1854 break;
1855 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1856 cirrus_hook_write_gr(s, 0x13, value);
1857 break;
1858 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1859 cirrus_hook_write_gr(s, 0x15, value);
1860 break;
1861 case (CIRRUS_MMIO_BLTWIDTH + 0):
1862 cirrus_hook_write_gr(s, 0x20, value);
1863 break;
1864 case (CIRRUS_MMIO_BLTWIDTH + 1):
1865 cirrus_hook_write_gr(s, 0x21, value);
1866 break;
1867 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1868 cirrus_hook_write_gr(s, 0x22, value);
1869 break;
1870 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1871 cirrus_hook_write_gr(s, 0x23, value);
1872 break;
1873 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1874 cirrus_hook_write_gr(s, 0x24, value);
1875 break;
1876 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1877 cirrus_hook_write_gr(s, 0x25, value);
1878 break;
1879 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1880 cirrus_hook_write_gr(s, 0x26, value);
1881 break;
1882 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1883 cirrus_hook_write_gr(s, 0x27, value);
1884 break;
1885 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1886 cirrus_hook_write_gr(s, 0x28, value);
1887 break;
1888 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1889 cirrus_hook_write_gr(s, 0x29, value);
1890 break;
1891 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1892 cirrus_hook_write_gr(s, 0x2a, value);
1893 break;
1894 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1895 /* ignored */
1896 break;
1897 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1898 cirrus_hook_write_gr(s, 0x2c, value);
1899 break;
1900 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1901 cirrus_hook_write_gr(s, 0x2d, value);
1902 break;
1903 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1904 cirrus_hook_write_gr(s, 0x2e, value);
1905 break;
1906 case CIRRUS_MMIO_BLTWRITEMASK:
1907 cirrus_hook_write_gr(s, 0x2f, value);
1908 break;
1909 case CIRRUS_MMIO_BLTMODE:
1910 cirrus_hook_write_gr(s, 0x30, value);
1911 break;
1912 case CIRRUS_MMIO_BLTROP:
1913 cirrus_hook_write_gr(s, 0x32, value);
1914 break;
1915 case CIRRUS_MMIO_BLTMODEEXT:
1916 cirrus_hook_write_gr(s, 0x33, value);
1917 break;
1918 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1919 cirrus_hook_write_gr(s, 0x34, value);
1920 break;
1921 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1922 cirrus_hook_write_gr(s, 0x35, value);
1923 break;
1924 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1925 cirrus_hook_write_gr(s, 0x38, value);
1926 break;
1927 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1928 cirrus_hook_write_gr(s, 0x39, value);
1929 break;
1930 case CIRRUS_MMIO_BLTSTATUS:
1931 cirrus_hook_write_gr(s, 0x31, value);
1932 break;
1933 default:
1934 #ifdef DEBUG_CIRRUS
1935 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1936 address, value);
1937 #endif
1938 break;
1939 }
1940 }
1941
1942 /***************************************
1943 *
1944 * write mode 4/5
1945 *
1946 * assume TARGET_PAGE_SIZE >= 16
1947 *
1948 ***************************************/
1949
1950 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1951 unsigned mode,
1952 unsigned offset,
1953 uint32_t mem_value)
1954 {
1955 int x;
1956 unsigned val = mem_value;
1957 uint8_t *dst;
1958
1959 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1960 for (x = 0; x < 8; x++) {
1961 if (val & 0x80) {
1962 *dst = s->cirrus_shadow_gr1;
1963 } else if (mode == 5) {
1964 *dst = s->cirrus_shadow_gr0;
1965 }
1966 val <<= 1;
1967 dst++;
1968 }
1969 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1970 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1971 }
1972
1973 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1974 unsigned mode,
1975 unsigned offset,
1976 uint32_t mem_value)
1977 {
1978 int x;
1979 unsigned val = mem_value;
1980 uint8_t *dst;
1981
1982 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1983 for (x = 0; x < 8; x++) {
1984 if (val & 0x80) {
1985 *dst = s->cirrus_shadow_gr1;
1986 *(dst + 1) = s->gr[0x11];
1987 } else if (mode == 5) {
1988 *dst = s->cirrus_shadow_gr0;
1989 *(dst + 1) = s->gr[0x10];
1990 }
1991 val <<= 1;
1992 dst += 2;
1993 }
1994 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1995 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1996 }
1997
1998 /***************************************
1999 *
2000 * memory access between 0xa0000-0xbffff
2001 *
2002 ***************************************/
2003
2004 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2005 {
2006 CirrusVGAState *s = opaque;
2007 unsigned bank_index;
2008 unsigned bank_offset;
2009 uint32_t val;
2010
2011 if ((s->sr[0x07] & 0x01) == 0) {
2012 return vga_mem_readb(s, addr);
2013 }
2014
2015 addr &= 0x1ffff;
2016
2017 if (addr < 0x10000) {
2018 /* XXX handle bitblt */
2019 /* video memory */
2020 bank_index = addr >> 15;
2021 bank_offset = addr & 0x7fff;
2022 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2023 bank_offset += s->cirrus_bank_base[bank_index];
2024 if ((s->gr[0x0B] & 0x14) == 0x14) {
2025 bank_offset <<= 4;
2026 } else if (s->gr[0x0B] & 0x02) {
2027 bank_offset <<= 3;
2028 }
2029 bank_offset &= s->cirrus_addr_mask;
2030 val = *(s->vram_ptr + bank_offset);
2031 } else
2032 val = 0xff;
2033 } else if (addr >= 0x18000 && addr < 0x18100) {
2034 /* memory-mapped I/O */
2035 val = 0xff;
2036 if ((s->sr[0x17] & 0x44) == 0x04) {
2037 val = cirrus_mmio_blt_read(s, addr & 0xff);
2038 }
2039 } else {
2040 val = 0xff;
2041 #ifdef DEBUG_CIRRUS
2042 printf("cirrus: mem_readb %06x\n", addr);
2043 #endif
2044 }
2045 return val;
2046 }
2047
2048 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2049 {
2050 uint32_t v;
2051 #ifdef TARGET_WORDS_BIGENDIAN
2052 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2053 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2054 #else
2055 v = cirrus_vga_mem_readb(opaque, addr);
2056 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2057 #endif
2058 return v;
2059 }
2060
2061 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2062 {
2063 uint32_t v;
2064 #ifdef TARGET_WORDS_BIGENDIAN
2065 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2066 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2067 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2068 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2069 #else
2070 v = cirrus_vga_mem_readb(opaque, addr);
2071 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2072 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2073 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2074 #endif
2075 return v;
2076 }
2077
2078 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2079 uint32_t mem_value)
2080 {
2081 CirrusVGAState *s = opaque;
2082 unsigned bank_index;
2083 unsigned bank_offset;
2084 unsigned mode;
2085
2086 if ((s->sr[0x07] & 0x01) == 0) {
2087 vga_mem_writeb(s, addr, mem_value);
2088 return;
2089 }
2090
2091 addr &= 0x1ffff;
2092
2093 if (addr < 0x10000) {
2094 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2095 /* bitblt */
2096 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2097 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2098 cirrus_bitblt_cputovideo_next(s);
2099 }
2100 } else {
2101 /* video memory */
2102 bank_index = addr >> 15;
2103 bank_offset = addr & 0x7fff;
2104 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2105 bank_offset += s->cirrus_bank_base[bank_index];
2106 if ((s->gr[0x0B] & 0x14) == 0x14) {
2107 bank_offset <<= 4;
2108 } else if (s->gr[0x0B] & 0x02) {
2109 bank_offset <<= 3;
2110 }
2111 bank_offset &= s->cirrus_addr_mask;
2112 mode = s->gr[0x05] & 0x7;
2113 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2114 *(s->vram_ptr + bank_offset) = mem_value;
2115 cpu_physical_memory_set_dirty(s->vram_offset +
2116 bank_offset);
2117 } else {
2118 if ((s->gr[0x0B] & 0x14) != 0x14) {
2119 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2120 bank_offset,
2121 mem_value);
2122 } else {
2123 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2124 bank_offset,
2125 mem_value);
2126 }
2127 }
2128 }
2129 }
2130 } else if (addr >= 0x18000 && addr < 0x18100) {
2131 /* memory-mapped I/O */
2132 if ((s->sr[0x17] & 0x44) == 0x04) {
2133 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2134 }
2135 } else {
2136 #ifdef DEBUG_CIRRUS
2137 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2138 #endif
2139 }
2140 }
2141
2142 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2143 {
2144 #ifdef TARGET_WORDS_BIGENDIAN
2145 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2146 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2147 #else
2148 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2149 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2150 #endif
2151 }
2152
2153 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2154 {
2155 #ifdef TARGET_WORDS_BIGENDIAN
2156 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2157 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2158 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2159 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2160 #else
2161 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2162 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2163 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2164 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2165 #endif
2166 }
2167
2168 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2169 cirrus_vga_mem_readb,
2170 cirrus_vga_mem_readw,
2171 cirrus_vga_mem_readl,
2172 };
2173
2174 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2175 cirrus_vga_mem_writeb,
2176 cirrus_vga_mem_writew,
2177 cirrus_vga_mem_writel,
2178 };
2179
2180 /***************************************
2181 *
2182 * hardware cursor
2183 *
2184 ***************************************/
2185
2186 static inline void invalidate_cursor1(CirrusVGAState *s)
2187 {
2188 if (s->last_hw_cursor_size) {
2189 vga_invalidate_scanlines((VGAState *)s,
2190 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2191 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2192 }
2193 }
2194
2195 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2196 {
2197 const uint8_t *src;
2198 uint32_t content;
2199 int y, y_min, y_max;
2200
2201 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2202 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2203 src += (s->sr[0x13] & 0x3c) * 256;
2204 y_min = 64;
2205 y_max = -1;
2206 for(y = 0; y < 64; y++) {
2207 content = ((uint32_t *)src)[0] |
2208 ((uint32_t *)src)[1] |
2209 ((uint32_t *)src)[2] |
2210 ((uint32_t *)src)[3];
2211 if (content) {
2212 if (y < y_min)
2213 y_min = y;
2214 if (y > y_max)
2215 y_max = y;
2216 }
2217 src += 16;
2218 }
2219 } else {
2220 src += (s->sr[0x13] & 0x3f) * 256;
2221 y_min = 32;
2222 y_max = -1;
2223 for(y = 0; y < 32; y++) {
2224 content = ((uint32_t *)src)[0] |
2225 ((uint32_t *)(src + 128))[0];
2226 if (content) {
2227 if (y < y_min)
2228 y_min = y;
2229 if (y > y_max)
2230 y_max = y;
2231 }
2232 src += 4;
2233 }
2234 }
2235 if (y_min > y_max) {
2236 s->last_hw_cursor_y_start = 0;
2237 s->last_hw_cursor_y_end = 0;
2238 } else {
2239 s->last_hw_cursor_y_start = y_min;
2240 s->last_hw_cursor_y_end = y_max + 1;
2241 }
2242 }
2243
2244 /* NOTE: we do not currently handle the cursor bitmap change, so we
2245 update the cursor only if it moves. */
2246 static void cirrus_cursor_invalidate(VGAState *s1)
2247 {
2248 CirrusVGAState *s = (CirrusVGAState *)s1;
2249 int size;
2250
2251 if (!s->sr[0x12] & CIRRUS_CURSOR_SHOW) {
2252 size = 0;
2253 } else {
2254 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2255 size = 64;
2256 else
2257 size = 32;
2258 }
2259 /* invalidate last cursor and new cursor if any change */
2260 if (s->last_hw_cursor_size != size ||
2261 s->last_hw_cursor_x != s->hw_cursor_x ||
2262 s->last_hw_cursor_y != s->hw_cursor_y) {
2263
2264 invalidate_cursor1(s);
2265
2266 s->last_hw_cursor_size = size;
2267 s->last_hw_cursor_x = s->hw_cursor_x;
2268 s->last_hw_cursor_y = s->hw_cursor_y;
2269 /* compute the real cursor min and max y */
2270 cirrus_cursor_compute_yrange(s);
2271 invalidate_cursor1(s);
2272 }
2273 }
2274
2275 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2276 {
2277 CirrusVGAState *s = (CirrusVGAState *)s1;
2278 int w, h, bpp, x1, x2, poffset;
2279 unsigned int color0, color1;
2280 const uint8_t *palette, *src;
2281 uint32_t content;
2282
2283 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2284 return;
2285 /* fast test to see if the cursor intersects with the scan line */
2286 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2287 h = 64;
2288 } else {
2289 h = 32;
2290 }
2291 if (scr_y < s->hw_cursor_y ||
2292 scr_y >= (s->hw_cursor_y + h))
2293 return;
2294
2295 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2296 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2297 src += (s->sr[0x13] & 0x3c) * 256;
2298 src += (scr_y - s->hw_cursor_y) * 16;
2299 poffset = 8;
2300 content = ((uint32_t *)src)[0] |
2301 ((uint32_t *)src)[1] |
2302 ((uint32_t *)src)[2] |
2303 ((uint32_t *)src)[3];
2304 } else {
2305 src += (s->sr[0x13] & 0x3f) * 256;
2306 src += (scr_y - s->hw_cursor_y) * 4;
2307 poffset = 128;
2308 content = ((uint32_t *)src)[0] |
2309 ((uint32_t *)(src + 128))[0];
2310 }
2311 /* if nothing to draw, no need to continue */
2312 if (!content)
2313 return;
2314 w = h;
2315
2316 x1 = s->hw_cursor_x;
2317 if (x1 >= s->last_scr_width)
2318 return;
2319 x2 = s->hw_cursor_x + w;
2320 if (x2 > s->last_scr_width)
2321 x2 = s->last_scr_width;
2322 w = x2 - x1;
2323 palette = s->cirrus_hidden_palette;
2324 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2325 c6_to_8(palette[0x0 * 3 + 1]),
2326 c6_to_8(palette[0x0 * 3 + 2]));
2327 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2328 c6_to_8(palette[0xf * 3 + 1]),
2329 c6_to_8(palette[0xf * 3 + 2]));
2330 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2331 d1 += x1 * bpp;
2332 switch(ds_get_bits_per_pixel(s->ds)) {
2333 default:
2334 break;
2335 case 8:
2336 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2337 break;
2338 case 15:
2339 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2340 break;
2341 case 16:
2342 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2343 break;
2344 case 32:
2345 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2346 break;
2347 }
2348 }
2349
2350 /***************************************
2351 *
2352 * LFB memory access
2353 *
2354 ***************************************/
2355
2356 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2357 {
2358 CirrusVGAState *s = (CirrusVGAState *) opaque;
2359 uint32_t ret;
2360
2361 addr &= s->cirrus_addr_mask;
2362
2363 if (((s->sr[0x17] & 0x44) == 0x44) &&
2364 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2365 /* memory-mapped I/O */
2366 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2367 } else if (0) {
2368 /* XXX handle bitblt */
2369 ret = 0xff;
2370 } else {
2371 /* video memory */
2372 if ((s->gr[0x0B] & 0x14) == 0x14) {
2373 addr <<= 4;
2374 } else if (s->gr[0x0B] & 0x02) {
2375 addr <<= 3;
2376 }
2377 addr &= s->cirrus_addr_mask;
2378 ret = *(s->vram_ptr + addr);
2379 }
2380
2381 return ret;
2382 }
2383
2384 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2385 {
2386 uint32_t v;
2387 #ifdef TARGET_WORDS_BIGENDIAN
2388 v = cirrus_linear_readb(opaque, addr) << 8;
2389 v |= cirrus_linear_readb(opaque, addr + 1);
2390 #else
2391 v = cirrus_linear_readb(opaque, addr);
2392 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2393 #endif
2394 return v;
2395 }
2396
2397 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2398 {
2399 uint32_t v;
2400 #ifdef TARGET_WORDS_BIGENDIAN
2401 v = cirrus_linear_readb(opaque, addr) << 24;
2402 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2403 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2404 v |= cirrus_linear_readb(opaque, addr + 3);
2405 #else
2406 v = cirrus_linear_readb(opaque, addr);
2407 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2408 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2409 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2410 #endif
2411 return v;
2412 }
2413
2414 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2415 uint32_t val)
2416 {
2417 CirrusVGAState *s = (CirrusVGAState *) opaque;
2418 unsigned mode;
2419
2420 addr &= s->cirrus_addr_mask;
2421
2422 if (((s->sr[0x17] & 0x44) == 0x44) &&
2423 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2424 /* memory-mapped I/O */
2425 cirrus_mmio_blt_write(s, addr & 0xff, val);
2426 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2427 /* bitblt */
2428 *s->cirrus_srcptr++ = (uint8_t) val;
2429 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2430 cirrus_bitblt_cputovideo_next(s);
2431 }
2432 } else {
2433 /* video memory */
2434 if ((s->gr[0x0B] & 0x14) == 0x14) {
2435 addr <<= 4;
2436 } else if (s->gr[0x0B] & 0x02) {
2437 addr <<= 3;
2438 }
2439 addr &= s->cirrus_addr_mask;
2440
2441 mode = s->gr[0x05] & 0x7;
2442 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2443 *(s->vram_ptr + addr) = (uint8_t) val;
2444 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2445 } else {
2446 if ((s->gr[0x0B] & 0x14) != 0x14) {
2447 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2448 } else {
2449 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2450 }
2451 }
2452 }
2453 }
2454
2455 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2456 uint32_t val)
2457 {
2458 #ifdef TARGET_WORDS_BIGENDIAN
2459 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2460 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2461 #else
2462 cirrus_linear_writeb(opaque, addr, val & 0xff);
2463 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2464 #endif
2465 }
2466
2467 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2468 uint32_t val)
2469 {
2470 #ifdef TARGET_WORDS_BIGENDIAN
2471 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2472 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2473 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2474 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2475 #else
2476 cirrus_linear_writeb(opaque, addr, val & 0xff);
2477 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2478 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2479 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2480 #endif
2481 }
2482
2483
2484 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2485 cirrus_linear_readb,
2486 cirrus_linear_readw,
2487 cirrus_linear_readl,
2488 };
2489
2490 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2491 cirrus_linear_writeb,
2492 cirrus_linear_writew,
2493 cirrus_linear_writel,
2494 };
2495
2496 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2497 uint32_t val)
2498 {
2499 CirrusVGAState *s = (CirrusVGAState *) opaque;
2500
2501 addr &= s->cirrus_addr_mask;
2502 *(s->vram_ptr + addr) = val;
2503 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2504 }
2505
2506 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2507 uint32_t val)
2508 {
2509 CirrusVGAState *s = (CirrusVGAState *) opaque;
2510
2511 addr &= s->cirrus_addr_mask;
2512 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2513 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2514 }
2515
2516 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2517 uint32_t val)
2518 {
2519 CirrusVGAState *s = (CirrusVGAState *) opaque;
2520
2521 addr &= s->cirrus_addr_mask;
2522 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2523 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2524 }
2525
2526 /***************************************
2527 *
2528 * system to screen memory access
2529 *
2530 ***************************************/
2531
2532
2533 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2534 {
2535 uint32_t ret;
2536
2537 /* XXX handle bitblt */
2538 ret = 0xff;
2539 return ret;
2540 }
2541
2542 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2543 {
2544 uint32_t v;
2545 #ifdef TARGET_WORDS_BIGENDIAN
2546 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2547 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2548 #else
2549 v = cirrus_linear_bitblt_readb(opaque, addr);
2550 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2551 #endif
2552 return v;
2553 }
2554
2555 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2556 {
2557 uint32_t v;
2558 #ifdef TARGET_WORDS_BIGENDIAN
2559 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2560 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2561 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2562 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2563 #else
2564 v = cirrus_linear_bitblt_readb(opaque, addr);
2565 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2566 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2567 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2568 #endif
2569 return v;
2570 }
2571
2572 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2573 uint32_t val)
2574 {
2575 CirrusVGAState *s = (CirrusVGAState *) opaque;
2576
2577 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2578 /* bitblt */
2579 *s->cirrus_srcptr++ = (uint8_t) val;
2580 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2581 cirrus_bitblt_cputovideo_next(s);
2582 }
2583 }
2584 }
2585
2586 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2587 uint32_t val)
2588 {
2589 #ifdef TARGET_WORDS_BIGENDIAN
2590 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2591 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2592 #else
2593 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2594 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2595 #endif
2596 }
2597
2598 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2599 uint32_t val)
2600 {
2601 #ifdef TARGET_WORDS_BIGENDIAN
2602 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2603 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2604 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2605 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2606 #else
2607 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2608 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2609 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2610 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2611 #endif
2612 }
2613
2614
2615 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2616 cirrus_linear_bitblt_readb,
2617 cirrus_linear_bitblt_readw,
2618 cirrus_linear_bitblt_readl,
2619 };
2620
2621 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2622 cirrus_linear_bitblt_writeb,
2623 cirrus_linear_bitblt_writew,
2624 cirrus_linear_bitblt_writel,
2625 };
2626
2627 static void map_linear_vram(CirrusVGAState *s)
2628 {
2629 vga_dirty_log_stop((VGAState *)s);
2630
2631 vga_dirty_log_stop((VGAState *)s);
2632 if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2633 s->map_addr = s->lfb_addr;
2634 s->map_end = s->lfb_end;
2635 cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2636 }
2637
2638 if (!s->map_addr)
2639 return;
2640
2641 #ifndef TARGET_IA64
2642 s->lfb_vram_mapped = 0;
2643
2644 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2645 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_UNASSIGNED);
2646 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2647 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_UNASSIGNED);
2648 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2649 && !((s->sr[0x07] & 0x01) == 0)
2650 && !((s->gr[0x0B] & 0x14) == 0x14)
2651 && !(s->gr[0x0B] & 0x02)) {
2652
2653 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2654 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2655 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2656 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2657
2658 s->lfb_vram_mapped = 1;
2659 }
2660 else {
2661 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2662 s->vga_io_memory);
2663 }
2664 #endif
2665
2666 vga_dirty_log_start((VGAState *)s);
2667 }
2668
2669 static void unmap_linear_vram(CirrusVGAState *s)
2670 {
2671 vga_dirty_log_stop((VGAState *)s);
2672 if (s->map_addr && s->lfb_addr && s->lfb_end)
2673 s->map_addr = s->map_end = 0;
2674
2675 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2676 s->vga_io_memory);
2677
2678 vga_dirty_log_start((VGAState *)s);
2679 }
2680
2681 /* Compute the memory access functions */
2682 static void cirrus_update_memory_access(CirrusVGAState *s)
2683 {
2684 unsigned mode;
2685
2686 if ((s->sr[0x17] & 0x44) == 0x44) {
2687 goto generic_io;
2688 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2689 goto generic_io;
2690 } else {
2691 if ((s->gr[0x0B] & 0x14) == 0x14) {
2692 goto generic_io;
2693 } else if (s->gr[0x0B] & 0x02) {
2694 goto generic_io;
2695 }
2696
2697 mode = s->gr[0x05] & 0x7;
2698 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2699 map_linear_vram(s);
2700 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2701 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2702 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2703 } else {
2704 generic_io:
2705 unmap_linear_vram(s);
2706 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2707 s->cirrus_linear_write[1] = cirrus_linear_writew;
2708 s->cirrus_linear_write[2] = cirrus_linear_writel;
2709 }
2710 }
2711 }
2712
2713
2714 /* I/O ports */
2715
2716 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2717 {
2718 CirrusVGAState *s = opaque;
2719 int val, index;
2720
2721 /* check port range access depending on color/monochrome mode */
2722 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2723 || (addr >= 0x3d0 && addr <= 0x3df
2724 && !(s->msr & MSR_COLOR_EMULATION))) {
2725 val = 0xff;
2726 } else {
2727 switch (addr) {
2728 case 0x3c0:
2729 if (s->ar_flip_flop == 0) {
2730 val = s->ar_index;
2731 } else {
2732 val = 0;
2733 }
2734 break;
2735 case 0x3c1:
2736 index = s->ar_index & 0x1f;
2737 if (index < 21)
2738 val = s->ar[index];
2739 else
2740 val = 0;
2741 break;
2742 case 0x3c2:
2743 val = s->st00;
2744 break;
2745 case 0x3c4:
2746 val = s->sr_index;
2747 break;
2748 case 0x3c5:
2749 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2750 break;
2751 val = s->sr[s->sr_index];
2752 #ifdef DEBUG_VGA_REG
2753 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2754 #endif
2755 break;
2756 case 0x3c6:
2757 cirrus_read_hidden_dac(s, &val);
2758 break;
2759 case 0x3c7:
2760 val = s->dac_state;
2761 break;
2762 case 0x3c8:
2763 val = s->dac_write_index;
2764 s->cirrus_hidden_dac_lockindex = 0;
2765 break;
2766 case 0x3c9:
2767 if (cirrus_hook_read_palette(s, &val))
2768 break;
2769 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2770 if (++s->dac_sub_index == 3) {
2771 s->dac_sub_index = 0;
2772 s->dac_read_index++;
2773 }
2774 break;
2775 case 0x3ca:
2776 val = s->fcr;
2777 break;
2778 case 0x3cc:
2779 val = s->msr;
2780 break;
2781 case 0x3ce:
2782 val = s->gr_index;
2783 break;
2784 case 0x3cf:
2785 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2786 break;
2787 val = s->gr[s->gr_index];
2788 #ifdef DEBUG_VGA_REG
2789 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2790 #endif
2791 break;
2792 case 0x3b4:
2793 case 0x3d4:
2794 val = s->cr_index;
2795 break;
2796 case 0x3b5:
2797 case 0x3d5:
2798 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2799 break;
2800 val = s->cr[s->cr_index];
2801 #ifdef DEBUG_VGA_REG
2802 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2803 #endif
2804 break;
2805 case 0x3ba:
2806 case 0x3da:
2807 /* just toggle to fool polling */
2808 val = s->st01 = s->retrace((VGAState *) s);
2809 s->ar_flip_flop = 0;
2810 break;
2811 default:
2812 val = 0x00;
2813 break;
2814 }
2815 }
2816 #if defined(DEBUG_VGA)
2817 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2818 #endif
2819 return val;
2820 }
2821
2822 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2823 {
2824 CirrusVGAState *s = opaque;
2825 int index;
2826
2827 /* check port range access depending on color/monochrome mode */
2828 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2829 || (addr >= 0x3d0 && addr <= 0x3df
2830 && !(s->msr & MSR_COLOR_EMULATION)))
2831 return;
2832
2833 #ifdef DEBUG_VGA
2834 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2835 #endif
2836
2837 switch (addr) {
2838 case 0x3c0:
2839 if (s->ar_flip_flop == 0) {
2840 val &= 0x3f;
2841 s->ar_index = val;
2842 } else {
2843 index = s->ar_index & 0x1f;
2844 switch (index) {
2845 case 0x00 ... 0x0f:
2846 s->ar[index] = val & 0x3f;
2847 break;
2848 case 0x10:
2849 s->ar[index] = val & ~0x10;
2850 break;
2851 case 0x11:
2852 s->ar[index] = val;
2853 break;
2854 case 0x12:
2855 s->ar[index] = val & ~0xc0;
2856 break;
2857 case 0x13:
2858 s->ar[index] = val & ~0xf0;
2859 break;
2860 case 0x14:
2861 s->ar[index] = val & ~0xf0;
2862 break;
2863 default:
2864 break;
2865 }
2866 }
2867 s->ar_flip_flop ^= 1;
2868 break;
2869 case 0x3c2:
2870 s->msr = val & ~0x10;
2871 s->update_retrace_info((VGAState *) s);
2872 break;
2873 case 0x3c4:
2874 s->sr_index = val;
2875 break;
2876 case 0x3c5:
2877 if (cirrus_hook_write_sr(s, s->sr_index, val))
2878 break;
2879 #ifdef DEBUG_VGA_REG
2880 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2881 #endif
2882 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2883 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2884 break;
2885 case 0x3c6:
2886 cirrus_write_hidden_dac(s, val);
2887 break;
2888 case 0x3c7:
2889 s->dac_read_index = val;
2890 s->dac_sub_index = 0;
2891 s->dac_state = 3;
2892 break;
2893 case 0x3c8:
2894 s->dac_write_index = val;
2895 s->dac_sub_index = 0;
2896 s->dac_state = 0;
2897 break;
2898 case 0x3c9:
2899 if (cirrus_hook_write_palette(s, val))
2900 break;
2901 s->dac_cache[s->dac_sub_index] = val;
2902 if (++s->dac_sub_index == 3) {
2903 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2904 s->dac_sub_index = 0;
2905 s->dac_write_index++;
2906 }
2907 break;
2908 case 0x3ce:
2909 s->gr_index = val;
2910 break;
2911 case 0x3cf:
2912 if (cirrus_hook_write_gr(s, s->gr_index, val))
2913 break;
2914 #ifdef DEBUG_VGA_REG
2915 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2916 #endif
2917 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2918 break;
2919 case 0x3b4:
2920 case 0x3d4:
2921 s->cr_index = val;
2922 break;
2923 case 0x3b5:
2924 case 0x3d5:
2925 if (cirrus_hook_write_cr(s, s->cr_index, val))
2926 break;
2927 #ifdef DEBUG_VGA_REG
2928 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2929 #endif
2930 /* handle CR0-7 protection */
2931 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2932 /* can always write bit 4 of CR7 */
2933 if (s->cr_index == 7)
2934 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2935 return;
2936 }
2937 switch (s->cr_index) {
2938 case 0x01: /* horizontal display end */
2939 case 0x07:
2940 case 0x09:
2941 case 0x0c:
2942 case 0x0d:
2943 case 0x12: /* vertical display end */
2944 s->cr[s->cr_index] = val;
2945 break;
2946
2947 default:
2948 s->cr[s->cr_index] = val;
2949 break;
2950 }
2951
2952 switch(s->cr_index) {
2953 case 0x00:
2954 case 0x04:
2955 case 0x05:
2956 case 0x06:
2957 case 0x07:
2958 case 0x11:
2959 case 0x17:
2960 s->update_retrace_info((VGAState *) s);
2961 break;
2962 }
2963 break;
2964 case 0x3ba:
2965 case 0x3da:
2966 s->fcr = val & 0x10;
2967 break;
2968 }
2969 }
2970
2971 /***************************************
2972 *
2973 * memory-mapped I/O access
2974 *
2975 ***************************************/
2976
2977 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2978 {
2979 CirrusVGAState *s = (CirrusVGAState *) opaque;
2980
2981 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2982
2983 if (addr >= 0x100) {
2984 return cirrus_mmio_blt_read(s, addr - 0x100);
2985 } else {
2986 return vga_ioport_read(s, addr + 0x3c0);
2987 }
2988 }
2989
2990 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2991 {
2992 uint32_t v;
2993 #ifdef TARGET_WORDS_BIGENDIAN
2994 v = cirrus_mmio_readb(opaque, addr) << 8;
2995 v |= cirrus_mmio_readb(opaque, addr + 1);
2996 #else
2997 v = cirrus_mmio_readb(opaque, addr);
2998 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2999 #endif
3000 return v;
3001 }
3002
3003 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
3004 {
3005 uint32_t v;
3006 #ifdef TARGET_WORDS_BIGENDIAN
3007 v = cirrus_mmio_readb(opaque, addr) << 24;
3008 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3009 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3010 v |= cirrus_mmio_readb(opaque, addr + 3);
3011 #else
3012 v = cirrus_mmio_readb(opaque, addr);
3013 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3014 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3015 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3016 #endif
3017 return v;
3018 }
3019
3020 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3021 uint32_t val)
3022 {
3023 CirrusVGAState *s = (CirrusVGAState *) opaque;
3024
3025 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3026
3027 if (addr >= 0x100) {
3028 cirrus_mmio_blt_write(s, addr - 0x100, val);
3029 } else {
3030 vga_ioport_write(s, addr + 0x3c0, val);
3031 }
3032 }
3033
3034 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3035 uint32_t val)
3036 {
3037 #ifdef TARGET_WORDS_BIGENDIAN
3038 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3039 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3040 #else
3041 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3042 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3043 #endif
3044 }
3045
3046 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3047 uint32_t val)
3048 {
3049 #ifdef TARGET_WORDS_BIGENDIAN
3050 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3051 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3052 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3053 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3054 #else
3055 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3056 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3057 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3058 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3059 #endif
3060 }
3061
3062
3063 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3064 cirrus_mmio_readb,
3065 cirrus_mmio_readw,
3066 cirrus_mmio_readl,
3067 };
3068
3069 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3070 cirrus_mmio_writeb,
3071 cirrus_mmio_writew,
3072 cirrus_mmio_writel,
3073 };
3074
3075 /* load/save state */
3076
3077 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3078 {
3079 CirrusVGAState *s = opaque;
3080
3081 if (s->pci_dev)
3082 pci_device_save(s->pci_dev, f);
3083
3084 qemu_put_be32s(f, &s->latch);
3085 qemu_put_8s(f, &s->sr_index);
3086 qemu_put_buffer(f, s->sr, 256);
3087 qemu_put_8s(f, &s->gr_index);
3088 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3089 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3090 qemu_put_buffer(f, s->gr + 2, 254);
3091 qemu_put_8s(f, &s->ar_index);
3092 qemu_put_buffer(f, s->ar, 21);
3093 qemu_put_be32(f, s->ar_flip_flop);
3094 qemu_put_8s(f, &s->cr_index);
3095 qemu_put_buffer(f, s->cr, 256);
3096 qemu_put_8s(f, &s->msr);
3097 qemu_put_8s(f, &s->fcr);
3098 qemu_put_8s(f, &s->st00);
3099 qemu_put_8s(f, &s->st01);
3100
3101 qemu_put_8s(f, &s->dac_state);
3102 qemu_put_8s(f, &s->dac_sub_index);
3103 qemu_put_8s(f, &s->dac_read_index);
3104 qemu_put_8s(f, &s->dac_write_index);
3105 qemu_put_buffer(f, s->dac_cache, 3);
3106 qemu_put_buffer(f, s->palette, 768);
3107
3108 qemu_put_be32(f, s->bank_offset);
3109
3110 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3111 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3112
3113 qemu_put_be32s(f, &s->hw_cursor_x);
3114 qemu_put_be32s(f, &s->hw_cursor_y);
3115 /* XXX: we do not save the bitblt state - we assume we do not save
3116 the state when the blitter is active */
3117 }
3118
3119 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3120 {
3121 CirrusVGAState *s = opaque;
3122 int ret;
3123
3124 if (version_id > 2)
3125 return -EINVAL;
3126
3127 if (s->pci_dev && version_id >= 2) {
3128 ret = pci_device_load(s->pci_dev, f);
3129 if (ret < 0)
3130 return ret;
3131 }
3132
3133 qemu_get_be32s(f, &s->latch);
3134 qemu_get_8s(f, &s->sr_index);
3135 qemu_get_buffer(f, s->sr, 256);
3136 qemu_get_8s(f, &s->gr_index);
3137 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3138 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3139 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3140 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3141 qemu_get_buffer(f, s->gr + 2, 254);
3142 qemu_get_8s(f, &s->ar_index);
3143 qemu_get_buffer(f, s->ar, 21);
3144 s->ar_flip_flop=qemu_get_be32(f);
3145 qemu_get_8s(f, &s->cr_index);
3146 qemu_get_buffer(f, s->cr, 256);
3147 qemu_get_8s(f, &s->msr);
3148 qemu_get_8s(f, &s->fcr);
3149 qemu_get_8s(f, &s->st00);
3150 qemu_get_8s(f, &s->st01);
3151
3152 qemu_get_8s(f, &s->dac_state);
3153 qemu_get_8s(f, &s->dac_sub_index);
3154 qemu_get_8s(f, &s->dac_read_index);
3155 qemu_get_8s(f, &s->dac_write_index);
3156 qemu_get_buffer(f, s->dac_cache, 3);
3157 qemu_get_buffer(f, s->palette, 768);
3158
3159 s->bank_offset=qemu_get_be32(f);
3160
3161 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3162 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3163
3164 qemu_get_be32s(f, &s->hw_cursor_x);
3165 qemu_get_be32s(f, &s->hw_cursor_y);
3166
3167 cirrus_update_memory_access(s);
3168 /* force refresh */
3169 s->graphic_mode = -1;
3170 cirrus_update_bank_ptr(s, 0);
3171 cirrus_update_bank_ptr(s, 1);
3172 return 0;
3173 }
3174
3175 /***************************************
3176 *
3177 * initialize
3178 *
3179 ***************************************/
3180
3181 static void cirrus_reset(void *opaque)
3182 {
3183 CirrusVGAState *s = opaque;
3184
3185 vga_reset(s);
3186 unmap_linear_vram(s);
3187 s->sr[0x06] = 0x0f;
3188 if (s->device_id == CIRRUS_ID_CLGD5446) {
3189 /* 4MB 64 bit memory config, always PCI */
3190 s->sr[0x1F] = 0x2d; // MemClock
3191 s->gr[0x18] = 0x0f; // fastest memory configuration
3192 s->sr[0x0f] = 0x98;
3193 s->sr[0x17] = 0x20;
3194 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3195 } else {
3196 s->sr[0x1F] = 0x22; // MemClock
3197 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3198 s->sr[0x17] = s->bustype;
3199 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3200 }
3201 s->cr[0x27] = s->device_id;
3202
3203 /* Win2K seems to assume that the pattern buffer is at 0xff
3204 initially ! */
3205 memset(s->vram_ptr, 0xff, s->real_vram_size);
3206
3207 s->cirrus_hidden_dac_lockindex = 5;
3208 s->cirrus_hidden_dac_data = 0;
3209 }
3210
3211 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3212 {
3213 int i;
3214 static int inited;
3215
3216 if (!inited) {
3217 inited = 1;
3218 for(i = 0;i < 256; i++)
3219 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3220 rop_to_index[CIRRUS_ROP_0] = 0;
3221 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3222 rop_to_index[CIRRUS_ROP_NOP] = 2;
3223 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3224 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3225 rop_to_index[CIRRUS_ROP_SRC] = 5;
3226 rop_to_index[CIRRUS_ROP_1] = 6;
3227 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3228 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3229 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3230 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3231 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3232 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3233 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3234 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3235 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3236 s->device_id = device_id;
3237 if (is_pci)
3238 s->bustype = CIRRUS_BUSTYPE_PCI;
3239 else
3240 s->bustype = CIRRUS_BUSTYPE_ISA;
3241 }
3242
3243 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3244
3245 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3246 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3247 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3248 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3249
3250 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3251
3252 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3253 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3254 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3255 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3256
3257 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3258 cirrus_vga_mem_write, s);
3259 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3260 s->vga_io_memory);
3261 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3262
3263 /* I/O handler for LFB */
3264 s->cirrus_linear_io_addr =
3265 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, s);
3266 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3267
3268 /* I/O handler for LFB */
3269 s->cirrus_linear_bitblt_io_addr =
3270 cpu_register_io_memory(0, cirrus_linear_bitblt_read,
3271 cirrus_linear_bitblt_write, s);
3272
3273 /* I/O handler for memory-mapped I/O */
3274 s->cirrus_mmio_io_addr =
3275 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3276
3277 s->real_vram_size =
3278 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3279
3280 /* XXX: s->vram_size must be a power of two */
3281 s->cirrus_addr_mask = s->real_vram_size - 1;
3282 s->linear_mmio_mask = s->real_vram_size - 256;
3283
3284 s->get_bpp = cirrus_get_bpp;
3285 s->get_offsets = cirrus_get_offsets;
3286 s->get_resolution = cirrus_get_resolution;
3287 s->cursor_invalidate = cirrus_cursor_invalidate;
3288 s->cursor_draw_line = cirrus_cursor_draw_line;
3289
3290 qemu_register_reset(cirrus_reset, s);
3291 cirrus_reset(s);
3292 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3293 }
3294
3295 /***************************************
3296 *
3297 * ISA bus support
3298 *
3299 ***************************************/
3300
3301 void isa_cirrus_vga_init(uint8_t *vga_ram_base,
3302 ram_addr_t vga_ram_offset, int vga_ram_size)
3303 {
3304 CirrusVGAState *s;
3305
3306 s = qemu_mallocz(sizeof(CirrusVGAState));
3307
3308 vga_common_init((VGAState *)s,
3309 vga_ram_base, vga_ram_offset, vga_ram_size);
3310 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3311 s->ds = graphic_console_init(s->update, s->invalidate,
3312 s->screen_dump, s->text_update, s);
3313 /* XXX ISA-LFB support */
3314 }
3315
3316 /***************************************
3317 *
3318 * PCI bus support
3319 *
3320 ***************************************/
3321
3322 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3323 uint32_t addr, uint32_t size, int type)
3324 {
3325 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3326
3327 vga_dirty_log_stop((VGAState *)s);
3328
3329 /* XXX: add byte swapping apertures */
3330 cpu_register_physical_memory(addr, s->vram_size,
3331 s->cirrus_linear_io_addr);
3332 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3333 s->cirrus_linear_bitblt_io_addr);
3334
3335 s->map_addr = s->map_end = 0;
3336 s->lfb_addr = addr & TARGET_PAGE_MASK;
3337 s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3338 /* account for overflow */
3339 if (s->lfb_end < addr + VGA_RAM_SIZE)
3340 s->lfb_end = addr + VGA_RAM_SIZE;
3341
3342 vga_dirty_log_start((VGAState *)s);
3343 }
3344
3345 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3346 uint32_t addr, uint32_t size, int type)
3347 {
3348 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3349
3350 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3351 s->cirrus_mmio_io_addr);
3352 }
3353
3354 static void pci_cirrus_write_config(PCIDevice *d,
3355 uint32_t address, uint32_t val, int len)
3356 {
3357 PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3358 CirrusVGAState *s = &pvs->cirrus_vga;
3359
3360 vga_dirty_log_stop((VGAState *)s);
3361
3362 pci_default_write_config(d, address, val, len);
3363 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
3364 s->map_addr = 0;
3365 cirrus_update_memory_access(s);
3366
3367 vga_dirty_log_start((VGAState *)s);
3368 }
3369
3370 void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
3371 ram_addr_t vga_ram_offset, int vga_ram_size)
3372 {
3373 PCICirrusVGAState *d;
3374 uint8_t *pci_conf;
3375 CirrusVGAState *s;
3376 int device_id;
3377
3378 device_id = CIRRUS_ID_CLGD5446;
3379
3380 /* setup PCI configuration registers */
3381 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3382 sizeof(PCICirrusVGAState),
3383 -1, NULL, pci_cirrus_write_config);
3384 pci_conf = d->dev.config;
3385 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3386 pci_config_set_device_id(pci_conf, device_id);
3387 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3388 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3389 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3390
3391 /* setup VGA */
3392 s = &d->cirrus_vga;
3393 vga_common_init((VGAState *)s,
3394 vga_ram_base, vga_ram_offset, vga_ram_size);
3395 cirrus_init_common(s, device_id, 1);
3396
3397 s->ds = graphic_console_init(s->update, s->invalidate,
3398 s->screen_dump, s->text_update, s);
3399
3400 s->pci_dev = (PCIDevice *)d;
3401
3402 /* setup memory space */
3403 /* memory #0 LFB */
3404 /* memory #1 memory-mapped I/O */
3405 /* XXX: s->vram_size must be a power of two */
3406 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3407 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3408 if (device_id == CIRRUS_ID_CLGD5446) {
3409 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3410 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3411 }
3412 /* XXX: ROM BIOS */
3413 }
Patches shipped by Fedora