gdbstub.c

   1 /*
   2  * gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include "config.h"
  21 #include "qemu-common.h"
  22 #ifdef CONFIG_USER_ONLY
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <stdarg.h>
  26 #include <string.h>
  27 #include <errno.h>
  28 #include <unistd.h>
  29 #include <fcntl.h>
  30
  31 #include "qemu.h"
  32 #else
  33 #include "monitor.h"
  34 #include "qemu-char.h"
  35 #include "sysemu.h"
  36 #include "gdbstub.h"
  37 #endif
  38 #include "qemu-kvm.h"
  39
  40 #define MAX_PACKET_LENGTH 4096
  41
  42 #include "qemu_socket.h"
  43 #include "kvm.h"
  44
  45
  46 enum {
  47     GDB_SIGNAL_0 = 0,
  48     GDB_SIGNAL_INT = 2,
  49     GDB_SIGNAL_TRAP = 5,
  50     GDB_SIGNAL_UNKNOWN = 143
  51 };
  52
  53 #ifdef CONFIG_USER_ONLY
  54
  55 /* Map target signal numbers to GDB protocol signal numbers and vice
  56  * versa.  For user emulation's currently supported systems, we can
  57  * assume most signals are defined.
  58  */
  59
  60 static int gdb_signal_table[] = {
  61     0,
  62     TARGET_SIGHUP,
  63     TARGET_SIGINT,
  64     TARGET_SIGQUIT,
  65     TARGET_SIGILL,
  66     TARGET_SIGTRAP,
  67     TARGET_SIGABRT,
  68     -1, /* SIGEMT */
  69     TARGET_SIGFPE,
  70     TARGET_SIGKILL,
  71     TARGET_SIGBUS,
  72     TARGET_SIGSEGV,
  73     TARGET_SIGSYS,
  74     TARGET_SIGPIPE,
  75     TARGET_SIGALRM,
  76     TARGET_SIGTERM,
  77     TARGET_SIGURG,
  78     TARGET_SIGSTOP,
  79     TARGET_SIGTSTP,
  80     TARGET_SIGCONT,
  81     TARGET_SIGCHLD,
  82     TARGET_SIGTTIN,
  83     TARGET_SIGTTOU,
  84     TARGET_SIGIO,
  85     TARGET_SIGXCPU,
  86     TARGET_SIGXFSZ,
  87     TARGET_SIGVTALRM,
  88     TARGET_SIGPROF,
  89     TARGET_SIGWINCH,
  90     -1, /* SIGLOST */
  91     TARGET_SIGUSR1,
  92     TARGET_SIGUSR2,
  93 #ifdef TARGET_SIGPWR
  94     TARGET_SIGPWR,
  95 #else
  96     -1,
  97 #endif
  98     -1, /* SIGPOLL */
  99     -1,
 100     -1,
 101     -1,
 102     -1,
 103     -1,
 104     -1,
 105     -1,
 106     -1,
 107     -1,
 108     -1,
 109     -1,
 110 #ifdef __SIGRTMIN
 111     __SIGRTMIN + 1,
 112     __SIGRTMIN + 2,
 113     __SIGRTMIN + 3,
 114     __SIGRTMIN + 4,
 115     __SIGRTMIN + 5,
 116     __SIGRTMIN + 6,
 117     __SIGRTMIN + 7,
 118     __SIGRTMIN + 8,
 119     __SIGRTMIN + 9,
 120     __SIGRTMIN + 10,
 121     __SIGRTMIN + 11,
 122     __SIGRTMIN + 12,
 123     __SIGRTMIN + 13,
 124     __SIGRTMIN + 14,
 125     __SIGRTMIN + 15,
 126     __SIGRTMIN + 16,
 127     __SIGRTMIN + 17,
 128     __SIGRTMIN + 18,
 129     __SIGRTMIN + 19,
 130     __SIGRTMIN + 20,
 131     __SIGRTMIN + 21,
 132     __SIGRTMIN + 22,
 133     __SIGRTMIN + 23,
 134     __SIGRTMIN + 24,
 135     __SIGRTMIN + 25,
 136     __SIGRTMIN + 26,
 137     __SIGRTMIN + 27,
 138     __SIGRTMIN + 28,
 139     __SIGRTMIN + 29,
 140     __SIGRTMIN + 30,
 141     __SIGRTMIN + 31,
 142     -1, /* SIGCANCEL */
 143     __SIGRTMIN,
 144     __SIGRTMIN + 32,
 145     __SIGRTMIN + 33,
 146     __SIGRTMIN + 34,
 147     __SIGRTMIN + 35,
 148     __SIGRTMIN + 36,
 149     __SIGRTMIN + 37,
 150     __SIGRTMIN + 38,
 151     __SIGRTMIN + 39,
 152     __SIGRTMIN + 40,
 153     __SIGRTMIN + 41,
 154     __SIGRTMIN + 42,
 155     __SIGRTMIN + 43,
 156     __SIGRTMIN + 44,
 157     __SIGRTMIN + 45,
 158     __SIGRTMIN + 46,
 159     __SIGRTMIN + 47,
 160     __SIGRTMIN + 48,
 161     __SIGRTMIN + 49,
 162     __SIGRTMIN + 50,
 163     __SIGRTMIN + 51,
 164     __SIGRTMIN + 52,
 165     __SIGRTMIN + 53,
 166     __SIGRTMIN + 54,
 167     __SIGRTMIN + 55,
 168     __SIGRTMIN + 56,
 169     __SIGRTMIN + 57,
 170     __SIGRTMIN + 58,
 171     __SIGRTMIN + 59,
 172     __SIGRTMIN + 60,
 173     __SIGRTMIN + 61,
 174     __SIGRTMIN + 62,
 175     __SIGRTMIN + 63,
 176     __SIGRTMIN + 64,
 177     __SIGRTMIN + 65,
 178     __SIGRTMIN + 66,
 179     __SIGRTMIN + 67,
 180     __SIGRTMIN + 68,
 181     __SIGRTMIN + 69,
 182     __SIGRTMIN + 70,
 183     __SIGRTMIN + 71,
 184     __SIGRTMIN + 72,
 185     __SIGRTMIN + 73,
 186     __SIGRTMIN + 74,
 187     __SIGRTMIN + 75,
 188     __SIGRTMIN + 76,
 189     __SIGRTMIN + 77,
 190     __SIGRTMIN + 78,
 191     __SIGRTMIN + 79,
 192     __SIGRTMIN + 80,
 193     __SIGRTMIN + 81,
 194     __SIGRTMIN + 82,
 195     __SIGRTMIN + 83,
 196     __SIGRTMIN + 84,
 197     __SIGRTMIN + 85,
 198     __SIGRTMIN + 86,
 199     __SIGRTMIN + 87,
 200     __SIGRTMIN + 88,
 201     __SIGRTMIN + 89,
 202     __SIGRTMIN + 90,
 203     __SIGRTMIN + 91,
 204     __SIGRTMIN + 92,
 205     __SIGRTMIN + 93,
 206     __SIGRTMIN + 94,
 207     __SIGRTMIN + 95,
 208     -1, /* SIGINFO */
 209     -1, /* UNKNOWN */
 210     -1, /* DEFAULT */
 211     -1,
 212     -1,
 213     -1,
 214     -1,
 215     -1,
 216     -1
 217 #endif
 218 };
 219 #else
 220 /* In system mode we only need SIGINT and SIGTRAP; other signals
 221    are not yet supported.  */
 222
 223 enum {
 224     TARGET_SIGINT = 2,
 225     TARGET_SIGTRAP = 5
 226 };
 227
 228 static int gdb_signal_table[] = {
 229     -1,
 230     -1,
 231     TARGET_SIGINT,
 232     -1,
 233     -1,
 234     TARGET_SIGTRAP
 235 };
 236 #endif
 237
 238 #ifdef CONFIG_USER_ONLY
 239 static int target_signal_to_gdb (int sig)
 240 {
 241     int i;
 242     for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
 243         if (gdb_signal_table[i] == sig)
 244             return i;
 245     return GDB_SIGNAL_UNKNOWN;
 246 }
 247 #endif
 248
 249 static int gdb_signal_to_target (int sig)
 250 {
 251     if (sig < ARRAY_SIZE (gdb_signal_table))
 252         return gdb_signal_table[sig];
 253     else
 254         return -1;
 255 }
 256
 257 //#define DEBUG_GDB
 258
 259 typedef struct GDBRegisterState {
 260     int base_reg;
 261     int num_regs;
 262     gdb_reg_cb get_reg;
 263     gdb_reg_cb set_reg;
 264     const char *xml;
 265     struct GDBRegisterState *next;
 266 } GDBRegisterState;
 267
 268 enum RSState {
 269     RS_INACTIVE,
 270     RS_IDLE,
 271     RS_GETLINE,
 272     RS_CHKSUM1,
 273     RS_CHKSUM2,
 274     RS_SYSCALL,
 275 };
 276 typedef struct GDBState {
 277     CPUState *c_cpu; /* current CPU for step/continue ops */
 278     CPUState *g_cpu; /* current CPU for other ops */
 279     CPUState *query_cpu; /* for q{f|s}ThreadInfo */
 280     enum RSState state; /* parsing state */
 281     char line_buf[MAX_PACKET_LENGTH];
 282     int line_buf_index;
 283     int line_csum;
 284     uint8_t last_packet[MAX_PACKET_LENGTH + 4];
 285     int last_packet_len;
 286     int signal;
 287 #ifdef CONFIG_USER_ONLY
 288     int fd;
 289     int running_state;
 290 #else
 291     CharDriverState *chr;
 292     CharDriverState *mon_chr;
 293 #endif
 294 } GDBState;
 295
 296 /* By default use no IRQs and no timers while single stepping so as to
 297  * make single stepping like an ICE HW step.
 298  */
 299 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
 300
 301 static GDBState *gdbserver_state;
 302
 303 /* This is an ugly hack to cope with both new and old gdb.
 304    If gdb sends qXfer:features:read then assume we're talking to a newish
 305    gdb that understands target descriptions.  */
 306 static int gdb_has_xml;
 307
 308 #ifdef CONFIG_USER_ONLY
 309 /* XXX: This is not thread safe.  Do we care?  */
 310 static int gdbserver_fd = -1;
 311
 312 static int get_char(GDBState *s)
 313 {
 314     uint8_t ch;
 315     int ret;
 316
 317     for(;;) {
 318         ret = recv(s->fd, &ch, 1, 0);
 319         if (ret < 0) {
 320             if (errno == ECONNRESET)
 321                 s->fd = -1;
 322             if (errno != EINTR && errno != EAGAIN)
 323                 return -1;
 324         } else if (ret == 0) {
 325             close(s->fd);
 326             s->fd = -1;
 327             return -1;
 328         } else {
 329             break;
 330         }
 331     }
 332     return ch;
 333 }
 334 #endif
 335
 336 static gdb_syscall_complete_cb gdb_current_syscall_cb;
 337
 338 static enum {
 339     GDB_SYS_UNKNOWN,
 340     GDB_SYS_ENABLED,
 341     GDB_SYS_DISABLED,
 342 } gdb_syscall_mode;
 343
 344 /* If gdb is connected when the first semihosting syscall occurs then use
 345    remote gdb syscalls.  Otherwise use native file IO.  */
 346 int use_gdb_syscalls(void)
 347 {
 348     if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
 349         gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
 350                                             : GDB_SYS_DISABLED);
 351     }
 352     return gdb_syscall_mode == GDB_SYS_ENABLED;
 353 }
 354
 355 /* Resume execution.  */
 356 static inline void gdb_continue(GDBState *s)
 357 {
 358 #ifdef CONFIG_USER_ONLY
 359     s->running_state = 1;
 360 #else
 361     vm_start();
 362 #endif
 363 }
 364
 365 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
 366 {
 367 #ifdef CONFIG_USER_ONLY
 368     int ret;
 369
 370     while (len > 0) {
 371         ret = send(s->fd, buf, len, 0);
 372         if (ret < 0) {
 373             if (errno != EINTR && errno != EAGAIN)
 374                 return;
 375         } else {
 376             buf += ret;
 377             len -= ret;
 378         }
 379     }
 380 #else
 381     qemu_chr_write(s->chr, buf, len);
 382 #endif
 383 }
 384
 385 static inline int fromhex(int v)
 386 {
 387     if (v >= '0' && v <= '9')
 388         return v - '0';
 389     else if (v >= 'A' && v <= 'F')
 390         return v - 'A' + 10;
 391     else if (v >= 'a' && v <= 'f')
 392         return v - 'a' + 10;
 393     else
 394         return 0;
 395 }
 396
 397 static inline int tohex(int v)
 398 {
 399     if (v < 10)
 400         return v + '0';
 401     else
 402         return v - 10 + 'a';
 403 }
 404
 405 static void memtohex(char *buf, const uint8_t *mem, int len)
 406 {
 407     int i, c;
 408     char *q;
 409     q = buf;
 410     for(i = 0; i < len; i++) {
 411         c = mem[i];
 412         *q++ = tohex(c >> 4);
 413         *q++ = tohex(c & 0xf);
 414     }
 415     *q = '\0';
 416 }
 417
 418 static void hextomem(uint8_t *mem, const char *buf, int len)
 419 {
 420     int i;
 421
 422     for(i = 0; i < len; i++) {
 423         mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
 424         buf += 2;
 425     }
 426 }
 427
 428 /* return -1 if error, 0 if OK */
 429 static int put_packet_binary(GDBState *s, const char *buf, int len)
 430 {
 431     int csum, i;
 432     uint8_t *p;
 433
 434     for(;;) {
 435         p = s->last_packet;
 436         *(p++) = '$';
 437         memcpy(p, buf, len);
 438         p += len;
 439         csum = 0;
 440         for(i = 0; i < len; i++) {
 441             csum += buf[i];
 442         }
 443         *(p++) = '#';
 444         *(p++) = tohex((csum >> 4) & 0xf);
 445         *(p++) = tohex((csum) & 0xf);
 446
 447         s->last_packet_len = p - s->last_packet;
 448         put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
 449
 450 #ifdef CONFIG_USER_ONLY
 451         i = get_char(s);
 452         if (i < 0)
 453             return -1;
 454         if (i == '+')
 455             break;
 456 #else
 457         break;
 458 #endif
 459     }
 460     return 0;
 461 }
 462
 463 /* return -1 if error, 0 if OK */
 464 static int put_packet(GDBState *s, const char *buf)
 465 {
 466 #ifdef DEBUG_GDB
 467     printf("reply='%s'\n", buf);
 468 #endif
 469
 470     return put_packet_binary(s, buf, strlen(buf));
 471 }
 472
 473 /* The GDB remote protocol transfers values in target byte order.  This means
 474    we can use the raw memory access routines to access the value buffer.
 475    Conveniently, these also handle the case where the buffer is mis-aligned.
 476  */
 477 #define GET_REG8(val) do { \
 478     stb_p(mem_buf, val); \
 479     return 1; \
 480     } while(0)
 481 #define GET_REG16(val) do { \
 482     stw_p(mem_buf, val); \
 483     return 2; \
 484     } while(0)
 485 #define GET_REG32(val) do { \
 486     stl_p(mem_buf, val); \
 487     return 4; \
 488     } while(0)
 489 #define GET_REG64(val) do { \
 490     stq_p(mem_buf, val); \
 491     return 8; \
 492     } while(0)
 493
 494 #if TARGET_LONG_BITS == 64
 495 #define GET_REGL(val) GET_REG64(val)
 496 #define ldtul_p(addr) ldq_p(addr)
 497 #else
 498 #define GET_REGL(val) GET_REG32(val)
 499 #define ldtul_p(addr) ldl_p(addr)
 500 #endif
 501
 502 #if defined(TARGET_I386)
 503
 504 #ifdef TARGET_X86_64
 505 static const int gpr_map[16] = {
 506     R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
 507     8, 9, 10, 11, 12, 13, 14, 15
 508 };
 509 #else
 510 static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7};
 511 #endif
 512
 513 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
 514
 515 #define IDX_IP_REG      CPU_NB_REGS
 516 #define IDX_FLAGS_REG   (IDX_IP_REG + 1)
 517 #define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
 518 #define IDX_FP_REGS     (IDX_SEG_REGS + 6)
 519 #define IDX_XMM_REGS    (IDX_FP_REGS + 16)
 520 #define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)
 521
 522 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 523 {
 524     if (n < CPU_NB_REGS) {
 525         GET_REGL(env->regs[gpr_map[n]]);
 526     } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
 527 #ifdef USE_X86LDOUBLE
 528         /* FIXME: byteswap float values - after fixing fpregs layout. */
 529         memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
 530 #else
 531         memset(mem_buf, 0, 10);
 532 #endif
 533         return 10;
 534     } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
 535         n -= IDX_XMM_REGS;
 536         stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
 537         stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
 538         return 16;
 539     } else {
 540         switch (n) {
 541         case IDX_IP_REG:    GET_REGL(env->eip);
 542         case IDX_FLAGS_REG: GET_REG32(env->eflags);
 543
 544         case IDX_SEG_REGS:     GET_REG32(env->segs[R_CS].selector);
 545         case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
 546         case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
 547         case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
 548         case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
 549         case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
 550
 551         case IDX_FP_REGS + 8:  GET_REG32(env->fpuc);
 552         case IDX_FP_REGS + 9:  GET_REG32((env->fpus & ~0x3800) |
 553                                          (env->fpstt & 0x7) << 11);
 554         case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
 555         case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
 556         case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
 557         case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
 558         case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
 559         case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
 560
 561         case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
 562         }
 563     }
 564     return 0;
 565 }
 566
 567 static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
 568 {
 569     uint16_t selector = ldl_p(mem_buf);
 570
 571     if (selector != env->segs[sreg].selector) {
 572 #if defined(CONFIG_USER_ONLY)
 573         cpu_x86_load_seg(env, sreg, selector);
 574 #else
 575         unsigned int limit, flags;
 576         target_ulong base;
 577
 578         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 579             base = selector << 4;
 580             limit = 0xffff;
 581             flags = 0;
 582         } else {
 583             if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
 584                 return 4;
 585         }
 586         cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
 587 #endif
 588     }
 589     return 4;
 590 }
 591
 592 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 593 {
 594     uint32_t tmp;
 595
 596     if (n < CPU_NB_REGS) {
 597         env->regs[gpr_map[n]] = ldtul_p(mem_buf);
 598         return sizeof(target_ulong);
 599     } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
 600 #ifdef USE_X86LDOUBLE
 601         /* FIXME: byteswap float values - after fixing fpregs layout. */
 602         memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
 603 #endif
 604         return 10;
 605     } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
 606         n -= IDX_XMM_REGS;
 607         env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
 608         env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
 609         return 16;
 610     } else {
 611         switch (n) {
 612         case IDX_IP_REG:
 613             env->eip = ldtul_p(mem_buf);
 614             return sizeof(target_ulong);
 615         case IDX_FLAGS_REG:
 616             env->eflags = ldl_p(mem_buf);
 617             return 4;
 618
 619         case IDX_SEG_REGS:     return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
 620         case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
 621         case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
 622         case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
 623         case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
 624         case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
 625
 626         case IDX_FP_REGS + 8:
 627             env->fpuc = ldl_p(mem_buf);
 628             return 4;
 629         case IDX_FP_REGS + 9:
 630             tmp = ldl_p(mem_buf);
 631             env->fpstt = (tmp >> 11) & 7;
 632             env->fpus = tmp & ~0x3800;
 633             return 4;
 634         case IDX_FP_REGS + 10: /* ftag */  return 4;
 635         case IDX_FP_REGS + 11: /* fiseg */ return 4;
 636         case IDX_FP_REGS + 12: /* fioff */ return 4;
 637         case IDX_FP_REGS + 13: /* foseg */ return 4;
 638         case IDX_FP_REGS + 14: /* fooff */ return 4;
 639         case IDX_FP_REGS + 15: /* fop */   return 4;
 640
 641         case IDX_MXCSR_REG:
 642             env->mxcsr = ldl_p(mem_buf);
 643             return 4;
 644         }
 645     }
 646     /* Unrecognised register.  */
 647     return 0;
 648 }
 649
 650 #elif defined (TARGET_PPC)
 651
 652 /* Old gdb always expects FP registers.  Newer (xml-aware) gdb only
 653    expects whatever the target description contains.  Due to a
 654    historical mishap the FP registers appear in between core integer
 655    regs and PC, MSR, CR, and so forth.  We hack round this by giving the
 656    FP regs zero size when talking to a newer gdb.  */
 657 #define NUM_CORE_REGS 71
 658 #if defined (TARGET_PPC64)
 659 #define GDB_CORE_XML "power64-core.xml"
 660 #else
 661 #define GDB_CORE_XML "power-core.xml"
 662 #endif
 663
 664 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 665 {
 666     if (n < 32) {
 667         /* gprs */
 668         GET_REGL(env->gpr[n]);
 669     } else if (n < 64) {
 670         /* fprs */
 671         if (gdb_has_xml)
 672             return 0;
 673         stfq_p(mem_buf, env->fpr[n-32]);
 674         return 8;
 675     } else {
 676         switch (n) {
 677         case 64: GET_REGL(env->nip);
 678         case 65: GET_REGL(env->msr);
 679         case 66:
 680             {
 681                 uint32_t cr = 0;
 682                 int i;
 683                 for (i = 0; i < 8; i++)
 684                     cr |= env->crf[i] << (32 - ((i + 1) * 4));
 685                 GET_REG32(cr);
 686             }
 687         case 67: GET_REGL(env->lr);
 688         case 68: GET_REGL(env->ctr);
 689         case 69: GET_REGL(env->xer);
 690         case 70:
 691             {
 692                 if (gdb_has_xml)
 693                     return 0;
 694                 GET_REG32(0); /* fpscr */
 695             }
 696         }
 697     }
 698     return 0;
 699 }
 700
 701 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 702 {
 703     if (n < 32) {
 704         /* gprs */
 705         env->gpr[n] = ldtul_p(mem_buf);
 706         return sizeof(target_ulong);
 707     } else if (n < 64) {
 708         /* fprs */
 709         if (gdb_has_xml)
 710             return 0;
 711         env->fpr[n-32] = ldfq_p(mem_buf);
 712         return 8;
 713     } else {
 714         switch (n) {
 715         case 64:
 716             env->nip = ldtul_p(mem_buf);
 717             return sizeof(target_ulong);
 718         case 65:
 719             ppc_store_msr(env, ldtul_p(mem_buf));
 720             return sizeof(target_ulong);
 721         case 66:
 722             {
 723                 uint32_t cr = ldl_p(mem_buf);
 724                 int i;
 725                 for (i = 0; i < 8; i++)
 726                     env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
 727                 return 4;
 728             }
 729         case 67:
 730             env->lr = ldtul_p(mem_buf);
 731             return sizeof(target_ulong);
 732         case 68:
 733             env->ctr = ldtul_p(mem_buf);
 734             return sizeof(target_ulong);
 735         case 69:
 736             env->xer = ldtul_p(mem_buf);
 737             return sizeof(target_ulong);
 738         case 70:
 739             /* fpscr */
 740             if (gdb_has_xml)
 741                 return 0;
 742             return 4;
 743         }
 744     }
 745     return 0;
 746 }
 747
 748 #elif defined (TARGET_SPARC)
 749
 750 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
 751 #define NUM_CORE_REGS 86
 752 #else
 753 #define NUM_CORE_REGS 72
 754 #endif
 755
 756 #ifdef TARGET_ABI32
 757 #define GET_REGA(val) GET_REG32(val)
 758 #else
 759 #define GET_REGA(val) GET_REGL(val)
 760 #endif
 761
 762 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 763 {
 764     if (n < 8) {
 765         /* g0..g7 */
 766         GET_REGA(env->gregs[n]);
 767     }
 768     if (n < 32) {
 769         /* register window */
 770         GET_REGA(env->regwptr[n - 8]);
 771     }
 772 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 773     if (n < 64) {
 774         /* fprs */
 775         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 776     }
 777     /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 778     switch (n) {
 779     case 64: GET_REGA(env->y);
 780     case 65: GET_REGA(GET_PSR(env));
 781     case 66: GET_REGA(env->wim);
 782     case 67: GET_REGA(env->tbr);
 783     case 68: GET_REGA(env->pc);
 784     case 69: GET_REGA(env->npc);
 785     case 70: GET_REGA(env->fsr);
 786     case 71: GET_REGA(0); /* csr */
 787     default: GET_REGA(0);
 788     }
 789 #else
 790     if (n < 64) {
 791         /* f0-f31 */
 792         GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
 793     }
 794     if (n < 80) {
 795         /* f32-f62 (double width, even numbers only) */
 796         uint64_t val;
 797
 798         val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
 799         val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
 800         GET_REG64(val);
 801     }
 802     switch (n) {
 803     case 80: GET_REGL(env->pc);
 804     case 81: GET_REGL(env->npc);
 805     case 82: GET_REGL(((uint64_t)GET_CCR(env) << 32) |
 806                            ((env->asi & 0xff) << 24) |
 807                            ((env->pstate & 0xfff) << 8) |
 808                            GET_CWP64(env));
 809     case 83: GET_REGL(env->fsr);
 810     case 84: GET_REGL(env->fprs);
 811     case 85: GET_REGL(env->y);
 812     }
 813 #endif
 814     return 0;
 815 }
 816
 817 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 818 {
 819 #if defined(TARGET_ABI32)
 820     abi_ulong tmp;
 821
 822     tmp = ldl_p(mem_buf);
 823 #else
 824     target_ulong tmp;
 825
 826     tmp = ldtul_p(mem_buf);
 827 #endif
 828
 829     if (n < 8) {
 830         /* g0..g7 */
 831         env->gregs[n] = tmp;
 832     } else if (n < 32) {
 833         /* register window */
 834         env->regwptr[n - 8] = tmp;
 835     }
 836 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
 837     else if (n < 64) {
 838         /* fprs */
 839         *((uint32_t *)&env->fpr[n - 32]) = tmp;
 840     } else {
 841         /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
 842         switch (n) {
 843         case 64: env->y = tmp; break;
 844         case 65: PUT_PSR(env, tmp); break;
 845         case 66: env->wim = tmp; break;
 846         case 67: env->tbr = tmp; break;
 847         case 68: env->pc = tmp; break;
 848         case 69: env->npc = tmp; break;
 849         case 70: env->fsr = tmp; break;
 850         default: return 0;
 851         }
 852     }
 853     return 4;
 854 #else
 855     else if (n < 64) {
 856         /* f0-f31 */
 857         env->fpr[n] = ldfl_p(mem_buf);
 858         return 4;
 859     } else if (n < 80) {
 860         /* f32-f62 (double width, even numbers only) */
 861         *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
 862         *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
 863     } else {
 864         switch (n) {
 865         case 80: env->pc = tmp; break;
 866         case 81: env->npc = tmp; break;
 867         case 82:
 868             PUT_CCR(env, tmp >> 32);
 869             env->asi = (tmp >> 24) & 0xff;
 870             env->pstate = (tmp >> 8) & 0xfff;
 871             PUT_CWP64(env, tmp & 0xff);
 872             break;
 873         case 83: env->fsr = tmp; break;
 874         case 84: env->fprs = tmp; break;
 875         case 85: env->y = tmp; break;
 876         default: return 0;
 877         }
 878     }
 879     return 8;
 880 #endif
 881 }
 882 #elif defined (TARGET_ARM)
 883
 884 /* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
 885    whatever the target description contains.  Due to a historical mishap
 886    the FPA registers appear in between core integer regs and the CPSR.
 887    We hack round this by giving the FPA regs zero size when talking to a
 888    newer gdb.  */
 889 #define NUM_CORE_REGS 26
 890 #define GDB_CORE_XML "arm-core.xml"
 891
 892 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 893 {
 894     if (n < 16) {
 895         /* Core integer register.  */
 896         GET_REG32(env->regs[n]);
 897     }
 898     if (n < 24) {
 899         /* FPA registers.  */
 900         if (gdb_has_xml)
 901             return 0;
 902         memset(mem_buf, 0, 12);
 903         return 12;
 904     }
 905     switch (n) {
 906     case 24:
 907         /* FPA status register.  */
 908         if (gdb_has_xml)
 909             return 0;
 910         GET_REG32(0);
 911     case 25:
 912         /* CPSR */
 913         GET_REG32(cpsr_read(env));
 914     }
 915     /* Unknown register.  */
 916     return 0;
 917 }
 918
 919 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 920 {
 921     uint32_t tmp;
 922
 923     tmp = ldl_p(mem_buf);
 924
 925     /* Mask out low bit of PC to workaround gdb bugs.  This will probably
 926        cause problems if we ever implement the Jazelle DBX extensions.  */
 927     if (n == 15)
 928         tmp &= ~1;
 929
 930     if (n < 16) {
 931         /* Core integer register.  */
 932         env->regs[n] = tmp;
 933         return 4;
 934     }
 935     if (n < 24) { /* 16-23 */
 936         /* FPA registers (ignored).  */
 937         if (gdb_has_xml)
 938             return 0;
 939         return 12;
 940     }
 941     switch (n) {
 942     case 24:
 943         /* FPA status register (ignored).  */
 944         if (gdb_has_xml)
 945             return 0;
 946         return 4;
 947     case 25:
 948         /* CPSR */
 949         cpsr_write (env, tmp, 0xffffffff);
 950         return 4;
 951     }
 952     /* Unknown register.  */
 953     return 0;
 954 }
 955
 956 #elif defined (TARGET_M68K)
 957
 958 #define NUM_CORE_REGS 18
 959
 960 #define GDB_CORE_XML "cf-core.xml"
 961
 962 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
 963 {
 964     if (n < 8) {
 965         /* D0-D7 */
 966         GET_REG32(env->dregs[n]);
 967     } else if (n < 16) {
 968         /* A0-A7 */
 969         GET_REG32(env->aregs[n - 8]);
 970     } else {
 971         switch (n) {
 972         case 16: GET_REG32(env->sr);
 973         case 17: GET_REG32(env->pc);
 974         }
 975     }
 976     /* FP registers not included here because they vary between
 977        ColdFire and m68k.  Use XML bits for these.  */
 978     return 0;
 979 }
 980
 981 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
 982 {
 983     uint32_t tmp;
 984
 985     tmp = ldl_p(mem_buf);
 986
 987     if (n < 8) {
 988         /* D0-D7 */
 989         env->dregs[n] = tmp;
 990     } else if (n < 8) {
 991         /* A0-A7 */
 992         env->aregs[n - 8] = tmp;
 993     } else {
 994         switch (n) {
 995         case 16: env->sr = tmp; break;
 996         case 17: env->pc = tmp; break;
 997         default: return 0;
 998         }
 999     }
1000     return 4;
1001 }
1002 #elif defined (TARGET_MIPS)
1003
1004 #define NUM_CORE_REGS 73
1005
1006 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1007 {
1008     if (n < 32) {
1009         GET_REGL(env->active_tc.gpr[n]);
1010     }
1011     if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1012         if (n >= 38 && n < 70) {
1013             if (env->CP0_Status & (1 << CP0St_FR))
1014                 GET_REGL(env->active_fpu.fpr[n - 38].d);
1015             else
1016                 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1017         }
1018         switch (n) {
1019         case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1020         case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1021         }
1022     }
1023     switch (n) {
1024     case 32: GET_REGL((int32_t)env->CP0_Status);
1025     case 33: GET_REGL(env->active_tc.LO[0]);
1026     case 34: GET_REGL(env->active_tc.HI[0]);
1027     case 35: GET_REGL(env->CP0_BadVAddr);
1028     case 36: GET_REGL((int32_t)env->CP0_Cause);
1029     case 37: GET_REGL(env->active_tc.PC);
1030     case 72: GET_REGL(0); /* fp */
1031     case 89: GET_REGL((int32_t)env->CP0_PRid);
1032     }
1033     if (n >= 73 && n <= 88) {
1034         /* 16 embedded regs.  */
1035         GET_REGL(0);
1036     }
1037
1038     return 0;
1039 }
1040
1041 /* convert MIPS rounding mode in FCR31 to IEEE library */
1042 static unsigned int ieee_rm[] =
1043   {
1044     float_round_nearest_even,
1045     float_round_to_zero,
1046     float_round_up,
1047     float_round_down
1048   };
1049 #define RESTORE_ROUNDING_MODE \
1050     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1051
1052 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1053 {
1054     target_ulong tmp;
1055
1056     tmp = ldtul_p(mem_buf);
1057
1058     if (n < 32) {
1059         env->active_tc.gpr[n] = tmp;
1060         return sizeof(target_ulong);
1061     }
1062     if (env->CP0_Config1 & (1 << CP0C1_FP)
1063             && n >= 38 && n < 73) {
1064         if (n < 70) {
1065             if (env->CP0_Status & (1 << CP0St_FR))
1066               env->active_fpu.fpr[n - 38].d = tmp;
1067             else
1068               env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1069         }
1070         switch (n) {
1071         case 70:
1072             env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1073             /* set rounding mode */
1074             RESTORE_ROUNDING_MODE;
1075 #ifndef CONFIG_SOFTFLOAT
1076             /* no floating point exception for native float */
1077             SET_FP_ENABLE(env->active_fpu.fcr31, 0);
1078 #endif
1079             break;
1080         case 71: env->active_fpu.fcr0 = tmp; break;
1081         }
1082         return sizeof(target_ulong);
1083     }
1084     switch (n) {
1085     case 32: env->CP0_Status = tmp; break;
1086     case 33: env->active_tc.LO[0] = tmp; break;
1087     case 34: env->active_tc.HI[0] = tmp; break;
1088     case 35: env->CP0_BadVAddr = tmp; break;
1089     case 36: env->CP0_Cause = tmp; break;
1090     case 37: env->active_tc.PC = tmp; break;
1091     case 72: /* fp, ignored */ break;
1092     default:
1093         if (n > 89)
1094             return 0;
1095         /* Other registers are readonly.  Ignore writes.  */
1096         break;
1097     }
1098
1099     return sizeof(target_ulong);
1100 }
1101 #elif defined (TARGET_SH4)
1102
1103 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1104 /* FIXME: We should use XML for this.  */
1105
1106 #define NUM_CORE_REGS 59
1107
1108 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1109 {
1110     if (n < 8) {
1111         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1112             GET_REGL(env->gregs[n + 16]);
1113         } else {
1114             GET_REGL(env->gregs[n]);
1115         }
1116     } else if (n < 16) {
1117         GET_REGL(env->gregs[n - 8]);
1118     } else if (n >= 25 && n < 41) {
1119         GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1120     } else if (n >= 43 && n < 51) {
1121         GET_REGL(env->gregs[n - 43]);
1122     } else if (n >= 51 && n < 59) {
1123         GET_REGL(env->gregs[n - (51 - 16)]);
1124     }
1125     switch (n) {
1126     case 16: GET_REGL(env->pc);
1127     case 17: GET_REGL(env->pr);
1128     case 18: GET_REGL(env->gbr);
1129     case 19: GET_REGL(env->vbr);
1130     case 20: GET_REGL(env->mach);
1131     case 21: GET_REGL(env->macl);
1132     case 22: GET_REGL(env->sr);
1133     case 23: GET_REGL(env->fpul);
1134     case 24: GET_REGL(env->fpscr);
1135     case 41: GET_REGL(env->ssr);
1136     case 42: GET_REGL(env->spc);
1137     }
1138
1139     return 0;
1140 }
1141
1142 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1143 {
1144     uint32_t tmp;
1145
1146     tmp = ldl_p(mem_buf);
1147
1148     if (n < 8) {
1149         if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1150             env->gregs[n + 16] = tmp;
1151         } else {
1152             env->gregs[n] = tmp;
1153         }
1154         return 4;
1155     } else if (n < 16) {
1156         env->gregs[n - 8] = tmp;
1157         return 4;
1158     } else if (n >= 25 && n < 41) {
1159         env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1160     } else if (n >= 43 && n < 51) {
1161         env->gregs[n - 43] = tmp;
1162         return 4;
1163     } else if (n >= 51 && n < 59) {
1164         env->gregs[n - (51 - 16)] = tmp;
1165         return 4;
1166     }
1167     switch (n) {
1168     case 16: env->pc = tmp;
1169     case 17: env->pr = tmp;
1170     case 18: env->gbr = tmp;
1171     case 19: env->vbr = tmp;
1172     case 20: env->mach = tmp;
1173     case 21: env->macl = tmp;
1174     case 22: env->sr = tmp;
1175     case 23: env->fpul = tmp;
1176     case 24: env->fpscr = tmp;
1177     case 41: env->ssr = tmp;
1178     case 42: env->spc = tmp;
1179     default: return 0;
1180     }
1181
1182     return 4;
1183 }
1184 #elif defined (TARGET_MICROBLAZE)
1185
1186 #define NUM_CORE_REGS (32 + 5)
1187
1188 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1189 {
1190     if (n < 32) {
1191         GET_REG32(env->regs[n]);
1192     } else {
1193         GET_REG32(env->sregs[n - 32]);
1194     }
1195     return 0;
1196 }
1197
1198 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1199 {
1200     uint32_t tmp;
1201
1202     if (n > NUM_CORE_REGS)
1203         return 0;
1204
1205     tmp = ldl_p(mem_buf);
1206
1207     if (n < 32) {
1208         env->regs[n] = tmp;
1209     } else {
1210         env->sregs[n - 32] = tmp;
1211     }
1212     return 4;
1213 }
1214 #elif defined (TARGET_CRIS)
1215
1216 #define NUM_CORE_REGS 49
1217
1218 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1219 {
1220     uint8_t srs;
1221
1222     srs = env->pregs[PR_SRS];
1223     if (n < 16) {
1224         GET_REG32(env->regs[n]);
1225     }
1226
1227     if (n >= 21 && n < 32) {
1228         GET_REG32(env->pregs[n - 16]);
1229     }
1230     if (n >= 33 && n < 49) {
1231         GET_REG32(env->sregs[srs][n - 33]);
1232     }
1233     switch (n) {
1234     case 16: GET_REG8(env->pregs[0]);
1235     case 17: GET_REG8(env->pregs[1]);
1236     case 18: GET_REG32(env->pregs[2]);
1237     case 19: GET_REG8(srs);
1238     case 20: GET_REG16(env->pregs[4]);
1239     case 32: GET_REG32(env->pc);
1240     }
1241
1242     return 0;
1243 }
1244
1245 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1246 {
1247     uint32_t tmp;
1248
1249     if (n > 49)
1250         return 0;
1251
1252     tmp = ldl_p(mem_buf);
1253
1254     if (n < 16) {
1255         env->regs[n] = tmp;
1256     }
1257
1258     if (n >= 21 && n < 32) {
1259         env->pregs[n - 16] = tmp;
1260     }
1261
1262     /* FIXME: Should support function regs be writable?  */
1263     switch (n) {
1264     case 16: return 1;
1265     case 17: return 1;
1266     case 18: env->pregs[PR_PID] = tmp; break;
1267     case 19: return 1;
1268     case 20: return 2;
1269     case 32: env->pc = tmp; break;
1270     }
1271
1272     return 4;
1273 }
1274 #elif defined (TARGET_ALPHA)
1275
1276 #define NUM_CORE_REGS 65
1277
1278 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1279 {
1280     if (n < 31) {
1281        GET_REGL(env->ir[n]);
1282     }
1283     else if (n == 31) {
1284        GET_REGL(0);
1285     }
1286     else if (n<63) {
1287        uint64_t val;
1288
1289        val=*((uint64_t *)&env->fir[n-32]);
1290        GET_REGL(val);
1291     }
1292     else if (n==63) {
1293        GET_REGL(env->fpcr);
1294     }
1295     else if (n==64) {
1296        GET_REGL(env->pc);
1297     }
1298     else {
1299        GET_REGL(0);
1300     }
1301
1302     return 0;
1303 }
1304
1305 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1306 {
1307     target_ulong tmp;
1308     tmp = ldtul_p(mem_buf);
1309
1310     if (n < 31) {
1311         env->ir[n] = tmp;
1312     }
1313
1314     if (n > 31 && n < 63) {
1315         env->fir[n - 32] = ldfl_p(mem_buf);
1316     }
1317
1318     if (n == 64 ) {
1319        env->pc=tmp;
1320     }
1321
1322     return 8;
1323 }
1324 #else
1325
1326 #define NUM_CORE_REGS 0
1327
1328 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1329 {
1330     return 0;
1331 }
1332
1333 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1334 {
1335     return 0;
1336 }
1337
1338 #endif
1339
1340 static int num_g_regs = NUM_CORE_REGS;
1341
1342 #ifdef GDB_CORE_XML
1343 /* Encode data using the encoding for 'x' packets.  */
1344 static int memtox(char *buf, const char *mem, int len)
1345 {
1346     char *p = buf;
1347     char c;
1348
1349     while (len--) {
1350         c = *(mem++);
1351         switch (c) {
1352         case '#': case '$': case '*': case '}':
1353             *(p++) = '}';
1354             *(p++) = c ^ 0x20;
1355             break;
1356         default:
1357             *(p++) = c;
1358             break;
1359         }
1360     }
1361     return p - buf;
1362 }
1363
1364 static const char *get_feature_xml(const char *p, const char **newp)
1365 {
1366     extern const char *const xml_builtin[][2];
1367     size_t len;
1368     int i;
1369     const char *name;
1370     static char target_xml[1024];
1371
1372     len = 0;
1373     while (p[len] && p[len] != ':')
1374         len++;
1375     *newp = p + len;
1376
1377     name = NULL;
1378     if (strncmp(p, "target.xml", len) == 0) {
1379         /* Generate the XML description for this CPU.  */
1380         if (!target_xml[0]) {
1381             GDBRegisterState *r;
1382
1383             snprintf(target_xml, sizeof(target_xml),
1384                      "<?xml version=\"1.0\"?>"
1385                      "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1386                      "<target>"
1387                      "<xi:include href=\"%s\"/>",
1388                      GDB_CORE_XML);
1389
1390             for (r = first_cpu->gdb_regs; r; r = r->next) {
1391                 pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1392                 pstrcat(target_xml, sizeof(target_xml), r->xml);
1393                 pstrcat(target_xml, sizeof(target_xml), "\"/>");
1394             }
1395             pstrcat(target_xml, sizeof(target_xml), "</target>");
1396         }
1397         return target_xml;
1398     }
1399     for (i = 0; ; i++) {
1400         name = xml_builtin[i][0];
1401         if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1402             break;
1403     }
1404     return name ? xml_builtin[i][1] : NULL;
1405 }
1406 #endif
1407
1408 static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1409 {
1410     GDBRegisterState *r;
1411
1412     if (reg < NUM_CORE_REGS)
1413         return cpu_gdb_read_register(env, mem_buf, reg);
1414
1415     for (r = env->gdb_regs; r; r = r->next) {
1416         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1417             return r->get_reg(env, mem_buf, reg - r->base_reg);
1418         }
1419     }
1420     return 0;
1421 }
1422
1423 static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1424 {
1425     GDBRegisterState *r;
1426
1427     if (reg < NUM_CORE_REGS)
1428         return cpu_gdb_write_register(env, mem_buf, reg);
1429
1430     for (r = env->gdb_regs; r; r = r->next) {
1431         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1432             return r->set_reg(env, mem_buf, reg - r->base_reg);
1433         }
1434     }
1435     return 0;
1436 }
1437
1438 /* Register a supplemental set of CPU registers.  If g_pos is nonzero it
1439    specifies the first register number and these registers are included in
1440    a standard "g" packet.  Direction is relative to gdb, i.e. get_reg is
1441    gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1442  */
1443
1444 void gdb_register_coprocessor(CPUState * env,
1445                              gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1446                              int num_regs, const char *xml, int g_pos)
1447 {
1448     GDBRegisterState *s;
1449     GDBRegisterState **p;
1450     static int last_reg = NUM_CORE_REGS;
1451
1452     s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1453     s->base_reg = last_reg;
1454     s->num_regs = num_regs;
1455     s->get_reg = get_reg;
1456     s->set_reg = set_reg;
1457     s->xml = xml;
1458     p = &env->gdb_regs;
1459     while (*p) {
1460         /* Check for duplicates.  */
1461         if (strcmp((*p)->xml, xml) == 0)
1462             return;
1463         p = &(*p)->next;
1464     }
1465     /* Add to end of list.  */
1466     last_reg += num_regs;
1467     *p = s;
1468     if (g_pos) {
1469         if (g_pos != s->base_reg) {
1470             fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1471                     "Expected %d got %d\n", xml, g_pos, s->base_reg);
1472         } else {
1473             num_g_regs = last_reg;
1474         }
1475     }
1476 }
1477
1478 #ifndef CONFIG_USER_ONLY
1479 static const int xlat_gdb_type[] = {
1480     [GDB_WATCHPOINT_WRITE]  = BP_GDB | BP_MEM_WRITE,
1481     [GDB_WATCHPOINT_READ]   = BP_GDB | BP_MEM_READ,
1482     [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1483 };
1484 #endif
1485
1486 static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1487 {
1488     CPUState *env;
1489     int err = 0;
1490
1491     if (kvm_enabled())
1492         return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1493
1494     switch (type) {
1495     case GDB_BREAKPOINT_SW:
1496     case GDB_BREAKPOINT_HW:
1497         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1498             err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1499             if (err)
1500                 break;
1501         }
1502         return err;
1503 #ifndef CONFIG_USER_ONLY
1504     case GDB_WATCHPOINT_WRITE:
1505     case GDB_WATCHPOINT_READ:
1506     case GDB_WATCHPOINT_ACCESS:
1507         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1508             err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1509                                         NULL);
1510             if (err)
1511                 break;
1512         }
1513         return err;
1514 #endif
1515     default:
1516         return -ENOSYS;
1517     }
1518 }
1519
1520 static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1521 {
1522     CPUState *env;
1523     int err = 0;
1524
1525     if (kvm_enabled())
1526         return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1527
1528     switch (type) {
1529     case GDB_BREAKPOINT_SW:
1530     case GDB_BREAKPOINT_HW:
1531         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1532             err = cpu_breakpoint_remove(env, addr, BP_GDB);
1533             if (err)
1534                 break;
1535         }
1536         return err;
1537 #ifndef CONFIG_USER_ONLY
1538     case GDB_WATCHPOINT_WRITE:
1539     case GDB_WATCHPOINT_READ:
1540     case GDB_WATCHPOINT_ACCESS:
1541         for (env = first_cpu; env != NULL; env = env->next_cpu) {
1542             err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1543             if (err)
1544                 break;
1545         }
1546         return err;
1547 #endif
1548     default:
1549         return -ENOSYS;
1550     }
1551 }
1552
1553 static void gdb_breakpoint_remove_all(void)
1554 {
1555     CPUState *env;
1556
1557     if (kvm_enabled()) {
1558         kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1559         return;
1560     }
1561
1562     for (env = first_cpu; env != NULL; env = env->next_cpu) {
1563         cpu_breakpoint_remove_all(env, BP_GDB);
1564 #ifndef CONFIG_USER_ONLY
1565         cpu_watchpoint_remove_all(env, BP_GDB);
1566 #endif
1567     }
1568 }
1569
1570 static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
1571 {
1572 #if defined(TARGET_I386)
1573     s->c_cpu->eip = pc;
1574     cpu_synchronize_state(s->c_cpu, 1);
1575 #elif defined (TARGET_PPC)
1576     s->c_cpu->nip = pc;
1577 #elif defined (TARGET_SPARC)
1578     s->c_cpu->pc = pc;
1579     s->c_cpu->npc = pc + 4;
1580 #elif defined (TARGET_ARM)
1581     s->c_cpu->regs[15] = pc;
1582 #elif defined (TARGET_SH4)
1583     s->c_cpu->pc = pc;
1584 #elif defined (TARGET_MIPS)
1585     s->c_cpu->active_tc.PC = pc;
1586 #elif defined (TARGET_MICROBLAZE)
1587     s->c_cpu->sregs[SR_PC] = pc;
1588 #elif defined (TARGET_CRIS)
1589     s->c_cpu->pc = pc;
1590 #elif defined (TARGET_ALPHA)
1591     s->c_cpu->pc = pc;
1592 #endif
1593 }
1594
1595 static inline int gdb_id(CPUState *env)
1596 {
1597 #if defined(CONFIG_USER_ONLY) && defined(USE_NPTL)
1598     return env->host_tid;
1599 #else
1600     return env->cpu_index + 1;
1601 #endif
1602 }
1603
1604 static CPUState *find_cpu(uint32_t thread_id)
1605 {
1606     CPUState *env;
1607
1608     for (env = first_cpu; env != NULL; env = env->next_cpu) {
1609         if (gdb_id(env) == thread_id) {
1610             return env;
1611         }
1612     }
1613
1614     return NULL;
1615 }
1616
1617 static int gdb_handle_packet(GDBState *s, const char *line_buf)
1618 {
1619     CPUState *env;
1620     const char *p;
1621     uint32_t thread;
1622     int ch, reg_size, type, res;
1623     char buf[MAX_PACKET_LENGTH];
1624     uint8_t mem_buf[MAX_PACKET_LENGTH];
1625     uint8_t *registers;
1626     target_ulong addr, len;
1627
1628 #ifdef DEBUG_GDB
1629     printf("command='%s'\n", line_buf);
1630 #endif
1631     p = line_buf;
1632     ch = *p++;
1633     switch(ch) {
1634     case '?':
1635         /* TODO: Make this return the correct value for user-mode.  */
1636         snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1637                  gdb_id(s->c_cpu));
1638         put_packet(s, buf);
1639         /* Remove all the breakpoints when this query is issued,
1640          * because gdb is doing and initial connect and the state
1641          * should be cleaned up.
1642          */
1643         gdb_breakpoint_remove_all();
1644         break;
1645     case 'c':
1646         if (*p != '\0') {
1647             addr = strtoull(p, (char **)&p, 16);
1648             gdb_set_cpu_pc(s, addr);
1649         }
1650         s->signal = 0;
1651         gdb_continue(s);
1652         return RS_IDLE;
1653     case 'C':
1654         s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
1655         if (s->signal == -1)
1656             s->signal = 0;
1657         gdb_continue(s);
1658         return RS_IDLE;
1659     case 'v':
1660         if (strncmp(p, "Cont", 4) == 0) {
1661             int res_signal, res_thread;
1662
1663             p += 4;
1664             if (*p == '?') {
1665                 put_packet(s, "vCont;c;C;s;S");
1666                 break;
1667             }
1668             res = 0;
1669             res_signal = 0;
1670             res_thread = 0;
1671             while (*p) {
1672                 int action, signal;
1673
1674                 if (*p++ != ';') {
1675                     res = 0;
1676                     break;
1677                 }
1678                 action = *p++;
1679                 signal = 0;
1680                 if (action == 'C' || action == 'S') {
1681                     signal = strtoul(p, (char **)&p, 16);
1682                 } else if (action != 'c' && action != 's') {
1683                     res = 0;
1684                     break;
1685                 }
1686                 thread = 0;
1687                 if (*p == ':') {
1688                     thread = strtoull(p+1, (char **)&p, 16);
1689                 }
1690                 action = tolower(action);
1691                 if (res == 0 || (res == 'c' && action == 's')) {
1692                     res = action;
1693                     res_signal = signal;
1694                     res_thread = thread;
1695                 }
1696             }
1697             if (res) {
1698                 if (res_thread != -1 && res_thread != 0) {
1699                     env = find_cpu(res_thread);
1700                     if (env == NULL) {
1701                         put_packet(s, "E22");
1702                         break;
1703                     }
1704                     s->c_cpu = env;
1705                 }
1706                 if (res == 's') {
1707                     cpu_single_step(s->c_cpu, sstep_flags);
1708                 }
1709                 s->signal = res_signal;
1710                 gdb_continue(s);
1711                 return RS_IDLE;
1712             }
1713             break;
1714         } else {
1715             goto unknown_command;
1716         }
1717     case 'k':
1718         /* Kill the target */
1719         fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1720         exit(0);
1721     case 'D':
1722         /* Detach packet */
1723         gdb_breakpoint_remove_all();
1724         gdb_continue(s);
1725         put_packet(s, "OK");
1726         break;
1727     case 's':
1728         if (*p != '\0') {
1729             addr = strtoull(p, (char **)&p, 16);
1730             gdb_set_cpu_pc(s, addr);
1731         }
1732         cpu_single_step(s->c_cpu, sstep_flags);
1733         gdb_continue(s);
1734         return RS_IDLE;
1735     case 'F':
1736         {
1737             target_ulong ret;
1738             target_ulong err;
1739
1740             ret = strtoull(p, (char **)&p, 16);
1741             if (*p == ',') {
1742                 p++;
1743                 err = strtoull(p, (char **)&p, 16);
1744             } else {
1745                 err = 0;
1746             }
1747             if (*p == ',')
1748                 p++;
1749             type = *p;
1750             if (gdb_current_syscall_cb)
1751                 gdb_current_syscall_cb(s->c_cpu, ret, err);
1752             if (type == 'C') {
1753                 put_packet(s, "T02");
1754             } else {
1755                 gdb_continue(s);
1756             }
1757         }
1758         break;
1759     case 'g':
1760         cpu_synchronize_state(s->g_cpu, 0);
1761         len = 0;
1762         for (addr = 0; addr < num_g_regs; addr++) {
1763             reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
1764             len += reg_size;
1765         }
1766         memtohex(buf, mem_buf, len);
1767         put_packet(s, buf);
1768         break;
1769     case 'G':
1770         registers = mem_buf;
1771         len = strlen(p) / 2;
1772         hextomem((uint8_t *)registers, p, len);
1773         for (addr = 0; addr < num_g_regs && len > 0; addr++) {
1774             reg_size = gdb_write_register(s->g_cpu, registers, addr);
1775             len -= reg_size;
1776             registers += reg_size;
1777         }
1778         cpu_synchronize_state(s->g_cpu, 1);
1779         put_packet(s, "OK");
1780         break;
1781     case 'm':
1782         addr = strtoull(p, (char **)&p, 16);
1783         if (*p == ',')
1784             p++;
1785         len = strtoull(p, NULL, 16);
1786         if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
1787             put_packet (s, "E14");
1788         } else {
1789             memtohex(buf, mem_buf, len);
1790             put_packet(s, buf);
1791         }
1792         break;
1793     case 'M':
1794         addr = strtoull(p, (char **)&p, 16);
1795         if (*p == ',')
1796             p++;
1797         len = strtoull(p, (char **)&p, 16);
1798         if (*p == ':')
1799             p++;
1800         hextomem(mem_buf, p, len);
1801         if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
1802             put_packet(s, "E14");
1803         else
1804             put_packet(s, "OK");
1805         break;
1806     case 'p':
1807         /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
1808            This works, but can be very slow.  Anything new enough to
1809            understand XML also knows how to use this properly.  */
1810         if (!gdb_has_xml)
1811             goto unknown_command;
1812         addr = strtoull(p, (char **)&p, 16);
1813         reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
1814         if (reg_size) {
1815             memtohex(buf, mem_buf, reg_size);
1816             put_packet(s, buf);
1817         } else {
1818             put_packet(s, "E14");
1819         }
1820         break;
1821     case 'P':
1822         if (!gdb_has_xml)
1823             goto unknown_command;
1824         addr = strtoull(p, (char **)&p, 16);
1825         if (*p == '=')
1826             p++;
1827         reg_size = strlen(p) / 2;
1828         hextomem(mem_buf, p, reg_size);
1829         gdb_write_register(s->g_cpu, mem_buf, addr);
1830         put_packet(s, "OK");
1831         break;
1832     case 'Z':
1833     case 'z':
1834         type = strtoul(p, (char **)&p, 16);
1835         if (*p == ',')
1836             p++;
1837         addr = strtoull(p, (char **)&p, 16);
1838         if (*p == ',')
1839             p++;
1840         len = strtoull(p, (char **)&p, 16);
1841         if (ch == 'Z')
1842             res = gdb_breakpoint_insert(addr, len, type);
1843         else
1844             res = gdb_breakpoint_remove(addr, len, type);
1845         if (res >= 0)
1846              put_packet(s, "OK");
1847         else if (res == -ENOSYS)
1848             put_packet(s, "");
1849         else
1850             put_packet(s, "E22");
1851         break;
1852     case 'H':
1853         type = *p++;
1854         thread = strtoull(p, (char **)&p, 16);
1855         if (thread == -1 || thread == 0) {
1856             put_packet(s, "OK");
1857             break;
1858         }
1859         env = find_cpu(thread);
1860         if (env == NULL) {
1861             put_packet(s, "E22");
1862             break;
1863         }
1864         switch (type) {
1865         case 'c':
1866             s->c_cpu = env;
1867             put_packet(s, "OK");
1868             break;
1869         case 'g':
1870             s->g_cpu = env;
1871             put_packet(s, "OK");
1872             break;
1873         default:
1874              put_packet(s, "E22");
1875              break;
1876         }
1877         break;
1878     case 'T':
1879         thread = strtoull(p, (char **)&p, 16);
1880         env = find_cpu(thread);
1881
1882         if (env != NULL) {
1883             put_packet(s, "OK");
1884         } else {
1885             put_packet(s, "E22");
1886         }
1887         break;
1888     case 'q':
1889     case 'Q':
1890         /* parse any 'q' packets here */
1891         if (!strcmp(p,"qemu.sstepbits")) {
1892             /* Query Breakpoint bit definitions */
1893             snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1894                      SSTEP_ENABLE,
1895                      SSTEP_NOIRQ,
1896                      SSTEP_NOTIMER);
1897             put_packet(s, buf);
1898             break;
1899         } else if (strncmp(p,"qemu.sstep",10) == 0) {
1900             /* Display or change the sstep_flags */
1901             p += 10;
1902             if (*p != '=') {
1903                 /* Display current setting */
1904                 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
1905                 put_packet(s, buf);
1906                 break;
1907             }
1908             p++;
1909             type = strtoul(p, (char **)&p, 16);
1910             sstep_flags = type;
1911             put_packet(s, "OK");
1912             break;
1913         } else if (strcmp(p,"C") == 0) {
1914             /* "Current thread" remains vague in the spec, so always return
1915              *  the first CPU (gdb returns the first thread). */
1916             put_packet(s, "QC1");
1917             break;
1918         } else if (strcmp(p,"fThreadInfo") == 0) {
1919             s->query_cpu = first_cpu;
1920             goto report_cpuinfo;
1921         } else if (strcmp(p,"sThreadInfo") == 0) {
1922         report_cpuinfo:
1923             if (s->query_cpu) {
1924                 snprintf(buf, sizeof(buf), "m%x", gdb_id(s->query_cpu));
1925                 put_packet(s, buf);
1926                 s->query_cpu = s->query_cpu->next_cpu;
1927             } else
1928                 put_packet(s, "l");
1929             break;
1930         } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
1931             thread = strtoull(p+16, (char **)&p, 16);
1932             env = find_cpu(thread);
1933             if (env != NULL) {
1934                 cpu_synchronize_state(env, 0);
1935                 len = snprintf((char *)mem_buf, sizeof(mem_buf),
1936                                "CPU#%d [%s]", env->cpu_index,
1937                                env->halted ? "halted " : "running");
1938                 memtohex(buf, mem_buf, len);
1939                 put_packet(s, buf);
1940             }
1941             break;
1942         }
1943 #ifdef CONFIG_USER_ONLY
1944         else if (strncmp(p, "Offsets", 7) == 0) {
1945             TaskState *ts = s->c_cpu->opaque;
1946
1947             snprintf(buf, sizeof(buf),
1948                      "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1949                      ";Bss=" TARGET_ABI_FMT_lx,
1950                      ts->info->code_offset,
1951                      ts->info->data_offset,
1952                      ts->info->data_offset);
1953             put_packet(s, buf);
1954             break;
1955         }
1956 #else /* !CONFIG_USER_ONLY */
1957         else if (strncmp(p, "Rcmd,", 5) == 0) {
1958             int len = strlen(p + 5);
1959
1960             if ((len % 2) != 0) {
1961                 put_packet(s, "E01");
1962                 break;
1963             }
1964             hextomem(mem_buf, p + 5, len);
1965             len = len / 2;
1966             mem_buf[len++] = 0;
1967             qemu_chr_read(s->mon_chr, mem_buf, len);
1968             put_packet(s, "OK");
1969             break;
1970         }
1971 #endif /* !CONFIG_USER_ONLY */
1972         if (strncmp(p, "Supported", 9) == 0) {
1973             snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
1974 #ifdef GDB_CORE_XML
1975             pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
1976 #endif
1977             put_packet(s, buf);
1978             break;
1979         }
1980 #ifdef GDB_CORE_XML
1981         if (strncmp(p, "Xfer:features:read:", 19) == 0) {
1982             const char *xml;
1983             target_ulong total_len;
1984
1985             gdb_has_xml = 1;
1986             p += 19;
1987             xml = get_feature_xml(p, &p);
1988             if (!xml) {
1989                 snprintf(buf, sizeof(buf), "E00");
1990                 put_packet(s, buf);
1991                 break;
1992             }
1993
1994             if (*p == ':')
1995                 p++;
1996             addr = strtoul(p, (char **)&p, 16);
1997             if (*p == ',')
1998                 p++;
1999             len = strtoul(p, (char **)&p, 16);
2000
2001             total_len = strlen(xml);
2002             if (addr > total_len) {
2003                 snprintf(buf, sizeof(buf), "E00");
2004                 put_packet(s, buf);
2005                 break;
2006             }
2007             if (len > (MAX_PACKET_LENGTH - 5) / 2)
2008                 len = (MAX_PACKET_LENGTH - 5) / 2;
2009             if (len < total_len - addr) {
2010                 buf[0] = 'm';
2011                 len = memtox(buf + 1, xml + addr, len);
2012             } else {
2013                 buf[0] = 'l';
2014                 len = memtox(buf + 1, xml + addr, total_len - addr);
2015             }
2016             put_packet_binary(s, buf, len + 1);
2017             break;
2018         }
2019 #endif
2020         /* Unrecognised 'q' command.  */
2021         goto unknown_command;
2022
2023     default:
2024     unknown_command:
2025         /* put empty packet */
2026         buf[0] = '\0';
2027         put_packet(s, buf);
2028         break;
2029     }
2030     return RS_IDLE;
2031 }
2032
2033 void gdb_set_stop_cpu(CPUState *env)
2034 {
2035     gdbserver_state->c_cpu = env;
2036     gdbserver_state->g_cpu = env;
2037 }
2038
2039 #ifndef CONFIG_USER_ONLY
2040 static void gdb_vm_state_change(void *opaque, int running, int reason)
2041 {
2042     GDBState *s = gdbserver_state;
2043     CPUState *env = s->c_cpu;
2044     char buf[256];
2045     const char *type;
2046     int ret;
2047
2048     if (running || (reason != EXCP_DEBUG && reason != EXCP_INTERRUPT) ||
2049         s->state == RS_INACTIVE || s->state == RS_SYSCALL)
2050         return;
2051
2052     /* disable single step if it was enable */
2053     cpu_single_step(env, 0);
2054
2055     if (reason == EXCP_DEBUG) {
2056         if (env->watchpoint_hit) {
2057             switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
2058             case BP_MEM_READ:
2059                 type = "r";
2060                 break;
2061             case BP_MEM_ACCESS:
2062                 type = "a";
2063                 break;
2064             default:
2065                 type = "";
2066                 break;
2067             }
2068             snprintf(buf, sizeof(buf),
2069                      "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
2070                      GDB_SIGNAL_TRAP, gdb_id(env), type,
2071                      env->watchpoint_hit->vaddr);
2072             put_packet(s, buf);
2073             env->watchpoint_hit = NULL;
2074             return;
2075         }
2076         tb_flush(env);
2077         ret = GDB_SIGNAL_TRAP;
2078     } else {
2079         ret = GDB_SIGNAL_INT;
2080     }
2081     snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, gdb_id(env));
2082     put_packet(s, buf);
2083 }
2084 #endif
2085
2086 /* Send a gdb syscall request.
2087    This accepts limited printf-style format specifiers, specifically:
2088     %x  - target_ulong argument printed in hex.
2089     %lx - 64-bit argument printed in hex.
2090     %s  - string pointer (target_ulong) and length (int) pair.  */
2091 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
2092 {
2093     va_list va;
2094     char buf[256];
2095     char *p;
2096     target_ulong addr;
2097     uint64_t i64;
2098     GDBState *s;
2099
2100     s = gdbserver_state;
2101     if (!s)
2102         return;
2103     gdb_current_syscall_cb = cb;
2104     s->state = RS_SYSCALL;
2105 #ifndef CONFIG_USER_ONLY
2106     vm_stop(EXCP_DEBUG);
2107 #endif
2108     s->state = RS_IDLE;
2109     va_start(va, fmt);
2110     p = buf;
2111     *(p++) = 'F';
2112     while (*fmt) {
2113         if (*fmt == '%') {
2114             fmt++;
2115             switch (*fmt++) {
2116             case 'x':
2117                 addr = va_arg(va, target_ulong);
2118                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
2119                 break;
2120             case 'l':
2121                 if (*(fmt++) != 'x')
2122                     goto bad_format;
2123                 i64 = va_arg(va, uint64_t);
2124                 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
2125                 break;
2126             case 's':
2127                 addr = va_arg(va, target_ulong);
2128                 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
2129                               addr, va_arg(va, int));
2130                 break;
2131             default:
2132             bad_format:
2133                 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2134                         fmt - 1);
2135                 break;
2136             }
2137         } else {
2138             *(p++) = *(fmt++);
2139         }
2140     }
2141     *p = 0;
2142     va_end(va);
2143     put_packet(s, buf);
2144 #ifdef CONFIG_USER_ONLY
2145     gdb_handlesig(s->c_cpu, 0);
2146 #else
2147     cpu_exit(s->c_cpu);
2148 #endif
2149 }
2150
2151 static void gdb_read_byte(GDBState *s, int ch)
2152 {
2153     int i, csum;
2154     uint8_t reply;
2155
2156 #ifndef CONFIG_USER_ONLY
2157     if (s->last_packet_len) {
2158         /* Waiting for a response to the last packet.  If we see the start
2159            of a new command then abandon the previous response.  */
2160         if (ch == '-') {
2161 #ifdef DEBUG_GDB
2162             printf("Got NACK, retransmitting\n");
2163 #endif
2164             put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2165         }
2166 #ifdef DEBUG_GDB
2167         else if (ch == '+')
2168             printf("Got ACK\n");
2169         else
2170             printf("Got '%c' when expecting ACK/NACK\n", ch);
2171 #endif
2172         if (ch == '+' || ch == '$')
2173             s->last_packet_len = 0;
2174         if (ch != '$')
2175             return;
2176     }
2177     if (vm_running) {
2178         /* when the CPU is running, we cannot do anything except stop
2179            it when receiving a char */
2180         vm_stop(EXCP_INTERRUPT);
2181     } else
2182 #endif
2183     {
2184         switch(s->state) {
2185         case RS_IDLE:
2186             if (ch == '$') {
2187                 s->line_buf_index = 0;
2188                 s->state = RS_GETLINE;
2189             }
2190             break;
2191         case RS_GETLINE:
2192             if (ch == '#') {
2193             s->state = RS_CHKSUM1;
2194             } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2195                 s->state = RS_IDLE;
2196             } else {
2197             s->line_buf[s->line_buf_index++] = ch;
2198             }
2199             break;
2200         case RS_CHKSUM1:
2201             s->line_buf[s->line_buf_index] = '\0';
2202             s->line_csum = fromhex(ch) << 4;
2203             s->state = RS_CHKSUM2;
2204             break;
2205         case RS_CHKSUM2:
2206             s->line_csum |= fromhex(ch);
2207             csum = 0;
2208             for(i = 0; i < s->line_buf_index; i++) {
2209                 csum += s->line_buf[i];
2210             }
2211             if (s->line_csum != (csum & 0xff)) {
2212                 reply = '-';
2213                 put_buffer(s, &reply, 1);
2214                 s->state = RS_IDLE;
2215             } else {
2216                 reply = '+';
2217                 put_buffer(s, &reply, 1);
2218                 s->state = gdb_handle_packet(s, s->line_buf);
2219             }
2220             break;
2221         default:
2222             abort();
2223         }
2224     }
2225 }
2226
2227 #ifdef CONFIG_USER_ONLY
2228 int
2229 gdb_queuesig (void)
2230 {
2231     GDBState *s;
2232
2233     s = gdbserver_state;
2234
2235     if (gdbserver_fd < 0 || s->fd < 0)
2236         return 0;
2237     else
2238         return 1;
2239 }
2240
2241 int
2242 gdb_handlesig (CPUState *env, int sig)
2243 {
2244   GDBState *s;
2245   char buf[256];
2246   int n;
2247
2248   s = gdbserver_state;
2249   if (gdbserver_fd < 0 || s->fd < 0)
2250     return sig;
2251
2252   /* disable single step if it was enabled */
2253   cpu_single_step(env, 0);
2254   tb_flush(env);
2255
2256   if (sig != 0)
2257     {
2258       snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2259       put_packet(s, buf);
2260     }
2261   /* put_packet() might have detected that the peer terminated the
2262      connection.  */
2263   if (s->fd < 0)
2264       return sig;
2265
2266   sig = 0;
2267   s->state = RS_IDLE;
2268   s->running_state = 0;
2269   while (s->running_state == 0) {
2270       n = read (s->fd, buf, 256);
2271       if (n > 0)
2272         {
2273           int i;
2274
2275           for (i = 0; i < n; i++)
2276             gdb_read_byte (s, buf[i]);
2277         }
2278       else if (n == 0 || errno != EAGAIN)
2279         {
2280           /* XXX: Connection closed.  Should probably wait for annother
2281              connection before continuing.  */
2282           return sig;
2283         }
2284   }
2285   sig = s->signal;
2286   s->signal = 0;
2287   return sig;
2288 }
2289
2290 /* Tell the remote gdb that the process has exited.  */
2291 void gdb_exit(CPUState *env, int code)
2292 {
2293   GDBState *s;
2294   char buf[4];
2295
2296   s = gdbserver_state;
2297   if (gdbserver_fd < 0 || s->fd < 0)
2298     return;
2299
2300   snprintf(buf, sizeof(buf), "W%02x", code);
2301   put_packet(s, buf);
2302 }
2303
2304 /* Tell the remote gdb that the process has exited due to SIG.  */
2305 void gdb_signalled(CPUState *env, int sig)
2306 {
2307   GDBState *s;
2308   char buf[4];
2309
2310   s = gdbserver_state;
2311   if (gdbserver_fd < 0 || s->fd < 0)
2312     return;
2313
2314   snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2315   put_packet(s, buf);
2316 }
2317
2318 static void gdb_accept(void)
2319 {
2320     GDBState *s;
2321     struct sockaddr_in sockaddr;
2322     socklen_t len;
2323     int val, fd;
2324
2325     for(;;) {
2326         len = sizeof(sockaddr);
2327         fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2328         if (fd < 0 && errno != EINTR) {
2329             perror("accept");
2330             return;
2331         } else if (fd >= 0) {
2332             break;
2333         }
2334     }
2335
2336     /* set short latency */
2337     val = 1;
2338     setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2339
2340     s = qemu_mallocz(sizeof(GDBState));
2341     s->c_cpu = first_cpu;
2342     s->g_cpu = first_cpu;
2343     s->fd = fd;
2344     gdb_has_xml = 0;
2345
2346     gdbserver_state = s;
2347
2348     fcntl(fd, F_SETFL, O_NONBLOCK);
2349 }
2350
2351 static int gdbserver_open(int port)
2352 {
2353     struct sockaddr_in sockaddr;
2354     int fd, val, ret;
2355
2356     fd = socket(PF_INET, SOCK_STREAM, 0);
2357     if (fd < 0) {
2358         perror("socket");
2359         return -1;
2360     }
2361
2362     /* allow fast reuse */
2363     val = 1;
2364     setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2365
2366     sockaddr.sin_family = AF_INET;
2367     sockaddr.sin_port = htons(port);
2368     sockaddr.sin_addr.s_addr = 0;
2369     ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2370     if (ret < 0) {
2371         perror("bind");
2372         return -1;
2373     }
2374     ret = listen(fd, 0);
2375     if (ret < 0) {
2376         perror("listen");
2377         return -1;
2378     }
2379     return fd;
2380 }
2381
2382 int gdbserver_start(int port)
2383 {
2384     gdbserver_fd = gdbserver_open(port);
2385     if (gdbserver_fd < 0)
2386         return -1;
2387     /* accept connections */
2388     gdb_accept();
2389     return 0;
2390 }
2391
2392 /* Disable gdb stub for child processes.  */
2393 void gdbserver_fork(CPUState *env)
2394 {
2395     GDBState *s = gdbserver_state;
2396     if (gdbserver_fd < 0 || s->fd < 0)
2397       return;
2398     close(s->fd);
2399     s->fd = -1;
2400     cpu_breakpoint_remove_all(env, BP_GDB);
2401     cpu_watchpoint_remove_all(env, BP_GDB);
2402 }
2403 #else
2404 static int gdb_chr_can_receive(void *opaque)
2405 {
2406   /* We can handle an arbitrarily large amount of data.
2407    Pick the maximum packet size, which is as good as anything.  */
2408   return MAX_PACKET_LENGTH;
2409 }
2410
2411 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2412 {
2413     int i;
2414
2415     for (i = 0; i < size; i++) {
2416         gdb_read_byte(gdbserver_state, buf[i]);
2417     }
2418 }
2419
2420 static void gdb_chr_event(void *opaque, int event)
2421 {
2422     switch (event) {
2423     case CHR_EVENT_RESET:
2424         vm_stop(EXCP_INTERRUPT);
2425         gdb_has_xml = 0;
2426         break;
2427     default:
2428         break;
2429     }
2430 }
2431
2432 static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2433 {
2434     char buf[MAX_PACKET_LENGTH];
2435
2436     buf[0] = 'O';
2437     if (len > (MAX_PACKET_LENGTH/2) - 1)
2438         len = (MAX_PACKET_LENGTH/2) - 1;
2439     memtohex(buf + 1, (uint8_t *)msg, len);
2440     put_packet(s, buf);
2441 }
2442
2443 static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2444 {
2445     const char *p = (const char *)buf;
2446     int max_sz;
2447
2448     max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2449     for (;;) {
2450         if (len <= max_sz) {
2451             gdb_monitor_output(gdbserver_state, p, len);
2452             break;
2453         }
2454         gdb_monitor_output(gdbserver_state, p, max_sz);
2455         p += max_sz;
2456         len -= max_sz;
2457     }
2458     return len;
2459 }
2460
2461 #ifndef _WIN32
2462 static void gdb_sigterm_handler(int signal)
2463 {
2464     if (vm_running)
2465         vm_stop(EXCP_INTERRUPT);
2466 }
2467 #endif
2468
2469 int gdbserver_start(const char *device)
2470 {
2471     GDBState *s;
2472     char gdbstub_device_name[128];
2473     CharDriverState *chr = NULL;
2474     CharDriverState *mon_chr;
2475
2476     if (!device)
2477         return -1;
2478     if (strcmp(device, "none") != 0) {
2479         if (strstart(device, "tcp:", NULL)) {
2480             /* enforce required TCP attributes */
2481             snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
2482                      "%s,nowait,nodelay,server", device);
2483             device = gdbstub_device_name;
2484         }
2485 #ifndef _WIN32
2486         else if (strcmp(device, "stdio") == 0) {
2487             struct sigaction act;
2488
2489             memset(&act, 0, sizeof(act));
2490             act.sa_handler = gdb_sigterm_handler;
2491             sigaction(SIGINT, &act, NULL);
2492         }
2493 #endif
2494         chr = qemu_chr_open("gdb", device, NULL);
2495         if (!chr)
2496             return -1;
2497
2498         qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2499                               gdb_chr_event, NULL);
2500     }
2501
2502     s = gdbserver_state;
2503     if (!s) {
2504         s = qemu_mallocz(sizeof(GDBState));
2505         gdbserver_state = s;
2506
2507         qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
2508
2509         /* Initialize a monitor terminal for gdb */
2510         mon_chr = qemu_mallocz(sizeof(*mon_chr));
2511         mon_chr->chr_write = gdb_monitor_write;
2512         monitor_init(mon_chr, 0);
2513     } else {
2514         if (s->chr)
2515             qemu_chr_close(s->chr);
2516         mon_chr = s->mon_chr;
2517         memset(s, 0, sizeof(GDBState));
2518     }
2519     s->c_cpu = first_cpu;
2520     s->g_cpu = first_cpu;
2521     s->chr = chr;
2522     s->state = chr ? RS_IDLE : RS_INACTIVE;
2523     s->mon_chr = mon_chr;
2524
2525     return 0;
2526 }
2527 #endif