qemu-kvm-x86.c

   1 /*
   2  * qemu/kvm integration, x86 specific code
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  *
   6  * Licensed under the terms of the GNU GPL version 2 or higher.
   7  */
   8
   9 #include "config.h"
  10 #include "config-host.h"
  11
  12 #include <string.h>
  13 #include "hw/hw.h"
  14
  15 #include "qemu-kvm.h"
  16 #include <libkvm.h>
  17 #include <pthread.h>
  18 #include <sys/utsname.h>
  19 #include <linux/kvm_para.h>
  20
  21 #define MSR_IA32_TSC            0x10
  22
  23 static struct kvm_msr_list *kvm_msr_list;
  24 extern unsigned int kvm_shadow_memory;
  25 extern kvm_context_t kvm_context;
  26 static int kvm_has_msr_star;
  27
  28 static int lm_capable_kernel;
  29
  30 int kvm_qemu_create_memory_alias(uint64_t phys_start,
  31                                  uint64_t len,
  32                                  uint64_t target_phys)
  33 {
  34     return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
  35 }
  36
  37 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
  38 {
  39         return kvm_destroy_memory_alias(kvm_context, phys_start);
  40 }
  41
  42 int kvm_arch_qemu_create_context(void)
  43 {
  44     int i;
  45     struct utsname utsname;
  46
  47     uname(&utsname);
  48     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
  49
  50     if (kvm_shadow_memory)
  51         kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
  52
  53     kvm_msr_list = kvm_get_msr_list(kvm_context);
  54     if (!kvm_msr_list)
  55                 return -1;
  56     for (i = 0; i < kvm_msr_list->nmsrs; ++i)
  57         if (kvm_msr_list->indices[i] == MSR_STAR)
  58             kvm_has_msr_star = 1;
  59         return 0;
  60 }
  61
  62 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
  63                           uint64_t data)
  64 {
  65     entry->index = index;
  66     entry->data  = data;
  67 }
  68
  69 /* returns 0 on success, non-0 on failure */
  70 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
  71 {
  72         switch (entry->index) {
  73         case MSR_IA32_SYSENTER_CS:
  74             env->sysenter_cs  = entry->data;
  75             break;
  76         case MSR_IA32_SYSENTER_ESP:
  77             env->sysenter_esp = entry->data;
  78             break;
  79         case MSR_IA32_SYSENTER_EIP:
  80             env->sysenter_eip = entry->data;
  81             break;
  82         case MSR_STAR:
  83             env->star         = entry->data;
  84             break;
  85 #ifdef TARGET_X86_64
  86         case MSR_CSTAR:
  87             env->cstar        = entry->data;
  88             break;
  89         case MSR_KERNELGSBASE:
  90             env->kernelgsbase = entry->data;
  91             break;
  92         case MSR_FMASK:
  93             env->fmask        = entry->data;
  94             break;
  95         case MSR_LSTAR:
  96             env->lstar        = entry->data;
  97             break;
  98 #endif
  99         case MSR_IA32_TSC:
 100             env->tsc          = entry->data;
 101             break;
 102         default:
 103             printf("Warning unknown msr index 0x%x\n", entry->index);
 104             return 1;
 105         }
 106         return 0;
 107 }
 108
 109 #ifdef TARGET_X86_64
 110 #define MSR_COUNT 9
 111 #else
 112 #define MSR_COUNT 5
 113 #endif
 114
 115 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 116 {
 117     lhs->selector = rhs->selector;
 118     lhs->base = rhs->base;
 119     lhs->limit = rhs->limit;
 120     lhs->type = 3;
 121     lhs->present = 1;
 122     lhs->dpl = 3;
 123     lhs->db = 0;
 124     lhs->s = 1;
 125     lhs->l = 0;
 126     lhs->g = 0;
 127     lhs->avl = 0;
 128     lhs->unusable = 0;
 129 }
 130
 131 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 132 {
 133     unsigned flags = rhs->flags;
 134     lhs->selector = rhs->selector;
 135     lhs->base = rhs->base;
 136     lhs->limit = rhs->limit;
 137     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 138     lhs->present = (flags & DESC_P_MASK) != 0;
 139     lhs->dpl = rhs->selector & 3;
 140     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 141     lhs->s = (flags & DESC_S_MASK) != 0;
 142     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 143     lhs->g = (flags & DESC_G_MASK) != 0;
 144     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 145     lhs->unusable = 0;
 146 }
 147
 148 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 149 {
 150     lhs->selector = rhs->selector;
 151     lhs->base = rhs->base;
 152     lhs->limit = rhs->limit;
 153     lhs->flags =
 154         (rhs->type << DESC_TYPE_SHIFT)
 155         | (rhs->present * DESC_P_MASK)
 156         | (rhs->dpl << DESC_DPL_SHIFT)
 157         | (rhs->db << DESC_B_SHIFT)
 158         | (rhs->s * DESC_S_MASK)
 159         | (rhs->l << DESC_L_SHIFT)
 160         | (rhs->g * DESC_G_MASK)
 161         | (rhs->avl * DESC_AVL_MASK);
 162 }
 163
 164 void kvm_arch_load_regs(CPUState *env)
 165 {
 166     struct kvm_regs regs;
 167     struct kvm_fpu fpu;
 168     struct kvm_sregs sregs;
 169     struct kvm_msr_entry msrs[MSR_COUNT];
 170     int rc, n, i;
 171
 172     regs.rax = env->regs[R_EAX];
 173     regs.rbx = env->regs[R_EBX];
 174     regs.rcx = env->regs[R_ECX];
 175     regs.rdx = env->regs[R_EDX];
 176     regs.rsi = env->regs[R_ESI];
 177     regs.rdi = env->regs[R_EDI];
 178     regs.rsp = env->regs[R_ESP];
 179     regs.rbp = env->regs[R_EBP];
 180 #ifdef TARGET_X86_64
 181     regs.r8 = env->regs[8];
 182     regs.r9 = env->regs[9];
 183     regs.r10 = env->regs[10];
 184     regs.r11 = env->regs[11];
 185     regs.r12 = env->regs[12];
 186     regs.r13 = env->regs[13];
 187     regs.r14 = env->regs[14];
 188     regs.r15 = env->regs[15];
 189 #endif
 190
 191     regs.rflags = env->eflags;
 192     regs.rip = env->eip;
 193
 194     kvm_set_regs(kvm_context, env->cpu_index, &regs);
 195
 196     memset(&fpu, 0, sizeof fpu);
 197     fpu.fsw = env->fpus & ~(7 << 11);
 198     fpu.fsw |= (env->fpstt & 7) << 11;
 199     fpu.fcw = env->fpuc;
 200     for (i = 0; i < 8; ++i)
 201         fpu.ftwx |= (!env->fptags[i]) << i;
 202     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 203     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 204     fpu.mxcsr = env->mxcsr;
 205     kvm_set_fpu(kvm_context, env->cpu_index, &fpu);
 206
 207     memcpy(sregs.interrupt_bitmap, env->kvm_interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
 208
 209     if ((env->eflags & VM_MASK)) {
 210             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 211             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 212             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 213             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 214             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 215             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 216     } else {
 217             set_seg(&sregs.cs, &env->segs[R_CS]);
 218             set_seg(&sregs.ds, &env->segs[R_DS]);
 219             set_seg(&sregs.es, &env->segs[R_ES]);
 220             set_seg(&sregs.fs, &env->segs[R_FS]);
 221             set_seg(&sregs.gs, &env->segs[R_GS]);
 222             set_seg(&sregs.ss, &env->segs[R_SS]);
 223
 224             if (env->cr[0] & CR0_PE_MASK) {
 225                 /* force ss cpl to cs cpl */
 226                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 227                         (sregs.cs.selector & 3);
 228                 sregs.ss.dpl = sregs.ss.selector & 3;
 229             }
 230     }
 231
 232     set_seg(&sregs.tr, &env->tr);
 233     set_seg(&sregs.ldt, &env->ldt);
 234
 235     sregs.idt.limit = env->idt.limit;
 236     sregs.idt.base = env->idt.base;
 237     sregs.gdt.limit = env->gdt.limit;
 238     sregs.gdt.base = env->gdt.base;
 239
 240     sregs.cr0 = env->cr[0];
 241     sregs.cr2 = env->cr[2];
 242     sregs.cr3 = env->cr[3];
 243     sregs.cr4 = env->cr[4];
 244
 245     sregs.cr8 = cpu_get_apic_tpr(env);
 246     sregs.apic_base = cpu_get_apic_base(env);
 247
 248     sregs.efer = env->efer;
 249
 250     kvm_set_sregs(kvm_context, env->cpu_index, &sregs);
 251
 252     /* msrs */
 253     n = 0;
 254     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS,  env->sysenter_cs);
 255     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 256     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 257     if (kvm_has_msr_star)
 258         set_msr_entry(&msrs[n++], MSR_STAR,              env->star);
 259     set_msr_entry(&msrs[n++], MSR_IA32_TSC, env->tsc);
 260 #ifdef TARGET_X86_64
 261     if (lm_capable_kernel) {
 262         set_msr_entry(&msrs[n++], MSR_CSTAR,             env->cstar);
 263         set_msr_entry(&msrs[n++], MSR_KERNELGSBASE,      env->kernelgsbase);
 264         set_msr_entry(&msrs[n++], MSR_FMASK,             env->fmask);
 265         set_msr_entry(&msrs[n++], MSR_LSTAR  ,           env->lstar);
 266     }
 267 #endif
 268
 269     rc = kvm_set_msrs(kvm_context, env->cpu_index, msrs, n);
 270     if (rc == -1)
 271         perror("kvm_set_msrs FAILED");
 272 }
 273
 274 void kvm_save_mpstate(CPUState *env)
 275 {
 276 #ifdef KVM_CAP_MP_STATE
 277     int r;
 278     struct kvm_mp_state mp_state;
 279
 280     r = kvm_get_mpstate(kvm_context, env->cpu_index, &mp_state);
 281     if (r < 0)
 282         env->mp_state = -1;
 283     else
 284         env->mp_state = mp_state.mp_state;
 285 #endif
 286 }
 287
 288 void kvm_load_mpstate(CPUState *env)
 289 {
 290 #ifdef KVM_CAP_MP_STATE
 291     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 292
 293     /*
 294      * -1 indicates that the host did not support GET_MP_STATE ioctl,
 295      *  so don't touch it.
 296      */
 297     if (env->mp_state != -1)
 298         kvm_set_mpstate(kvm_context, env->cpu_index, &mp_state);
 299 #endif
 300 }
 301
 302 void kvm_arch_save_regs(CPUState *env)
 303 {
 304     struct kvm_regs regs;
 305     struct kvm_fpu fpu;
 306     struct kvm_sregs sregs;
 307     struct kvm_msr_entry msrs[MSR_COUNT];
 308     uint32_t hflags;
 309     uint32_t i, n, rc;
 310
 311     kvm_get_regs(kvm_context, env->cpu_index, &regs);
 312
 313     env->regs[R_EAX] = regs.rax;
 314     env->regs[R_EBX] = regs.rbx;
 315     env->regs[R_ECX] = regs.rcx;
 316     env->regs[R_EDX] = regs.rdx;
 317     env->regs[R_ESI] = regs.rsi;
 318     env->regs[R_EDI] = regs.rdi;
 319     env->regs[R_ESP] = regs.rsp;
 320     env->regs[R_EBP] = regs.rbp;
 321 #ifdef TARGET_X86_64
 322     env->regs[8] = regs.r8;
 323     env->regs[9] = regs.r9;
 324     env->regs[10] = regs.r10;
 325     env->regs[11] = regs.r11;
 326     env->regs[12] = regs.r12;
 327     env->regs[13] = regs.r13;
 328     env->regs[14] = regs.r14;
 329     env->regs[15] = regs.r15;
 330 #endif
 331
 332     env->eflags = regs.rflags;
 333     env->eip = regs.rip;
 334
 335     kvm_get_fpu(kvm_context, env->cpu_index, &fpu);
 336     env->fpstt = (fpu.fsw >> 11) & 7;
 337     env->fpus = fpu.fsw;
 338     env->fpuc = fpu.fcw;
 339     for (i = 0; i < 8; ++i)
 340         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 341     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 342     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 343     env->mxcsr = fpu.mxcsr;
 344
 345     kvm_get_sregs(kvm_context, env->cpu_index, &sregs);
 346
 347     memcpy(env->kvm_interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->kvm_interrupt_bitmap));
 348
 349     get_seg(&env->segs[R_CS], &sregs.cs);
 350     get_seg(&env->segs[R_DS], &sregs.ds);
 351     get_seg(&env->segs[R_ES], &sregs.es);
 352     get_seg(&env->segs[R_FS], &sregs.fs);
 353     get_seg(&env->segs[R_GS], &sregs.gs);
 354     get_seg(&env->segs[R_SS], &sregs.ss);
 355
 356     get_seg(&env->tr, &sregs.tr);
 357     get_seg(&env->ldt, &sregs.ldt);
 358
 359     env->idt.limit = sregs.idt.limit;
 360     env->idt.base = sregs.idt.base;
 361     env->gdt.limit = sregs.gdt.limit;
 362     env->gdt.base = sregs.gdt.base;
 363
 364     env->cr[0] = sregs.cr0;
 365     env->cr[2] = sregs.cr2;
 366     env->cr[3] = sregs.cr3;
 367     env->cr[4] = sregs.cr4;
 368
 369     cpu_set_apic_base(env, sregs.apic_base);
 370
 371     env->efer = sregs.efer;
 372     //cpu_set_apic_tpr(env, sregs.cr8);
 373
 374 #define HFLAG_COPY_MASK ~( \
 375                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 376                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 377                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 378                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 379
 380
 381
 382     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 383     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 384     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 385             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 386     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 387     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 388             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 389
 390     if (env->efer & MSR_EFER_LMA) {
 391         hflags |= HF_LMA_MASK;
 392     }
 393
 394     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 395         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 396     } else {
 397         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 398                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 399         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 400                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 401         if (!(env->cr[0] & CR0_PE_MASK) ||
 402                    (env->eflags & VM_MASK) ||
 403                    !(hflags & HF_CS32_MASK)) {
 404                 hflags |= HF_ADDSEG_MASK;
 405             } else {
 406                 hflags |= ((env->segs[R_DS].base |
 407                                 env->segs[R_ES].base |
 408                                 env->segs[R_SS].base) != 0) <<
 409                     HF_ADDSEG_SHIFT;
 410             }
 411     }
 412     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 413     env->cc_src = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 414     env->df = 1 - (2 * ((env->eflags >> 10) & 1));
 415     env->cc_op = CC_OP_EFLAGS;
 416     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 417
 418     /* msrs */
 419     n = 0;
 420     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 421     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 422     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 423     if (kvm_has_msr_star)
 424         msrs[n++].index = MSR_STAR;
 425     msrs[n++].index = MSR_IA32_TSC;
 426 #ifdef TARGET_X86_64
 427     if (lm_capable_kernel) {
 428         msrs[n++].index = MSR_CSTAR;
 429         msrs[n++].index = MSR_KERNELGSBASE;
 430         msrs[n++].index = MSR_FMASK;
 431         msrs[n++].index = MSR_LSTAR;
 432     }
 433 #endif
 434     rc = kvm_get_msrs(kvm_context, env->cpu_index, msrs, n);
 435     if (rc == -1) {
 436         perror("kvm_get_msrs FAILED");
 437     }
 438     else {
 439         n = rc; /* actual number of MSRs */
 440         for (i=0 ; i<n; i++) {
 441             if (get_msr_entry(&msrs[i], env))
 442                 return;
 443         }
 444     }
 445 }
 446
 447 static void host_cpuid(uint32_t function, uint32_t *eax, uint32_t *ebx,
 448                        uint32_t *ecx, uint32_t *edx)
 449 {
 450     uint32_t vec[4];
 451
 452 #ifdef __x86_64__
 453     asm volatile("cpuid"
 454                  : "=a"(vec[0]), "=b"(vec[1]),
 455                    "=c"(vec[2]), "=d"(vec[3])
 456                  : "0"(function) : "cc");
 457 #else
 458     asm volatile("pusha \n\t"
 459                  "cpuid \n\t"
 460                  "mov %%eax, 0(%1) \n\t"
 461                  "mov %%ebx, 4(%1) \n\t"
 462                  "mov %%ecx, 8(%1) \n\t"
 463                  "mov %%edx, 12(%1) \n\t"
 464                  "popa"
 465                  : : "a"(function), "S"(vec)
 466                  : "memory", "cc");
 467 #endif
 468
 469     if (eax)
 470         *eax = vec[0];
 471     if (ebx)
 472         *ebx = vec[1];
 473     if (ecx)
 474         *ecx = vec[2];
 475     if (edx)
 476         *edx = vec[3];
 477 }
 478
 479
 480 static void do_cpuid_ent(struct kvm_cpuid_entry *e, uint32_t function,
 481                          CPUState *env)
 482 {
 483     env->regs[R_EAX] = function;
 484     qemu_kvm_cpuid_on_env(env);
 485     e->function = function;
 486     e->eax = env->regs[R_EAX];
 487     e->ebx = env->regs[R_EBX];
 488     e->ecx = env->regs[R_ECX];
 489     e->edx = env->regs[R_EDX];
 490     if (function == 0x80000001) {
 491         uint32_t h_eax, h_edx;
 492
 493         host_cpuid(function, &h_eax, NULL, NULL, &h_edx);
 494
 495         // long mode
 496         if ((h_edx & 0x20000000) == 0 || !lm_capable_kernel)
 497             e->edx &= ~0x20000000u;
 498         // syscall
 499         if ((h_edx & 0x00000800) == 0)
 500             e->edx &= ~0x00000800u;
 501         // nx
 502         if ((h_edx & 0x00100000) == 0)
 503             e->edx &= ~0x00100000u;
 504         // svm
 505         if (e->ecx & 4)
 506             e->ecx &= ~4u;
 507     }
 508     // sysenter isn't supported on compatibility mode on AMD.  and syscall
 509     // isn't supported in compatibility mode on Intel.  so advertise the
 510     // actuall cpu, and say goodbye to migration between different vendors
 511     // is you use compatibility mode.
 512     if (function == 0) {
 513         uint32_t bcd[3];
 514
 515         host_cpuid(0, NULL, &bcd[0], &bcd[1], &bcd[2]);
 516         e->ebx = bcd[0];
 517         e->ecx = bcd[1];
 518         e->edx = bcd[2];
 519     }
 520     // "Hypervisor present" bit for Microsoft guests
 521     if (function == 1)
 522         e->ecx |= (1u << 31);
 523
 524     // 3dnow isn't properly emulated yet
 525     if (function == 0x80000001)
 526         e->edx &= ~0xc0000000;
 527 }
 528
 529 struct kvm_para_features {
 530         int cap;
 531         int feature;
 532 } para_features[] = {
 533 #ifdef KVM_CAP_CLOCKSOURCE
 534         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 535 #endif
 536 #ifdef KVM_CAP_NOP_IO_DELAY
 537         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 538 #endif
 539 #ifdef KVM_CAP_PV_MMU
 540         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 541 #endif
 542 #ifdef KVM_CAP_CR3_CACHE
 543         { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
 544 #endif
 545         { -1, -1 }
 546 };
 547
 548 static int get_para_features(kvm_context_t kvm_context)
 549 {
 550         int i, features = 0;
 551
 552         for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
 553                 if (kvm_check_extension(kvm_context, para_features[i].cap))
 554                         features |= (1 << para_features[i].feature);
 555         }
 556
 557         return features;
 558 }
 559
 560 int kvm_arch_qemu_init_env(CPUState *cenv)
 561 {
 562     struct kvm_cpuid_entry cpuid_ent[100];
 563 #ifdef KVM_CPUID_SIGNATURE
 564     struct kvm_cpuid_entry *pv_ent;
 565     uint32_t signature[3];
 566 #endif
 567     int cpuid_nent = 0;
 568     CPUState copy;
 569     uint32_t i, limit;
 570
 571     copy = *cenv;
 572
 573 #ifdef KVM_CPUID_SIGNATURE
 574     /* Paravirtualization CPUIDs */
 575     memcpy(signature, "KVMKVMKVM", 12);
 576     pv_ent = &cpuid_ent[cpuid_nent++];
 577     memset(pv_ent, 0, sizeof(*pv_ent));
 578     pv_ent->function = KVM_CPUID_SIGNATURE;
 579     pv_ent->eax = 0;
 580     pv_ent->ebx = signature[0];
 581     pv_ent->ecx = signature[1];
 582     pv_ent->edx = signature[2];
 583
 584     pv_ent = &cpuid_ent[cpuid_nent++];
 585     memset(pv_ent, 0, sizeof(*pv_ent));
 586     pv_ent->function = KVM_CPUID_FEATURES;
 587     pv_ent->eax = get_para_features(kvm_context);
 588 #endif
 589
 590     copy.regs[R_EAX] = 0;
 591     qemu_kvm_cpuid_on_env(&copy);
 592     limit = copy.regs[R_EAX];
 593
 594     for (i = 0; i <= limit; ++i)
 595         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
 596
 597     copy.regs[R_EAX] = 0x80000000;
 598     qemu_kvm_cpuid_on_env(&copy);
 599     limit = copy.regs[R_EAX];
 600
 601     for (i = 0x80000000; i <= limit; ++i)
 602         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, &copy);
 603
 604     kvm_setup_cpuid(kvm_context, cenv->cpu_index, cpuid_nent, cpuid_ent);
 605     return 0;
 606 }
 607
 608 int kvm_arch_halt(void *opaque, int vcpu)
 609 {
 610     CPUState *env = cpu_single_env;
 611
 612     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 613           (env->eflags & IF_MASK)) &&
 614         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 615             env->halted = 1;
 616             env->exception_index = EXCP_HLT;
 617     }
 618     return 1;
 619 }
 620
 621 void kvm_arch_pre_kvm_run(void *opaque, int vcpu)
 622 {
 623     CPUState *env = cpu_single_env;
 624
 625     if (!kvm_irqchip_in_kernel(kvm_context))
 626         kvm_set_cr8(kvm_context, vcpu, cpu_get_apic_tpr(env));
 627 }
 628
 629 void kvm_arch_post_kvm_run(void *opaque, int vcpu)
 630 {
 631     CPUState *env = qemu_kvm_cpu_env(vcpu);
 632     cpu_single_env = env;
 633
 634     env->eflags = kvm_get_interrupt_flag(kvm_context, vcpu)
 635         ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
 636
 637     cpu_set_apic_tpr(env, kvm_get_cr8(kvm_context, vcpu));
 638     cpu_set_apic_base(env, kvm_get_apic_base(kvm_context, vcpu));
 639 }
 640
 641 int kvm_arch_has_work(CPUState *env)
 642 {
 643     if (((env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT)) &&
 644          (env->eflags & IF_MASK)) ||
 645         (env->interrupt_request & CPU_INTERRUPT_NMI))
 646         return 1;
 647     return 0;
 648 }
 649
 650 int kvm_arch_try_push_interrupts(void *opaque)
 651 {
 652     CPUState *env = cpu_single_env;
 653     int r, irq;
 654
 655     if (kvm_is_ready_for_interrupt_injection(kvm_context, env->cpu_index) &&
 656         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 657         (env->eflags & IF_MASK)) {
 658             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 659             irq = cpu_get_pic_interrupt(env);
 660             if (irq >= 0) {
 661                 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
 662                 if (r < 0)
 663                     printf("cpu %d fail inject %x\n", env->cpu_index, irq);
 664             }
 665     }
 666
 667     return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
 668 }
 669
 670 int kvm_arch_try_push_nmi(void *opaque)
 671 {
 672     CPUState *env = cpu_single_env;
 673     int r;
 674
 675     if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
 676         return 0;
 677
 678     if (kvm_is_ready_for_nmi_injection(kvm_context, env->cpu_index)) {
 679         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 680         r = kvm_inject_nmi(kvm_context, env->cpu_index);
 681         if (r < 0)
 682             printf("cpu %d fail inject NMI\n", env->cpu_index);
 683     }
 684
 685     return (env->interrupt_request & CPU_INTERRUPT_NMI) != 0;
 686 }
 687
 688 void kvm_arch_update_regs_for_sipi(CPUState *env)
 689 {
 690     SegmentCache cs = env->segs[R_CS];
 691
 692     kvm_arch_save_regs(env);
 693     env->segs[R_CS] = cs;
 694     env->eip = 0;
 695     kvm_arch_load_regs(env);
 696 }
 697
 698 int handle_tpr_access(void *opaque, int vcpu,
 699                              uint64_t rip, int is_write)
 700 {
 701     kvm_tpr_access_report(cpu_single_env, rip, is_write);
 702     return 0;
 703 }
 704
 705 void kvm_arch_cpu_reset(CPUState *env)
 706 {
 707     kvm_arch_load_regs(env);
 708     if (env->cpu_index != 0) {
 709         if (kvm_irqchip_in_kernel(kvm_context)) {
 710 #ifdef KVM_CAP_MP_STATE
 711             kvm_reset_mpstate(kvm_context, env->cpu_index);
 712 #endif
 713         } else {
 714             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 715             env->halted = 1;
 716             env->exception_index = EXCP_HLT;
 717         }
 718     }
 719 }