Temporary workaround for ppc on ppc
[qemu-kvm/fedora.git] / qemu-kvm-x86.c
blob8e0f0b232e1f716cacd30e6a5b6ae86a679b0338
1 /*
2 * qemu/kvm integration, x86 specific code
4 * Copyright (C) 2006-2008 Qumranet Technologies
6 * Licensed under the terms of the GNU GPL version 2 or higher.
7 */
9 #include "config.h"
10 #include "config-host.h"
12 #include <string.h>
13 #include "hw/hw.h"
14 #include "gdbstub.h"
15 #include <sys/io.h>
17 #include "qemu-kvm.h"
18 #include <libkvm.h>
19 #include <pthread.h>
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
23 #define MSR_IA32_TSC 0x10
25 static struct kvm_msr_list *kvm_msr_list;
26 extern unsigned int kvm_shadow_memory;
27 static int kvm_has_msr_star;
28 static int kvm_has_vm_hsave_pa;
30 static int lm_capable_kernel;
32 int kvm_qemu_create_memory_alias(uint64_t phys_start,
33 uint64_t len,
34 uint64_t target_phys)
36 return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
39 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
41 return kvm_destroy_memory_alias(kvm_context, phys_start);
44 int kvm_arch_qemu_create_context(void)
46 int i;
47 struct utsname utsname;
49 uname(&utsname);
50 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
52 if (kvm_shadow_memory)
53 kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
55 kvm_msr_list = kvm_get_msr_list(kvm_context);
56 if (!kvm_msr_list)
57 return -1;
58 for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
59 if (kvm_msr_list->indices[i] == MSR_STAR)
60 kvm_has_msr_star = 1;
61 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
62 kvm_has_vm_hsave_pa = 1;
65 return 0;
68 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
69 uint64_t data)
71 entry->index = index;
72 entry->data = data;
75 /* returns 0 on success, non-0 on failure */
76 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
78 switch (entry->index) {
79 case MSR_IA32_SYSENTER_CS:
80 env->sysenter_cs = entry->data;
81 break;
82 case MSR_IA32_SYSENTER_ESP:
83 env->sysenter_esp = entry->data;
84 break;
85 case MSR_IA32_SYSENTER_EIP:
86 env->sysenter_eip = entry->data;
87 break;
88 case MSR_STAR:
89 env->star = entry->data;
90 break;
91 #ifdef TARGET_X86_64
92 case MSR_CSTAR:
93 env->cstar = entry->data;
94 break;
95 case MSR_KERNELGSBASE:
96 env->kernelgsbase = entry->data;
97 break;
98 case MSR_FMASK:
99 env->fmask = entry->data;
100 break;
101 case MSR_LSTAR:
102 env->lstar = entry->data;
103 break;
104 #endif
105 case MSR_IA32_TSC:
106 env->tsc = entry->data;
107 break;
108 case MSR_VM_HSAVE_PA:
109 env->vm_hsave = entry->data;
110 break;
111 default:
112 printf("Warning unknown msr index 0x%x\n", entry->index);
113 return 1;
115 return 0;
118 #ifdef TARGET_X86_64
119 #define MSR_COUNT 9
120 #else
121 #define MSR_COUNT 5
122 #endif
124 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
126 lhs->selector = rhs->selector;
127 lhs->base = rhs->base;
128 lhs->limit = rhs->limit;
129 lhs->type = 3;
130 lhs->present = 1;
131 lhs->dpl = 3;
132 lhs->db = 0;
133 lhs->s = 1;
134 lhs->l = 0;
135 lhs->g = 0;
136 lhs->avl = 0;
137 lhs->unusable = 0;
140 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
142 unsigned flags = rhs->flags;
143 lhs->selector = rhs->selector;
144 lhs->base = rhs->base;
145 lhs->limit = rhs->limit;
146 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
147 lhs->present = (flags & DESC_P_MASK) != 0;
148 lhs->dpl = rhs->selector & 3;
149 lhs->db = (flags >> DESC_B_SHIFT) & 1;
150 lhs->s = (flags & DESC_S_MASK) != 0;
151 lhs->l = (flags >> DESC_L_SHIFT) & 1;
152 lhs->g = (flags & DESC_G_MASK) != 0;
153 lhs->avl = (flags & DESC_AVL_MASK) != 0;
154 lhs->unusable = 0;
157 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
159 lhs->selector = rhs->selector;
160 lhs->base = rhs->base;
161 lhs->limit = rhs->limit;
162 lhs->flags =
163 (rhs->type << DESC_TYPE_SHIFT)
164 | (rhs->present * DESC_P_MASK)
165 | (rhs->dpl << DESC_DPL_SHIFT)
166 | (rhs->db << DESC_B_SHIFT)
167 | (rhs->s * DESC_S_MASK)
168 | (rhs->l << DESC_L_SHIFT)
169 | (rhs->g * DESC_G_MASK)
170 | (rhs->avl * DESC_AVL_MASK);
173 void kvm_arch_load_regs(CPUState *env)
175 struct kvm_regs regs;
176 struct kvm_fpu fpu;
177 struct kvm_sregs sregs;
178 struct kvm_msr_entry msrs[MSR_COUNT];
179 int rc, n, i;
181 regs.rax = env->regs[R_EAX];
182 regs.rbx = env->regs[R_EBX];
183 regs.rcx = env->regs[R_ECX];
184 regs.rdx = env->regs[R_EDX];
185 regs.rsi = env->regs[R_ESI];
186 regs.rdi = env->regs[R_EDI];
187 regs.rsp = env->regs[R_ESP];
188 regs.rbp = env->regs[R_EBP];
189 #ifdef TARGET_X86_64
190 regs.r8 = env->regs[8];
191 regs.r9 = env->regs[9];
192 regs.r10 = env->regs[10];
193 regs.r11 = env->regs[11];
194 regs.r12 = env->regs[12];
195 regs.r13 = env->regs[13];
196 regs.r14 = env->regs[14];
197 regs.r15 = env->regs[15];
198 #endif
200 regs.rflags = env->eflags;
201 regs.rip = env->eip;
203 kvm_set_regs(kvm_context, env->cpu_index, &regs);
205 memset(&fpu, 0, sizeof fpu);
206 fpu.fsw = env->fpus & ~(7 << 11);
207 fpu.fsw |= (env->fpstt & 7) << 11;
208 fpu.fcw = env->fpuc;
209 for (i = 0; i < 8; ++i)
210 fpu.ftwx |= (!env->fptags[i]) << i;
211 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
212 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
213 fpu.mxcsr = env->mxcsr;
214 kvm_set_fpu(kvm_context, env->cpu_index, &fpu);
216 memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
218 if ((env->eflags & VM_MASK)) {
219 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
220 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
221 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
222 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
223 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
224 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
225 } else {
226 set_seg(&sregs.cs, &env->segs[R_CS]);
227 set_seg(&sregs.ds, &env->segs[R_DS]);
228 set_seg(&sregs.es, &env->segs[R_ES]);
229 set_seg(&sregs.fs, &env->segs[R_FS]);
230 set_seg(&sregs.gs, &env->segs[R_GS]);
231 set_seg(&sregs.ss, &env->segs[R_SS]);
233 if (env->cr[0] & CR0_PE_MASK) {
234 /* force ss cpl to cs cpl */
235 sregs.ss.selector = (sregs.ss.selector & ~3) |
236 (sregs.cs.selector & 3);
237 sregs.ss.dpl = sregs.ss.selector & 3;
241 set_seg(&sregs.tr, &env->tr);
242 set_seg(&sregs.ldt, &env->ldt);
244 sregs.idt.limit = env->idt.limit;
245 sregs.idt.base = env->idt.base;
246 sregs.gdt.limit = env->gdt.limit;
247 sregs.gdt.base = env->gdt.base;
249 sregs.cr0 = env->cr[0];
250 sregs.cr2 = env->cr[2];
251 sregs.cr3 = env->cr[3];
252 sregs.cr4 = env->cr[4];
254 sregs.cr8 = cpu_get_apic_tpr(env);
255 sregs.apic_base = cpu_get_apic_base(env);
257 sregs.efer = env->efer;
259 kvm_set_sregs(kvm_context, env->cpu_index, &sregs);
261 /* msrs */
262 n = 0;
263 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
264 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
265 set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
266 if (kvm_has_msr_star)
267 set_msr_entry(&msrs[n++], MSR_STAR, env->star);
268 if (kvm_has_vm_hsave_pa)
269 set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
270 #ifdef TARGET_X86_64
271 if (lm_capable_kernel) {
272 set_msr_entry(&msrs[n++], MSR_CSTAR, env->cstar);
273 set_msr_entry(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
274 set_msr_entry(&msrs[n++], MSR_FMASK, env->fmask);
275 set_msr_entry(&msrs[n++], MSR_LSTAR , env->lstar);
277 #endif
279 rc = kvm_set_msrs(kvm_context, env->cpu_index, msrs, n);
280 if (rc == -1)
281 perror("kvm_set_msrs FAILED");
284 void kvm_load_tsc(CPUState *env)
286 int rc;
287 struct kvm_msr_entry msr;
289 set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
291 rc = kvm_set_msrs(kvm_context, env->cpu_index, &msr, 1);
292 if (rc == -1)
293 perror("kvm_set_tsc FAILED.\n");
296 void kvm_save_mpstate(CPUState *env)
298 #ifdef KVM_CAP_MP_STATE
299 int r;
300 struct kvm_mp_state mp_state;
302 r = kvm_get_mpstate(kvm_context, env->cpu_index, &mp_state);
303 if (r < 0)
304 env->mp_state = -1;
305 else
306 env->mp_state = mp_state.mp_state;
307 #endif
310 void kvm_load_mpstate(CPUState *env)
312 #ifdef KVM_CAP_MP_STATE
313 struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
316 * -1 indicates that the host did not support GET_MP_STATE ioctl,
317 * so don't touch it.
319 if (env->mp_state != -1)
320 kvm_set_mpstate(kvm_context, env->cpu_index, &mp_state);
321 #endif
324 void kvm_arch_save_regs(CPUState *env)
326 struct kvm_regs regs;
327 struct kvm_fpu fpu;
328 struct kvm_sregs sregs;
329 struct kvm_msr_entry msrs[MSR_COUNT];
330 uint32_t hflags;
331 uint32_t i, n, rc;
333 kvm_get_regs(kvm_context, env->cpu_index, &regs);
335 env->regs[R_EAX] = regs.rax;
336 env->regs[R_EBX] = regs.rbx;
337 env->regs[R_ECX] = regs.rcx;
338 env->regs[R_EDX] = regs.rdx;
339 env->regs[R_ESI] = regs.rsi;
340 env->regs[R_EDI] = regs.rdi;
341 env->regs[R_ESP] = regs.rsp;
342 env->regs[R_EBP] = regs.rbp;
343 #ifdef TARGET_X86_64
344 env->regs[8] = regs.r8;
345 env->regs[9] = regs.r9;
346 env->regs[10] = regs.r10;
347 env->regs[11] = regs.r11;
348 env->regs[12] = regs.r12;
349 env->regs[13] = regs.r13;
350 env->regs[14] = regs.r14;
351 env->regs[15] = regs.r15;
352 #endif
354 env->eflags = regs.rflags;
355 env->eip = regs.rip;
357 kvm_get_fpu(kvm_context, env->cpu_index, &fpu);
358 env->fpstt = (fpu.fsw >> 11) & 7;
359 env->fpus = fpu.fsw;
360 env->fpuc = fpu.fcw;
361 for (i = 0; i < 8; ++i)
362 env->fptags[i] = !((fpu.ftwx >> i) & 1);
363 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
364 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
365 env->mxcsr = fpu.mxcsr;
367 kvm_get_sregs(kvm_context, env->cpu_index, &sregs);
369 memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
371 get_seg(&env->segs[R_CS], &sregs.cs);
372 get_seg(&env->segs[R_DS], &sregs.ds);
373 get_seg(&env->segs[R_ES], &sregs.es);
374 get_seg(&env->segs[R_FS], &sregs.fs);
375 get_seg(&env->segs[R_GS], &sregs.gs);
376 get_seg(&env->segs[R_SS], &sregs.ss);
378 get_seg(&env->tr, &sregs.tr);
379 get_seg(&env->ldt, &sregs.ldt);
381 env->idt.limit = sregs.idt.limit;
382 env->idt.base = sregs.idt.base;
383 env->gdt.limit = sregs.gdt.limit;
384 env->gdt.base = sregs.gdt.base;
386 env->cr[0] = sregs.cr0;
387 env->cr[2] = sregs.cr2;
388 env->cr[3] = sregs.cr3;
389 env->cr[4] = sregs.cr4;
391 cpu_set_apic_base(env, sregs.apic_base);
393 env->efer = sregs.efer;
394 //cpu_set_apic_tpr(env, sregs.cr8);
396 #define HFLAG_COPY_MASK ~( \
397 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
398 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
399 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
400 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
404 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
405 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
406 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
407 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
408 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
409 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
410 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
412 if (env->efer & MSR_EFER_LMA) {
413 hflags |= HF_LMA_MASK;
416 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
417 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
418 } else {
419 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
420 (DESC_B_SHIFT - HF_CS32_SHIFT);
421 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
422 (DESC_B_SHIFT - HF_SS32_SHIFT);
423 if (!(env->cr[0] & CR0_PE_MASK) ||
424 (env->eflags & VM_MASK) ||
425 !(hflags & HF_CS32_MASK)) {
426 hflags |= HF_ADDSEG_MASK;
427 } else {
428 hflags |= ((env->segs[R_DS].base |
429 env->segs[R_ES].base |
430 env->segs[R_SS].base) != 0) <<
431 HF_ADDSEG_SHIFT;
434 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
436 /* msrs */
437 n = 0;
438 msrs[n++].index = MSR_IA32_SYSENTER_CS;
439 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
440 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
441 if (kvm_has_msr_star)
442 msrs[n++].index = MSR_STAR;
443 msrs[n++].index = MSR_IA32_TSC;
444 if (kvm_has_vm_hsave_pa)
445 msrs[n++].index = MSR_VM_HSAVE_PA;
446 #ifdef TARGET_X86_64
447 if (lm_capable_kernel) {
448 msrs[n++].index = MSR_CSTAR;
449 msrs[n++].index = MSR_KERNELGSBASE;
450 msrs[n++].index = MSR_FMASK;
451 msrs[n++].index = MSR_LSTAR;
453 #endif
454 rc = kvm_get_msrs(kvm_context, env->cpu_index, msrs, n);
455 if (rc == -1) {
456 perror("kvm_get_msrs FAILED");
458 else {
459 n = rc; /* actual number of MSRs */
460 for (i=0 ; i<n; i++) {
461 if (get_msr_entry(&msrs[i], env))
462 return;
467 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
468 uint32_t count, CPUState *env)
470 env->regs[R_EAX] = function;
471 env->regs[R_ECX] = count;
472 qemu_kvm_cpuid_on_env(env);
473 e->function = function;
474 e->flags = 0;
475 e->index = 0;
476 e->eax = env->regs[R_EAX];
477 e->ebx = env->regs[R_EBX];
478 e->ecx = env->regs[R_ECX];
479 e->edx = env->regs[R_EDX];
482 struct kvm_para_features {
483 int cap;
484 int feature;
485 } para_features[] = {
486 #ifdef KVM_CAP_CLOCKSOURCE
487 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
488 #endif
489 #ifdef KVM_CAP_NOP_IO_DELAY
490 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
491 #endif
492 #ifdef KVM_CAP_PV_MMU
493 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
494 #endif
495 #ifdef KVM_CAP_CR3_CACHE
496 { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
497 #endif
498 { -1, -1 }
501 static int get_para_features(kvm_context_t kvm_context)
503 int i, features = 0;
505 for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
506 if (kvm_check_extension(kvm_context, para_features[i].cap))
507 features |= (1 << para_features[i].feature);
510 return features;
513 int kvm_arch_qemu_init_env(CPUState *cenv)
515 struct kvm_cpuid_entry2 cpuid_ent[100];
516 #ifdef KVM_CPUID_SIGNATURE
517 struct kvm_cpuid_entry2 *pv_ent;
518 uint32_t signature[3];
519 #endif
520 int cpuid_nent = 0;
521 CPUState copy;
522 uint32_t i, j, limit;
524 copy = *cenv;
526 #ifdef KVM_CPUID_SIGNATURE
527 /* Paravirtualization CPUIDs */
528 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
529 pv_ent = &cpuid_ent[cpuid_nent++];
530 memset(pv_ent, 0, sizeof(*pv_ent));
531 pv_ent->function = KVM_CPUID_SIGNATURE;
532 pv_ent->eax = 0;
533 pv_ent->ebx = signature[0];
534 pv_ent->ecx = signature[1];
535 pv_ent->edx = signature[2];
537 pv_ent = &cpuid_ent[cpuid_nent++];
538 memset(pv_ent, 0, sizeof(*pv_ent));
539 pv_ent->function = KVM_CPUID_FEATURES;
540 pv_ent->eax = get_para_features(kvm_context);
541 #endif
543 copy.regs[R_EAX] = 0;
544 qemu_kvm_cpuid_on_env(&copy);
545 limit = copy.regs[R_EAX];
547 for (i = 0; i <= limit; ++i) {
548 if (i == 4 || i == 0xb || i == 0xd) {
549 for (j = 0; ; ++j) {
550 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
552 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
553 cpuid_ent[cpuid_nent].index = j;
555 cpuid_nent++;
557 if (i == 4 && copy.regs[R_EAX] == 0)
558 break;
559 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
560 break;
561 if (i == 0xd && copy.regs[R_EAX] == 0)
562 break;
564 } else
565 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
568 copy.regs[R_EAX] = 0x80000000;
569 qemu_kvm_cpuid_on_env(&copy);
570 limit = copy.regs[R_EAX];
572 for (i = 0x80000000; i <= limit; ++i)
573 do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
575 kvm_setup_cpuid2(kvm_context, cenv->cpu_index, cpuid_nent, cpuid_ent);
576 return 0;
579 int kvm_arch_halt(void *opaque, int vcpu)
581 CPUState *env = cpu_single_env;
583 if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
584 (env->eflags & IF_MASK)) &&
585 !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
586 env->halted = 1;
587 env->exception_index = EXCP_HLT;
589 return 1;
592 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
594 if (!kvm_irqchip_in_kernel(kvm_context))
595 kvm_set_cr8(kvm_context, env->cpu_index, cpu_get_apic_tpr(env));
598 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
600 int vcpu = env->cpu_index;
602 cpu_single_env = env;
604 env->eflags = kvm_get_interrupt_flag(kvm_context, vcpu)
605 ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
607 cpu_set_apic_tpr(env, kvm_get_cr8(kvm_context, vcpu));
608 cpu_set_apic_base(env, kvm_get_apic_base(kvm_context, vcpu));
611 int kvm_arch_has_work(CPUState *env)
613 if (((env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXIT)) &&
614 (env->eflags & IF_MASK)) ||
615 (env->interrupt_request & CPU_INTERRUPT_NMI))
616 return 1;
617 return 0;
620 int kvm_arch_try_push_interrupts(void *opaque)
622 CPUState *env = cpu_single_env;
623 int r, irq;
625 if (kvm_is_ready_for_interrupt_injection(kvm_context, env->cpu_index) &&
626 (env->interrupt_request & CPU_INTERRUPT_HARD) &&
627 (env->eflags & IF_MASK)) {
628 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
629 irq = cpu_get_pic_interrupt(env);
630 if (irq >= 0) {
631 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
632 if (r < 0)
633 printf("cpu %d fail inject %x\n", env->cpu_index, irq);
637 return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
640 #ifdef KVM_CAP_USER_NMI
641 void kvm_arch_push_nmi(void *opaque)
643 CPUState *env = cpu_single_env;
644 int r;
646 if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
647 return;
649 env->interrupt_request &= ~CPU_INTERRUPT_NMI;
650 r = kvm_inject_nmi(kvm_context, env->cpu_index);
651 if (r < 0)
652 printf("cpu %d fail inject NMI\n", env->cpu_index);
654 #endif /* KVM_CAP_USER_NMI */
656 void kvm_arch_update_regs_for_sipi(CPUState *env)
658 SegmentCache cs = env->segs[R_CS];
660 kvm_arch_save_regs(env);
661 env->segs[R_CS] = cs;
662 env->eip = 0;
663 kvm_arch_load_regs(env);
666 int handle_tpr_access(void *opaque, int vcpu,
667 uint64_t rip, int is_write)
669 kvm_tpr_access_report(cpu_single_env, rip, is_write);
670 return 0;
673 void kvm_arch_cpu_reset(CPUState *env)
675 kvm_arch_load_regs(env);
676 if (env->cpu_index != 0) {
677 if (kvm_irqchip_in_kernel(kvm_context)) {
678 #ifdef KVM_CAP_MP_STATE
679 kvm_reset_mpstate(kvm_context, env->cpu_index);
680 #endif
681 } else {
682 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
683 env->halted = 1;
684 env->exception_index = EXCP_HLT;
689 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
691 uint8_t int3 = 0xcc;
693 if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
694 cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
695 return -EINVAL;
696 return 0;
699 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
701 uint8_t int3;
703 if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
704 cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
705 return -EINVAL;
706 return 0;
709 #ifdef KVM_CAP_SET_GUEST_DEBUG
710 static struct {
711 target_ulong addr;
712 int len;
713 int type;
714 } hw_breakpoint[4];
716 static int nb_hw_breakpoint;
718 static int find_hw_breakpoint(target_ulong addr, int len, int type)
720 int n;
722 for (n = 0; n < nb_hw_breakpoint; n++)
723 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
724 (hw_breakpoint[n].len == len || len == -1))
725 return n;
726 return -1;
729 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
730 target_ulong len, int type)
732 switch (type) {
733 case GDB_BREAKPOINT_HW:
734 len = 1;
735 break;
736 case GDB_WATCHPOINT_WRITE:
737 case GDB_WATCHPOINT_ACCESS:
738 switch (len) {
739 case 1:
740 break;
741 case 2:
742 case 4:
743 case 8:
744 if (addr & (len - 1))
745 return -EINVAL;
746 break;
747 default:
748 return -EINVAL;
750 break;
751 default:
752 return -ENOSYS;
755 if (nb_hw_breakpoint == 4)
756 return -ENOBUFS;
758 if (find_hw_breakpoint(addr, len, type) >= 0)
759 return -EEXIST;
761 hw_breakpoint[nb_hw_breakpoint].addr = addr;
762 hw_breakpoint[nb_hw_breakpoint].len = len;
763 hw_breakpoint[nb_hw_breakpoint].type = type;
764 nb_hw_breakpoint++;
766 return 0;
769 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
770 target_ulong len, int type)
772 int n;
774 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
775 if (n < 0)
776 return -ENOENT;
778 nb_hw_breakpoint--;
779 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
781 return 0;
784 void kvm_arch_remove_all_hw_breakpoints(void)
786 nb_hw_breakpoint = 0;
789 static CPUWatchpoint hw_watchpoint;
791 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
793 int handle = 0;
794 int n;
796 if (arch_info->exception == 1) {
797 if (arch_info->dr6 & (1 << 14)) {
798 if (cpu_single_env->singlestep_enabled)
799 handle = 1;
800 } else {
801 for (n = 0; n < 4; n++)
802 if (arch_info->dr6 & (1 << n))
803 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
804 case 0x0:
805 handle = 1;
806 break;
807 case 0x1:
808 handle = 1;
809 cpu_single_env->watchpoint_hit = &hw_watchpoint;
810 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
811 hw_watchpoint.flags = BP_MEM_WRITE;
812 break;
813 case 0x3:
814 handle = 1;
815 cpu_single_env->watchpoint_hit = &hw_watchpoint;
816 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
817 hw_watchpoint.flags = BP_MEM_ACCESS;
818 break;
821 } else if (kvm_find_sw_breakpoint(arch_info->pc))
822 handle = 1;
824 if (!handle)
825 kvm_update_guest_debug(cpu_single_env,
826 (arch_info->exception == 1) ?
827 KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
829 return handle;
832 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
834 const uint8_t type_code[] = {
835 [GDB_BREAKPOINT_HW] = 0x0,
836 [GDB_WATCHPOINT_WRITE] = 0x1,
837 [GDB_WATCHPOINT_ACCESS] = 0x3
839 const uint8_t len_code[] = {
840 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
842 int n;
844 if (!TAILQ_EMPTY(&kvm_sw_breakpoints))
845 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
847 if (nb_hw_breakpoint > 0) {
848 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
849 dbg->arch.debugreg[7] = 0x0600;
850 for (n = 0; n < nb_hw_breakpoint; n++) {
851 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
852 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
853 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
854 (len_code[hw_breakpoint[n].len] << (18 + n*4));
858 #endif
860 void kvm_arch_do_ioperm(void *_data)
862 struct ioperm_data *data = _data;
863 ioperm(data->start_port, data->num, data->turn_on);
866 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
867 int reg)
869 return kvm_get_supported_cpuid(kvm_context, function, reg);