Fix 32-bit overflow in parallels image support
[qemu-kvm/fedora.git] / hw / sh_intc.h
blobc117d6fb8c0bf6fe8468555233a46b9599c7c77d
1 #ifndef __SH_INTC_H__
2 #define __SH_INTC_H__
4 #include "qemu-common.h"
5 #include "irq.h"
7 typedef unsigned char intc_enum;
9 struct intc_vect {
10 intc_enum enum_id;
11 unsigned short vect;
14 #define INTC_VECT(enum_id, vect) { enum_id, vect }
16 struct intc_group {
17 intc_enum enum_id;
18 intc_enum enum_ids[32];
21 #define INTC_GROUP(enum_id, ...) { enum_id, { __VA_ARGS__ } }
23 struct intc_mask_reg {
24 unsigned long set_reg, clr_reg, reg_width;
25 intc_enum enum_ids[32];
26 unsigned long value;
29 struct intc_prio_reg {
30 unsigned long set_reg, clr_reg, reg_width, field_width;
31 intc_enum enum_ids[16];
32 unsigned long value;
35 #define _INTC_ARRAY(a) a, ARRAY_SIZE(a)
37 struct intc_source {
38 unsigned short vect;
39 intc_enum next_enum_id;
41 int asserted; /* emulates the interrupt signal line from device to intc */
42 int enable_count;
43 int enable_max;
44 int pending; /* emulates the result of signal and masking */
45 struct intc_desc *parent;
48 struct intc_desc {
49 qemu_irq *irqs;
50 struct intc_source *sources;
51 int nr_sources;
52 struct intc_mask_reg *mask_regs;
53 int nr_mask_regs;
54 struct intc_prio_reg *prio_regs;
55 int nr_prio_regs;
56 int iomemtype;
57 int pending; /* number of interrupt sources that has pending set */
60 int sh_intc_get_pending_vector(struct intc_desc *desc, int imask);
61 struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id);
62 void sh_intc_toggle_source(struct intc_source *source,
63 int enable_adj, int assert_adj);
65 void sh_intc_register_sources(struct intc_desc *desc,
66 struct intc_vect *vectors,
67 int nr_vectors,
68 struct intc_group *groups,
69 int nr_groups);
71 int sh_intc_init(struct intc_desc *desc,
72 int nr_sources,
73 struct intc_mask_reg *mask_regs,
74 int nr_mask_regs,
75 struct intc_prio_reg *prio_regs,
76 int nr_prio_regs);
78 void sh_intc_set_irl(void *opaque, int n, int level);
80 #endif /* __SH_INTC_H__ */