hw/sbi.c

   1 /*
   2  * QEMU Sparc SBI interrupt controller emulation
   3  *
   4  * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "console.h"
  27
  28 //#define DEBUG_IRQ
  29
  30 #ifdef DEBUG_IRQ
  31 #define DPRINTF(fmt, ...)                                       \
  32     do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
  33 #else
  34 #define DPRINTF(fmt, ...)
  35 #endif
  36
  37 #define MAX_CPUS 16
  38
  39 #define SBI_NREGS 16
  40
  41 typedef struct SBIState {
  42     uint32_t regs[SBI_NREGS];
  43     uint32_t intreg_pending[MAX_CPUS];
  44     qemu_irq *cpu_irqs[MAX_CPUS];
  45     uint32_t pil_out[MAX_CPUS];
  46 } SBIState;
  47
  48 #define SBI_SIZE (SBI_NREGS * 4)
  49
  50 static void sbi_set_irq(void *opaque, int irq, int level)
  51 {
  52 }
  53
  54 static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level)
  55 {
  56 }
  57
  58 static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
  59 {
  60     SBIState *s = opaque;
  61     uint32_t saddr, ret;
  62
  63     saddr = addr >> 2;
  64     switch (saddr) {
  65     default:
  66         ret = s->regs[saddr];
  67         break;
  68     }
  69     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
  70
  71     return ret;
  72 }
  73
  74 static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  75 {
  76     SBIState *s = opaque;
  77     uint32_t saddr;
  78
  79     saddr = addr >> 2;
  80     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
  81     switch (saddr) {
  82     default:
  83         s->regs[saddr] = val;
  84         break;
  85     }
  86 }
  87
  88 static CPUReadMemoryFunc *sbi_mem_read[3] = {
  89     NULL,
  90     NULL,
  91     sbi_mem_readl,
  92 };
  93
  94 static CPUWriteMemoryFunc *sbi_mem_write[3] = {
  95     NULL,
  96     NULL,
  97     sbi_mem_writel,
  98 };
  99
 100 static void sbi_save(QEMUFile *f, void *opaque)
 101 {
 102     SBIState *s = opaque;
 103     unsigned int i;
 104
 105     for (i = 0; i < MAX_CPUS; i++) {
 106         qemu_put_be32s(f, &s->intreg_pending[i]);
 107     }
 108 }
 109
 110 static int sbi_load(QEMUFile *f, void *opaque, int version_id)
 111 {
 112     SBIState *s = opaque;
 113     unsigned int i;
 114
 115     if (version_id != 1)
 116         return -EINVAL;
 117
 118     for (i = 0; i < MAX_CPUS; i++) {
 119         qemu_get_be32s(f, &s->intreg_pending[i]);
 120     }
 121
 122     return 0;
 123 }
 124
 125 static void sbi_reset(void *opaque)
 126 {
 127     SBIState *s = opaque;
 128     unsigned int i;
 129
 130     for (i = 0; i < MAX_CPUS; i++) {
 131         s->intreg_pending[i] = 0;
 132     }
 133 }
 134
 135 void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
 136                qemu_irq **parent_irq)
 137 {
 138     unsigned int i;
 139     int sbi_io_memory;
 140     SBIState *s;
 141
 142     s = qemu_mallocz(sizeof(SBIState));
 143
 144     for (i = 0; i < MAX_CPUS; i++) {
 145         s->cpu_irqs[i] = parent_irq[i];
 146     }
 147
 148     sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s);
 149     cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
 150
 151     register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
 152     qemu_register_reset(sbi_reset, s);
 153     *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
 154     *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
 155     sbi_reset(s);
 156
 157     return s;
 158 }