hw/iommu.c

   1 /*
   2  * QEMU SPARC iommu emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sun4m.h"
  26 #include "sysbus.h"
  27
  28 /* debug iommu */
  29 //#define DEBUG_IOMMU
  30
  31 #ifdef DEBUG_IOMMU
  32 #define DPRINTF(fmt, ...)                                       \
  33     do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
  34 #else
  35 #define DPRINTF(fmt, ...)
  36 #endif
  37
  38 #define IOMMU_NREGS         (4*4096/4)
  39 #define IOMMU_CTRL          (0x0000 >> 2)
  40 #define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
  41 #define IOMMU_CTRL_VERS     0x0f000000 /* Version */
  42 #define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
  43 #define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
  44 #define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
  45 #define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
  46 #define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
  47 #define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
  48 #define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
  49 #define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
  50 #define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
  51 #define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
  52 #define IOMMU_CTRL_MASK     0x0000001d
  53
  54 #define IOMMU_BASE          (0x0004 >> 2)
  55 #define IOMMU_BASE_MASK     0x07fffc00
  56
  57 #define IOMMU_TLBFLUSH      (0x0014 >> 2)
  58 #define IOMMU_TLBFLUSH_MASK 0xffffffff
  59
  60 #define IOMMU_PGFLUSH       (0x0018 >> 2)
  61 #define IOMMU_PGFLUSH_MASK  0xffffffff
  62
  63 #define IOMMU_AFSR          (0x1000 >> 2)
  64 #define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
  65 #define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
  66                                           transaction */
  67 #define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
  68                                           12.8 us. */
  69 #define IOMMU_AFSR_BE       0x10000000 /* Write access received error
  70                                           acknowledge */
  71 #define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
  72 #define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
  73 #define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
  74                                           hardware */
  75 #define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
  76 #define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
  77 #define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
  78 #define IOMMU_AFSR_MASK     0xff0fffff
  79
  80 #define IOMMU_AFAR          (0x1004 >> 2)
  81
  82 #define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
  83 #define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
  84 #define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
  85 #define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
  86 #define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
  87 #define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
  88 #define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
  89 #define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
  90 #define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
  91 #define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
  92 #define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
  93 #define IOMMU_AER_MASK      0x801f000f
  94
  95 #define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
  96 #define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
  97 #define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
  98 #define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
  99 #define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
 100                                           bypass enabled */
 101 #define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
 102 #define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
 103 #define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
 104                                           produced by this device as pure
 105                                           physical. */
 106 #define IOMMU_SBCFG_MASK    0x00010003
 107
 108 #define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
 109 #define IOMMU_ARBEN_MASK    0x001f0000
 110 #define IOMMU_MID           0x00000008
 111
 112 #define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
 113 #define IOMMU_MASK_ID_MASK  0x00ffffff
 114
 115 #define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
 116 #define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */
 117
 118 /* The format of an iopte in the page tables */
 119 #define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
 120 #define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
 121                                           Viking/MXCC) */
 122 #define IOPTE_WRITE         0x00000004 /* Writeable */
 123 #define IOPTE_VALID         0x00000002 /* IOPTE is valid */
 124 #define IOPTE_WAZ           0x00000001 /* Write as zeros */
 125
 126 #define IOMMU_PAGE_SHIFT    12
 127 #define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)
 128 #define IOMMU_PAGE_MASK     ~(IOMMU_PAGE_SIZE - 1)
 129
 130 typedef struct IOMMUState {
 131     SysBusDevice busdev;
 132     uint32_t regs[IOMMU_NREGS];
 133     target_phys_addr_t iostart;
 134     uint32_t version;
 135     qemu_irq irq;
 136 } IOMMUState;
 137
 138 static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
 139 {
 140     IOMMUState *s = opaque;
 141     target_phys_addr_t saddr;
 142     uint32_t ret;
 143
 144     saddr = addr >> 2;
 145     switch (saddr) {
 146     default:
 147         ret = s->regs[saddr];
 148         break;
 149     case IOMMU_AFAR:
 150     case IOMMU_AFSR:
 151         ret = s->regs[saddr];
 152         qemu_irq_lower(s->irq);
 153         break;
 154     }
 155     DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
 156     return ret;
 157 }
 158
 159 static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
 160                              uint32_t val)
 161 {
 162     IOMMUState *s = opaque;
 163     target_phys_addr_t saddr;
 164
 165     saddr = addr >> 2;
 166     DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
 167     switch (saddr) {
 168     case IOMMU_CTRL:
 169         switch (val & IOMMU_CTRL_RNGE) {
 170         case IOMMU_RNGE_16MB:
 171             s->iostart = 0xffffffffff000000ULL;
 172             break;
 173         case IOMMU_RNGE_32MB:
 174             s->iostart = 0xfffffffffe000000ULL;
 175             break;
 176         case IOMMU_RNGE_64MB:
 177             s->iostart = 0xfffffffffc000000ULL;
 178             break;
 179         case IOMMU_RNGE_128MB:
 180             s->iostart = 0xfffffffff8000000ULL;
 181             break;
 182         case IOMMU_RNGE_256MB:
 183             s->iostart = 0xfffffffff0000000ULL;
 184             break;
 185         case IOMMU_RNGE_512MB:
 186             s->iostart = 0xffffffffe0000000ULL;
 187             break;
 188         case IOMMU_RNGE_1GB:
 189             s->iostart = 0xffffffffc0000000ULL;
 190             break;
 191         default:
 192         case IOMMU_RNGE_2GB:
 193             s->iostart = 0xffffffff80000000ULL;
 194             break;
 195         }
 196         DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
 197         s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
 198         break;
 199     case IOMMU_BASE:
 200         s->regs[saddr] = val & IOMMU_BASE_MASK;
 201         break;
 202     case IOMMU_TLBFLUSH:
 203         DPRINTF("tlb flush %x\n", val);
 204         s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
 205         break;
 206     case IOMMU_PGFLUSH:
 207         DPRINTF("page flush %x\n", val);
 208         s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
 209         break;
 210     case IOMMU_AFAR:
 211         s->regs[saddr] = val;
 212         qemu_irq_lower(s->irq);
 213         break;
 214     case IOMMU_AER:
 215         s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
 216         break;
 217     case IOMMU_AFSR:
 218         s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
 219         qemu_irq_lower(s->irq);
 220         break;
 221     case IOMMU_SBCFG0:
 222     case IOMMU_SBCFG1:
 223     case IOMMU_SBCFG2:
 224     case IOMMU_SBCFG3:
 225         s->regs[saddr] = val & IOMMU_SBCFG_MASK;
 226         break;
 227     case IOMMU_ARBEN:
 228         // XXX implement SBus probing: fault when reading unmapped
 229         // addresses, fault cause and address stored to MMU/IOMMU
 230         s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
 231         break;
 232     case IOMMU_MASK_ID:
 233         s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
 234         break;
 235     default:
 236         s->regs[saddr] = val;
 237         break;
 238     }
 239 }
 240
 241 static CPUReadMemoryFunc *iommu_mem_read[3] = {
 242     NULL,
 243     NULL,
 244     iommu_mem_readl,
 245 };
 246
 247 static CPUWriteMemoryFunc *iommu_mem_write[3] = {
 248     NULL,
 249     NULL,
 250     iommu_mem_writel,
 251 };
 252
 253 static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
 254 {
 255     uint32_t ret;
 256     target_phys_addr_t iopte;
 257 #ifdef DEBUG_IOMMU
 258     target_phys_addr_t pa = addr;
 259 #endif
 260
 261     iopte = s->regs[IOMMU_BASE] << 4;
 262     addr &= ~s->iostart;
 263     iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
 264     cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
 265     tswap32s(&ret);
 266     DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
 267             ", *pte = %x\n", pa, iopte, ret);
 268
 269     return ret;
 270 }
 271
 272 static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
 273                                              uint32_t pte)
 274 {
 275     uint32_t tmppte;
 276     target_phys_addr_t pa;
 277
 278     tmppte = pte;
 279     pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
 280     DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
 281             " (iopte = %x)\n", addr, pa, tmppte);
 282
 283     return pa;
 284 }
 285
 286 static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
 287                            int is_write)
 288 {
 289     DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
 290     s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
 291         IOMMU_AFSR_FAV;
 292     if (!is_write)
 293         s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
 294     s->regs[IOMMU_AFAR] = addr;
 295     qemu_irq_raise(s->irq);
 296 }
 297
 298 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
 299                            uint8_t *buf, int len, int is_write)
 300 {
 301     int l;
 302     uint32_t flags;
 303     target_phys_addr_t page, phys_addr;
 304
 305     while (len > 0) {
 306         page = addr & IOMMU_PAGE_MASK;
 307         l = (page + IOMMU_PAGE_SIZE) - addr;
 308         if (l > len)
 309             l = len;
 310         flags = iommu_page_get_flags(opaque, page);
 311         if (!(flags & IOPTE_VALID)) {
 312             iommu_bad_addr(opaque, page, is_write);
 313             return;
 314         }
 315         phys_addr = iommu_translate_pa(addr, flags);
 316         if (is_write) {
 317             if (!(flags & IOPTE_WRITE)) {
 318                 iommu_bad_addr(opaque, page, is_write);
 319                 return;
 320             }
 321             cpu_physical_memory_write(phys_addr, buf, l);
 322         } else {
 323             cpu_physical_memory_read(phys_addr, buf, l);
 324         }
 325         len -= l;
 326         buf += l;
 327         addr += l;
 328     }
 329 }
 330
 331 static void iommu_save(QEMUFile *f, void *opaque)
 332 {
 333     IOMMUState *s = opaque;
 334     int i;
 335
 336     for (i = 0; i < IOMMU_NREGS; i++)
 337         qemu_put_be32s(f, &s->regs[i]);
 338     qemu_put_be64s(f, &s->iostart);
 339 }
 340
 341 static int iommu_load(QEMUFile *f, void *opaque, int version_id)
 342 {
 343     IOMMUState *s = opaque;
 344     int i;
 345
 346     if (version_id != 2)
 347         return -EINVAL;
 348
 349     for (i = 0; i < IOMMU_NREGS; i++)
 350         qemu_get_be32s(f, &s->regs[i]);
 351     qemu_get_be64s(f, &s->iostart);
 352
 353     return 0;
 354 }
 355
 356 static void iommu_reset(void *opaque)
 357 {
 358     IOMMUState *s = opaque;
 359
 360     memset(s->regs, 0, IOMMU_NREGS * 4);
 361     s->iostart = 0;
 362     s->regs[IOMMU_CTRL] = s->version;
 363     s->regs[IOMMU_ARBEN] = IOMMU_MID;
 364     s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
 365     s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
 366     s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
 367 }
 368
 369 void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
 370 {
 371     DeviceState *dev;
 372     SysBusDevice *s;
 373     IOMMUState *d;
 374
 375     dev = qdev_create(NULL, "iommu");
 376     qdev_prop_set_uint32(dev, "version", version);
 377     qdev_init(dev);
 378     s = sysbus_from_qdev(dev);
 379     sysbus_connect_irq(s, 0, irq);
 380     sysbus_mmio_map(s, 0, addr);
 381
 382     d = FROM_SYSBUS(IOMMUState, s);
 383
 384     return d;
 385 }
 386
 387 static void iommu_init1(SysBusDevice *dev)
 388 {
 389     IOMMUState *s = FROM_SYSBUS(IOMMUState, dev);
 390     int io;
 391
 392     sysbus_init_irq(dev, &s->irq);
 393
 394     io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s);
 395     sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io);
 396
 397     register_savevm("iommu", -1, 2, iommu_save, iommu_load, s);
 398     qemu_register_reset(iommu_reset, s);
 399     iommu_reset(s);
 400 }
 401
 402 static SysBusDeviceInfo iommu_info = {
 403     .init = iommu_init1,
 404     .qdev.name  = "iommu",
 405     .qdev.size  = sizeof(IOMMUState),
 406     .qdev.props = (Property[]) {
 407         {
 408             .name = "version",
 409             .info = &qdev_prop_hex32,
 410             .offset = offsetof(IOMMUState, version),
 411         },
 412         {/* end of property list */}
 413     }
 414 };
 415
 416 static void iommu_register_devices(void)
 417 {
 418     sysbus_register_withprop(&iommu_info);
 419 }
 420
 421 device_init(iommu_register_devices)