Fix 32-bit overflow in parallels image support
[qemu-kvm/fedora.git] / hw / grackle_pci.c
blobfde9fead3bda2bfeb8386a5009a72a53b63e1854
1 /*
2 * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
4 * Copyright (c) 2006-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
26 #include "hw.h"
27 #include "ppc_mac.h"
28 #include "pci.h"
30 /* debug Grackle */
31 //#define DEBUG_GRACKLE
33 #ifdef DEBUG_GRACKLE
34 #define GRACKLE_DPRINTF(fmt, ...) \
35 do { printf("GRACKLE: " fmt , ## __VA_ARGS__); } while (0)
36 #else
37 #define GRACKLE_DPRINTF(fmt, ...)
38 #endif
40 typedef target_phys_addr_t pci_addr_t;
41 #include "pci_host.h"
43 typedef PCIHostState GrackleState;
45 static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
46 uint32_t val)
48 GrackleState *s = opaque;
50 GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
51 val);
52 #ifdef TARGET_WORDS_BIGENDIAN
53 val = bswap32(val);
54 #endif
55 s->config_reg = val;
58 static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
60 GrackleState *s = opaque;
61 uint32_t val;
63 val = s->config_reg;
64 #ifdef TARGET_WORDS_BIGENDIAN
65 val = bswap32(val);
66 #endif
67 GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
68 val);
69 return val;
72 static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
73 &pci_grackle_config_writel,
74 &pci_grackle_config_writel,
75 &pci_grackle_config_writel,
78 static CPUReadMemoryFunc *pci_grackle_config_read[] = {
79 &pci_grackle_config_readl,
80 &pci_grackle_config_readl,
81 &pci_grackle_config_readl,
84 static CPUWriteMemoryFunc *pci_grackle_write[] = {
85 &pci_host_data_writeb,
86 &pci_host_data_writew,
87 &pci_host_data_writel,
90 static CPUReadMemoryFunc *pci_grackle_read[] = {
91 &pci_host_data_readb,
92 &pci_host_data_readw,
93 &pci_host_data_readl,
96 /* Don't know if this matches real hardware, but it agrees with OHW. */
97 static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
99 return (irq_num + (pci_dev->devfn >> 3)) & 3;
102 static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
104 GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
105 qemu_set_irq(pic[irq_num + 0x15], level);
108 static void pci_grackle_save(QEMUFile* f, void *opaque)
110 PCIDevice *d = opaque;
112 pci_device_save(d, f);
115 static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id)
117 PCIDevice *d = opaque;
119 if (version_id != 1)
120 return -EINVAL;
122 return pci_device_load(d, f);
125 static void pci_grackle_reset(void *opaque)
129 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
131 GrackleState *s;
132 PCIDevice *d;
133 int pci_mem_config, pci_mem_data;
135 s = qemu_mallocz(sizeof(GrackleState));
136 s->bus = pci_register_bus(NULL, "pci",
137 pci_grackle_set_irq, pci_grackle_map_irq,
138 pic, 0, 4);
140 pci_mem_config = cpu_register_io_memory(pci_grackle_config_read,
141 pci_grackle_config_write, s);
142 pci_mem_data = cpu_register_io_memory(pci_grackle_read,
143 pci_grackle_write, s);
144 cpu_register_physical_memory(base, 0x1000, pci_mem_config);
145 cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
146 d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
147 0, NULL, NULL);
148 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
149 pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
150 d->config[0x08] = 0x00; // revision
151 d->config[0x09] = 0x01;
152 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
153 d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
155 #if 0
156 /* PCI2PCI bridge same values as PearPC - check this */
157 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
158 pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
159 d->config[0x08] = 0x02; // revision
160 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
161 d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
163 d->config[0x18] = 0x0; // primary_bus
164 d->config[0x19] = 0x1; // secondary_bus
165 d->config[0x1a] = 0x1; // subordinate_bus
166 d->config[0x1c] = 0x10; // io_base
167 d->config[0x1d] = 0x20; // io_limit
169 d->config[0x20] = 0x80; // memory_base
170 d->config[0x21] = 0x80;
171 d->config[0x22] = 0x90; // memory_limit
172 d->config[0x23] = 0x80;
174 d->config[0x24] = 0x00; // prefetchable_memory_base
175 d->config[0x25] = 0x84;
176 d->config[0x26] = 0x00; // prefetchable_memory_limit
177 d->config[0x27] = 0x85;
178 #endif
179 register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);
180 qemu_register_reset(pci_grackle_reset, d);
181 pci_grackle_reset(d);
183 return s->bus;