?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Make binary stripping conditional (Riku Voipio)
[qemu-kvm/fedora.git] / target-ppc / helper.c
blob027c8e7b19c3245d540cae47eec52ddae1a3ce48
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "helper_regs.h"
31 #include "qemu-common.h"
32 #define KVM_UPSTREAM
33 #include "kvm.h"
34
35 //#define DEBUG_MMU
36 //#define DEBUG_BATS
37 //#define DEBUG_SLB
38 //#define DEBUG_SOFTWARE_TLB
39 //#define DUMP_PAGE_TABLES
40 //#define DEBUG_EXCEPTIONS
41 //#define FLUSH_ALL_TLBS
42
43 #ifdef DEBUG_MMU
44 # define LOG_MMU(...) qemu_log(__VA_ARGS__)
45 # define LOG_MMU_STATE(env) log_cpu_state((env), 0)
46 #else
47 # define LOG_MMU(...) do { } while (0)
48 # define LOG_MMU_STATE(...) do { } while (0)
49 #endif
50
51
52 #ifdef DEBUG_SOFTWARE_TLB
53 # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
54 #else
55 # define LOG_SWTLB(...) do { } while (0)
56 #endif
57
58 #ifdef DEBUG_BATS
59 # define LOG_BATS(...) qemu_log(__VA_ARGS__)
60 #else
61 # define LOG_BATS(...) do { } while (0)
62 #endif
63
64 #ifdef DEBUG_SLB
65 # define LOG_SLB(...) qemu_log(__VA_ARGS__)
66 #else
67 # define LOG_SLB(...) do { } while (0)
68 #endif
69
70 #ifdef DEBUG_EXCEPTIONS
71 # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
72 #else
73 # define LOG_EXCP(...) do { } while (0)
74 #endif
75
76
77 /*****************************************************************************/
78 /* PowerPC MMU emulation */
79
80 #if defined(CONFIG_USER_ONLY)
81 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
82 int mmu_idx, int is_softmmu)
83 {
84 int exception, error_code;
85
86 if (rw == 2) {
87 exception = POWERPC_EXCP_ISI;
88 error_code = 0x40000000;
89 } else {
90 exception = POWERPC_EXCP_DSI;
91 error_code = 0x40000000;
92 if (rw)
93 error_code |= 0x02000000;
94 env->spr[SPR_DAR] = address;
95 env->spr[SPR_DSISR] = error_code;
96 }
97 env->exception_index = exception;
98 env->error_code = error_code;
99
100 return 1;
101 }
102
103 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
104 {
105 return addr;
106 }
107
108 #else
109 /* Common routines used by software and hardware TLBs emulation */
110 static always_inline int pte_is_valid (target_ulong pte0)
111 {
112 return pte0 & 0x80000000 ? 1 : 0;
113 }
114
115 static always_inline void pte_invalidate (target_ulong *pte0)
116 {
117 *pte0 &= ~0x80000000;
118 }
119
120 #if defined(TARGET_PPC64)
121 static always_inline int pte64_is_valid (target_ulong pte0)
122 {
123 return pte0 & 0x0000000000000001ULL ? 1 : 0;
124 }
125
126 static always_inline void pte64_invalidate (target_ulong *pte0)
127 {
128 *pte0 &= ~0x0000000000000001ULL;
129 }
130 #endif
131
132 #define PTE_PTEM_MASK 0x7FFFFFBF
133 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
134 #if defined(TARGET_PPC64)
135 #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
136 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
137 #endif
138
139 static always_inline int pp_check (int key, int pp, int nx)
140 {
141 int access;
142
143 /* Compute access rights */
144 /* When pp is 3/7, the result is undefined. Set it to noaccess */
145 access = 0;
146 if (key == 0) {
147 switch (pp) {
148 case 0x0:
149 case 0x1:
150 case 0x2:
151 access |= PAGE_WRITE;
152 /* No break here */
153 case 0x3:
154 case 0x6:
155 access |= PAGE_READ;
156 break;
157 }
158 } else {
159 switch (pp) {
160 case 0x0:
161 case 0x6:
162 access = 0;
163 break;
164 case 0x1:
165 case 0x3:
166 access = PAGE_READ;
167 break;
168 case 0x2:
169 access = PAGE_READ | PAGE_WRITE;
170 break;
171 }
172 }
173 if (nx == 0)
174 access |= PAGE_EXEC;
175
176 return access;
177 }
178
179 static always_inline int check_prot (int prot, int rw, int access_type)
180 {
181 int ret;
182
183 if (access_type == ACCESS_CODE) {
184 if (prot & PAGE_EXEC)
185 ret = 0;
186 else
187 ret = -2;
188 } else if (rw) {
189 if (prot & PAGE_WRITE)
190 ret = 0;
191 else
192 ret = -2;
193 } else {
194 if (prot & PAGE_READ)
195 ret = 0;
196 else
197 ret = -2;
198 }
199
200 return ret;
201 }
202
203 static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
204 target_ulong pte0, target_ulong pte1,
205 int h, int rw, int type)
206 {
207 target_ulong ptem, mmask;
208 int access, ret, pteh, ptev, pp;
209
210 access = 0;
211 ret = -1;
212 /* Check validity and table match */
213 #if defined(TARGET_PPC64)
214 if (is_64b) {
215 ptev = pte64_is_valid(pte0);
216 pteh = (pte0 >> 1) & 1;
217 } else
218 #endif
219 {
220 ptev = pte_is_valid(pte0);
221 pteh = (pte0 >> 6) & 1;
222 }
223 if (ptev && h == pteh) {
224 /* Check vsid & api */
225 #if defined(TARGET_PPC64)
226 if (is_64b) {
227 ptem = pte0 & PTE64_PTEM_MASK;
228 mmask = PTE64_CHECK_MASK;
229 pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
230 ctx->nx |= (pte1 >> 2) & 1; /* No execute bit */
231 ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
232 } else
233 #endif
234 {
235 ptem = pte0 & PTE_PTEM_MASK;
236 mmask = PTE_CHECK_MASK;
237 pp = pte1 & 0x00000003;
238 }
239 if (ptem == ctx->ptem) {
240 if (ctx->raddr != (target_phys_addr_t)-1ULL) {
241 /* all matches should have equal RPN, WIMG & PP */
242 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
243 qemu_log("Bad RPN/WIMG/PP\n");
244 return -3;
245 }
246 }
247 /* Compute access rights */
248 access = pp_check(ctx->key, pp, ctx->nx);
249 /* Keep the matching PTE informations */
250 ctx->raddr = pte1;
251 ctx->prot = access;
252 ret = check_prot(ctx->prot, rw, type);
253 if (ret == 0) {
254 /* Access granted */
255 LOG_MMU("PTE access granted !\n");
256 } else {
257 /* Access right violation */
258 LOG_MMU("PTE access rejected\n");
259 }
260 }
261 }
262
263 return ret;
264 }
265
266 static always_inline int pte32_check (mmu_ctx_t *ctx,
267 target_ulong pte0, target_ulong pte1,
268 int h, int rw, int type)
269 {
270 return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
271 }
272
273 #if defined(TARGET_PPC64)
274 static always_inline int pte64_check (mmu_ctx_t *ctx,
275 target_ulong pte0, target_ulong pte1,
276 int h, int rw, int type)
277 {
278 return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
279 }
280 #endif
281
282 static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
283 int ret, int rw)
284 {
285 int store = 0;
286
287 /* Update page flags */
288 if (!(*pte1p & 0x00000100)) {
289 /* Update accessed flag */
290 *pte1p |= 0x00000100;
291 store = 1;
292 }
293 if (!(*pte1p & 0x00000080)) {
294 if (rw == 1 && ret == 0) {
295 /* Update changed flag */
296 *pte1p |= 0x00000080;
297 store = 1;
298 } else {
299 /* Force page fault for first write access */
300 ctx->prot &= ~PAGE_WRITE;
301 }
302 }
303
304 return store;
305 }
306
307 /* Software driven TLB helpers */
308 static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
309 int way, int is_code)
310 {
311 int nr;
312
313 /* Select TLB num in a way from address */
314 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
315 /* Select TLB way */
316 nr += env->tlb_per_way * way;
317 /* 6xx have separate TLBs for instructions and data */
318 if (is_code && env->id_tlbs == 1)
319 nr += env->nb_tlb;
320
321 return nr;
322 }
323
324 static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
325 {
326 ppc6xx_tlb_t *tlb;
327 int nr, max;
328
329 //LOG_SWTLB("Invalidate all TLBs\n");
330 /* Invalidate all defined software TLB */
331 max = env->nb_tlb;
332 if (env->id_tlbs == 1)
333 max *= 2;
334 for (nr = 0; nr < max; nr++) {
335 tlb = &env->tlb[nr].tlb6;
336 pte_invalidate(&tlb->pte0);
337 }
338 tlb_flush(env, 1);
339 }
340
341 static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
342 target_ulong eaddr,
343 int is_code,
344 int match_epn)
345 {
346 #if !defined(FLUSH_ALL_TLBS)
347 ppc6xx_tlb_t *tlb;
348 int way, nr;
349
350 /* Invalidate ITLB + DTLB, all ways */
351 for (way = 0; way < env->nb_ways; way++) {
352 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
353 tlb = &env->tlb[nr].tlb6;
354 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
355 LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n",
356 nr, env->nb_tlb, eaddr);
357 pte_invalidate(&tlb->pte0);
358 tlb_flush_page(env, tlb->EPN);
359 }
360 }
361 #else
362 /* XXX: PowerPC specification say this is valid as well */
363 ppc6xx_tlb_invalidate_all(env);
364 #endif
365 }
366
367 static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env,
368 target_ulong eaddr,
369 int is_code)
370 {
371 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
372 }
373
374 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
375 target_ulong pte0, target_ulong pte1)
376 {
377 ppc6xx_tlb_t *tlb;
378 int nr;
379
380 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
381 tlb = &env->tlb[nr].tlb6;
382 LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
383 " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
384 /* Invalidate any pending reference in Qemu for this virtual address */
385 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
386 tlb->pte0 = pte0;
387 tlb->pte1 = pte1;
388 tlb->EPN = EPN;
389 /* Store last way for LRU mechanism */
390 env->last_way = way;
391 }
392
393 static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
394 target_ulong eaddr, int rw,
395 int access_type)
396 {
397 ppc6xx_tlb_t *tlb;
398 int nr, best, way;
399 int ret;
400
401 best = -1;
402 ret = -1; /* No TLB found */
403 for (way = 0; way < env->nb_ways; way++) {
404 nr = ppc6xx_tlb_getnum(env, eaddr, way,
405 access_type == ACCESS_CODE ? 1 : 0);
406 tlb = &env->tlb[nr].tlb6;
407 /* This test "emulates" the PTE index match for hardware TLBs */
408 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
409 LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX
410 "] <> " ADDRX "\n",
411 nr, env->nb_tlb,
412 pte_is_valid(tlb->pte0) ? "valid" : "inval",
413 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
414 continue;
415 }
416 LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
417 " %c %c\n",
418 nr, env->nb_tlb,
419 pte_is_valid(tlb->pte0) ? "valid" : "inval",
420 tlb->EPN, eaddr, tlb->pte1,
421 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
422 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
423 case -3:
424 /* TLB inconsistency */
425 return -1;
426 case -2:
427 /* Access violation */
428 ret = -2;
429 best = nr;
430 break;
431 case -1:
432 default:
433 /* No match */
434 break;
435 case 0:
436 /* access granted */
437 /* XXX: we should go on looping to check all TLBs consistency
438 * but we can speed-up the whole thing as the
439 * result would be undefined if TLBs are not consistent.
440 */
441 ret = 0;
442 best = nr;
443 goto done;
444 }
445 }
446 if (best != -1) {
447 done:
448 LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n",
449 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
450 /* Update page flags */
451 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
452 }
453
454 return ret;
455 }
456
457 /* Perform BAT hit & translation */
458 static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
459 int *validp, int *protp,
460 target_ulong *BATu, target_ulong *BATl)
461 {
462 target_ulong bl;
463 int pp, valid, prot;
464
465 bl = (*BATu & 0x00001FFC) << 15;
466 valid = 0;
467 prot = 0;
468 if (((msr_pr == 0) && (*BATu & 0x00000002)) ||
469 ((msr_pr != 0) && (*BATu & 0x00000001))) {
470 valid = 1;
471 pp = *BATl & 0x00000003;
472 if (pp != 0) {
473 prot = PAGE_READ | PAGE_EXEC;
474 if (pp == 0x2)
475 prot |= PAGE_WRITE;
476 }
477 }
478 *blp = bl;
479 *validp = valid;
480 *protp = prot;
481 }
482
483 static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
484 int *validp, int *protp,
485 target_ulong *BATu,
486 target_ulong *BATl)
487 {
488 target_ulong bl;
489 int key, pp, valid, prot;
490
491 bl = (*BATl & 0x0000003F) << 17;
492 LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n",
493 (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
494 prot = 0;
495 valid = (*BATl >> 6) & 1;
496 if (valid) {
497 pp = *BATu & 0x00000003;
498 if (msr_pr == 0)
499 key = (*BATu >> 3) & 1;
500 else
501 key = (*BATu >> 2) & 1;
502 prot = pp_check(key, pp, 0);
503 }
504 *blp = bl;
505 *validp = valid;
506 *protp = prot;
507 }
508
509 static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
510 target_ulong virtual, int rw, int type)
511 {
512 target_ulong *BATlt, *BATut, *BATu, *BATl;
513 target_ulong base, BEPIl, BEPIu, bl;
514 int i, valid, prot;
515 int ret = -1;
516
517 LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__,
518 type == ACCESS_CODE ? 'I' : 'D', virtual);
519 switch (type) {
520 case ACCESS_CODE:
521 BATlt = env->IBAT[1];
522 BATut = env->IBAT[0];
523 break;
524 default:
525 BATlt = env->DBAT[1];
526 BATut = env->DBAT[0];
527 break;
528 }
529 base = virtual & 0xFFFC0000;
530 for (i = 0; i < env->nb_BATs; i++) {
531 BATu = &BATut[i];
532 BATl = &BATlt[i];
533 BEPIu = *BATu & 0xF0000000;
534 BEPIl = *BATu & 0x0FFE0000;
535 if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
536 bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);
537 } else {
538 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
539 }
540 LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX
541 " BATl " ADDRX "\n", __func__,
542 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
543 if ((virtual & 0xF0000000) == BEPIu &&
544 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
545 /* BAT matches */
546 if (valid != 0) {
547 /* Get physical address */
548 ctx->raddr = (*BATl & 0xF0000000) |
549 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
550 (virtual & 0x0001F000);
551 /* Compute access rights */
552 ctx->prot = prot;
553 ret = check_prot(ctx->prot, rw, type);
554 if (ret == 0)
555 LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n",
556 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
557 ctx->prot & PAGE_WRITE ? 'W' : '-');
558 break;
559 }
560 }
561 }
562 if (ret < 0) {
563 #if defined(DEBUG_BATS)
564 if (IS_LOGGING) {
565 QEMU_LOG0("no BAT match for " ADDRX ":\n", virtual);
566 for (i = 0; i < 4; i++) {
567 BATu = &BATut[i];
568 BATl = &BATlt[i];
569 BEPIu = *BATu & 0xF0000000;
570 BEPIl = *BATu & 0x0FFE0000;
571 bl = (*BATu & 0x00001FFC) << 15;
572 QEMU_LOG0("%s: %cBAT%d v " ADDRX " BATu " ADDRX
573 " BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n",
574 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
575 *BATu, *BATl, BEPIu, BEPIl, bl);
576 }
577 }
578 #endif
579 }
580 /* No hit */
581 return ret;
582 }
583
584 /* PTE table lookup */
585 static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
586 int rw, int type)
587 {
588 target_ulong base, pte0, pte1;
589 int i, good = -1;
590 int ret, r;
591
592 ret = -1; /* No entry found */
593 base = ctx->pg_addr[h];
594 for (i = 0; i < 8; i++) {
595 #if defined(TARGET_PPC64)
596 if (is_64b) {
597 pte0 = ldq_phys(base + (i * 16));
598 pte1 = ldq_phys(base + (i * 16) + 8);
599 r = pte64_check(ctx, pte0, pte1, h, rw, type);
600 LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
601 " %d %d %d " ADDRX "\n",
602 base + (i * 16), pte0, pte1,
603 (int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
604 ctx->ptem);
605 } else
606 #endif
607 {
608 pte0 = ldl_phys(base + (i * 8));
609 pte1 = ldl_phys(base + (i * 8) + 4);
610 r = pte32_check(ctx, pte0, pte1, h, rw, type);
611 LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
612 " %d %d %d " ADDRX "\n",
613 base + (i * 8), pte0, pte1,
614 (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
615 ctx->ptem);
616 }
617 switch (r) {
618 case -3:
619 /* PTE inconsistency */
620 return -1;
621 case -2:
622 /* Access violation */
623 ret = -2;
624 good = i;
625 break;
626 case -1:
627 default:
628 /* No PTE match */
629 break;
630 case 0:
631 /* access granted */
632 /* XXX: we should go on looping to check all PTEs consistency
633 * but if we can speed-up the whole thing as the
634 * result would be undefined if PTEs are not consistent.
635 */
636 ret = 0;
637 good = i;
638 goto done;
639 }
640 }
641 if (good != -1) {
642 done:
643 LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n",
644 ctx->raddr, ctx->prot, ret);
645 /* Update page flags */
646 pte1 = ctx->raddr;
647 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
648 #if defined(TARGET_PPC64)
649 if (is_64b) {
650 stq_phys_notdirty(base + (good * 16) + 8, pte1);
651 } else
652 #endif
653 {
654 stl_phys_notdirty(base + (good * 8) + 4, pte1);
655 }
656 }
657 }
658
659 return ret;
660 }
661
662 static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw, int type)
663 {
664 return _find_pte(ctx, 0, h, rw, type);
665 }
666
667 #if defined(TARGET_PPC64)
668 static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw, int type)
669 {
670 return _find_pte(ctx, 1, h, rw, type);
671 }
672 #endif
673
674 static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
675 int h, int rw, int type)
676 {
677 #if defined(TARGET_PPC64)
678 if (env->mmu_model & POWERPC_MMU_64)
679 return find_pte64(ctx, h, rw, type);
680 #endif
681
682 return find_pte32(ctx, h, rw, type);
683 }
684
685 #if defined(TARGET_PPC64)
686 static always_inline int slb_is_valid (uint64_t slb64)
687 {
688 return slb64 & 0x0000000008000000ULL ? 1 : 0;
689 }
690
691 static always_inline void slb_invalidate (uint64_t *slb64)
692 {
693 *slb64 &= ~0x0000000008000000ULL;
694 }
695
696 static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
697 target_ulong *vsid,
698 target_ulong *page_mask, int *attr)
699 {
700 target_phys_addr_t sr_base;
701 target_ulong mask;
702 uint64_t tmp64;
703 uint32_t tmp;
704 int n, ret;
705
706 ret = -5;
707 sr_base = env->spr[SPR_ASR];
708 LOG_SLB("%s: eaddr " ADDRX " base " PADDRX "\n",
709 __func__, eaddr, sr_base);
710 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
711 for (n = 0; n < env->slb_nr; n++) {
712 tmp64 = ldq_phys(sr_base);
713 tmp = ldl_phys(sr_base + 8);
714 LOG_SLB("%s: seg %d " PADDRX " %016" PRIx64 " %08"
715 PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
716 if (slb_is_valid(tmp64)) {
717 /* SLB entry is valid */
718 switch (tmp64 & 0x0000000006000000ULL) {
719 case 0x0000000000000000ULL:
720 /* 256 MB segment */
721 mask = 0xFFFFFFFFF0000000ULL;
722 break;
723 case 0x0000000002000000ULL:
724 /* 1 TB segment */
725 mask = 0xFFFF000000000000ULL;
726 break;
727 case 0x0000000004000000ULL:
728 case 0x0000000006000000ULL:
729 /* Reserved => segment is invalid */
730 continue;
731 }
732 if ((eaddr & mask) == (tmp64 & mask)) {
733 /* SLB match */
734 *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
735 *page_mask = ~mask;
736 *attr = tmp & 0xFF;
737 ret = n;
738 break;
739 }
740 }
741 sr_base += 12;
742 }
743
744 return ret;
745 }
746
747 void ppc_slb_invalidate_all (CPUPPCState *env)
748 {
749 target_phys_addr_t sr_base;
750 uint64_t tmp64;
751 int n, do_invalidate;
752
753 do_invalidate = 0;
754 sr_base = env->spr[SPR_ASR];
755 /* XXX: Warning: slbia never invalidates the first segment */
756 for (n = 1; n < env->slb_nr; n++) {
757 tmp64 = ldq_phys(sr_base);
758 if (slb_is_valid(tmp64)) {
759 slb_invalidate(&tmp64);
760 stq_phys(sr_base, tmp64);
761 /* XXX: given the fact that segment size is 256 MB or 1TB,
762 * and we still don't have a tlb_flush_mask(env, n, mask)
763 * in Qemu, we just invalidate all TLBs
764 */
765 do_invalidate = 1;
766 }
767 sr_base += 12;
768 }
769 if (do_invalidate)
770 tlb_flush(env, 1);
771 }
772
773 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
774 {
775 target_phys_addr_t sr_base;
776 target_ulong vsid, page_mask;
777 uint64_t tmp64;
778 int attr;
779 int n;
780
781 n = slb_lookup(env, T0, &vsid, &page_mask, &attr);
782 if (n >= 0) {
783 sr_base = env->spr[SPR_ASR];
784 sr_base += 12 * n;
785 tmp64 = ldq_phys(sr_base);
786 if (slb_is_valid(tmp64)) {
787 slb_invalidate(&tmp64);
788 stq_phys(sr_base, tmp64);
789 /* XXX: given the fact that segment size is 256 MB or 1TB,
790 * and we still don't have a tlb_flush_mask(env, n, mask)
791 * in Qemu, we just invalidate all TLBs
792 */
793 tlb_flush(env, 1);
794 }
795 }
796 }
797
798 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
799 {
800 target_phys_addr_t sr_base;
801 target_ulong rt;
802 uint64_t tmp64;
803 uint32_t tmp;
804
805 sr_base = env->spr[SPR_ASR];
806 sr_base += 12 * slb_nr;
807 tmp64 = ldq_phys(sr_base);
808 tmp = ldl_phys(sr_base + 8);
809 if (tmp64 & 0x0000000008000000ULL) {
810 /* SLB entry is valid */
811 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
812 rt = tmp >> 8; /* 65:88 => 40:63 */
813 rt |= (tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
814 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
815 rt |= ((tmp >> 4) & 0xF) << 27;
816 } else {
817 rt = 0;
818 }
819 LOG_SLB("%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
820 ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
821
822 return rt;
823 }
824
825 void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
826 {
827 target_phys_addr_t sr_base;
828 uint64_t tmp64;
829 uint32_t tmp;
830
831 sr_base = env->spr[SPR_ASR];
832 sr_base += 12 * slb_nr;
833 /* Copy Rs bits 37:63 to SLB 62:88 */
834 tmp = rs << 8;
835 tmp64 = (rs >> 24) & 0x7;
836 /* Copy Rs bits 33:36 to SLB 89:92 */
837 tmp |= ((rs >> 27) & 0xF) << 4;
838 /* Set the valid bit */
839 tmp64 |= 1 << 27;
840 /* Set ESID */
841 tmp64 |= (uint32_t)slb_nr << 28;
842 LOG_SLB("%s: %d " ADDRX " => " PADDRX " %016" PRIx64
843 " %08" PRIx32 "\n", __func__,
844 slb_nr, rs, sr_base, tmp64, tmp);
845 /* Write SLB entry to memory */
846 stq_phys(sr_base, tmp64);
847 stl_phys(sr_base + 8, tmp);
848 }
849 #endif /* defined(TARGET_PPC64) */
850
851 /* Perform segment based translation */
852 static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
853 int sdr_sh,
854 target_phys_addr_t hash,
855 target_phys_addr_t mask)
856 {
857 return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
858 }
859
860 static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
861 target_ulong eaddr, int rw, int type)
862 {
863 target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
864 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
865 #if defined(TARGET_PPC64)
866 int attr;
867 #endif
868 int ds, vsid_sh, sdr_sh, pr;
869 int ret, ret2;
870
871 pr = msr_pr;
872 #if defined(TARGET_PPC64)
873 if (env->mmu_model & POWERPC_MMU_64) {
874 LOG_MMU("Check SLBs\n");
875 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
876 if (ret < 0)
877 return ret;
878 ctx->key = ((attr & 0x40) && (pr != 0)) ||
879 ((attr & 0x80) && (pr == 0)) ? 1 : 0;
880 ds = 0;
881 ctx->nx = attr & 0x20 ? 1 : 0;
882 vsid_mask = 0x00003FFFFFFFFF80ULL;
883 vsid_sh = 7;
884 sdr_sh = 18;
885 sdr_mask = 0x3FF80;
886 } else
887 #endif /* defined(TARGET_PPC64) */
888 {
889 sr = env->sr[eaddr >> 28];
890 page_mask = 0x0FFFFFFF;
891 ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
892 ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
893 ds = sr & 0x80000000 ? 1 : 0;
894 ctx->nx = sr & 0x10000000 ? 1 : 0;
895 vsid = sr & 0x00FFFFFF;
896 vsid_mask = 0x01FFFFC0;
897 vsid_sh = 6;
898 sdr_sh = 16;
899 sdr_mask = 0xFFC0;
900 LOG_MMU("Check segment v=" ADDRX " %d " ADDRX
901 " nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
902 eaddr, (int)(eaddr >> 28), sr, env->nip,
903 env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
904 rw, type);
905 }
906 LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
907 ctx->key, ds, ctx->nx, vsid);
908 ret = -1;
909 if (!ds) {
910 /* Check if instruction fetch is allowed, if needed */
911 if (type != ACCESS_CODE || ctx->nx == 0) {
912 /* Page address translation */
913 /* Primary table address */
914 sdr = env->sdr1;
915 pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
916 #if defined(TARGET_PPC64)
917 if (env->mmu_model & POWERPC_MMU_64) {
918 htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
919 /* XXX: this is false for 1 TB segments */
920 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
921 } else
922 #endif
923 {
924 htab_mask = sdr & 0x000001FF;
925 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
926 }
927 mask = (htab_mask << sdr_sh) | sdr_mask;
928 LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
929 " mask " PADDRX " " ADDRX "\n",
930 sdr, sdr_sh, hash, mask, page_mask);
931 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
932 /* Secondary table address */
933 hash = (~hash) & vsid_mask;
934 LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
935 " mask " PADDRX "\n",
936 sdr, sdr_sh, hash, mask);
937 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
938 #if defined(TARGET_PPC64)
939 if (env->mmu_model & POWERPC_MMU_64) {
940 /* Only 5 bits of the page index are used in the AVPN */
941 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
942 } else
943 #endif
944 {
945 ctx->ptem = (vsid << 7) | (pgidx >> 10);
946 }
947 /* Initialize real address with an invalid value */
948 ctx->raddr = (target_phys_addr_t)-1ULL;
949 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
950 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
951 /* Software TLB search */
952 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
953 } else {
954 LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " "
955 "api=" ADDRX " hash=" PADDRX
956 " pg_addr=" PADDRX "\n",
957 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
958 /* Primary table lookup */
959 ret = find_pte(env, ctx, 0, rw, type);
960 if (ret < 0) {
961 /* Secondary table lookup */
962 if (eaddr != 0xEFFFFFFF)
963 LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " "
964 "api=" ADDRX " hash=" PADDRX
965 " pg_addr=" PADDRX "\n",
966 sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
967 ret2 = find_pte(env, ctx, 1, rw, type);
968 if (ret2 != -1)
969 ret = ret2;
970 }
971 }
972 #if defined (DUMP_PAGE_TABLES)
973 if (qemu_log_enabled()) {
974 target_phys_addr_t curaddr;
975 uint32_t a0, a1, a2, a3;
976 qemu_log("Page table: " PADDRX " len " PADDRX "\n",
977 sdr, mask + 0x80);
978 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
979 curaddr += 16) {
980 a0 = ldl_phys(curaddr);
981 a1 = ldl_phys(curaddr + 4);
982 a2 = ldl_phys(curaddr + 8);
983 a3 = ldl_phys(curaddr + 12);
984 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
985 qemu_log(PADDRX ": %08x %08x %08x %08x\n",
986 curaddr, a0, a1, a2, a3);
987 }
988 }
989 }
990 #endif
991 } else {
992 LOG_MMU("No access allowed\n");
993 ret = -3;
994 }
995 } else {
996 LOG_MMU("direct store...\n");
997 /* Direct-store segment : absolutely *BUGGY* for now */
998 switch (type) {
999 case ACCESS_INT:
1000 /* Integer load/store : only access allowed */
1001 break;
1002 case ACCESS_CODE:
1003 /* No code fetch is allowed in direct-store areas */
1004 return -4;
1005 case ACCESS_FLOAT:
1006 /* Floating point load/store */
1007 return -4;
1008 case ACCESS_RES:
1009 /* lwarx, ldarx or srwcx. */
1010 return -4;
1011 case ACCESS_CACHE:
1012 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
1013 /* Should make the instruction do no-op.
1014 * As it already do no-op, it's quite easy :-)
1015 */
1016 ctx->raddr = eaddr;
1017 return 0;
1018 case ACCESS_EXT:
1019 /* eciwx or ecowx */
1020 return -4;
1021 default:
1022 qemu_log("ERROR: instruction should not need "
1023 "address translation\n");
1024 return -4;
1025 }
1026 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
1027 ctx->raddr = eaddr;
1028 ret = 2;
1029 } else {
1030 ret = -2;
1031 }
1032 }
1033
1034 return ret;
1035 }
1036
1037 /* Generic TLB check function for embedded PowerPC implementations */
1038 static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
1039 target_phys_addr_t *raddrp,
1040 target_ulong address,
1041 uint32_t pid, int ext, int i)
1042 {
1043 target_ulong mask;
1044
1045 /* Check valid flag */
1046 if (!(tlb->prot & PAGE_VALID)) {
1047 qemu_log("%s: TLB %d not valid\n", __func__, i);
1048 return -1;
1049 }
1050 mask = ~(tlb->size - 1);
1051 LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
1052 " " ADDRX " %u\n",
1053 __func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID);
1054 /* Check PID */
1055 if (tlb->PID != 0 && tlb->PID != pid)
1056 return -1;
1057 /* Check effective address */
1058 if ((address & mask) != tlb->EPN)
1059 return -1;
1060 *raddrp = (tlb->RPN & mask) | (address & ~mask);
1061 #if (TARGET_PHYS_ADDR_BITS >= 36)
1062 if (ext) {
1063 /* Extend the physical address to 36 bits */
1064 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
1065 }
1066 #endif
1067
1068 return 0;
1069 }
1070
1071 /* Generic TLB search function for PowerPC embedded implementations */
1072 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
1073 {
1074 ppcemb_tlb_t *tlb;
1075 target_phys_addr_t raddr;
1076 int i, ret;
1077
1078 /* Default return value is no match */
1079 ret = -1;
1080 for (i = 0; i < env->nb_tlb; i++) {
1081 tlb = &env->tlb[i].tlbe;
1082 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
1083 ret = i;
1084 break;
1085 }
1086 }
1087
1088 return ret;
1089 }
1090
1091 /* Helpers specific to PowerPC 40x implementations */
1092 static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
1093 {
1094 ppcemb_tlb_t *tlb;
1095 int i;
1096
1097 for (i = 0; i < env->nb_tlb; i++) {
1098 tlb = &env->tlb[i].tlbe;
1099 tlb->prot &= ~PAGE_VALID;
1100 }
1101 tlb_flush(env, 1);
1102 }
1103
1104 static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env,
1105 target_ulong eaddr,
1106 uint32_t pid)
1107 {
1108 #if !defined(FLUSH_ALL_TLBS)
1109 ppcemb_tlb_t *tlb;
1110 target_phys_addr_t raddr;
1111 target_ulong page, end;
1112 int i;
1113
1114 for (i = 0; i < env->nb_tlb; i++) {
1115 tlb = &env->tlb[i].tlbe;
1116 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
1117 end = tlb->EPN + tlb->size;
1118 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1119 tlb_flush_page(env, page);
1120 tlb->prot &= ~PAGE_VALID;
1121 break;
1122 }
1123 }
1124 #else
1125 ppc4xx_tlb_invalidate_all(env);
1126 #endif
1127 }
1128
1129 static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1130 target_ulong address, int rw, int access_type)
1131 {
1132 ppcemb_tlb_t *tlb;
1133 target_phys_addr_t raddr;
1134 int i, ret, zsel, zpr, pr;
1135
1136 ret = -1;
1137 raddr = (target_phys_addr_t)-1ULL;
1138 pr = msr_pr;
1139 for (i = 0; i < env->nb_tlb; i++) {
1140 tlb = &env->tlb[i].tlbe;
1141 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1142 env->spr[SPR_40x_PID], 0, i) < 0)
1143 continue;
1144 zsel = (tlb->attr >> 4) & 0xF;
1145 zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
1146 LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1147 __func__, i, zsel, zpr, rw, tlb->attr);
1148 /* Check execute enable bit */
1149 switch (zpr) {
1150 case 0x2:
1151 if (pr != 0)
1152 goto check_perms;
1153 /* No break here */
1154 case 0x3:
1155 /* All accesses granted */
1156 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1157 ret = 0;
1158 break;
1159 case 0x0:
1160 if (pr != 0) {
1161 ctx->prot = 0;
1162 ret = -2;
1163 break;
1164 }
1165 /* No break here */
1166 case 0x1:
1167 check_perms:
1168 /* Check from TLB entry */
1169 /* XXX: there is a problem here or in the TLB fill code... */
1170 ctx->prot = tlb->prot;
1171 ctx->prot |= PAGE_EXEC;
1172 ret = check_prot(ctx->prot, rw, access_type);
1173 break;
1174 }
1175 if (ret >= 0) {
1176 ctx->raddr = raddr;
1177 LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX
1178 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1179 ret);
1180 return 0;
1181 }
1182 }
1183 LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX
1184 " %d %d\n", __func__, address, raddr, ctx->prot,
1185 ret);
1186
1187 return ret;
1188 }
1189
1190 void store_40x_sler (CPUPPCState *env, uint32_t val)
1191 {
1192 /* XXX: TO BE FIXED */
1193 if (val != 0x00000000) {
1194 cpu_abort(env, "Little-endian regions are not supported by now\n");
1195 }
1196 env->spr[SPR_405_SLER] = val;
1197 }
1198
1199 static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1200 target_ulong address, int rw,
1201 int access_type)
1202 {
1203 ppcemb_tlb_t *tlb;
1204 target_phys_addr_t raddr;
1205 int i, prot, ret;
1206
1207 ret = -1;
1208 raddr = (target_phys_addr_t)-1ULL;
1209 for (i = 0; i < env->nb_tlb; i++) {
1210 tlb = &env->tlb[i].tlbe;
1211 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1212 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1213 continue;
1214 if (msr_pr != 0)
1215 prot = tlb->prot & 0xF;
1216 else
1217 prot = (tlb->prot >> 4) & 0xF;
1218 /* Check the address space */
1219 if (access_type == ACCESS_CODE) {
1220 if (msr_ir != (tlb->attr & 1))
1221 continue;
1222 ctx->prot = prot;
1223 if (prot & PAGE_EXEC) {
1224 ret = 0;
1225 break;
1226 }
1227 ret = -3;
1228 } else {
1229 if (msr_dr != (tlb->attr & 1))
1230 continue;
1231 ctx->prot = prot;
1232 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1233 ret = 0;
1234 break;
1235 }
1236 ret = -2;
1237 }
1238 }
1239 if (ret >= 0)
1240 ctx->raddr = raddr;
1241
1242 return ret;
1243 }
1244
1245 static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
1246 target_ulong eaddr, int rw)
1247 {
1248 int in_plb, ret;
1249
1250 ctx->raddr = eaddr;
1251 ctx->prot = PAGE_READ | PAGE_EXEC;
1252 ret = 0;
1253 switch (env->mmu_model) {
1254 case POWERPC_MMU_32B:
1255 case POWERPC_MMU_601:
1256 case POWERPC_MMU_SOFT_6xx:
1257 case POWERPC_MMU_SOFT_74xx:
1258 case POWERPC_MMU_SOFT_4xx:
1259 case POWERPC_MMU_REAL:
1260 case POWERPC_MMU_BOOKE:
1261 ctx->prot |= PAGE_WRITE;
1262 break;
1263 #if defined(TARGET_PPC64)
1264 case POWERPC_MMU_620:
1265 case POWERPC_MMU_64B:
1266 /* Real address are 60 bits long */
1267 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1268 ctx->prot |= PAGE_WRITE;
1269 break;
1270 #endif
1271 case POWERPC_MMU_SOFT_4xx_Z:
1272 if (unlikely(msr_pe != 0)) {
1273 /* 403 family add some particular protections,
1274 * using PBL/PBU registers for accesses with no translation.
1275 */
1276 in_plb =
1277 /* Check PLB validity */
1278 (env->pb[0] < env->pb[1] &&
1279 /* and address in plb area */
1280 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1281 (env->pb[2] < env->pb[3] &&
1282 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1283 if (in_plb ^ msr_px) {
1284 /* Access in protected area */
1285 if (rw == 1) {
1286 /* Access is not allowed */
1287 ret = -2;
1288 }
1289 } else {
1290 /* Read-write access is allowed */
1291 ctx->prot |= PAGE_WRITE;
1292 }
1293 }
1294 break;
1295 case POWERPC_MMU_MPC8xx:
1296 /* XXX: TODO */
1297 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1298 break;
1299 case POWERPC_MMU_BOOKE_FSL:
1300 /* XXX: TODO */
1301 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1302 break;
1303 default:
1304 cpu_abort(env, "Unknown or invalid MMU model\n");
1305 return -1;
1306 }
1307
1308 return ret;
1309 }
1310
1311 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1312 int rw, int access_type)
1313 {
1314 int ret;
1315
1316 #if 0
1317 qemu_log("%s\n", __func__);
1318 #endif
1319 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1320 (access_type != ACCESS_CODE && msr_dr == 0)) {
1321 /* No address translation */
1322 ret = check_physical(env, ctx, eaddr, rw);
1323 } else {
1324 ret = -1;
1325 switch (env->mmu_model) {
1326 case POWERPC_MMU_32B:
1327 case POWERPC_MMU_601:
1328 case POWERPC_MMU_SOFT_6xx:
1329 case POWERPC_MMU_SOFT_74xx:
1330 #if defined(TARGET_PPC64)
1331 case POWERPC_MMU_620:
1332 case POWERPC_MMU_64B:
1333 #endif
1334 /* Try to find a BAT */
1335 if (env->nb_BATs != 0)
1336 ret = get_bat(env, ctx, eaddr, rw, access_type);
1337 if (ret < 0) {
1338 /* We didn't match any BAT entry or don't have BATs */
1339 ret = get_segment(env, ctx, eaddr, rw, access_type);
1340 }
1341 break;
1342 case POWERPC_MMU_SOFT_4xx:
1343 case POWERPC_MMU_SOFT_4xx_Z:
1344 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1345 rw, access_type);
1346 break;
1347 case POWERPC_MMU_BOOKE:
1348 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1349 rw, access_type);
1350 break;
1351 case POWERPC_MMU_MPC8xx:
1352 /* XXX: TODO */
1353 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1354 break;
1355 case POWERPC_MMU_BOOKE_FSL:
1356 /* XXX: TODO */
1357 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1358 return -1;
1359 case POWERPC_MMU_REAL:
1360 cpu_abort(env, "PowerPC in real mode do not do any translation\n");
1361 return -1;
1362 default:
1363 cpu_abort(env, "Unknown or invalid MMU model\n");
1364 return -1;
1365 }
1366 }
1367 #if 0
1368 qemu_log("%s address " ADDRX " => %d " PADDRX "\n",
1369 __func__, eaddr, ret, ctx->raddr);
1370 #endif
1371
1372 return ret;
1373 }
1374
1375 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1376 {
1377 mmu_ctx_t ctx;
1378
1379 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0))
1380 return -1;
1381
1382 return ctx.raddr & TARGET_PAGE_MASK;
1383 }
1384
1385 /* Perform address translation */
1386 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1387 int mmu_idx, int is_softmmu)
1388 {
1389 mmu_ctx_t ctx;
1390 int access_type;
1391 int ret = 0;
1392
1393 if (rw == 2) {
1394 /* code access */
1395 rw = 0;
1396 access_type = ACCESS_CODE;
1397 } else {
1398 /* data access */
1399 access_type = env->access_type;
1400 }
1401 ret = get_physical_address(env, &ctx, address, rw, access_type);
1402 if (ret == 0) {
1403 ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK,
1404 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1405 mmu_idx, is_softmmu);
1406 } else if (ret < 0) {
1407 LOG_MMU_STATE(env);
1408 if (access_type == ACCESS_CODE) {
1409 switch (ret) {
1410 case -1:
1411 /* No matches in page tables or TLB */
1412 switch (env->mmu_model) {
1413 case POWERPC_MMU_SOFT_6xx:
1414 env->exception_index = POWERPC_EXCP_IFTLB;
1415 env->error_code = 1 << 18;
1416 env->spr[SPR_IMISS] = address;
1417 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1418 goto tlb_miss;
1419 case POWERPC_MMU_SOFT_74xx:
1420 env->exception_index = POWERPC_EXCP_IFTLB;
1421 goto tlb_miss_74xx;
1422 case POWERPC_MMU_SOFT_4xx:
1423 case POWERPC_MMU_SOFT_4xx_Z:
1424 env->exception_index = POWERPC_EXCP_ITLB;
1425 env->error_code = 0;
1426 env->spr[SPR_40x_DEAR] = address;
1427 env->spr[SPR_40x_ESR] = 0x00000000;
1428 break;
1429 case POWERPC_MMU_32B:
1430 case POWERPC_MMU_601:
1431 #if defined(TARGET_PPC64)
1432 case POWERPC_MMU_620:
1433 case POWERPC_MMU_64B:
1434 #endif
1435 env->exception_index = POWERPC_EXCP_ISI;
1436 env->error_code = 0x40000000;
1437 break;
1438 case POWERPC_MMU_BOOKE:
1439 /* XXX: TODO */
1440 cpu_abort(env, "BookE MMU model is not implemented\n");
1441 return -1;
1442 case POWERPC_MMU_BOOKE_FSL:
1443 /* XXX: TODO */
1444 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1445 return -1;
1446 case POWERPC_MMU_MPC8xx:
1447 /* XXX: TODO */
1448 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1449 break;
1450 case POWERPC_MMU_REAL:
1451 cpu_abort(env, "PowerPC in real mode should never raise "
1452 "any MMU exceptions\n");
1453 return -1;
1454 default:
1455 cpu_abort(env, "Unknown or invalid MMU model\n");
1456 return -1;
1457 }
1458 break;
1459 case -2:
1460 /* Access rights violation */
1461 env->exception_index = POWERPC_EXCP_ISI;
1462 env->error_code = 0x08000000;
1463 break;
1464 case -3:
1465 /* No execute protection violation */
1466 env->exception_index = POWERPC_EXCP_ISI;
1467 env->error_code = 0x10000000;
1468 break;
1469 case -4:
1470 /* Direct store exception */
1471 /* No code fetch is allowed in direct-store areas */
1472 env->exception_index = POWERPC_EXCP_ISI;
1473 env->error_code = 0x10000000;
1474 break;
1475 #if defined(TARGET_PPC64)
1476 case -5:
1477 /* No match in segment table */
1478 if (env->mmu_model == POWERPC_MMU_620) {
1479 env->exception_index = POWERPC_EXCP_ISI;
1480 /* XXX: this might be incorrect */
1481 env->error_code = 0x40000000;
1482 } else {
1483 env->exception_index = POWERPC_EXCP_ISEG;
1484 env->error_code = 0;
1485 }
1486 break;
1487 #endif
1488 }
1489 } else {
1490 switch (ret) {
1491 case -1:
1492 /* No matches in page tables or TLB */
1493 switch (env->mmu_model) {
1494 case POWERPC_MMU_SOFT_6xx:
1495 if (rw == 1) {
1496 env->exception_index = POWERPC_EXCP_DSTLB;
1497 env->error_code = 1 << 16;
1498 } else {
1499 env->exception_index = POWERPC_EXCP_DLTLB;
1500 env->error_code = 0;
1501 }
1502 env->spr[SPR_DMISS] = address;
1503 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1504 tlb_miss:
1505 env->error_code |= ctx.key << 19;
1506 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1507 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1508 break;
1509 case POWERPC_MMU_SOFT_74xx:
1510 if (rw == 1) {
1511 env->exception_index = POWERPC_EXCP_DSTLB;
1512 } else {
1513 env->exception_index = POWERPC_EXCP_DLTLB;
1514 }
1515 tlb_miss_74xx:
1516 /* Implement LRU algorithm */
1517 env->error_code = ctx.key << 19;
1518 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1519 ((env->last_way + 1) & (env->nb_ways - 1));
1520 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
1521 break;
1522 case POWERPC_MMU_SOFT_4xx:
1523 case POWERPC_MMU_SOFT_4xx_Z:
1524 env->exception_index = POWERPC_EXCP_DTLB;
1525 env->error_code = 0;
1526 env->spr[SPR_40x_DEAR] = address;
1527 if (rw)
1528 env->spr[SPR_40x_ESR] = 0x00800000;
1529 else
1530 env->spr[SPR_40x_ESR] = 0x00000000;
1531 break;
1532 case POWERPC_MMU_32B:
1533 case POWERPC_MMU_601:
1534 #if defined(TARGET_PPC64)
1535 case POWERPC_MMU_620:
1536 case POWERPC_MMU_64B:
1537 #endif
1538 env->exception_index = POWERPC_EXCP_DSI;
1539 env->error_code = 0;
1540 env->spr[SPR_DAR] = address;
1541 if (rw == 1)
1542 env->spr[SPR_DSISR] = 0x42000000;
1543 else
1544 env->spr[SPR_DSISR] = 0x40000000;
1545 break;
1546 case POWERPC_MMU_MPC8xx:
1547 /* XXX: TODO */
1548 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1549 break;
1550 case POWERPC_MMU_BOOKE:
1551 /* XXX: TODO */
1552 cpu_abort(env, "BookE MMU model is not implemented\n");
1553 return -1;
1554 case POWERPC_MMU_BOOKE_FSL:
1555 /* XXX: TODO */
1556 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1557 return -1;
1558 case POWERPC_MMU_REAL:
1559 cpu_abort(env, "PowerPC in real mode should never raise "
1560 "any MMU exceptions\n");
1561 return -1;
1562 default:
1563 cpu_abort(env, "Unknown or invalid MMU model\n");
1564 return -1;
1565 }
1566 break;
1567 case -2:
1568 /* Access rights violation */
1569 env->exception_index = POWERPC_EXCP_DSI;
1570 env->error_code = 0;
1571 env->spr[SPR_DAR] = address;
1572 if (rw == 1)
1573 env->spr[SPR_DSISR] = 0x0A000000;
1574 else
1575 env->spr[SPR_DSISR] = 0x08000000;
1576 break;
1577 case -4:
1578 /* Direct store exception */
1579 switch (access_type) {
1580 case ACCESS_FLOAT:
1581 /* Floating point load/store */
1582 env->exception_index = POWERPC_EXCP_ALIGN;
1583 env->error_code = POWERPC_EXCP_ALIGN_FP;
1584 env->spr[SPR_DAR] = address;
1585 break;
1586 case ACCESS_RES:
1587 /* lwarx, ldarx or stwcx. */
1588 env->exception_index = POWERPC_EXCP_DSI;
1589 env->error_code = 0;
1590 env->spr[SPR_DAR] = address;
1591 if (rw == 1)
1592 env->spr[SPR_DSISR] = 0x06000000;
1593 else
1594 env->spr[SPR_DSISR] = 0x04000000;
1595 break;
1596 case ACCESS_EXT:
1597 /* eciwx or ecowx */
1598 env->exception_index = POWERPC_EXCP_DSI;
1599 env->error_code = 0;
1600 env->spr[SPR_DAR] = address;
1601 if (rw == 1)
1602 env->spr[SPR_DSISR] = 0x06100000;
1603 else
1604 env->spr[SPR_DSISR] = 0x04100000;
1605 break;
1606 default:
1607 printf("DSI: invalid exception (%d)\n", ret);
1608 env->exception_index = POWERPC_EXCP_PROGRAM;
1609 env->error_code =
1610 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1611 env->spr[SPR_DAR] = address;
1612 break;
1613 }
1614 break;
1615 #if defined(TARGET_PPC64)
1616 case -5:
1617 /* No match in segment table */
1618 if (env->mmu_model == POWERPC_MMU_620) {
1619 env->exception_index = POWERPC_EXCP_DSI;
1620 env->error_code = 0;
1621 env->spr[SPR_DAR] = address;
1622 /* XXX: this might be incorrect */
1623 if (rw == 1)
1624 env->spr[SPR_DSISR] = 0x42000000;
1625 else
1626 env->spr[SPR_DSISR] = 0x40000000;
1627 } else {
1628 env->exception_index = POWERPC_EXCP_DSEG;
1629 env->error_code = 0;
1630 env->spr[SPR_DAR] = address;
1631 }
1632 break;
1633 #endif
1634 }
1635 }
1636 #if 0
1637 printf("%s: set exception to %d %02x\n", __func__,
1638 env->exception, env->error_code);
1639 #endif
1640 ret = 1;
1641 }
1642
1643 return ret;
1644 }
1645
1646 /*****************************************************************************/
1647 /* BATs management */
1648 #if !defined(FLUSH_ALL_TLBS)
1649 static always_inline void do_invalidate_BAT (CPUPPCState *env,
1650 target_ulong BATu,
1651 target_ulong mask)
1652 {
1653 target_ulong base, end, page;
1654
1655 base = BATu & ~0x0001FFFF;
1656 end = base + mask + 0x00020000;
1657 LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1658 base, end, mask);
1659 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1660 tlb_flush_page(env, page);
1661 LOG_BATS("Flush done\n");
1662 }
1663 #endif
1664
1665 static always_inline void dump_store_bat (CPUPPCState *env, char ID,
1666 int ul, int nr, target_ulong value)
1667 {
1668 LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
1669 ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1670 }
1671
1672 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1673 {
1674 target_ulong mask;
1675
1676 dump_store_bat(env, 'I', 0, nr, value);
1677 if (env->IBAT[0][nr] != value) {
1678 mask = (value << 15) & 0x0FFE0000UL;
1679 #if !defined(FLUSH_ALL_TLBS)
1680 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1681 #endif
1682 /* When storing valid upper BAT, mask BEPI and BRPN
1683 * and invalidate all TLBs covered by this BAT
1684 */
1685 mask = (value << 15) & 0x0FFE0000UL;
1686 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1687 (value & ~0x0001FFFFUL & ~mask);
1688 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1689 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1690 #if !defined(FLUSH_ALL_TLBS)
1691 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1692 #else
1693 tlb_flush(env, 1);
1694 #endif
1695 }
1696 }
1697
1698 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1699 {
1700 dump_store_bat(env, 'I', 1, nr, value);
1701 env->IBAT[1][nr] = value;
1702 }
1703
1704 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1705 {
1706 target_ulong mask;
1707
1708 dump_store_bat(env, 'D', 0, nr, value);
1709 if (env->DBAT[0][nr] != value) {
1710 /* When storing valid upper BAT, mask BEPI and BRPN
1711 * and invalidate all TLBs covered by this BAT
1712 */
1713 mask = (value << 15) & 0x0FFE0000UL;
1714 #if !defined(FLUSH_ALL_TLBS)
1715 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1716 #endif
1717 mask = (value << 15) & 0x0FFE0000UL;
1718 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1719 (value & ~0x0001FFFFUL & ~mask);
1720 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1721 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1722 #if !defined(FLUSH_ALL_TLBS)
1723 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1724 #else
1725 tlb_flush(env, 1);
1726 #endif
1727 }
1728 }
1729
1730 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1731 {
1732 dump_store_bat(env, 'D', 1, nr, value);
1733 env->DBAT[1][nr] = value;
1734 }
1735
1736 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
1737 {
1738 target_ulong mask;
1739 int do_inval;
1740
1741 dump_store_bat(env, 'I', 0, nr, value);
1742 if (env->IBAT[0][nr] != value) {
1743 do_inval = 0;
1744 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1745 if (env->IBAT[1][nr] & 0x40) {
1746 /* Invalidate BAT only if it is valid */
1747 #if !defined(FLUSH_ALL_TLBS)
1748 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1749 #else
1750 do_inval = 1;
1751 #endif
1752 }
1753 /* When storing valid upper BAT, mask BEPI and BRPN
1754 * and invalidate all TLBs covered by this BAT
1755 */
1756 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1757 (value & ~0x0001FFFFUL & ~mask);
1758 env->DBAT[0][nr] = env->IBAT[0][nr];
1759 if (env->IBAT[1][nr] & 0x40) {
1760 #if !defined(FLUSH_ALL_TLBS)
1761 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1762 #else
1763 do_inval = 1;
1764 #endif
1765 }
1766 #if defined(FLUSH_ALL_TLBS)
1767 if (do_inval)
1768 tlb_flush(env, 1);
1769 #endif
1770 }
1771 }
1772
1773 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
1774 {
1775 target_ulong mask;
1776 int do_inval;
1777
1778 dump_store_bat(env, 'I', 1, nr, value);
1779 if (env->IBAT[1][nr] != value) {
1780 do_inval = 0;
1781 if (env->IBAT[1][nr] & 0x40) {
1782 #if !defined(FLUSH_ALL_TLBS)
1783 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1784 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1785 #else
1786 do_inval = 1;
1787 #endif
1788 }
1789 if (value & 0x40) {
1790 #if !defined(FLUSH_ALL_TLBS)
1791 mask = (value << 17) & 0x0FFE0000UL;
1792 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1793 #else
1794 do_inval = 1;
1795 #endif
1796 }
1797 env->IBAT[1][nr] = value;
1798 env->DBAT[1][nr] = value;
1799 #if defined(FLUSH_ALL_TLBS)
1800 if (do_inval)
1801 tlb_flush(env, 1);
1802 #endif
1803 }
1804 }
1805
1806 /*****************************************************************************/
1807 /* TLB management */
1808 void ppc_tlb_invalidate_all (CPUPPCState *env)
1809 {
1810 switch (env->mmu_model) {
1811 case POWERPC_MMU_SOFT_6xx:
1812 case POWERPC_MMU_SOFT_74xx:
1813 ppc6xx_tlb_invalidate_all(env);
1814 break;
1815 case POWERPC_MMU_SOFT_4xx:
1816 case POWERPC_MMU_SOFT_4xx_Z:
1817 ppc4xx_tlb_invalidate_all(env);
1818 break;
1819 case POWERPC_MMU_REAL:
1820 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1821 break;
1822 case POWERPC_MMU_MPC8xx:
1823 /* XXX: TODO */
1824 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1825 break;
1826 case POWERPC_MMU_BOOKE:
1827 /* XXX: TODO */
1828 cpu_abort(env, "BookE MMU model is not implemented\n");
1829 break;
1830 case POWERPC_MMU_BOOKE_FSL:
1831 /* XXX: TODO */
1832 if (!kvm_enabled())
1833 cpu_abort(env, "BookE MMU model is not implemented\n");
1834 break;
1835 case POWERPC_MMU_32B:
1836 case POWERPC_MMU_601:
1837 #if defined(TARGET_PPC64)
1838 case POWERPC_MMU_620:
1839 case POWERPC_MMU_64B:
1840 #endif /* defined(TARGET_PPC64) */
1841 tlb_flush(env, 1);
1842 break;
1843 default:
1844 /* XXX: TODO */
1845 cpu_abort(env, "Unknown MMU model\n");
1846 break;
1847 }
1848 }
1849
1850 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1851 {
1852 #if !defined(FLUSH_ALL_TLBS)
1853 addr &= TARGET_PAGE_MASK;
1854 switch (env->mmu_model) {
1855 case POWERPC_MMU_SOFT_6xx:
1856 case POWERPC_MMU_SOFT_74xx:
1857 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1858 if (env->id_tlbs == 1)
1859 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1860 break;
1861 case POWERPC_MMU_SOFT_4xx:
1862 case POWERPC_MMU_SOFT_4xx_Z:
1863 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1864 break;
1865 case POWERPC_MMU_REAL:
1866 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1867 break;
1868 case POWERPC_MMU_MPC8xx:
1869 /* XXX: TODO */
1870 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1871 break;
1872 case POWERPC_MMU_BOOKE:
1873 /* XXX: TODO */
1874 cpu_abort(env, "BookE MMU model is not implemented\n");
1875 break;
1876 case POWERPC_MMU_BOOKE_FSL:
1877 /* XXX: TODO */
1878 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1879 break;
1880 case POWERPC_MMU_32B:
1881 case POWERPC_MMU_601:
1882 /* tlbie invalidate TLBs for all segments */
1883 addr &= ~((target_ulong)-1ULL << 28);
1884 /* XXX: this case should be optimized,
1885 * giving a mask to tlb_flush_page
1886 */
1887 tlb_flush_page(env, addr | (0x0 << 28));
1888 tlb_flush_page(env, addr | (0x1 << 28));
1889 tlb_flush_page(env, addr | (0x2 << 28));
1890 tlb_flush_page(env, addr | (0x3 << 28));
1891 tlb_flush_page(env, addr | (0x4 << 28));
1892 tlb_flush_page(env, addr | (0x5 << 28));
1893 tlb_flush_page(env, addr | (0x6 << 28));
1894 tlb_flush_page(env, addr | (0x7 << 28));
1895 tlb_flush_page(env, addr | (0x8 << 28));
1896 tlb_flush_page(env, addr | (0x9 << 28));
1897 tlb_flush_page(env, addr | (0xA << 28));
1898 tlb_flush_page(env, addr | (0xB << 28));
1899 tlb_flush_page(env, addr | (0xC << 28));
1900 tlb_flush_page(env, addr | (0xD << 28));
1901 tlb_flush_page(env, addr | (0xE << 28));
1902 tlb_flush_page(env, addr | (0xF << 28));
1903 break;
1904 #if defined(TARGET_PPC64)
1905 case POWERPC_MMU_620:
1906 case POWERPC_MMU_64B:
1907 /* tlbie invalidate TLBs for all segments */
1908 /* XXX: given the fact that there are too many segments to invalidate,
1909 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
1910 * we just invalidate all TLBs
1911 */
1912 tlb_flush(env, 1);
1913 break;
1914 #endif /* defined(TARGET_PPC64) */
1915 default:
1916 /* XXX: TODO */
1917 cpu_abort(env, "Unknown MMU model\n");
1918 break;
1919 }
1920 #else
1921 ppc_tlb_invalidate_all(env);
1922 #endif
1923 }
1924
1925 /*****************************************************************************/
1926 /* Special registers manipulation */
1927 #if defined(TARGET_PPC64)
1928 void ppc_store_asr (CPUPPCState *env, target_ulong value)
1929 {
1930 if (env->asr != value) {
1931 env->asr = value;
1932 tlb_flush(env, 1);
1933 }
1934 }
1935 #endif
1936
1937 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
1938 {
1939 LOG_MMU("%s: " ADDRX "\n", __func__, value);
1940 if (env->sdr1 != value) {
1941 /* XXX: for PowerPC 64, should check that the HTABSIZE value
1942 * is <= 28
1943 */
1944 env->sdr1 = value;
1945 tlb_flush(env, 1);
1946 }
1947 }
1948
1949 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1950 {
1951 LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n",
1952 __func__, srnum, value, env->sr[srnum]);
1953 if (env->sr[srnum] != value) {
1954 env->sr[srnum] = value;
1955 #if !defined(FLUSH_ALL_TLBS) && 0
1956 {
1957 target_ulong page, end;
1958 /* Invalidate 256 MB of virtual memory */
1959 page = (16 << 20) * srnum;
1960 end = page + (16 << 20);
1961 for (; page != end; page += TARGET_PAGE_SIZE)
1962 tlb_flush_page(env, page);
1963 }
1964 #else
1965 tlb_flush(env, 1);
1966 #endif
1967 }
1968 }
1969 #endif /* !defined (CONFIG_USER_ONLY) */
1970
1971 /* GDBstub can read and write MSR... */
1972 void ppc_store_msr (CPUPPCState *env, target_ulong value)
1973 {
1974 hreg_store_msr(env, value, 0);
1975 }
1976
1977 /*****************************************************************************/
1978 /* Exception processing */
1979 #if defined (CONFIG_USER_ONLY)
1980 void do_interrupt (CPUState *env)
1981 {
1982 env->exception_index = POWERPC_EXCP_NONE;
1983 env->error_code = 0;
1984 }
1985
1986 void ppc_hw_interrupt (CPUState *env)
1987 {
1988 env->exception_index = POWERPC_EXCP_NONE;
1989 env->error_code = 0;
1990 }
1991 #else /* defined (CONFIG_USER_ONLY) */
1992 static always_inline void dump_syscall (CPUState *env)
1993 {
1994 qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX
1995 " r5=" REGX " r6=" REGX " nip=" ADDRX "\n",
1996 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), ppc_dump_gpr(env, 4),
1997 ppc_dump_gpr(env, 5), ppc_dump_gpr(env, 6), env->nip);
1998 }
1999
2000 /* Note that this function should be greatly optimized
2001 * when called with a constant excp, from ppc_hw_interrupt
2002 */
2003 static always_inline void powerpc_excp (CPUState *env,
2004 int excp_model, int excp)
2005 {
2006 target_ulong msr, new_msr, vector;
2007 int srr0, srr1, asrr0, asrr1;
2008 int lpes0, lpes1, lev;
2009
2010 if (0) {
2011 /* XXX: find a suitable condition to enable the hypervisor mode */
2012 lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
2013 lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
2014 } else {
2015 /* Those values ensure we won't enter the hypervisor mode */
2016 lpes0 = 0;
2017 lpes1 = 1;
2018 }
2019
2020 qemu_log_mask(CPU_LOG_INT, "Raise exception at " ADDRX " => %08x (%02x)\n",
2021 env->nip, excp, env->error_code);
2022 msr = env->msr;
2023 new_msr = msr;
2024 srr0 = SPR_SRR0;
2025 srr1 = SPR_SRR1;
2026 asrr0 = -1;
2027 asrr1 = -1;
2028 msr &= ~((target_ulong)0x783F0000);
2029 switch (excp) {
2030 case POWERPC_EXCP_NONE:
2031 /* Should never happen */
2032 return;
2033 case POWERPC_EXCP_CRITICAL: /* Critical input */
2034 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2035 switch (excp_model) {
2036 case POWERPC_EXCP_40x:
2037 srr0 = SPR_40x_SRR2;
2038 srr1 = SPR_40x_SRR3;
2039 break;
2040 case POWERPC_EXCP_BOOKE:
2041 srr0 = SPR_BOOKE_CSRR0;
2042 srr1 = SPR_BOOKE_CSRR1;
2043 break;
2044 case POWERPC_EXCP_G2:
2045 break;
2046 default:
2047 goto excp_invalid;
2048 }
2049 goto store_next;
2050 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2051 if (msr_me == 0) {
2052 /* Machine check exception is not enabled.
2053 * Enter checkstop state.
2054 */
2055 if (qemu_log_enabled()) {
2056 qemu_log("Machine check while not allowed. "
2057 "Entering checkstop state\n");
2058 } else {
2059 fprintf(stderr, "Machine check while not allowed. "
2060 "Entering checkstop state\n");
2061 }
2062 env->halted = 1;
2063 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2064 }
2065 new_msr &= ~((target_ulong)1 << MSR_RI);
2066 new_msr &= ~((target_ulong)1 << MSR_ME);
2067 if (0) {
2068 /* XXX: find a suitable condition to enable the hypervisor mode */
2069 new_msr |= (target_ulong)MSR_HVB;
2070 }
2071 /* XXX: should also have something loaded in DAR / DSISR */
2072 switch (excp_model) {
2073 case POWERPC_EXCP_40x:
2074 srr0 = SPR_40x_SRR2;
2075 srr1 = SPR_40x_SRR3;
2076 break;
2077 case POWERPC_EXCP_BOOKE:
2078 srr0 = SPR_BOOKE_MCSRR0;
2079 srr1 = SPR_BOOKE_MCSRR1;
2080 asrr0 = SPR_BOOKE_CSRR0;
2081 asrr1 = SPR_BOOKE_CSRR1;
2082 break;
2083 default:
2084 break;
2085 }
2086 goto store_next;
2087 case POWERPC_EXCP_DSI: /* Data storage exception */
2088 LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
2089 env->spr[SPR_DSISR], env->spr[SPR_DAR]);
2090 new_msr &= ~((target_ulong)1 << MSR_RI);
2091 if (lpes1 == 0)
2092 new_msr |= (target_ulong)MSR_HVB;
2093 goto store_next;
2094 case POWERPC_EXCP_ISI: /* Instruction storage exception */
2095 LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
2096 msr, env->nip);
2097 new_msr &= ~((target_ulong)1 << MSR_RI);
2098 if (lpes1 == 0)
2099 new_msr |= (target_ulong)MSR_HVB;
2100 msr |= env->error_code;
2101 goto store_next;
2102 case POWERPC_EXCP_EXTERNAL: /* External input */
2103 new_msr &= ~((target_ulong)1 << MSR_RI);
2104 if (lpes0 == 1)
2105 new_msr |= (target_ulong)MSR_HVB;
2106 goto store_next;
2107 case POWERPC_EXCP_ALIGN: /* Alignment exception */
2108 new_msr &= ~((target_ulong)1 << MSR_RI);
2109 if (lpes1 == 0)
2110 new_msr |= (target_ulong)MSR_HVB;
2111 /* XXX: this is false */
2112 /* Get rS/rD and rA from faulting opcode */
2113 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
2114 goto store_current;
2115 case POWERPC_EXCP_PROGRAM: /* Program exception */
2116 switch (env->error_code & ~0xF) {
2117 case POWERPC_EXCP_FP:
2118 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2119 LOG_EXCP("Ignore floating point exception\n");
2120 env->exception_index = POWERPC_EXCP_NONE;
2121 env->error_code = 0;
2122 return;
2123 }
2124 new_msr &= ~((target_ulong)1 << MSR_RI);
2125 if (lpes1 == 0)
2126 new_msr |= (target_ulong)MSR_HVB;
2127 msr |= 0x00100000;
2128 if (msr_fe0 == msr_fe1)
2129 goto store_next;
2130 msr |= 0x00010000;
2131 break;
2132 case POWERPC_EXCP_INVAL:
2133 LOG_EXCP("Invalid instruction at " ADDRX "\n",
2134 env->nip);
2135 new_msr &= ~((target_ulong)1 << MSR_RI);
2136 if (lpes1 == 0)
2137 new_msr |= (target_ulong)MSR_HVB;
2138 msr |= 0x00080000;
2139 break;
2140 case POWERPC_EXCP_PRIV:
2141 new_msr &= ~((target_ulong)1 << MSR_RI);
2142 if (lpes1 == 0)
2143 new_msr |= (target_ulong)MSR_HVB;
2144 msr |= 0x00040000;
2145 break;
2146 case POWERPC_EXCP_TRAP:
2147 new_msr &= ~((target_ulong)1 << MSR_RI);
2148 if (lpes1 == 0)
2149 new_msr |= (target_ulong)MSR_HVB;
2150 msr |= 0x00020000;
2151 break;
2152 default:
2153 /* Should never occur */
2154 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2155 env->error_code);
2156 break;
2157 }
2158 goto store_current;
2159 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2160 new_msr &= ~((target_ulong)1 << MSR_RI);
2161 if (lpes1 == 0)
2162 new_msr |= (target_ulong)MSR_HVB;
2163 goto store_current;
2164 case POWERPC_EXCP_SYSCALL: /* System call exception */
2165 /* NOTE: this is a temporary hack to support graphics OSI
2166 calls from the MOL driver */
2167 /* XXX: To be removed */
2168 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2169 env->osi_call) {
2170 if (env->osi_call(env) != 0) {
2171 env->exception_index = POWERPC_EXCP_NONE;
2172 env->error_code = 0;
2173 return;
2174 }
2175 }
2176 dump_syscall(env);
2177 new_msr &= ~((target_ulong)1 << MSR_RI);
2178 lev = env->error_code;
2179 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2180 new_msr |= (target_ulong)MSR_HVB;
2181 goto store_next;
2182 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2183 new_msr &= ~((target_ulong)1 << MSR_RI);
2184 goto store_current;
2185 case POWERPC_EXCP_DECR: /* Decrementer exception */
2186 new_msr &= ~((target_ulong)1 << MSR_RI);
2187 if (lpes1 == 0)
2188 new_msr |= (target_ulong)MSR_HVB;
2189 goto store_next;
2190 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2191 /* FIT on 4xx */
2192 LOG_EXCP("FIT exception\n");
2193 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2194 goto store_next;
2195 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2196 LOG_EXCP("WDT exception\n");
2197 switch (excp_model) {
2198 case POWERPC_EXCP_BOOKE:
2199 srr0 = SPR_BOOKE_CSRR0;
2200 srr1 = SPR_BOOKE_CSRR1;
2201 break;
2202 default:
2203 break;
2204 }
2205 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2206 goto store_next;
2207 case POWERPC_EXCP_DTLB: /* Data TLB error */
2208 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2209 goto store_next;
2210 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2211 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2212 goto store_next;
2213 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2214 switch (excp_model) {
2215 case POWERPC_EXCP_BOOKE:
2216 srr0 = SPR_BOOKE_DSRR0;
2217 srr1 = SPR_BOOKE_DSRR1;
2218 asrr0 = SPR_BOOKE_CSRR0;
2219 asrr1 = SPR_BOOKE_CSRR1;
2220 break;
2221 default:
2222 break;
2223 }
2224 /* XXX: TODO */
2225 cpu_abort(env, "Debug exception is not implemented yet !\n");
2226 goto store_next;
2227 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2228 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2229 goto store_current;
2230 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2231 /* XXX: TODO */
2232 cpu_abort(env, "Embedded floating point data exception "
2233 "is not implemented yet !\n");
2234 goto store_next;
2235 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2236 /* XXX: TODO */
2237 cpu_abort(env, "Embedded floating point round exception "
2238 "is not implemented yet !\n");
2239 goto store_next;
2240 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2241 new_msr &= ~((target_ulong)1 << MSR_RI);
2242 /* XXX: TODO */
2243 cpu_abort(env,
2244 "Performance counter exception is not implemented yet !\n");
2245 goto store_next;
2246 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
2247 /* XXX: TODO */
2248 cpu_abort(env,
2249 "Embedded doorbell interrupt is not implemented yet !\n");
2250 goto store_next;
2251 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2252 switch (excp_model) {
2253 case POWERPC_EXCP_BOOKE:
2254 srr0 = SPR_BOOKE_CSRR0;
2255 srr1 = SPR_BOOKE_CSRR1;
2256 break;
2257 default:
2258 break;
2259 }
2260 /* XXX: TODO */
2261 cpu_abort(env, "Embedded doorbell critical interrupt "
2262 "is not implemented yet !\n");
2263 goto store_next;
2264 case POWERPC_EXCP_RESET: /* System reset exception */
2265 new_msr &= ~((target_ulong)1 << MSR_RI);
2266 if (0) {
2267 /* XXX: find a suitable condition to enable the hypervisor mode */
2268 new_msr |= (target_ulong)MSR_HVB;
2269 }
2270 goto store_next;
2271 case POWERPC_EXCP_DSEG: /* Data segment exception */
2272 new_msr &= ~((target_ulong)1 << MSR_RI);
2273 if (lpes1 == 0)
2274 new_msr |= (target_ulong)MSR_HVB;
2275 goto store_next;
2276 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2277 new_msr &= ~((target_ulong)1 << MSR_RI);
2278 if (lpes1 == 0)
2279 new_msr |= (target_ulong)MSR_HVB;
2280 goto store_next;
2281 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2282 srr0 = SPR_HSRR0;
2283 srr1 = SPR_HSRR1;
2284 new_msr |= (target_ulong)MSR_HVB;
2285 goto store_next;
2286 case POWERPC_EXCP_TRACE: /* Trace exception */
2287 new_msr &= ~((target_ulong)1 << MSR_RI);
2288 if (lpes1 == 0)
2289 new_msr |= (target_ulong)MSR_HVB;
2290 goto store_next;
2291 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2292 srr0 = SPR_HSRR0;
2293 srr1 = SPR_HSRR1;
2294 new_msr |= (target_ulong)MSR_HVB;
2295 goto store_next;
2296 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2297 srr0 = SPR_HSRR0;
2298 srr1 = SPR_HSRR1;
2299 new_msr |= (target_ulong)MSR_HVB;
2300 goto store_next;
2301 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2302 srr0 = SPR_HSRR0;
2303 srr1 = SPR_HSRR1;
2304 new_msr |= (target_ulong)MSR_HVB;
2305 goto store_next;
2306 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2307 srr0 = SPR_HSRR0;
2308 srr1 = SPR_HSRR1;
2309 new_msr |= (target_ulong)MSR_HVB;
2310 goto store_next;
2311 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2312 new_msr &= ~((target_ulong)1 << MSR_RI);
2313 if (lpes1 == 0)
2314 new_msr |= (target_ulong)MSR_HVB;
2315 goto store_current;
2316 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
2317 LOG_EXCP("PIT exception\n");
2318 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2319 goto store_next;
2320 case POWERPC_EXCP_IO: /* IO error exception */
2321 /* XXX: TODO */
2322 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2323 goto store_next;
2324 case POWERPC_EXCP_RUNM: /* Run mode exception */
2325 /* XXX: TODO */
2326 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2327 goto store_next;
2328 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2329 /* XXX: TODO */
2330 cpu_abort(env, "602 emulation trap exception "
2331 "is not implemented yet !\n");
2332 goto store_next;
2333 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2334 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2335 if (lpes1 == 0) /* XXX: check this */
2336 new_msr |= (target_ulong)MSR_HVB;
2337 switch (excp_model) {
2338 case POWERPC_EXCP_602:
2339 case POWERPC_EXCP_603:
2340 case POWERPC_EXCP_603E:
2341 case POWERPC_EXCP_G2:
2342 goto tlb_miss_tgpr;
2343 case POWERPC_EXCP_7x5:
2344 goto tlb_miss;
2345 case POWERPC_EXCP_74xx:
2346 goto tlb_miss_74xx;
2347 default:
2348 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2349 break;
2350 }
2351 break;
2352 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2353 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2354 if (lpes1 == 0) /* XXX: check this */
2355 new_msr |= (target_ulong)MSR_HVB;
2356 switch (excp_model) {
2357 case POWERPC_EXCP_602:
2358 case POWERPC_EXCP_603:
2359 case POWERPC_EXCP_603E:
2360 case POWERPC_EXCP_G2:
2361 goto tlb_miss_tgpr;
2362 case POWERPC_EXCP_7x5:
2363 goto tlb_miss;
2364 case POWERPC_EXCP_74xx:
2365 goto tlb_miss_74xx;
2366 default:
2367 cpu_abort(env, "Invalid data load TLB miss exception\n");
2368 break;
2369 }
2370 break;
2371 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2372 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2373 if (lpes1 == 0) /* XXX: check this */
2374 new_msr |= (target_ulong)MSR_HVB;
2375 switch (excp_model) {
2376 case POWERPC_EXCP_602:
2377 case POWERPC_EXCP_603:
2378 case POWERPC_EXCP_603E:
2379 case POWERPC_EXCP_G2:
2380 tlb_miss_tgpr:
2381 /* Swap temporary saved registers with GPRs */
2382 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
2383 new_msr |= (target_ulong)1 << MSR_TGPR;
2384 hreg_swap_gpr_tgpr(env);
2385 }
2386 goto tlb_miss;
2387 case POWERPC_EXCP_7x5:
2388 tlb_miss:
2389 #if defined (DEBUG_SOFTWARE_TLB)
2390 if (qemu_log_enabled()) {
2391 const unsigned char *es;
2392 target_ulong *miss, *cmp;
2393 int en;
2394 if (excp == POWERPC_EXCP_IFTLB) {
2395 es = "I";
2396 en = 'I';
2397 miss = &env->spr[SPR_IMISS];
2398 cmp = &env->spr[SPR_ICMP];
2399 } else {
2400 if (excp == POWERPC_EXCP_DLTLB)
2401 es = "DL";
2402 else
2403 es = "DS";
2404 en = 'D';
2405 miss = &env->spr[SPR_DMISS];
2406 cmp = &env->spr[SPR_DCMP];
2407 }
2408 qemu_log("6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2409 " H1 " ADDRX " H2 " ADDRX " %08x\n",
2410 es, en, *miss, en, *cmp,
2411 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2412 env->error_code);
2413 }
2414 #endif
2415 msr |= env->crf[0] << 28;
2416 msr |= env->error_code; /* key, D/I, S/L bits */
2417 /* Set way using a LRU mechanism */
2418 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2419 break;
2420 case POWERPC_EXCP_74xx:
2421 tlb_miss_74xx:
2422 #if defined (DEBUG_SOFTWARE_TLB)
2423 if (qemu_log_enabled()) {
2424 const unsigned char *es;
2425 target_ulong *miss, *cmp;
2426 int en;
2427 if (excp == POWERPC_EXCP_IFTLB) {
2428 es = "I";
2429 en = 'I';
2430 miss = &env->spr[SPR_TLBMISS];
2431 cmp = &env->spr[SPR_PTEHI];
2432 } else {
2433 if (excp == POWERPC_EXCP_DLTLB)
2434 es = "DL";
2435 else
2436 es = "DS";
2437 en = 'D';
2438 miss = &env->spr[SPR_TLBMISS];
2439 cmp = &env->spr[SPR_PTEHI];
2440 }
2441 qemu_log("74xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2442 " %08x\n",
2443 es, en, *miss, en, *cmp, env->error_code);
2444 }
2445 #endif
2446 msr |= env->error_code; /* key bit */
2447 break;
2448 default:
2449 cpu_abort(env, "Invalid data store TLB miss exception\n");
2450 break;
2451 }
2452 goto store_next;
2453 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2454 /* XXX: TODO */
2455 cpu_abort(env, "Floating point assist exception "
2456 "is not implemented yet !\n");
2457 goto store_next;
2458 case POWERPC_EXCP_DABR: /* Data address breakpoint */
2459 /* XXX: TODO */
2460 cpu_abort(env, "DABR exception is not implemented yet !\n");
2461 goto store_next;
2462 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2463 /* XXX: TODO */
2464 cpu_abort(env, "IABR exception is not implemented yet !\n");
2465 goto store_next;
2466 case POWERPC_EXCP_SMI: /* System management interrupt */
2467 /* XXX: TODO */
2468 cpu_abort(env, "SMI exception is not implemented yet !\n");
2469 goto store_next;
2470 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2471 /* XXX: TODO */
2472 cpu_abort(env, "Thermal management exception "
2473 "is not implemented yet !\n");
2474 goto store_next;
2475 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2476 new_msr &= ~((target_ulong)1 << MSR_RI);
2477 if (lpes1 == 0)
2478 new_msr |= (target_ulong)MSR_HVB;
2479 /* XXX: TODO */
2480 cpu_abort(env,
2481 "Performance counter exception is not implemented yet !\n");
2482 goto store_next;
2483 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2484 /* XXX: TODO */
2485 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2486 goto store_next;
2487 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2488 /* XXX: TODO */
2489 cpu_abort(env,
2490 "970 soft-patch exception is not implemented yet !\n");
2491 goto store_next;
2492 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2493 /* XXX: TODO */
2494 cpu_abort(env,
2495 "970 maintenance exception is not implemented yet !\n");
2496 goto store_next;
2497 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
2498 /* XXX: TODO */
2499 cpu_abort(env, "Maskable external exception "
2500 "is not implemented yet !\n");
2501 goto store_next;
2502 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
2503 /* XXX: TODO */
2504 cpu_abort(env, "Non maskable external exception "
2505 "is not implemented yet !\n");
2506 goto store_next;
2507 default:
2508 excp_invalid:
2509 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2510 break;
2511 store_current:
2512 /* save current instruction location */
2513 env->spr[srr0] = env->nip - 4;
2514 break;
2515 store_next:
2516 /* save next instruction location */
2517 env->spr[srr0] = env->nip;
2518 break;
2519 }
2520 /* Save MSR */
2521 env->spr[srr1] = msr;
2522 /* If any alternate SRR register are defined, duplicate saved values */
2523 if (asrr0 != -1)
2524 env->spr[asrr0] = env->spr[srr0];
2525 if (asrr1 != -1)
2526 env->spr[asrr1] = env->spr[srr1];
2527 /* If we disactivated any translation, flush TLBs */
2528 if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
2529 tlb_flush(env, 1);
2530 /* reload MSR with correct bits */
2531 new_msr &= ~((target_ulong)1 << MSR_EE);
2532 new_msr &= ~((target_ulong)1 << MSR_PR);
2533 new_msr &= ~((target_ulong)1 << MSR_FP);
2534 new_msr &= ~((target_ulong)1 << MSR_FE0);
2535 new_msr &= ~((target_ulong)1 << MSR_SE);
2536 new_msr &= ~((target_ulong)1 << MSR_BE);
2537 new_msr &= ~((target_ulong)1 << MSR_FE1);
2538 new_msr &= ~((target_ulong)1 << MSR_IR);
2539 new_msr &= ~((target_ulong)1 << MSR_DR);
2540 #if 0 /* Fix this: not on all targets */
2541 new_msr &= ~((target_ulong)1 << MSR_PMM);
2542 #endif
2543 new_msr &= ~((target_ulong)1 << MSR_LE);
2544 if (msr_ile)
2545 new_msr |= (target_ulong)1 << MSR_LE;
2546 else
2547 new_msr &= ~((target_ulong)1 << MSR_LE);
2548 /* Jump to handler */
2549 vector = env->excp_vectors[excp];
2550 if (vector == (target_ulong)-1ULL) {
2551 cpu_abort(env, "Raised an exception without defined vector %d\n",
2552 excp);
2553 }
2554 vector |= env->excp_prefix;
2555 #if defined(TARGET_PPC64)
2556 if (excp_model == POWERPC_EXCP_BOOKE) {
2557 if (!msr_icm) {
2558 new_msr &= ~((target_ulong)1 << MSR_CM);
2559 vector = (uint32_t)vector;
2560 } else {
2561 new_msr |= (target_ulong)1 << MSR_CM;
2562 }
2563 } else {
2564 if (!msr_isf) {
2565 new_msr &= ~((target_ulong)1 << MSR_SF);
2566 vector = (uint32_t)vector;
2567 } else {
2568 new_msr |= (target_ulong)1 << MSR_SF;
2569 }
2570 }
2571 #endif
2572 /* XXX: we don't use hreg_store_msr here as already have treated
2573 * any special case that could occur. Just store MSR and update hflags
2574 */
2575 env->msr = new_msr & env->msr_mask;
2576 hreg_compute_hflags(env);
2577 env->nip = vector;
2578 /* Reset exception state */
2579 env->exception_index = POWERPC_EXCP_NONE;
2580 env->error_code = 0;
2581 }
2582
2583 void do_interrupt (CPUState *env)
2584 {
2585 powerpc_excp(env, env->excp_model, env->exception_index);
2586 }
2587
2588 void ppc_hw_interrupt (CPUPPCState *env)
2589 {
2590 int hdice;
2591
2592 #if 0
2593 qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
2594 __func__, env, env->pending_interrupts,
2595 env->interrupt_request, (int)msr_me, (int)msr_ee);
2596 #endif
2597 /* External reset */
2598 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2599 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2600 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2601 return;
2602 }
2603 /* Machine check exception */
2604 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2605 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2606 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2607 return;
2608 }
2609 #if 0 /* TODO */
2610 /* External debug exception */
2611 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2612 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2613 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2614 return;
2615 }
2616 #endif
2617 if (0) {
2618 /* XXX: find a suitable condition to enable the hypervisor mode */
2619 hdice = env->spr[SPR_LPCR] & 1;
2620 } else {
2621 hdice = 0;
2622 }
2623 if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
2624 /* Hypervisor decrementer exception */
2625 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2626 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2627 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2628 return;
2629 }
2630 }
2631 if (msr_ce != 0) {
2632 /* External critical interrupt */
2633 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2634 /* Taking a critical external interrupt does not clear the external
2635 * critical interrupt status
2636 */
2637 #if 0
2638 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2639 #endif
2640 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2641 return;
2642 }
2643 }
2644 if (msr_ee != 0) {
2645 /* Watchdog timer on embedded PowerPC */
2646 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2647 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2648 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2649 return;
2650 }
2651 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2652 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2653 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2654 return;
2655 }
2656 /* Fixed interval timer on embedded PowerPC */
2657 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2658 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2659 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2660 return;
2661 }
2662 /* Programmable interval timer on embedded PowerPC */
2663 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2664 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2665 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2666 return;
2667 }
2668 /* Decrementer exception */
2669 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2670 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2671 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2672 return;
2673 }
2674 /* External interrupt */
2675 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2676 /* Taking an external interrupt does not clear the external
2677 * interrupt status
2678 */
2679 #if 0
2680 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2681 #endif
2682 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2683 return;
2684 }
2685 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2686 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2687 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2688 return;
2689 }
2690 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2691 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2692 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2693 return;
2694 }
2695 /* Thermal interrupt */
2696 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2697 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2698 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2699 return;
2700 }
2701 }
2702 }
2703 #endif /* !CONFIG_USER_ONLY */
2704
2705 void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2706 {
2707 qemu_log("Return from exception at " ADDRX " with flags " ADDRX "\n",
2708 RA, msr);
2709 }
2710
2711 void cpu_ppc_reset (void *opaque)
2712 {
2713 CPUPPCState *env = opaque;
2714 target_ulong msr;
2715
2716 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
2717 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
2718 log_cpu_state(env, 0);
2719 }
2720
2721 msr = (target_ulong)0;
2722 if (0) {
2723 /* XXX: find a suitable condition to enable the hypervisor mode */
2724 msr |= (target_ulong)MSR_HVB;
2725 }
2726 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
2727 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
2728 msr |= (target_ulong)1 << MSR_EP;
2729 #if defined (DO_SINGLE_STEP) && 0
2730 /* Single step trace mode */
2731 msr |= (target_ulong)1 << MSR_SE;
2732 msr |= (target_ulong)1 << MSR_BE;
2733 #endif
2734 #if defined(CONFIG_USER_ONLY)
2735 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
2736 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
2737 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
2738 msr |= (target_ulong)1 << MSR_PR;
2739 #else
2740 env->nip = env->hreset_vector | env->excp_prefix;
2741 if (env->mmu_model != POWERPC_MMU_REAL)
2742 ppc_tlb_invalidate_all(env);
2743 #endif
2744 env->msr = msr & env->msr_mask;
2745 hreg_compute_hflags(env);
2746 env->reserve = (target_ulong)-1ULL;
2747 /* Be sure no exception or interrupt is pending */
2748 env->pending_interrupts = 0;
2749 env->exception_index = POWERPC_EXCP_NONE;
2750 env->error_code = 0;
2751 /* Flush all TLBs */
2752 tlb_flush(env, 1);
2753 }
2754
2755 CPUPPCState *cpu_ppc_init (const char *cpu_model)
2756 {
2757 CPUPPCState *env;
2758 const ppc_def_t *def;
2759
2760 def = cpu_ppc_find_by_name(cpu_model);
2761 if (!def)
2762 return NULL;
2763
2764 env = qemu_mallocz(sizeof(CPUPPCState));
2765 cpu_exec_init(env);
2766 ppc_translate_init();
2767 env->cpu_model_str = cpu_model;
2768 cpu_ppc_register_internal(env, def);
2769 cpu_ppc_reset(env);
2770
2771 if (kvm_enabled())
2772 kvm_init_vcpu(env);
2773
2774 return env;
2775 }
2776
2777 void cpu_ppc_close (CPUPPCState *env)
2778 {
2779 /* Should also remove all opcode tables... */
2780 qemu_free(env);
2781 }
Patches shipped by Fedora