?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Make binary stripping conditional (Riku Voipio)
[qemu-kvm/fedora.git] / hw / vga.c
blob9f5d051fc0d7433d8836f1278143c31351597513
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "console.h"
26 #include "pc.h"
27 #include "pci.h"
28 #include "vga_int.h"
29 #include "pixel_ops.h"
30 #include "qemu-timer.h"
31 #include "kvm.h"
32 #include "qemu-kvm.h"
33
34 //#define DEBUG_VGA
35 //#define DEBUG_VGA_MEM
36 //#define DEBUG_VGA_REG
37
38 //#define DEBUG_BOCHS_VBE
39
40 /* force some bits to zero */
41 const uint8_t sr_mask[8] = {
42 (uint8_t)~0xfc,
43 (uint8_t)~0xc2,
44 (uint8_t)~0xf0,
45 (uint8_t)~0xc0,
46 (uint8_t)~0xf1,
47 (uint8_t)~0xff,
48 (uint8_t)~0xff,
49 (uint8_t)~0x00,
50 };
51
52 const uint8_t gr_mask[16] = {
53 (uint8_t)~0xf0, /* 0x00 */
54 (uint8_t)~0xf0, /* 0x01 */
55 (uint8_t)~0xf0, /* 0x02 */
56 (uint8_t)~0xe0, /* 0x03 */
57 (uint8_t)~0xfc, /* 0x04 */
58 (uint8_t)~0x84, /* 0x05 */
59 (uint8_t)~0xf0, /* 0x06 */
60 (uint8_t)~0xf0, /* 0x07 */
61 (uint8_t)~0x00, /* 0x08 */
62 (uint8_t)~0xff, /* 0x09 */
63 (uint8_t)~0xff, /* 0x0a */
64 (uint8_t)~0xff, /* 0x0b */
65 (uint8_t)~0xff, /* 0x0c */
66 (uint8_t)~0xff, /* 0x0d */
67 (uint8_t)~0xff, /* 0x0e */
68 (uint8_t)~0xff, /* 0x0f */
69 };
70
71 #define cbswap_32(__x) \
72 ((uint32_t)( \
73 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
74 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
75 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
76 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
77
78 #ifdef WORDS_BIGENDIAN
79 #define PAT(x) cbswap_32(x)
80 #else
81 #define PAT(x) (x)
82 #endif
83
84 #ifdef WORDS_BIGENDIAN
85 #define BIG 1
86 #else
87 #define BIG 0
88 #endif
89
90 #ifdef WORDS_BIGENDIAN
91 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
92 #else
93 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
94 #endif
95
96 static const uint32_t mask16[16] = {
97 PAT(0x00000000),
98 PAT(0x000000ff),
99 PAT(0x0000ff00),
100 PAT(0x0000ffff),
101 PAT(0x00ff0000),
102 PAT(0x00ff00ff),
103 PAT(0x00ffff00),
104 PAT(0x00ffffff),
105 PAT(0xff000000),
106 PAT(0xff0000ff),
107 PAT(0xff00ff00),
108 PAT(0xff00ffff),
109 PAT(0xffff0000),
110 PAT(0xffff00ff),
111 PAT(0xffffff00),
112 PAT(0xffffffff),
113 };
114
115 #undef PAT
116
117 #ifdef WORDS_BIGENDIAN
118 #define PAT(x) (x)
119 #else
120 #define PAT(x) cbswap_32(x)
121 #endif
122
123 static const uint32_t dmask16[16] = {
124 PAT(0x00000000),
125 PAT(0x000000ff),
126 PAT(0x0000ff00),
127 PAT(0x0000ffff),
128 PAT(0x00ff0000),
129 PAT(0x00ff00ff),
130 PAT(0x00ffff00),
131 PAT(0x00ffffff),
132 PAT(0xff000000),
133 PAT(0xff0000ff),
134 PAT(0xff00ff00),
135 PAT(0xff00ffff),
136 PAT(0xffff0000),
137 PAT(0xffff00ff),
138 PAT(0xffffff00),
139 PAT(0xffffffff),
140 };
141
142 static const uint32_t dmask4[4] = {
143 PAT(0x00000000),
144 PAT(0x0000ffff),
145 PAT(0xffff0000),
146 PAT(0xffffffff),
147 };
148
149 static uint32_t expand4[256];
150 static uint16_t expand2[256];
151 static uint8_t expand4to8[16];
152
153 static void vga_screen_dump(void *opaque, const char *filename);
154
155 static void vga_dumb_update_retrace_info(VGAState *s)
156 {
157 (void) s;
158 }
159
160 static void vga_precise_update_retrace_info(VGAState *s)
161 {
162 int htotal_chars;
163 int hretr_start_char;
164 int hretr_skew_chars;
165 int hretr_end_char;
166
167 int vtotal_lines;
168 int vretr_start_line;
169 int vretr_end_line;
170
171 int div2, sldiv2, dots;
172 int clocking_mode;
173 int clock_sel;
174 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
175 int64_t chars_per_sec;
176 struct vga_precise_retrace *r = &s->retrace_info.precise;
177
178 htotal_chars = s->cr[0x00] + 5;
179 hretr_start_char = s->cr[0x04];
180 hretr_skew_chars = (s->cr[0x05] >> 5) & 3;
181 hretr_end_char = s->cr[0x05] & 0x1f;
182
183 vtotal_lines = (s->cr[0x06]
184 | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2
185 ;
186 vretr_start_line = s->cr[0x10]
187 | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)
188 ;
189 vretr_end_line = s->cr[0x11] & 0xf;
190
191
192 div2 = (s->cr[0x17] >> 2) & 1;
193 sldiv2 = (s->cr[0x17] >> 3) & 1;
194
195 clocking_mode = (s->sr[0x01] >> 3) & 1;
196 clock_sel = (s->msr >> 2) & 3;
197 dots = (s->msr & 1) ? 8 : 9;
198
199 chars_per_sec = clk_hz[clock_sel] / dots;
200
201 htotal_chars <<= clocking_mode;
202
203 r->total_chars = vtotal_lines * htotal_chars;
204 if (r->freq) {
205 r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);
206 } else {
207 r->ticks_per_char = ticks_per_sec / chars_per_sec;
208 }
209
210 r->vstart = vretr_start_line;
211 r->vend = r->vstart + vretr_end_line + 1;
212
213 r->hstart = hretr_start_char + hretr_skew_chars;
214 r->hend = r->hstart + hretr_end_char + 1;
215 r->htotal = htotal_chars;
216
217 #if 0
218 printf (
219 "hz=%f\n"
220 "htotal = %d\n"
221 "hretr_start = %d\n"
222 "hretr_skew = %d\n"
223 "hretr_end = %d\n"
224 "vtotal = %d\n"
225 "vretr_start = %d\n"
226 "vretr_end = %d\n"
227 "div2 = %d sldiv2 = %d\n"
228 "clocking_mode = %d\n"
229 "clock_sel = %d %d\n"
230 "dots = %d\n"
231 "ticks/char = %lld\n"
232 "\n",
233 (double) ticks_per_sec / (r->ticks_per_char * r->total_chars),
234 htotal_chars,
235 hretr_start_char,
236 hretr_skew_chars,
237 hretr_end_char,
238 vtotal_lines,
239 vretr_start_line,
240 vretr_end_line,
241 div2, sldiv2,
242 clocking_mode,
243 clock_sel,
244 clk_hz[clock_sel],
245 dots,
246 r->ticks_per_char
247 );
248 #endif
249 }
250
251 static uint8_t vga_precise_retrace(VGAState *s)
252 {
253 struct vga_precise_retrace *r = &s->retrace_info.precise;
254 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
255
256 if (r->total_chars) {
257 int cur_line, cur_line_char, cur_char;
258 int64_t cur_tick;
259
260 cur_tick = qemu_get_clock(vm_clock);
261
262 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
263 cur_line = cur_char / r->htotal;
264
265 if (cur_line >= r->vstart && cur_line <= r->vend) {
266 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
267 } else {
268 cur_line_char = cur_char % r->htotal;
269 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
270 val |= ST01_DISP_ENABLE;
271 }
272 }
273
274 return val;
275 } else {
276 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
277 }
278 }
279
280 static uint8_t vga_dumb_retrace(VGAState *s)
281 {
282 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
283 }
284
285 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
286 {
287 VGAState *s = opaque;
288 int val, index;
289
290 /* check port range access depending on color/monochrome mode */
291 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
292 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
293 val = 0xff;
294 } else {
295 switch(addr) {
296 case 0x3c0:
297 if (s->ar_flip_flop == 0) {
298 val = s->ar_index;
299 } else {
300 val = 0;
301 }
302 break;
303 case 0x3c1:
304 index = s->ar_index & 0x1f;
305 if (index < 21)
306 val = s->ar[index];
307 else
308 val = 0;
309 break;
310 case 0x3c2:
311 val = s->st00;
312 break;
313 case 0x3c4:
314 val = s->sr_index;
315 break;
316 case 0x3c5:
317 val = s->sr[s->sr_index];
318 #ifdef DEBUG_VGA_REG
319 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
320 #endif
321 break;
322 case 0x3c7:
323 val = s->dac_state;
324 break;
325 case 0x3c8:
326 val = s->dac_write_index;
327 break;
328 case 0x3c9:
329 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
330 if (++s->dac_sub_index == 3) {
331 s->dac_sub_index = 0;
332 s->dac_read_index++;
333 }
334 break;
335 case 0x3ca:
336 val = s->fcr;
337 break;
338 case 0x3cc:
339 val = s->msr;
340 break;
341 case 0x3ce:
342 val = s->gr_index;
343 break;
344 case 0x3cf:
345 val = s->gr[s->gr_index];
346 #ifdef DEBUG_VGA_REG
347 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
348 #endif
349 break;
350 case 0x3b4:
351 case 0x3d4:
352 val = s->cr_index;
353 break;
354 case 0x3b5:
355 case 0x3d5:
356 val = s->cr[s->cr_index];
357 #ifdef DEBUG_VGA_REG
358 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
359 #endif
360 break;
361 case 0x3ba:
362 case 0x3da:
363 /* just toggle to fool polling */
364 val = s->st01 = s->retrace(s);
365 s->ar_flip_flop = 0;
366 break;
367 default:
368 val = 0x00;
369 break;
370 }
371 }
372 #if defined(DEBUG_VGA)
373 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
374 #endif
375 return val;
376 }
377
378 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
379 {
380 VGAState *s = opaque;
381 int index;
382
383 /* check port range access depending on color/monochrome mode */
384 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
385 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
386 return;
387
388 #ifdef DEBUG_VGA
389 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
390 #endif
391
392 switch(addr) {
393 case 0x3c0:
394 if (s->ar_flip_flop == 0) {
395 val &= 0x3f;
396 s->ar_index = val;
397 } else {
398 index = s->ar_index & 0x1f;
399 switch(index) {
400 case 0x00 ... 0x0f:
401 s->ar[index] = val & 0x3f;
402 break;
403 case 0x10:
404 s->ar[index] = val & ~0x10;
405 break;
406 case 0x11:
407 s->ar[index] = val;
408 break;
409 case 0x12:
410 s->ar[index] = val & ~0xc0;
411 break;
412 case 0x13:
413 s->ar[index] = val & ~0xf0;
414 break;
415 case 0x14:
416 s->ar[index] = val & ~0xf0;
417 break;
418 default:
419 break;
420 }
421 }
422 s->ar_flip_flop ^= 1;
423 break;
424 case 0x3c2:
425 s->msr = val & ~0x10;
426 s->update_retrace_info(s);
427 break;
428 case 0x3c4:
429 s->sr_index = val & 7;
430 break;
431 case 0x3c5:
432 #ifdef DEBUG_VGA_REG
433 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
434 #endif
435 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
436 if (s->sr_index == 1) s->update_retrace_info(s);
437 break;
438 case 0x3c7:
439 s->dac_read_index = val;
440 s->dac_sub_index = 0;
441 s->dac_state = 3;
442 break;
443 case 0x3c8:
444 s->dac_write_index = val;
445 s->dac_sub_index = 0;
446 s->dac_state = 0;
447 break;
448 case 0x3c9:
449 s->dac_cache[s->dac_sub_index] = val;
450 if (++s->dac_sub_index == 3) {
451 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
452 s->dac_sub_index = 0;
453 s->dac_write_index++;
454 }
455 break;
456 case 0x3ce:
457 s->gr_index = val & 0x0f;
458 break;
459 case 0x3cf:
460 #ifdef DEBUG_VGA_REG
461 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
462 #endif
463 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
464 break;
465 case 0x3b4:
466 case 0x3d4:
467 s->cr_index = val;
468 break;
469 case 0x3b5:
470 case 0x3d5:
471 #ifdef DEBUG_VGA_REG
472 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
473 #endif
474 /* handle CR0-7 protection */
475 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
476 /* can always write bit 4 of CR7 */
477 if (s->cr_index == 7)
478 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
479 return;
480 }
481 switch(s->cr_index) {
482 case 0x01: /* horizontal display end */
483 case 0x07:
484 case 0x09:
485 case 0x0c:
486 case 0x0d:
487 case 0x12: /* vertical display end */
488 s->cr[s->cr_index] = val;
489 break;
490 default:
491 s->cr[s->cr_index] = val;
492 break;
493 }
494
495 switch(s->cr_index) {
496 case 0x00:
497 case 0x04:
498 case 0x05:
499 case 0x06:
500 case 0x07:
501 case 0x11:
502 case 0x17:
503 s->update_retrace_info(s);
504 break;
505 }
506 break;
507 case 0x3ba:
508 case 0x3da:
509 s->fcr = val & 0x10;
510 break;
511 }
512 }
513
514 #ifdef CONFIG_BOCHS_VBE
515 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
516 {
517 VGAState *s = opaque;
518 uint32_t val;
519 val = s->vbe_index;
520 return val;
521 }
522
523 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
524 {
525 VGAState *s = opaque;
526 uint32_t val;
527
528 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
529 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
530 switch(s->vbe_index) {
531 /* XXX: do not hardcode ? */
532 case VBE_DISPI_INDEX_XRES:
533 val = VBE_DISPI_MAX_XRES;
534 break;
535 case VBE_DISPI_INDEX_YRES:
536 val = VBE_DISPI_MAX_YRES;
537 break;
538 case VBE_DISPI_INDEX_BPP:
539 val = VBE_DISPI_MAX_BPP;
540 break;
541 default:
542 val = s->vbe_regs[s->vbe_index];
543 break;
544 }
545 } else {
546 val = s->vbe_regs[s->vbe_index];
547 }
548 } else {
549 val = 0;
550 }
551 #ifdef DEBUG_BOCHS_VBE
552 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
553 #endif
554 return val;
555 }
556
557 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
558 {
559 VGAState *s = opaque;
560 s->vbe_index = val;
561 }
562
563 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
564 {
565 VGAState *s = opaque;
566
567 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
568 #ifdef DEBUG_BOCHS_VBE
569 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
570 #endif
571 switch(s->vbe_index) {
572 case VBE_DISPI_INDEX_ID:
573 if (val == VBE_DISPI_ID0 ||
574 val == VBE_DISPI_ID1 ||
575 val == VBE_DISPI_ID2 ||
576 val == VBE_DISPI_ID3 ||
577 val == VBE_DISPI_ID4) {
578 s->vbe_regs[s->vbe_index] = val;
579 }
580 break;
581 case VBE_DISPI_INDEX_XRES:
582 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
583 s->vbe_regs[s->vbe_index] = val;
584 }
585 break;
586 case VBE_DISPI_INDEX_YRES:
587 if (val <= VBE_DISPI_MAX_YRES) {
588 s->vbe_regs[s->vbe_index] = val;
589 }
590 break;
591 case VBE_DISPI_INDEX_BPP:
592 if (val == 0)
593 val = 8;
594 if (val == 4 || val == 8 || val == 15 ||
595 val == 16 || val == 24 || val == 32) {
596 s->vbe_regs[s->vbe_index] = val;
597 }
598 break;
599 case VBE_DISPI_INDEX_BANK:
600 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
601 val &= (s->vbe_bank_mask >> 2);
602 } else {
603 val &= s->vbe_bank_mask;
604 }
605 s->vbe_regs[s->vbe_index] = val;
606 s->bank_offset = (val << 16);
607 break;
608 case VBE_DISPI_INDEX_ENABLE:
609 if ((val & VBE_DISPI_ENABLED) &&
610 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
611 int h, shift_control;
612
613 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
614 s->vbe_regs[VBE_DISPI_INDEX_XRES];
615 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
616 s->vbe_regs[VBE_DISPI_INDEX_YRES];
617 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
618 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
619
620 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
621 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
622 else
623 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
624 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
625 s->vbe_start_addr = 0;
626
627 /* clear the screen (should be done in BIOS) */
628 if (!(val & VBE_DISPI_NOCLEARMEM)) {
629 memset(s->vram_ptr, 0,
630 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
631 }
632
633 /* we initialize the VGA graphic mode (should be done
634 in BIOS) */
635 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
636 s->cr[0x17] |= 3; /* no CGA modes */
637 s->cr[0x13] = s->vbe_line_offset >> 3;
638 /* width */
639 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
640 /* height (only meaningful if < 1024) */
641 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
642 s->cr[0x12] = h;
643 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
644 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
645 /* line compare to 1023 */
646 s->cr[0x18] = 0xff;
647 s->cr[0x07] |= 0x10;
648 s->cr[0x09] |= 0x40;
649
650 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
651 shift_control = 0;
652 s->sr[0x01] &= ~8; /* no double line */
653 } else {
654 shift_control = 2;
655 s->sr[4] |= 0x08; /* set chain 4 mode */
656 s->sr[2] |= 0x0f; /* activate all planes */
657 }
658 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
659 s->cr[0x09] &= ~0x9f; /* no double scan */
660 } else {
661 /* XXX: the bios should do that */
662 s->bank_offset = 0;
663 }
664 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
665 s->vbe_regs[s->vbe_index] = val;
666 break;
667 case VBE_DISPI_INDEX_VIRT_WIDTH:
668 {
669 int w, h, line_offset;
670
671 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
672 return;
673 w = val;
674 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
675 line_offset = w >> 1;
676 else
677 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
678 h = s->vram_size / line_offset;
679 /* XXX: support weird bochs semantics ? */
680 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
681 return;
682 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
683 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
684 s->vbe_line_offset = line_offset;
685 }
686 break;
687 case VBE_DISPI_INDEX_X_OFFSET:
688 case VBE_DISPI_INDEX_Y_OFFSET:
689 {
690 int x;
691 s->vbe_regs[s->vbe_index] = val;
692 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
693 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
694 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
695 s->vbe_start_addr += x >> 1;
696 else
697 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
698 s->vbe_start_addr >>= 2;
699 }
700 break;
701 default:
702 break;
703 }
704 }
705 }
706 #endif
707
708 /* called for accesses between 0xa0000 and 0xc0000 */
709 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
710 {
711 VGAState *s = opaque;
712 int memory_map_mode, plane;
713 uint32_t ret;
714
715 /* convert to VGA memory offset */
716 memory_map_mode = (s->gr[6] >> 2) & 3;
717 addr &= 0x1ffff;
718 switch(memory_map_mode) {
719 case 0:
720 break;
721 case 1:
722 if (addr >= 0x10000)
723 return 0xff;
724 addr += s->bank_offset;
725 break;
726 case 2:
727 addr -= 0x10000;
728 if (addr >= 0x8000)
729 return 0xff;
730 break;
731 default:
732 case 3:
733 addr -= 0x18000;
734 if (addr >= 0x8000)
735 return 0xff;
736 break;
737 }
738
739 if (s->sr[4] & 0x08) {
740 /* chain 4 mode : simplest access */
741 ret = s->vram_ptr[addr];
742 } else if (s->gr[5] & 0x10) {
743 /* odd/even mode (aka text mode mapping) */
744 plane = (s->gr[4] & 2) | (addr & 1);
745 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
746 } else {
747 /* standard VGA latched access */
748 s->latch = ((uint32_t *)s->vram_ptr)[addr];
749
750 if (!(s->gr[5] & 0x08)) {
751 /* read mode 0 */
752 plane = s->gr[4];
753 ret = GET_PLANE(s->latch, plane);
754 } else {
755 /* read mode 1 */
756 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
757 ret |= ret >> 16;
758 ret |= ret >> 8;
759 ret = (~ret) & 0xff;
760 }
761 }
762 return ret;
763 }
764
765 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
766 {
767 uint32_t v;
768 #ifdef TARGET_WORDS_BIGENDIAN
769 v = vga_mem_readb(opaque, addr) << 8;
770 v |= vga_mem_readb(opaque, addr + 1);
771 #else
772 v = vga_mem_readb(opaque, addr);
773 v |= vga_mem_readb(opaque, addr + 1) << 8;
774 #endif
775 return v;
776 }
777
778 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
779 {
780 uint32_t v;
781 #ifdef TARGET_WORDS_BIGENDIAN
782 v = vga_mem_readb(opaque, addr) << 24;
783 v |= vga_mem_readb(opaque, addr + 1) << 16;
784 v |= vga_mem_readb(opaque, addr + 2) << 8;
785 v |= vga_mem_readb(opaque, addr + 3);
786 #else
787 v = vga_mem_readb(opaque, addr);
788 v |= vga_mem_readb(opaque, addr + 1) << 8;
789 v |= vga_mem_readb(opaque, addr + 2) << 16;
790 v |= vga_mem_readb(opaque, addr + 3) << 24;
791 #endif
792 return v;
793 }
794
795 /* called for accesses between 0xa0000 and 0xc0000 */
796 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
797 {
798 VGAState *s = opaque;
799 int memory_map_mode, plane, write_mode, b, func_select, mask;
800 uint32_t write_mask, bit_mask, set_mask;
801
802 #ifdef DEBUG_VGA_MEM
803 printf("vga: [0x%x] = 0x%02x\n", addr, val);
804 #endif
805 /* convert to VGA memory offset */
806 memory_map_mode = (s->gr[6] >> 2) & 3;
807 addr &= 0x1ffff;
808 switch(memory_map_mode) {
809 case 0:
810 break;
811 case 1:
812 if (addr >= 0x10000)
813 return;
814 addr += s->bank_offset;
815 break;
816 case 2:
817 addr -= 0x10000;
818 if (addr >= 0x8000)
819 return;
820 break;
821 default:
822 case 3:
823 addr -= 0x18000;
824 if (addr >= 0x8000)
825 return;
826 break;
827 }
828
829 if (s->sr[4] & 0x08) {
830 /* chain 4 mode : simplest access */
831 plane = addr & 3;
832 mask = (1 << plane);
833 if (s->sr[2] & mask) {
834 s->vram_ptr[addr] = val;
835 #ifdef DEBUG_VGA_MEM
836 printf("vga: chain4: [0x%x]\n", addr);
837 #endif
838 s->plane_updated |= mask; /* only used to detect font change */
839 cpu_physical_memory_set_dirty(s->vram_offset + addr);
840 }
841 } else if (s->gr[5] & 0x10) {
842 /* odd/even mode (aka text mode mapping) */
843 plane = (s->gr[4] & 2) | (addr & 1);
844 mask = (1 << plane);
845 if (s->sr[2] & mask) {
846 addr = ((addr & ~1) << 1) | plane;
847 s->vram_ptr[addr] = val;
848 #ifdef DEBUG_VGA_MEM
849 printf("vga: odd/even: [0x%x]\n", addr);
850 #endif
851 s->plane_updated |= mask; /* only used to detect font change */
852 cpu_physical_memory_set_dirty(s->vram_offset + addr);
853 }
854 } else {
855 /* standard VGA latched access */
856 write_mode = s->gr[5] & 3;
857 switch(write_mode) {
858 default:
859 case 0:
860 /* rotate */
861 b = s->gr[3] & 7;
862 val = ((val >> b) | (val << (8 - b))) & 0xff;
863 val |= val << 8;
864 val |= val << 16;
865
866 /* apply set/reset mask */
867 set_mask = mask16[s->gr[1]];
868 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
869 bit_mask = s->gr[8];
870 break;
871 case 1:
872 val = s->latch;
873 goto do_write;
874 case 2:
875 val = mask16[val & 0x0f];
876 bit_mask = s->gr[8];
877 break;
878 case 3:
879 /* rotate */
880 b = s->gr[3] & 7;
881 val = (val >> b) | (val << (8 - b));
882
883 bit_mask = s->gr[8] & val;
884 val = mask16[s->gr[0]];
885 break;
886 }
887
888 /* apply logical operation */
889 func_select = s->gr[3] >> 3;
890 switch(func_select) {
891 case 0:
892 default:
893 /* nothing to do */
894 break;
895 case 1:
896 /* and */
897 val &= s->latch;
898 break;
899 case 2:
900 /* or */
901 val |= s->latch;
902 break;
903 case 3:
904 /* xor */
905 val ^= s->latch;
906 break;
907 }
908
909 /* apply bit mask */
910 bit_mask |= bit_mask << 8;
911 bit_mask |= bit_mask << 16;
912 val = (val & bit_mask) | (s->latch & ~bit_mask);
913
914 do_write:
915 /* mask data according to sr[2] */
916 mask = s->sr[2];
917 s->plane_updated |= mask; /* only used to detect font change */
918 write_mask = mask16[mask];
919 ((uint32_t *)s->vram_ptr)[addr] =
920 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
921 (val & write_mask);
922 #ifdef DEBUG_VGA_MEM
923 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
924 addr * 4, write_mask, val);
925 #endif
926 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
927 }
928 }
929
930 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
931 {
932 #ifdef TARGET_WORDS_BIGENDIAN
933 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
934 vga_mem_writeb(opaque, addr + 1, val & 0xff);
935 #else
936 vga_mem_writeb(opaque, addr, val & 0xff);
937 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
938 #endif
939 }
940
941 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
942 {
943 #ifdef TARGET_WORDS_BIGENDIAN
944 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
945 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
946 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
947 vga_mem_writeb(opaque, addr + 3, val & 0xff);
948 #else
949 vga_mem_writeb(opaque, addr, val & 0xff);
950 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
951 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
952 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
953 #endif
954 }
955
956 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
957 const uint8_t *font_ptr, int h,
958 uint32_t fgcol, uint32_t bgcol);
959 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
960 const uint8_t *font_ptr, int h,
961 uint32_t fgcol, uint32_t bgcol, int dup9);
962 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
963 const uint8_t *s, int width);
964
965 #define DEPTH 8
966 #include "vga_template.h"
967
968 #define DEPTH 15
969 #include "vga_template.h"
970
971 #define BGR_FORMAT
972 #define DEPTH 15
973 #include "vga_template.h"
974
975 #define DEPTH 16
976 #include "vga_template.h"
977
978 #define BGR_FORMAT
979 #define DEPTH 16
980 #include "vga_template.h"
981
982 #define DEPTH 32
983 #include "vga_template.h"
984
985 #define BGR_FORMAT
986 #define DEPTH 32
987 #include "vga_template.h"
988
989 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
990 {
991 unsigned int col;
992 col = rgb_to_pixel8(r, g, b);
993 col |= col << 8;
994 col |= col << 16;
995 return col;
996 }
997
998 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
999 {
1000 unsigned int col;
1001 col = rgb_to_pixel15(r, g, b);
1002 col |= col << 16;
1003 return col;
1004 }
1005
1006 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1007 unsigned int b)
1008 {
1009 unsigned int col;
1010 col = rgb_to_pixel15bgr(r, g, b);
1011 col |= col << 16;
1012 return col;
1013 }
1014
1015 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1016 {
1017 unsigned int col;
1018 col = rgb_to_pixel16(r, g, b);
1019 col |= col << 16;
1020 return col;
1021 }
1022
1023 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1024 unsigned int b)
1025 {
1026 unsigned int col;
1027 col = rgb_to_pixel16bgr(r, g, b);
1028 col |= col << 16;
1029 return col;
1030 }
1031
1032 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1033 {
1034 unsigned int col;
1035 col = rgb_to_pixel32(r, g, b);
1036 return col;
1037 }
1038
1039 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1040 {
1041 unsigned int col;
1042 col = rgb_to_pixel32bgr(r, g, b);
1043 return col;
1044 }
1045
1046 /* return true if the palette was modified */
1047 static int update_palette16(VGAState *s)
1048 {
1049 int full_update, i;
1050 uint32_t v, col, *palette;
1051
1052 full_update = 0;
1053 palette = s->last_palette;
1054 for(i = 0; i < 16; i++) {
1055 v = s->ar[i];
1056 if (s->ar[0x10] & 0x80)
1057 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1058 else
1059 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1060 v = v * 3;
1061 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1062 c6_to_8(s->palette[v + 1]),
1063 c6_to_8(s->palette[v + 2]));
1064 if (col != palette[i]) {
1065 full_update = 1;
1066 palette[i] = col;
1067 }
1068 }
1069 return full_update;
1070 }
1071
1072 /* return true if the palette was modified */
1073 static int update_palette256(VGAState *s)
1074 {
1075 int full_update, i;
1076 uint32_t v, col, *palette;
1077
1078 full_update = 0;
1079 palette = s->last_palette;
1080 v = 0;
1081 for(i = 0; i < 256; i++) {
1082 if (s->dac_8bit) {
1083 col = s->rgb_to_pixel(s->palette[v],
1084 s->palette[v + 1],
1085 s->palette[v + 2]);
1086 } else {
1087 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1088 c6_to_8(s->palette[v + 1]),
1089 c6_to_8(s->palette[v + 2]));
1090 }
1091 if (col != palette[i]) {
1092 full_update = 1;
1093 palette[i] = col;
1094 }
1095 v += 3;
1096 }
1097 return full_update;
1098 }
1099
1100 static void vga_get_offsets(VGAState *s,
1101 uint32_t *pline_offset,
1102 uint32_t *pstart_addr,
1103 uint32_t *pline_compare)
1104 {
1105 uint32_t start_addr, line_offset, line_compare;
1106 #ifdef CONFIG_BOCHS_VBE
1107 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1108 line_offset = s->vbe_line_offset;
1109 start_addr = s->vbe_start_addr;
1110 line_compare = 65535;
1111 } else
1112 #endif
1113 {
1114 /* compute line_offset in bytes */
1115 line_offset = s->cr[0x13];
1116 line_offset <<= 3;
1117
1118 /* starting address */
1119 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1120
1121 /* line compare */
1122 line_compare = s->cr[0x18] |
1123 ((s->cr[0x07] & 0x10) << 4) |
1124 ((s->cr[0x09] & 0x40) << 3);
1125 }
1126 *pline_offset = line_offset;
1127 *pstart_addr = start_addr;
1128 *pline_compare = line_compare;
1129 }
1130
1131 /* update start_addr and line_offset. Return TRUE if modified */
1132 static int update_basic_params(VGAState *s)
1133 {
1134 int full_update;
1135 uint32_t start_addr, line_offset, line_compare;
1136
1137 full_update = 0;
1138
1139 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1140
1141 if (line_offset != s->line_offset ||
1142 start_addr != s->start_addr ||
1143 line_compare != s->line_compare) {
1144 s->line_offset = line_offset;
1145 s->start_addr = start_addr;
1146 s->line_compare = line_compare;
1147 full_update = 1;
1148 }
1149 return full_update;
1150 }
1151
1152 #define NB_DEPTHS 7
1153
1154 static inline int get_depth_index(DisplayState *s)
1155 {
1156 switch(ds_get_bits_per_pixel(s)) {
1157 default:
1158 case 8:
1159 return 0;
1160 case 15:
1161 return 1;
1162 case 16:
1163 return 2;
1164 case 32:
1165 return 3;
1166 }
1167 }
1168
1169 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
1170 vga_draw_glyph8_8,
1171 vga_draw_glyph8_16,
1172 vga_draw_glyph8_16,
1173 vga_draw_glyph8_32,
1174 vga_draw_glyph8_32,
1175 vga_draw_glyph8_16,
1176 vga_draw_glyph8_16,
1177 };
1178
1179 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1180 vga_draw_glyph16_8,
1181 vga_draw_glyph16_16,
1182 vga_draw_glyph16_16,
1183 vga_draw_glyph16_32,
1184 vga_draw_glyph16_32,
1185 vga_draw_glyph16_16,
1186 vga_draw_glyph16_16,
1187 };
1188
1189 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1190 vga_draw_glyph9_8,
1191 vga_draw_glyph9_16,
1192 vga_draw_glyph9_16,
1193 vga_draw_glyph9_32,
1194 vga_draw_glyph9_32,
1195 vga_draw_glyph9_16,
1196 vga_draw_glyph9_16,
1197 };
1198
1199 static const uint8_t cursor_glyph[32 * 4] = {
1200 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1201 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1202 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1203 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1204 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1205 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1206 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1207 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1208 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1209 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1212 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1213 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1214 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1215 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1216 };
1217
1218 static void vga_get_text_resolution(VGAState *s, int *pwidth, int *pheight,
1219 int *pcwidth, int *pcheight)
1220 {
1221 int width, cwidth, height, cheight;
1222
1223 /* total width & height */
1224 cheight = (s->cr[9] & 0x1f) + 1;
1225 cwidth = 8;
1226 if (!(s->sr[1] & 0x01))
1227 cwidth = 9;
1228 if (s->sr[1] & 0x08)
1229 cwidth = 16; /* NOTE: no 18 pixel wide */
1230 width = (s->cr[0x01] + 1);
1231 if (s->cr[0x06] == 100) {
1232 /* ugly hack for CGA 160x100x16 - explain me the logic */
1233 height = 100;
1234 } else {
1235 height = s->cr[0x12] |
1236 ((s->cr[0x07] & 0x02) << 7) |
1237 ((s->cr[0x07] & 0x40) << 3);
1238 height = (height + 1) / cheight;
1239 }
1240
1241 *pwidth = width;
1242 *pheight = height;
1243 *pcwidth = cwidth;
1244 *pcheight = cheight;
1245 }
1246
1247 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1248
1249 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1250 rgb_to_pixel8_dup,
1251 rgb_to_pixel15_dup,
1252 rgb_to_pixel16_dup,
1253 rgb_to_pixel32_dup,
1254 rgb_to_pixel32bgr_dup,
1255 rgb_to_pixel15bgr_dup,
1256 rgb_to_pixel16bgr_dup,
1257 };
1258
1259 /*
1260 * Text mode update
1261 * Missing:
1262 * - double scan
1263 * - double width
1264 * - underline
1265 * - flashing
1266 */
1267 static void vga_draw_text(VGAState *s, int full_update)
1268 {
1269 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1270 int cx_min, cx_max, linesize, x_incr;
1271 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1272 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1273 const uint8_t *font_ptr, *font_base[2];
1274 int dup9, line_offset, depth_index;
1275 uint32_t *palette;
1276 uint32_t *ch_attr_ptr;
1277 vga_draw_glyph8_func *vga_draw_glyph8;
1278 vga_draw_glyph9_func *vga_draw_glyph9;
1279
1280 vga_dirty_log_stop(s);
1281
1282 /* compute font data address (in plane 2) */
1283 v = s->sr[3];
1284 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1285 if (offset != s->font_offsets[0]) {
1286 s->font_offsets[0] = offset;
1287 full_update = 1;
1288 }
1289 font_base[0] = s->vram_ptr + offset;
1290
1291 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1292 font_base[1] = s->vram_ptr + offset;
1293 if (offset != s->font_offsets[1]) {
1294 s->font_offsets[1] = offset;
1295 full_update = 1;
1296 }
1297 if (s->plane_updated & (1 << 2)) {
1298 /* if the plane 2 was modified since the last display, it
1299 indicates the font may have been modified */
1300 s->plane_updated = 0;
1301 full_update = 1;
1302 }
1303 full_update |= update_basic_params(s);
1304
1305 line_offset = s->line_offset;
1306 s1 = s->vram_ptr + (s->start_addr * 4);
1307
1308 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1309 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1310 if ((height * width) > CH_ATTR_SIZE) {
1311 /* better than nothing: exit if transient size is too big */
1312 return;
1313 }
1314
1315 if (width != s->last_width || height != s->last_height ||
1316 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1317 s->last_scr_width = width * cw;
1318 s->last_scr_height = height * cheight;
1319 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1320 s->last_depth = 0;
1321 s->last_width = width;
1322 s->last_height = height;
1323 s->last_ch = cheight;
1324 s->last_cw = cw;
1325 full_update = 1;
1326 }
1327 s->rgb_to_pixel =
1328 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1329 full_update |= update_palette16(s);
1330 palette = s->last_palette;
1331 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1332
1333 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1334 if (cursor_offset != s->cursor_offset ||
1335 s->cr[0xa] != s->cursor_start ||
1336 s->cr[0xb] != s->cursor_end) {
1337 /* if the cursor position changed, we update the old and new
1338 chars */
1339 if (s->cursor_offset < CH_ATTR_SIZE)
1340 s->last_ch_attr[s->cursor_offset] = -1;
1341 if (cursor_offset < CH_ATTR_SIZE)
1342 s->last_ch_attr[cursor_offset] = -1;
1343 s->cursor_offset = cursor_offset;
1344 s->cursor_start = s->cr[0xa];
1345 s->cursor_end = s->cr[0xb];
1346 }
1347 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1348
1349 depth_index = get_depth_index(s->ds);
1350 if (cw == 16)
1351 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1352 else
1353 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1354 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1355
1356 dest = ds_get_data(s->ds);
1357 linesize = ds_get_linesize(s->ds);
1358 ch_attr_ptr = s->last_ch_attr;
1359 for(cy = 0; cy < height; cy++) {
1360 d1 = dest;
1361 src = s1;
1362 cx_min = width;
1363 cx_max = -1;
1364 for(cx = 0; cx < width; cx++) {
1365 ch_attr = *(uint16_t *)src;
1366 if (full_update || ch_attr != *ch_attr_ptr) {
1367 if (cx < cx_min)
1368 cx_min = cx;
1369 if (cx > cx_max)
1370 cx_max = cx;
1371 *ch_attr_ptr = ch_attr;
1372 #ifdef WORDS_BIGENDIAN
1373 ch = ch_attr >> 8;
1374 cattr = ch_attr & 0xff;
1375 #else
1376 ch = ch_attr & 0xff;
1377 cattr = ch_attr >> 8;
1378 #endif
1379 font_ptr = font_base[(cattr >> 3) & 1];
1380 font_ptr += 32 * 4 * ch;
1381 bgcol = palette[cattr >> 4];
1382 fgcol = palette[cattr & 0x0f];
1383 if (cw != 9) {
1384 vga_draw_glyph8(d1, linesize,
1385 font_ptr, cheight, fgcol, bgcol);
1386 } else {
1387 dup9 = 0;
1388 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1389 dup9 = 1;
1390 vga_draw_glyph9(d1, linesize,
1391 font_ptr, cheight, fgcol, bgcol, dup9);
1392 }
1393 if (src == cursor_ptr &&
1394 !(s->cr[0x0a] & 0x20)) {
1395 int line_start, line_last, h;
1396 /* draw the cursor */
1397 line_start = s->cr[0x0a] & 0x1f;
1398 line_last = s->cr[0x0b] & 0x1f;
1399 /* XXX: check that */
1400 if (line_last > cheight - 1)
1401 line_last = cheight - 1;
1402 if (line_last >= line_start && line_start < cheight) {
1403 h = line_last - line_start + 1;
1404 d = d1 + linesize * line_start;
1405 if (cw != 9) {
1406 vga_draw_glyph8(d, linesize,
1407 cursor_glyph, h, fgcol, bgcol);
1408 } else {
1409 vga_draw_glyph9(d, linesize,
1410 cursor_glyph, h, fgcol, bgcol, 1);
1411 }
1412 }
1413 }
1414 }
1415 d1 += x_incr;
1416 src += 4;
1417 ch_attr_ptr++;
1418 }
1419 if (cx_max != -1) {
1420 dpy_update(s->ds, cx_min * cw, cy * cheight,
1421 (cx_max - cx_min + 1) * cw, cheight);
1422 }
1423 dest += linesize * cheight;
1424 s1 += line_offset;
1425 }
1426 }
1427
1428 enum {
1429 VGA_DRAW_LINE2,
1430 VGA_DRAW_LINE2D2,
1431 VGA_DRAW_LINE4,
1432 VGA_DRAW_LINE4D2,
1433 VGA_DRAW_LINE8D2,
1434 VGA_DRAW_LINE8,
1435 VGA_DRAW_LINE15,
1436 VGA_DRAW_LINE16,
1437 VGA_DRAW_LINE24,
1438 VGA_DRAW_LINE32,
1439 VGA_DRAW_LINE_NB,
1440 };
1441
1442 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1443 vga_draw_line2_8,
1444 vga_draw_line2_16,
1445 vga_draw_line2_16,
1446 vga_draw_line2_32,
1447 vga_draw_line2_32,
1448 vga_draw_line2_16,
1449 vga_draw_line2_16,
1450
1451 vga_draw_line2d2_8,
1452 vga_draw_line2d2_16,
1453 vga_draw_line2d2_16,
1454 vga_draw_line2d2_32,
1455 vga_draw_line2d2_32,
1456 vga_draw_line2d2_16,
1457 vga_draw_line2d2_16,
1458
1459 vga_draw_line4_8,
1460 vga_draw_line4_16,
1461 vga_draw_line4_16,
1462 vga_draw_line4_32,
1463 vga_draw_line4_32,
1464 vga_draw_line4_16,
1465 vga_draw_line4_16,
1466
1467 vga_draw_line4d2_8,
1468 vga_draw_line4d2_16,
1469 vga_draw_line4d2_16,
1470 vga_draw_line4d2_32,
1471 vga_draw_line4d2_32,
1472 vga_draw_line4d2_16,
1473 vga_draw_line4d2_16,
1474
1475 vga_draw_line8d2_8,
1476 vga_draw_line8d2_16,
1477 vga_draw_line8d2_16,
1478 vga_draw_line8d2_32,
1479 vga_draw_line8d2_32,
1480 vga_draw_line8d2_16,
1481 vga_draw_line8d2_16,
1482
1483 vga_draw_line8_8,
1484 vga_draw_line8_16,
1485 vga_draw_line8_16,
1486 vga_draw_line8_32,
1487 vga_draw_line8_32,
1488 vga_draw_line8_16,
1489 vga_draw_line8_16,
1490
1491 vga_draw_line15_8,
1492 vga_draw_line15_15,
1493 vga_draw_line15_16,
1494 vga_draw_line15_32,
1495 vga_draw_line15_32bgr,
1496 vga_draw_line15_15bgr,
1497 vga_draw_line15_16bgr,
1498
1499 vga_draw_line16_8,
1500 vga_draw_line16_15,
1501 vga_draw_line16_16,
1502 vga_draw_line16_32,
1503 vga_draw_line16_32bgr,
1504 vga_draw_line16_15bgr,
1505 vga_draw_line16_16bgr,
1506
1507 vga_draw_line24_8,
1508 vga_draw_line24_15,
1509 vga_draw_line24_16,
1510 vga_draw_line24_32,
1511 vga_draw_line24_32bgr,
1512 vga_draw_line24_15bgr,
1513 vga_draw_line24_16bgr,
1514
1515 vga_draw_line32_8,
1516 vga_draw_line32_15,
1517 vga_draw_line32_16,
1518 vga_draw_line32_32,
1519 vga_draw_line32_32bgr,
1520 vga_draw_line32_15bgr,
1521 vga_draw_line32_16bgr,
1522 };
1523
1524 static int vga_get_bpp(VGAState *s)
1525 {
1526 int ret;
1527 #ifdef CONFIG_BOCHS_VBE
1528 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1529 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1530 } else
1531 #endif
1532 {
1533 ret = 0;
1534 }
1535 return ret;
1536 }
1537
1538 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1539 {
1540 int width, height;
1541
1542 #ifdef CONFIG_BOCHS_VBE
1543 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1544 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1545 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1546 } else
1547 #endif
1548 {
1549 width = (s->cr[0x01] + 1) * 8;
1550 height = s->cr[0x12] |
1551 ((s->cr[0x07] & 0x02) << 7) |
1552 ((s->cr[0x07] & 0x40) << 3);
1553 height = (height + 1);
1554 }
1555 *pwidth = width;
1556 *pheight = height;
1557 }
1558
1559 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1560 {
1561 int y;
1562 if (y1 >= VGA_MAX_HEIGHT)
1563 return;
1564 if (y2 >= VGA_MAX_HEIGHT)
1565 y2 = VGA_MAX_HEIGHT;
1566 for(y = y1; y < y2; y++) {
1567 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1568 }
1569 }
1570
1571 static void vga_sync_dirty_bitmap(VGAState *s)
1572 {
1573 if (s->map_addr)
1574 cpu_physical_sync_dirty_bitmap(s->map_addr, s->map_end);
1575
1576 if (s->lfb_vram_mapped) {
1577 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa0000, 0xa8000);
1578 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa8000, 0xb0000);
1579 }
1580 vga_dirty_log_start(s);
1581 }
1582
1583 /*
1584 * graphic modes
1585 */
1586 static void vga_draw_graphic(VGAState *s, int full_update)
1587 {
1588 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1589 int width, height, shift_control, line_offset, bwidth, bits;
1590 int disp_width, multi_scan, multi_run;
1591 uint8_t *d;
1592 uint32_t v, addr1, addr;
1593 long page0, page1, page_min, page_max;
1594 vga_draw_line_func *vga_draw_line;
1595
1596 full_update |= update_basic_params(s);
1597
1598 if (!full_update)
1599 vga_sync_dirty_bitmap(s);
1600
1601 s->get_resolution(s, &width, &height);
1602 disp_width = width;
1603
1604 shift_control = (s->gr[0x05] >> 5) & 3;
1605 double_scan = (s->cr[0x09] >> 7);
1606 if (shift_control != 1) {
1607 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1608 } else {
1609 /* in CGA modes, multi_scan is ignored */
1610 /* XXX: is it correct ? */
1611 multi_scan = double_scan;
1612 }
1613 multi_run = multi_scan;
1614 if (shift_control != s->shift_control ||
1615 double_scan != s->double_scan) {
1616 full_update = 1;
1617 s->shift_control = shift_control;
1618 s->double_scan = double_scan;
1619 }
1620
1621 if (shift_control == 0) {
1622 if (s->sr[0x01] & 8) {
1623 disp_width <<= 1;
1624 }
1625 } else if (shift_control == 1) {
1626 if (s->sr[0x01] & 8) {
1627 disp_width <<= 1;
1628 }
1629 }
1630
1631 depth = s->get_bpp(s);
1632 if (s->line_offset != s->last_line_offset ||
1633 disp_width != s->last_width ||
1634 height != s->last_height ||
1635 s->last_depth != depth) {
1636 #if defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1637 if (depth == 16 || depth == 32) {
1638 #else
1639 if (depth == 32) {
1640 #endif
1641 if (is_graphic_console()) {
1642 qemu_free_displaysurface(s->ds->surface);
1643 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1644 s->line_offset,
1645 s->vram_ptr + (s->start_addr * 4));
1646 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1647 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
1648 #endif
1649 dpy_resize(s->ds);
1650 } else {
1651 qemu_console_resize(s->ds, disp_width, height);
1652 }
1653 } else {
1654 qemu_console_resize(s->ds, disp_width, height);
1655 }
1656 s->last_scr_width = disp_width;
1657 s->last_scr_height = height;
1658 s->last_width = disp_width;
1659 s->last_height = height;
1660 s->last_line_offset = s->line_offset;
1661 s->last_depth = depth;
1662 full_update = 1;
1663 } else if (is_graphic_console() && is_buffer_shared(s->ds->surface) &&
1664 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1665 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1666 dpy_setdata(s->ds);
1667 }
1668
1669 s->rgb_to_pixel =
1670 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1671
1672 if (shift_control == 0) {
1673 full_update |= update_palette16(s);
1674 if (s->sr[0x01] & 8) {
1675 v = VGA_DRAW_LINE4D2;
1676 } else {
1677 v = VGA_DRAW_LINE4;
1678 }
1679 bits = 4;
1680 } else if (shift_control == 1) {
1681 full_update |= update_palette16(s);
1682 if (s->sr[0x01] & 8) {
1683 v = VGA_DRAW_LINE2D2;
1684 } else {
1685 v = VGA_DRAW_LINE2;
1686 }
1687 bits = 4;
1688 } else {
1689 switch(s->get_bpp(s)) {
1690 default:
1691 case 0:
1692 full_update |= update_palette256(s);
1693 v = VGA_DRAW_LINE8D2;
1694 bits = 4;
1695 break;
1696 case 8:
1697 full_update |= update_palette256(s);
1698 v = VGA_DRAW_LINE8;
1699 bits = 8;
1700 break;
1701 case 15:
1702 v = VGA_DRAW_LINE15;
1703 bits = 16;
1704 break;
1705 case 16:
1706 v = VGA_DRAW_LINE16;
1707 bits = 16;
1708 break;
1709 case 24:
1710 v = VGA_DRAW_LINE24;
1711 bits = 24;
1712 break;
1713 case 32:
1714 v = VGA_DRAW_LINE32;
1715 bits = 32;
1716 break;
1717 }
1718 }
1719 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1720
1721 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
1722 s->cursor_invalidate(s);
1723
1724 line_offset = s->line_offset;
1725 #if 0
1726 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1727 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1728 #endif
1729 addr1 = (s->start_addr * 4);
1730 bwidth = (width * bits + 7) / 8;
1731 y_start = -1;
1732 page_min = 0x7fffffff;
1733 page_max = -1;
1734 d = ds_get_data(s->ds);
1735 linesize = ds_get_linesize(s->ds);
1736 y1 = 0;
1737 for(y = 0; y < height; y++) {
1738 addr = addr1;
1739 if (!(s->cr[0x17] & 1)) {
1740 int shift;
1741 /* CGA compatibility handling */
1742 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1743 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1744 }
1745 if (!(s->cr[0x17] & 2)) {
1746 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1747 }
1748 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1749 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1750 update = full_update |
1751 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1752 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1753 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1754 /* if wide line, can use another page */
1755 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1756 VGA_DIRTY_FLAG);
1757 }
1758 /* explicit invalidation for the hardware cursor */
1759 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1760 if (update) {
1761 if (y_start < 0)
1762 y_start = y;
1763 if (page0 < page_min)
1764 page_min = page0;
1765 if (page1 > page_max)
1766 page_max = page1;
1767 if (!(is_buffer_shared(s->ds->surface))) {
1768 vga_draw_line(s, d, s->vram_ptr + addr, width);
1769 if (s->cursor_draw_line)
1770 s->cursor_draw_line(s, d, y);
1771 }
1772 } else {
1773 if (y_start >= 0) {
1774 /* flush to display */
1775 dpy_update(s->ds, 0, y_start,
1776 disp_width, y - y_start);
1777 y_start = -1;
1778 }
1779 }
1780 if (!multi_run) {
1781 mask = (s->cr[0x17] & 3) ^ 3;
1782 if ((y1 & mask) == mask)
1783 addr1 += line_offset;
1784 y1++;
1785 multi_run = multi_scan;
1786 } else {
1787 multi_run--;
1788 }
1789 /* line compare acts on the displayed lines */
1790 if (y == s->line_compare)
1791 addr1 = 0;
1792 d += linesize;
1793 }
1794 if (y_start >= 0) {
1795 /* flush to display */
1796 dpy_update(s->ds, 0, y_start,
1797 disp_width, y - y_start);
1798 }
1799 /* reset modified pages */
1800 if (page_max != -1) {
1801 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1802 VGA_DIRTY_FLAG);
1803 }
1804 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1805 }
1806
1807 static void vga_draw_blank(VGAState *s, int full_update)
1808 {
1809 int i, w, val;
1810 uint8_t *d;
1811
1812 if (!full_update)
1813 return;
1814 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1815 return;
1816 vga_dirty_log_stop(s);
1817
1818 s->rgb_to_pixel =
1819 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1820 if (ds_get_bits_per_pixel(s->ds) == 8)
1821 val = s->rgb_to_pixel(0, 0, 0);
1822 else
1823 val = 0;
1824 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1825 d = ds_get_data(s->ds);
1826 for(i = 0; i < s->last_scr_height; i++) {
1827 memset(d, val, w);
1828 d += ds_get_linesize(s->ds);
1829 }
1830 dpy_update(s->ds, 0, 0,
1831 s->last_scr_width, s->last_scr_height);
1832 }
1833
1834 #define GMODE_TEXT 0
1835 #define GMODE_GRAPH 1
1836 #define GMODE_BLANK 2
1837
1838 static void vga_update_display(void *opaque)
1839 {
1840 VGAState *s = (VGAState *)opaque;
1841 int full_update, graphic_mode;
1842
1843 if (ds_get_bits_per_pixel(s->ds) == 0) {
1844 /* nothing to do */
1845 } else {
1846 full_update = 0;
1847 if (!(s->ar_index & 0x20)) {
1848 graphic_mode = GMODE_BLANK;
1849 } else {
1850 graphic_mode = s->gr[6] & 1;
1851 }
1852 if (graphic_mode != s->graphic_mode) {
1853 s->graphic_mode = graphic_mode;
1854 full_update = 1;
1855 }
1856 switch(graphic_mode) {
1857 case GMODE_TEXT:
1858 vga_draw_text(s, full_update);
1859 break;
1860 case GMODE_GRAPH:
1861 #ifdef TARGET_IA64
1862 full_update = 1;
1863 #endif
1864 vga_draw_graphic(s, full_update);
1865 break;
1866 case GMODE_BLANK:
1867 default:
1868 vga_draw_blank(s, full_update);
1869 break;
1870 }
1871 }
1872 }
1873
1874 /* force a full display refresh */
1875 static void vga_invalidate_display(void *opaque)
1876 {
1877 VGAState *s = (VGAState *)opaque;
1878
1879 s->last_width = -1;
1880 s->last_height = -1;
1881 }
1882
1883 void vga_reset(void *opaque)
1884 {
1885 VGAState *s = (VGAState *) opaque;
1886
1887 s->lfb_addr = 0;
1888 s->lfb_end = 0;
1889 s->map_addr = 0;
1890 s->map_end = 0;
1891 s->lfb_vram_mapped = 0;
1892 s->bios_offset = 0;
1893 s->bios_size = 0;
1894 s->sr_index = 0;
1895 memset(s->sr, '\0', sizeof(s->sr));
1896 s->gr_index = 0;
1897 memset(s->gr, '\0', sizeof(s->gr));
1898 s->ar_index = 0;
1899 memset(s->ar, '\0', sizeof(s->ar));
1900 s->ar_flip_flop = 0;
1901 s->cr_index = 0;
1902 memset(s->cr, '\0', sizeof(s->cr));
1903 s->msr = 0;
1904 s->fcr = 0;
1905 s->st00 = 0;
1906 s->st01 = 0;
1907 s->dac_state = 0;
1908 s->dac_sub_index = 0;
1909 s->dac_read_index = 0;
1910 s->dac_write_index = 0;
1911 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1912 s->dac_8bit = 0;
1913 memset(s->palette, '\0', sizeof(s->palette));
1914 s->bank_offset = 0;
1915 #ifdef CONFIG_BOCHS_VBE
1916 s->vbe_index = 0;
1917 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1918 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
1919 s->vbe_start_addr = 0;
1920 s->vbe_line_offset = 0;
1921 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1922 #endif
1923 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1924 s->graphic_mode = -1; /* force full update */
1925 s->shift_control = 0;
1926 s->double_scan = 0;
1927 s->line_offset = 0;
1928 s->line_compare = 0;
1929 s->start_addr = 0;
1930 s->plane_updated = 0;
1931 s->last_cw = 0;
1932 s->last_ch = 0;
1933 s->last_width = 0;
1934 s->last_height = 0;
1935 s->last_scr_width = 0;
1936 s->last_scr_height = 0;
1937 s->cursor_start = 0;
1938 s->cursor_end = 0;
1939 s->cursor_offset = 0;
1940 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1941 memset(s->last_palette, '\0', sizeof(s->last_palette));
1942 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1943 switch (vga_retrace_method) {
1944 case VGA_RETRACE_DUMB:
1945 break;
1946 case VGA_RETRACE_PRECISE:
1947 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1948 break;
1949 }
1950 }
1951
1952 #define TEXTMODE_X(x) ((x) % width)
1953 #define TEXTMODE_Y(x) ((x) / width)
1954 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1955 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1956 /* relay text rendering to the display driver
1957 * instead of doing a full vga_update_display() */
1958 static void vga_update_text(void *opaque, console_ch_t *chardata)
1959 {
1960 VGAState *s = (VGAState *) opaque;
1961 int graphic_mode, i, cursor_offset, cursor_visible;
1962 int cw, cheight, width, height, size, c_min, c_max;
1963 uint32_t *src;
1964 console_ch_t *dst, val;
1965 char msg_buffer[80];
1966 int full_update = 0;
1967
1968 if (!(s->ar_index & 0x20)) {
1969 graphic_mode = GMODE_BLANK;
1970 } else {
1971 graphic_mode = s->gr[6] & 1;
1972 }
1973 if (graphic_mode != s->graphic_mode) {
1974 s->graphic_mode = graphic_mode;
1975 full_update = 1;
1976 }
1977 if (s->last_width == -1) {
1978 s->last_width = 0;
1979 full_update = 1;
1980 }
1981
1982 switch (graphic_mode) {
1983 case GMODE_TEXT:
1984 /* TODO: update palette */
1985 full_update |= update_basic_params(s);
1986
1987 /* total width & height */
1988 cheight = (s->cr[9] & 0x1f) + 1;
1989 cw = 8;
1990 if (!(s->sr[1] & 0x01))
1991 cw = 9;
1992 if (s->sr[1] & 0x08)
1993 cw = 16; /* NOTE: no 18 pixel wide */
1994 width = (s->cr[0x01] + 1);
1995 if (s->cr[0x06] == 100) {
1996 /* ugly hack for CGA 160x100x16 - explain me the logic */
1997 height = 100;
1998 } else {
1999 height = s->cr[0x12] |
2000 ((s->cr[0x07] & 0x02) << 7) |
2001 ((s->cr[0x07] & 0x40) << 3);
2002 height = (height + 1) / cheight;
2003 }
2004
2005 size = (height * width);
2006 if (size > CH_ATTR_SIZE) {
2007 if (!full_update)
2008 return;
2009
2010 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2011 width, height);
2012 break;
2013 }
2014
2015 if (width != s->last_width || height != s->last_height ||
2016 cw != s->last_cw || cheight != s->last_ch) {
2017 s->last_scr_width = width * cw;
2018 s->last_scr_height = height * cheight;
2019 s->ds->surface->width = width;
2020 s->ds->surface->height = height;
2021 dpy_resize(s->ds);
2022 s->last_width = width;
2023 s->last_height = height;
2024 s->last_ch = cheight;
2025 s->last_cw = cw;
2026 full_update = 1;
2027 }
2028
2029 /* Update "hardware" cursor */
2030 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
2031 if (cursor_offset != s->cursor_offset ||
2032 s->cr[0xa] != s->cursor_start ||
2033 s->cr[0xb] != s->cursor_end || full_update) {
2034 cursor_visible = !(s->cr[0xa] & 0x20);
2035 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2036 dpy_cursor(s->ds,
2037 TEXTMODE_X(cursor_offset),
2038 TEXTMODE_Y(cursor_offset));
2039 else
2040 dpy_cursor(s->ds, -1, -1);
2041 s->cursor_offset = cursor_offset;
2042 s->cursor_start = s->cr[0xa];
2043 s->cursor_end = s->cr[0xb];
2044 }
2045
2046 src = (uint32_t *) s->vram_ptr + s->start_addr;
2047 dst = chardata;
2048
2049 if (full_update) {
2050 for (i = 0; i < size; src ++, dst ++, i ++)
2051 console_write_ch(dst, VMEM2CHTYPE(*src));
2052
2053 dpy_update(s->ds, 0, 0, width, height);
2054 } else {
2055 c_max = 0;
2056
2057 for (i = 0; i < size; src ++, dst ++, i ++) {
2058 console_write_ch(&val, VMEM2CHTYPE(*src));
2059 if (*dst != val) {
2060 *dst = val;
2061 c_max = i;
2062 break;
2063 }
2064 }
2065 c_min = i;
2066 for (; i < size; src ++, dst ++, i ++) {
2067 console_write_ch(&val, VMEM2CHTYPE(*src));
2068 if (*dst != val) {
2069 *dst = val;
2070 c_max = i;
2071 }
2072 }
2073
2074 if (c_min <= c_max) {
2075 i = TEXTMODE_Y(c_min);
2076 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2077 }
2078 }
2079
2080 return;
2081 case GMODE_GRAPH:
2082 if (!full_update)
2083 return;
2084
2085 s->get_resolution(s, &width, &height);
2086 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2087 width, height);
2088 break;
2089 case GMODE_BLANK:
2090 default:
2091 if (!full_update)
2092 return;
2093
2094 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2095 break;
2096 }
2097
2098 /* Display a message */
2099 s->last_width = 60;
2100 s->last_height = height = 3;
2101 dpy_cursor(s->ds, -1, -1);
2102 s->ds->surface->width = s->last_width;
2103 s->ds->surface->height = height;
2104 dpy_resize(s->ds);
2105
2106 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2107 console_write_ch(dst ++, ' ');
2108
2109 size = strlen(msg_buffer);
2110 width = (s->last_width - size) / 2;
2111 dst = chardata + s->last_width + width;
2112 for (i = 0; i < size; i ++)
2113 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2114
2115 dpy_update(s->ds, 0, 0, s->last_width, height);
2116 }
2117
2118 static CPUReadMemoryFunc *vga_mem_read[3] = {
2119 vga_mem_readb,
2120 vga_mem_readw,
2121 vga_mem_readl,
2122 };
2123
2124 static CPUWriteMemoryFunc *vga_mem_write[3] = {
2125 vga_mem_writeb,
2126 vga_mem_writew,
2127 vga_mem_writel,
2128 };
2129
2130 static void vga_save(QEMUFile *f, void *opaque)
2131 {
2132 VGAState *s = opaque;
2133 int i;
2134
2135 if (s->pci_dev)
2136 pci_device_save(s->pci_dev, f);
2137
2138 qemu_put_be32s(f, &s->latch);
2139 qemu_put_8s(f, &s->sr_index);
2140 qemu_put_buffer(f, s->sr, 8);
2141 qemu_put_8s(f, &s->gr_index);
2142 qemu_put_buffer(f, s->gr, 16);
2143 qemu_put_8s(f, &s->ar_index);
2144 qemu_put_buffer(f, s->ar, 21);
2145 qemu_put_be32(f, s->ar_flip_flop);
2146 qemu_put_8s(f, &s->cr_index);
2147 qemu_put_buffer(f, s->cr, 256);
2148 qemu_put_8s(f, &s->msr);
2149 qemu_put_8s(f, &s->fcr);
2150 qemu_put_byte(f, s->st00);
2151 qemu_put_8s(f, &s->st01);
2152
2153 qemu_put_8s(f, &s->dac_state);
2154 qemu_put_8s(f, &s->dac_sub_index);
2155 qemu_put_8s(f, &s->dac_read_index);
2156 qemu_put_8s(f, &s->dac_write_index);
2157 qemu_put_buffer(f, s->dac_cache, 3);
2158 qemu_put_buffer(f, s->palette, 768);
2159
2160 qemu_put_be32(f, s->bank_offset);
2161 #ifdef CONFIG_BOCHS_VBE
2162 qemu_put_byte(f, 1);
2163 qemu_put_be16s(f, &s->vbe_index);
2164 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2165 qemu_put_be16s(f, &s->vbe_regs[i]);
2166 qemu_put_be32s(f, &s->vbe_start_addr);
2167 qemu_put_be32s(f, &s->vbe_line_offset);
2168 qemu_put_be32s(f, &s->vbe_bank_mask);
2169 #else
2170 qemu_put_byte(f, 0);
2171 #endif
2172 }
2173
2174 static int vga_load(QEMUFile *f, void *opaque, int version_id)
2175 {
2176 VGAState *s = opaque;
2177 int is_vbe, i, ret;
2178
2179 if (version_id > 2)
2180 return -EINVAL;
2181
2182 if (s->pci_dev && version_id >= 2) {
2183 ret = pci_device_load(s->pci_dev, f);
2184 if (ret < 0)
2185 return ret;
2186 }
2187
2188 qemu_get_be32s(f, &s->latch);
2189 qemu_get_8s(f, &s->sr_index);
2190 qemu_get_buffer(f, s->sr, 8);
2191 qemu_get_8s(f, &s->gr_index);
2192 qemu_get_buffer(f, s->gr, 16);
2193 qemu_get_8s(f, &s->ar_index);
2194 qemu_get_buffer(f, s->ar, 21);
2195 s->ar_flip_flop=qemu_get_be32(f);
2196 qemu_get_8s(f, &s->cr_index);
2197 qemu_get_buffer(f, s->cr, 256);
2198 qemu_get_8s(f, &s->msr);
2199 qemu_get_8s(f, &s->fcr);
2200 qemu_get_8s(f, &s->st00);
2201 qemu_get_8s(f, &s->st01);
2202
2203 qemu_get_8s(f, &s->dac_state);
2204 qemu_get_8s(f, &s->dac_sub_index);
2205 qemu_get_8s(f, &s->dac_read_index);
2206 qemu_get_8s(f, &s->dac_write_index);
2207 qemu_get_buffer(f, s->dac_cache, 3);
2208 qemu_get_buffer(f, s->palette, 768);
2209
2210 s->bank_offset=qemu_get_be32(f);
2211 is_vbe = qemu_get_byte(f);
2212 #ifdef CONFIG_BOCHS_VBE
2213 if (!is_vbe)
2214 return -EINVAL;
2215 qemu_get_be16s(f, &s->vbe_index);
2216 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2217 qemu_get_be16s(f, &s->vbe_regs[i]);
2218 qemu_get_be32s(f, &s->vbe_start_addr);
2219 qemu_get_be32s(f, &s->vbe_line_offset);
2220 qemu_get_be32s(f, &s->vbe_bank_mask);
2221 #else
2222 if (is_vbe)
2223 return -EINVAL;
2224 #endif
2225
2226 /* force refresh */
2227 s->graphic_mode = -1;
2228 return 0;
2229 }
2230
2231 typedef struct PCIVGAState {
2232 PCIDevice dev;
2233 VGAState vga_state;
2234 } PCIVGAState;
2235
2236 static int s1, s2;
2237
2238 static void mark_dirty(target_phys_addr_t start, target_phys_addr_t len)
2239 {
2240 target_phys_addr_t end = start + len;
2241
2242 while (start < end) {
2243 cpu_physical_memory_set_dirty(cpu_get_physical_page_desc(start));
2244 start += TARGET_PAGE_SIZE;
2245 }
2246 }
2247
2248 void vga_dirty_log_start(VGAState *s)
2249 {
2250 if (kvm_enabled() && s->map_addr)
2251 if (!s1) {
2252 kvm_log_start(s->map_addr, s->map_end - s->map_addr);
2253 mark_dirty(s->map_addr, s->map_end - s->map_addr);
2254 s1 = 1;
2255 }
2256 if (kvm_enabled() && s->lfb_vram_mapped) {
2257 if (!s2) {
2258 kvm_log_start(isa_mem_base + 0xa0000, 0x8000);
2259 kvm_log_start(isa_mem_base + 0xa8000, 0x8000);
2260 mark_dirty(isa_mem_base + 0xa0000, 0x10000);
2261 }
2262 s2 = 1;
2263 }
2264 }
2265
2266 void vga_dirty_log_stop(VGAState *s)
2267 {
2268 if (kvm_enabled() && s->map_addr && s1)
2269 kvm_log_stop(s->map_addr, s->map_end - s->map_addr);
2270
2271 if (kvm_enabled() && s->lfb_vram_mapped && s2) {
2272 kvm_log_stop(isa_mem_base + 0xa0000, 0x8000);
2273 kvm_log_stop(isa_mem_base + 0xa8000, 0x8000);
2274 }
2275 s1 = s2 = 0;
2276 }
2277
2278 static void vga_map(PCIDevice *pci_dev, int region_num,
2279 uint32_t addr, uint32_t size, int type)
2280 {
2281 PCIVGAState *d = (PCIVGAState *)pci_dev;
2282 VGAState *s = &d->vga_state;
2283 if (region_num == PCI_ROM_SLOT) {
2284 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
2285 } else {
2286 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2287 }
2288
2289 s->map_addr = addr;
2290 s->map_end = addr + VGA_RAM_SIZE;
2291
2292 vga_dirty_log_start(s);
2293 }
2294
2295 #ifdef TARGET_IA64
2296 /* do the same job as vgabios before vgabios get ready - yeah */
2297 void vga_bios_init(VGAState *s)
2298 {
2299 uint8_t palette_model[192] = {
2300 0, 0, 0, 0, 0, 170, 0, 170,
2301 0, 0, 170, 170, 170, 0, 0, 170,
2302 0, 170, 170, 85, 0, 170, 170, 170,
2303 85, 85, 85, 85, 85, 255, 85, 255,
2304 85, 85, 255, 255, 255, 85, 85, 255,
2305 85, 255, 255, 255, 85, 255, 255, 255,
2306 0, 21, 0, 0, 21, 42, 0, 63,
2307 0, 0, 63, 42, 42, 21, 0, 42,
2308 21, 42, 42, 63, 0, 42, 63, 42,
2309 0, 21, 21, 0, 21, 63, 0, 63,
2310 21, 0, 63, 63, 42, 21, 21, 42,
2311 21, 63, 42, 63, 21, 42, 63, 63,
2312 21, 0, 0, 21, 0, 42, 21, 42,
2313 0, 21, 42, 42, 63, 0, 0, 63,
2314 0, 42, 63, 42, 0, 63, 42, 42,
2315 21, 0, 21, 21, 0, 63, 21, 42,
2316 21, 21, 42, 63, 63, 0, 21, 63,
2317 0, 63, 63, 42, 21, 63, 42, 63,
2318 21, 21, 0, 21, 21, 42, 21, 63,
2319 0, 21, 63, 42, 63, 21, 0, 63,
2320 21, 42, 63, 63, 0, 63, 63, 42,
2321 21, 21, 21, 21, 21, 63, 21, 63,
2322 21, 21, 63, 63, 63, 21, 21, 63,
2323 21, 63, 63, 63, 21, 63, 63, 63
2324 };
2325
2326 s->latch = 0;
2327
2328 s->sr_index = 3;
2329 s->sr[0] = 3;
2330 s->sr[1] = 0;
2331 s->sr[2] = 3;
2332 s->sr[3] = 0;
2333 s->sr[4] = 2;
2334 s->sr[5] = 0;
2335 s->sr[6] = 0;
2336 s->sr[7] = 0;
2337
2338 s->gr_index = 5;
2339 s->gr[0] = 0;
2340 s->gr[1] = 0;
2341 s->gr[2] = 0;
2342 s->gr[3] = 0;
2343 s->gr[4] = 0;
2344 s->gr[5] = 16;
2345 s->gr[6] = 14;
2346 s->gr[7] = 15;
2347 s->gr[8] = 255;
2348
2349 /* changed by out 0x03c0 */
2350 s->ar_index = 32;
2351 s->ar[0] = 0;
2352 s->ar[1] = 1;
2353 s->ar[2] = 2;
2354 s->ar[3] = 3;
2355 s->ar[4] = 4;
2356 s->ar[5] = 5;
2357 s->ar[6] = 6;
2358 s->ar[7] = 7;
2359 s->ar[8] = 8;
2360 s->ar[9] = 9;
2361 s->ar[10] = 10;
2362 s->ar[11] = 11;
2363 s->ar[12] = 12;
2364 s->ar[13] = 13;
2365 s->ar[14] = 14;
2366 s->ar[15] = 15;
2367 s->ar[16] = 12;
2368 s->ar[17] = 0;
2369 s->ar[18] = 15;
2370 s->ar[19] = 8;
2371 s->ar[20] = 0;
2372
2373 s->ar_flip_flop = 1;
2374
2375 s->cr_index = 15;
2376 s->cr[0] = 95;
2377 s->cr[1] = 79;
2378 s->cr[2] = 80;
2379 s->cr[3] = 130;
2380 s->cr[4] = 85;
2381 s->cr[5] = 129;
2382 s->cr[6] = 191;
2383 s->cr[7] = 31;
2384 s->cr[8] = 0;
2385 s->cr[9] = 79;
2386 s->cr[10] = 14;
2387 s->cr[11] = 15;
2388 s->cr[12] = 0;
2389 s->cr[13] = 0;
2390 s->cr[14] = 5;
2391 s->cr[15] = 160;
2392 s->cr[16] = 156;
2393 s->cr[17] = 142;
2394 s->cr[18] = 143;
2395 s->cr[19] = 40;
2396 s->cr[20] = 31;
2397 s->cr[21] = 150;
2398 s->cr[22] = 185;
2399 s->cr[23] = 163;
2400 s->cr[24] = 255;
2401
2402 s->msr = 103;
2403 s->fcr = 0;
2404 s->st00 = 0;
2405 s->st01 = 0;
2406
2407 /* dac_* & palette will be initialized by os through out 0x03c8 &
2408 * out 0c03c9(1:3) */
2409 s->dac_state = 0;
2410 s->dac_sub_index = 0;
2411 s->dac_read_index = 0;
2412 s->dac_write_index = 16;
2413 s->dac_cache[0] = 255;
2414 s->dac_cache[1] = 255;
2415 s->dac_cache[2] = 255;
2416
2417 /* palette */
2418 memcpy(s->palette, palette_model, 192);
2419
2420 s->bank_offset = 0;
2421 s->graphic_mode = -1;
2422
2423 /* TODO: add vbe support if enabled */
2424 }
2425 #endif
2426
2427 void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
2428 ram_addr_t vga_ram_offset, int vga_ram_size)
2429 {
2430 int i, j, v, b;
2431
2432 for(i = 0;i < 256; i++) {
2433 v = 0;
2434 for(j = 0; j < 8; j++) {
2435 v |= ((i >> j) & 1) << (j * 4);
2436 }
2437 expand4[i] = v;
2438
2439 v = 0;
2440 for(j = 0; j < 4; j++) {
2441 v |= ((i >> (2 * j)) & 3) << (j * 4);
2442 }
2443 expand2[i] = v;
2444 }
2445 for(i = 0; i < 16; i++) {
2446 v = 0;
2447 for(j = 0; j < 4; j++) {
2448 b = ((i >> j) & 1);
2449 v |= b << (2 * j);
2450 v |= b << (2 * j + 1);
2451 }
2452 expand4to8[i] = v;
2453 }
2454
2455 s->vram_ptr = vga_ram_base;
2456 s->vram_offset = vga_ram_offset;
2457 s->vram_size = vga_ram_size;
2458 s->get_bpp = vga_get_bpp;
2459 s->get_offsets = vga_get_offsets;
2460 s->get_resolution = vga_get_resolution;
2461 s->update = vga_update_display;
2462 s->invalidate = vga_invalidate_display;
2463 s->screen_dump = vga_screen_dump;
2464 s->text_update = vga_update_text;
2465 switch (vga_retrace_method) {
2466 case VGA_RETRACE_DUMB:
2467 s->retrace = vga_dumb_retrace;
2468 s->update_retrace_info = vga_dumb_update_retrace_info;
2469 break;
2470
2471 case VGA_RETRACE_PRECISE:
2472 s->retrace = vga_precise_retrace;
2473 s->update_retrace_info = vga_precise_update_retrace_info;
2474 break;
2475 }
2476 vga_reset(s);
2477 #ifdef TARGET_IA64
2478 vga_bios_init(s);
2479 #endif
2480 }
2481
2482 /* used by both ISA and PCI */
2483 void vga_init(VGAState *s)
2484 {
2485 int vga_io_memory;
2486
2487 qemu_register_reset(vga_reset, s);
2488 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2489
2490 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2491
2492 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2493 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2494 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2495 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2496
2497 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2498
2499 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2500 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2501 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2502 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2503 s->bank_offset = 0;
2504
2505 #ifdef CONFIG_BOCHS_VBE
2506 #if defined (TARGET_I386)
2507 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2508 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2509
2510 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2511 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2512
2513 /* old Bochs IO ports */
2514 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2515 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2516
2517 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2518 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2519 #else
2520 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2521 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2522
2523 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2524 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2525 #endif
2526 #endif /* CONFIG_BOCHS_VBE */
2527
2528 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2529 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2530 vga_io_memory);
2531 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2532 }
2533
2534 /* Memory mapped interface */
2535 static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
2536 {
2537 VGAState *s = opaque;
2538
2539 return vga_ioport_read(s, addr >> s->it_shift) & 0xff;
2540 }
2541
2542 static void vga_mm_writeb (void *opaque,
2543 target_phys_addr_t addr, uint32_t value)
2544 {
2545 VGAState *s = opaque;
2546
2547 vga_ioport_write(s, addr >> s->it_shift, value & 0xff);
2548 }
2549
2550 static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
2551 {
2552 VGAState *s = opaque;
2553
2554 return vga_ioport_read(s, addr >> s->it_shift) & 0xffff;
2555 }
2556
2557 static void vga_mm_writew (void *opaque,
2558 target_phys_addr_t addr, uint32_t value)
2559 {
2560 VGAState *s = opaque;
2561
2562 vga_ioport_write(s, addr >> s->it_shift, value & 0xffff);
2563 }
2564
2565 static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
2566 {
2567 VGAState *s = opaque;
2568
2569 return vga_ioport_read(s, addr >> s->it_shift);
2570 }
2571
2572 static void vga_mm_writel (void *opaque,
2573 target_phys_addr_t addr, uint32_t value)
2574 {
2575 VGAState *s = opaque;
2576
2577 vga_ioport_write(s, addr >> s->it_shift, value);
2578 }
2579
2580 static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
2581 &vga_mm_readb,
2582 &vga_mm_readw,
2583 &vga_mm_readl,
2584 };
2585
2586 static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
2587 &vga_mm_writeb,
2588 &vga_mm_writew,
2589 &vga_mm_writel,
2590 };
2591
2592 static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
2593 target_phys_addr_t ctrl_base, int it_shift)
2594 {
2595 int s_ioport_ctrl, vga_io_memory;
2596
2597 s->it_shift = it_shift;
2598 s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);
2599 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2600
2601 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2602
2603 cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
2604 s->bank_offset = 0;
2605 cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
2606 qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
2607 }
2608
2609 int isa_vga_init(uint8_t *vga_ram_base,
2610 unsigned long vga_ram_offset, int vga_ram_size)
2611 {
2612 VGAState *s;
2613
2614 s = qemu_mallocz(sizeof(VGAState));
2615
2616 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2617 vga_init(s);
2618
2619 s->ds = graphic_console_init(s->update, s->invalidate,
2620 s->screen_dump, s->text_update, s);
2621
2622 #ifdef CONFIG_BOCHS_VBE
2623 /* XXX: use optimized standard vga accesses */
2624 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2625 vga_ram_size, vga_ram_offset);
2626 #endif
2627 return 0;
2628 }
2629
2630 int isa_vga_mm_init(uint8_t *vga_ram_base,
2631 unsigned long vga_ram_offset, int vga_ram_size,
2632 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
2633 int it_shift)
2634 {
2635 VGAState *s;
2636
2637 s = qemu_mallocz(sizeof(VGAState));
2638
2639 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2640 vga_mm_init(s, vram_base, ctrl_base, it_shift);
2641
2642 s->ds = graphic_console_init(s->update, s->invalidate,
2643 s->screen_dump, s->text_update, s);
2644
2645 #ifdef CONFIG_BOCHS_VBE
2646 /* XXX: use optimized standard vga accesses */
2647 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2648 vga_ram_size, vga_ram_offset);
2649 #endif
2650 return 0;
2651 }
2652
2653 static void pci_vga_write_config(PCIDevice *d,
2654 uint32_t address, uint32_t val, int len)
2655 {
2656 PCIVGAState *pvs = container_of(d, PCIVGAState, dev);
2657 VGAState *s = &pvs->vga_state;
2658
2659 vga_dirty_log_stop(s);
2660 pci_default_write_config(d, address, val, len);
2661 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
2662 s->map_addr = 0;
2663 vga_dirty_log_start(s);
2664 }
2665
2666 int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
2667 unsigned long vga_ram_offset, int vga_ram_size,
2668 unsigned long vga_bios_offset, int vga_bios_size)
2669 {
2670 PCIVGAState *d;
2671 VGAState *s;
2672 uint8_t *pci_conf;
2673
2674 d = (PCIVGAState *)pci_register_device(bus, "VGA",
2675 sizeof(PCIVGAState),
2676 -1, NULL, pci_vga_write_config);
2677 if (!d)
2678 return -1;
2679 s = &d->vga_state;
2680
2681 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2682 vga_init(s);
2683
2684 s->ds = graphic_console_init(s->update, s->invalidate,
2685 s->screen_dump, s->text_update, s);
2686
2687 s->pci_dev = &d->dev;
2688
2689 pci_conf = d->dev.config;
2690 // dummy VGA (same as Bochs ID)
2691 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
2692 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
2693 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
2694 pci_conf[0x0e] = 0x00; // header_type
2695
2696 /* XXX: vga_ram_size must be a power of two */
2697 pci_register_io_region(&d->dev, 0, vga_ram_size,
2698 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2699 if (vga_bios_size != 0) {
2700 unsigned int bios_total_size;
2701 s->bios_offset = vga_bios_offset;
2702 s->bios_size = vga_bios_size;
2703 /* must be a power of two */
2704 bios_total_size = 1;
2705 while (bios_total_size < vga_bios_size)
2706 bios_total_size <<= 1;
2707 pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
2708 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2709 }
2710 return 0;
2711 }
2712
2713 /********************************************************/
2714 /* vga screen dump */
2715
2716 static void vga_save_dpy_update(DisplayState *s,
2717 int x, int y, int w, int h)
2718 {
2719 }
2720
2721 static void vga_save_dpy_resize(DisplayState *s)
2722 {
2723 }
2724
2725 static void vga_save_dpy_refresh(DisplayState *s)
2726 {
2727 }
2728
2729 int ppm_save(const char *filename, struct DisplaySurface *ds)
2730 {
2731 FILE *f;
2732 uint8_t *d, *d1;
2733 uint32_t v;
2734 int y, x;
2735 uint8_t r, g, b;
2736
2737 f = fopen(filename, "wb");
2738 if (!f)
2739 return -1;
2740 fprintf(f, "P6\n%d %d\n%d\n",
2741 ds->width, ds->height, 255);
2742 d1 = ds->data;
2743 for(y = 0; y < ds->height; y++) {
2744 d = d1;
2745 for(x = 0; x < ds->width; x++) {
2746 if (ds->pf.bits_per_pixel == 32)
2747 v = *(uint32_t *)d;
2748 else
2749 v = (uint32_t) (*(uint16_t *)d);
2750 r = ((v >> ds->pf.rshift) & ds->pf.rmax) * 256 /
2751 (ds->pf.rmax + 1);
2752 g = ((v >> ds->pf.gshift) & ds->pf.gmax) * 256 /
2753 (ds->pf.gmax + 1);
2754 b = ((v >> ds->pf.bshift) & ds->pf.bmax) * 256 /
2755 (ds->pf.bmax + 1);
2756 fputc(r, f);
2757 fputc(g, f);
2758 fputc(b, f);
2759 d += ds->pf.bytes_per_pixel;
2760 }
2761 d1 += ds->linesize;
2762 }
2763 fclose(f);
2764 return 0;
2765 }
2766
2767 static void vga_screen_dump_blank(VGAState *s, const char *filename)
2768 {
2769 FILE *f;
2770 unsigned int y, x, w, h;
2771 unsigned char blank_sample[3] = { 0, 0, 0 };
2772
2773 w = s->last_scr_width;
2774 h = s->last_scr_height;
2775
2776 f = fopen(filename, "wb");
2777 if (!f)
2778 return;
2779 fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
2780 for (y = 0; y < h; y++) {
2781 for (x = 0; x < w; x++) {
2782 fwrite(blank_sample, 3, 1, f);
2783 }
2784 }
2785 fclose(f);
2786 }
2787
2788 static void vga_screen_dump_common(VGAState *s, const char *filename,
2789 int w, int h)
2790 {
2791 DisplayState *saved_ds, ds1, *ds = &ds1;
2792 DisplayChangeListener dcl;
2793
2794 /* XXX: this is a little hackish */
2795 vga_invalidate_display(s);
2796 saved_ds = s->ds;
2797
2798 memset(ds, 0, sizeof(DisplayState));
2799 memset(&dcl, 0, sizeof(DisplayChangeListener));
2800 dcl.dpy_update = vga_save_dpy_update;
2801 dcl.dpy_resize = vga_save_dpy_resize;
2802 dcl.dpy_refresh = vga_save_dpy_refresh;
2803 register_displaychangelistener(ds, &dcl);
2804 ds->surface = qemu_create_displaysurface(w, h, 32, 4 * w);
2805
2806 s->ds = ds;
2807 s->graphic_mode = -1;
2808 vga_update_display(s);
2809
2810 ppm_save(filename, ds->surface);
2811
2812 qemu_free_displaysurface(ds->surface);
2813 s->ds = saved_ds;
2814 }
2815
2816 static void vga_screen_dump_graphic(VGAState *s, const char *filename)
2817 {
2818 int w, h;
2819
2820 s->get_resolution(s, &w, &h);
2821 vga_screen_dump_common(s, filename, w, h);
2822 }
2823
2824 static void vga_screen_dump_text(VGAState *s, const char *filename)
2825 {
2826 int w, h, cwidth, cheight;
2827
2828 vga_get_text_resolution(s, &w, &h, &cwidth, &cheight);
2829 vga_screen_dump_common(s, filename, w * cwidth, h * cheight);
2830 }
2831
2832 /* save the vga display in a PPM image even if no display is
2833 available */
2834 static void vga_screen_dump(void *opaque, const char *filename)
2835 {
2836 VGAState *s = (VGAState *)opaque;
2837
2838 if (!(s->ar_index & 0x20))
2839 vga_screen_dump_blank(s, filename);
2840 else if (s->gr[6] & 1)
2841 vga_screen_dump_graphic(s, filename);
2842 else
2843 vga_screen_dump_text(s, filename);
2844 vga_invalidate_display(s);
2845 }
Patches shipped by Fedora