hw/ppc4xx.h

   1 /*
   2  * QEMU PowerPC 4xx emulation shared definitions
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Copyright 2008 IBM Corp.
   7  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #if !defined(PPC_4XX_H)
  29 #define PPC_4XX_H
  30
  31 #include "pci.h"
  32
  33 /* PowerPC 4xx core initialization */
  34 CPUState *ppc4xx_init (const char *cpu_model,
  35                        clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
  36                        uint32_t sysclk);
  37
  38 typedef struct ppc4xx_mmio_t ppc4xx_mmio_t;
  39 int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,
  40                           target_phys_addr_t offset, uint32_t len,
  41                           CPUReadMemoryFunc **mem_read,
  42                           CPUWriteMemoryFunc **mem_write, void *opaque);
  43 ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base);
  44
  45 /* PowerPC 4xx universal interrupt controller */
  46 enum {
  47     PPCUIC_OUTPUT_INT = 0,
  48     PPCUIC_OUTPUT_CINT = 1,
  49     PPCUIC_OUTPUT_NB,
  50 };
  51 qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
  52                        uint32_t dcr_base, int has_ssr, int has_vr);
  53
  54 ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
  55                                target_phys_addr_t ram_bases[],
  56                                target_phys_addr_t ram_sizes[],
  57                                const unsigned int sdram_bank_sizes[]);
  58
  59 void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
  60                         target_phys_addr_t *ram_bases,
  61                         target_phys_addr_t *ram_sizes,
  62                         int do_init);
  63
  64 PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
  65                         target_phys_addr_t config_space,
  66                         target_phys_addr_t int_ack,
  67                         target_phys_addr_t special_cycle,
  68                         target_phys_addr_t registers);
  69
  70 #endif /* !defined(PPC_4XX_H) */