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Make binary stripping conditional (Riku Voipio)
[qemu-kvm/fedora.git] / hw / e1000.c
blobf7bf37a5823252ba79c2306a298d1287f79237d6
1 /*
2 * QEMU e1000 emulation
3 *
4 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
5 * Copyright (c) 2008 Qumranet
6 * Based on work done by:
7 * Copyright (c) 2007 Dan Aloni
8 * Copyright (c) 2004 Antony T Curtis
9 *
10 * This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU Lesser General Public
12 * License as published by the Free Software Foundation; either
13 * version 2 of the License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * Lesser General Public License for more details.
19 *
20 * You should have received a copy of the GNU Lesser General Public
21 * License along with this library; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
23 */
24
25
26 #include "hw.h"
27 #include "pci.h"
28 #include "net.h"
29 #include "qemu-kvm.h"
30
31 #include "e1000_hw.h"
32
33 #define DEBUG
34
35 #ifdef DEBUG
36 enum {
37 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
38 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
39 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
40 DEBUG_RXFILTER, DEBUG_NOTYET,
41 };
42 #define DBGBIT(x) (1<<DEBUG_##x)
43 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
44
45 #define DBGOUT(what, fmt, params...) do { \
46 if (debugflags & DBGBIT(what)) \
47 fprintf(stderr, "e1000: " fmt, ##params); \
48 } while (0)
49 #else
50 #define DBGOUT(what, fmt, params...) do {} while (0)
51 #endif
52
53 #define IOPORT_SIZE 0x40
54 #define PNPMMIO_SIZE 0x20000
55
56 /*
57 * HW models:
58 * E1000_DEV_ID_82540EM works with Windows and Linux
59 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
60 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
61 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
62 * Others never tested
63 */
64 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
65
66 /*
67 * May need to specify additional MAC-to-PHY entries --
68 * Intel's Windows driver refuses to initialize unless they match
69 */
70 enum {
71 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
72 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
73 /* default to E1000_DEV_ID_82540EM */ 0xc20
74 };
75
76 typedef struct E1000State_st {
77 PCIDevice dev;
78 VLANClientState *vc;
79 int mmio_index;
80
81 uint32_t mac_reg[0x8000];
82 uint16_t phy_reg[0x20];
83 uint16_t eeprom_data[64];
84
85 uint32_t rxbuf_size;
86 uint32_t rxbuf_min_shift;
87 int check_rxov;
88 struct e1000_tx {
89 unsigned char header[256];
90 unsigned char vlan_header[4];
91 unsigned char vlan[4];
92 unsigned char data[0x10000];
93 uint16_t size;
94 unsigned char sum_needed;
95 unsigned char vlan_needed;
96 uint8_t ipcss;
97 uint8_t ipcso;
98 uint16_t ipcse;
99 uint8_t tucss;
100 uint8_t tucso;
101 uint16_t tucse;
102 uint8_t hdr_len;
103 uint16_t mss;
104 uint32_t paylen;
105 uint16_t tso_frames;
106 char tse;
107 int8_t ip;
108 int8_t tcp;
109 char cptse; // current packet tse bit
110 } tx;
111
112 struct {
113 uint32_t val_in; // shifted in from guest driver
114 uint16_t bitnum_in;
115 uint16_t bitnum_out;
116 uint16_t reading;
117 uint32_t old_eecd;
118 } eecd_state;
119 } E1000State;
120
121 #define defreg(x) x = (E1000_##x>>2)
122 enum {
123 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
124 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
125 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
126 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
127 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
128 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
129 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
130 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
131 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
132 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
133 defreg(VET),
134 };
135
136 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
137 static const char phy_regcap[0x20] = {
138 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
139 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
140 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
141 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
142 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
143 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
144 };
145
146 static void
147 ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr,
148 uint32_t size, int type)
149 {
150 DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
151 }
152
153 static void
154 set_interrupt_cause(E1000State *s, int index, uint32_t val)
155 {
156 if (val)
157 val |= E1000_ICR_INT_ASSERTED;
158 s->mac_reg[ICR] = val;
159 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
160 }
161
162 static void
163 set_ics(E1000State *s, int index, uint32_t val)
164 {
165 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
166 s->mac_reg[IMS]);
167 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
168 }
169
170 static int
171 rxbufsize(uint32_t v)
172 {
173 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
174 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
175 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
176 switch (v) {
177 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
178 return 16384;
179 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
180 return 8192;
181 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
182 return 4096;
183 case E1000_RCTL_SZ_1024:
184 return 1024;
185 case E1000_RCTL_SZ_512:
186 return 512;
187 case E1000_RCTL_SZ_256:
188 return 256;
189 }
190 return 2048;
191 }
192
193 static void
194 set_ctrl(E1000State *s, int index, uint32_t val)
195 {
196 /* RST is self clearing */
197 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
198 }
199
200 static void
201 set_rx_control(E1000State *s, int index, uint32_t val)
202 {
203 s->mac_reg[RCTL] = val;
204 s->rxbuf_size = rxbufsize(val);
205 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
206 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
207 s->mac_reg[RCTL]);
208 }
209
210 static void
211 set_mdic(E1000State *s, int index, uint32_t val)
212 {
213 uint32_t data = val & E1000_MDIC_DATA_MASK;
214 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
215
216 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
217 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
218 else if (val & E1000_MDIC_OP_READ) {
219 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
220 if (!(phy_regcap[addr] & PHY_R)) {
221 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
222 val |= E1000_MDIC_ERROR;
223 } else
224 val = (val ^ data) | s->phy_reg[addr];
225 } else if (val & E1000_MDIC_OP_WRITE) {
226 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
227 if (!(phy_regcap[addr] & PHY_W)) {
228 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
229 val |= E1000_MDIC_ERROR;
230 } else
231 s->phy_reg[addr] = data;
232 }
233 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
234 set_ics(s, 0, E1000_ICR_MDAC);
235 }
236
237 static uint32_t
238 get_eecd(E1000State *s, int index)
239 {
240 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
241
242 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
243 s->eecd_state.bitnum_out, s->eecd_state.reading);
244 if (!s->eecd_state.reading ||
245 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
246 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
247 ret |= E1000_EECD_DO;
248 return ret;
249 }
250
251 static void
252 set_eecd(E1000State *s, int index, uint32_t val)
253 {
254 uint32_t oldval = s->eecd_state.old_eecd;
255
256 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
257 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
258 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
259 return;
260 if (!(E1000_EECD_SK & val)) { // falling edge
261 s->eecd_state.bitnum_out++;
262 return;
263 }
264 if (!(val & E1000_EECD_CS)) { // rising, no CS (EEPROM reset)
265 memset(&s->eecd_state, 0, sizeof s->eecd_state);
266 return;
267 }
268 s->eecd_state.val_in <<= 1;
269 if (val & E1000_EECD_DI)
270 s->eecd_state.val_in |= 1;
271 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
272 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
273 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
274 EEPROM_READ_OPCODE_MICROWIRE);
275 }
276 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
277 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
278 s->eecd_state.reading);
279 }
280
281 static uint32_t
282 flash_eerd_read(E1000State *s, int x)
283 {
284 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
285
286 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
287 return 0;
288 return (s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
289 E1000_EEPROM_RW_REG_DONE | r;
290 }
291
292 static void
293 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
294 {
295 uint32_t sum;
296
297 if (cse && cse < n)
298 n = cse + 1;
299 if (sloc < n-1) {
300 sum = net_checksum_add(n-css, data+css);
301 cpu_to_be16wu((uint16_t *)(data + sloc),
302 net_checksum_finish(sum));
303 }
304 }
305
306 static inline int
307 vlan_enabled(E1000State *s)
308 {
309 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
310 }
311
312 static inline int
313 vlan_rx_filter_enabled(E1000State *s)
314 {
315 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
316 }
317
318 static inline int
319 is_vlan_packet(E1000State *s, const uint8_t *buf)
320 {
321 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
322 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
323 }
324
325 static inline int
326 is_vlan_txd(uint32_t txd_lower)
327 {
328 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
329 }
330
331 static void
332 xmit_seg(E1000State *s)
333 {
334 uint16_t len, *sp;
335 unsigned int frames = s->tx.tso_frames, css, sofar, n;
336 struct e1000_tx *tp = &s->tx;
337
338 if (tp->tse && tp->cptse) {
339 css = tp->ipcss;
340 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
341 frames, tp->size, css);
342 if (tp->ip) { // IPv4
343 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
344 tp->size - css);
345 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
346 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
347 } else // IPv6
348 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
349 tp->size - css);
350 css = tp->tucss;
351 len = tp->size - css;
352 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
353 if (tp->tcp) {
354 sofar = frames * tp->mss;
355 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
356 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
357 if (tp->paylen - sofar > tp->mss)
358 tp->data[css + 13] &= ~9; // PSH, FIN
359 } else // UDP
360 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
361 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
362 // add pseudo-header length before checksum calculation
363 sp = (uint16_t *)(tp->data + tp->tucso);
364 cpu_to_be16wu(sp, be16_to_cpup(sp) + len);
365 }
366 tp->tso_frames++;
367 }
368
369 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
370 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
371 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
372 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
373 if (tp->vlan_needed) {
374 memmove(tp->vlan, tp->data, 12);
375 memcpy(tp->data + 8, tp->vlan_header, 4);
376 qemu_send_packet(s->vc, tp->vlan, tp->size + 4);
377 } else
378 qemu_send_packet(s->vc, tp->data, tp->size);
379 s->mac_reg[TPT]++;
380 s->mac_reg[GPTC]++;
381 n = s->mac_reg[TOTL];
382 if ((s->mac_reg[TOTL] += s->tx.size) < n)
383 s->mac_reg[TOTH]++;
384 }
385
386 static void
387 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
388 {
389 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
390 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
391 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
392 unsigned int msh = 0xfffff, hdr = 0;
393 uint64_t addr;
394 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
395 struct e1000_tx *tp = &s->tx;
396
397 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
398 op = le32_to_cpu(xp->cmd_and_length);
399 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
400 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
401 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
402 tp->tucss = xp->upper_setup.tcp_fields.tucss;
403 tp->tucso = xp->upper_setup.tcp_fields.tucso;
404 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
405 tp->paylen = op & 0xfffff;
406 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
407 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
408 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
409 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
410 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
411 tp->tso_frames = 0;
412 if (tp->tucso == 0) { // this is probably wrong
413 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
414 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
415 }
416 return;
417 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
418 // data descriptor
419 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
420 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
421 } else
422 // legacy descriptor
423 tp->cptse = 0;
424
425 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
426 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
427 tp->vlan_needed = 1;
428 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
429 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
430 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
431 le16_to_cpu(dp->upper.fields.special));
432 }
433
434 addr = le64_to_cpu(dp->buffer_addr);
435 if (tp->tse && tp->cptse) {
436 hdr = tp->hdr_len;
437 msh = hdr + tp->mss;
438 do {
439 bytes = split_size;
440 if (tp->size + bytes > msh)
441 bytes = msh - tp->size;
442 cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
443 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
444 memmove(tp->header, tp->data, hdr);
445 tp->size = sz;
446 addr += bytes;
447 if (sz == msh) {
448 xmit_seg(s);
449 memmove(tp->data, tp->header, hdr);
450 tp->size = hdr;
451 }
452 } while (split_size -= bytes);
453 } else if (!tp->tse && tp->cptse) {
454 // context descriptor TSE is not set, while data descriptor TSE is set
455 DBGOUT(TXERR, "TCP segmentaion Error\n");
456 } else {
457 cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
458 tp->size += split_size;
459 }
460
461 if (!(txd_lower & E1000_TXD_CMD_EOP))
462 return;
463 if (!(tp->tse && tp->cptse && tp->size < hdr))
464 xmit_seg(s);
465 tp->tso_frames = 0;
466 tp->sum_needed = 0;
467 tp->vlan_needed = 0;
468 tp->size = 0;
469 tp->cptse = 0;
470 }
471
472 static uint32_t
473 txdesc_writeback(target_phys_addr_t base, struct e1000_tx_desc *dp)
474 {
475 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
476
477 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
478 return 0;
479 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
480 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
481 dp->upper.data = cpu_to_le32(txd_upper);
482 cpu_physical_memory_write(base + ((char *)&dp->upper - (char *)dp),
483 (void *)&dp->upper, sizeof(dp->upper));
484 return E1000_ICR_TXDW;
485 }
486
487 static void
488 start_xmit(E1000State *s)
489 {
490 target_phys_addr_t base;
491 struct e1000_tx_desc desc;
492 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
493
494 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
495 DBGOUT(TX, "tx disabled\n");
496 return;
497 }
498
499 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
500 base = ((uint64_t)s->mac_reg[TDBAH] << 32) + s->mac_reg[TDBAL] +
501 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
502 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
503
504 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
505 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
506 desc.upper.data);
507
508 process_tx_desc(s, &desc);
509 cause |= txdesc_writeback(base, &desc);
510
511 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
512 s->mac_reg[TDH] = 0;
513 /*
514 * the following could happen only if guest sw assigns
515 * bogus values to TDT/TDLEN.
516 * there's nothing too intelligent we could do about this.
517 */
518 if (s->mac_reg[TDH] == tdh_start) {
519 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
520 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
521 break;
522 }
523 }
524 set_ics(s, 0, cause);
525 }
526
527 static int
528 receive_filter(E1000State *s, const uint8_t *buf, int size)
529 {
530 static uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
531 static int mta_shift[] = {4, 3, 2, 0};
532 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
533
534 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
535 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
536 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
537 ((vid >> 5) & 0x7f));
538 if ((vfta & (1 << (vid & 0x1f))) == 0)
539 return 0;
540 }
541
542 if (rctl & E1000_RCTL_UPE) // promiscuous
543 return 1;
544
545 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
546 return 1;
547
548 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
549 return 1;
550
551 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
552 if (!(rp[1] & E1000_RAH_AV))
553 continue;
554 ra[0] = cpu_to_le32(rp[0]);
555 ra[1] = cpu_to_le32(rp[1]);
556 if (!memcmp(buf, (uint8_t *)ra, 6)) {
557 DBGOUT(RXFILTER,
558 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
559 (int)(rp - s->mac_reg - RA)/2,
560 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
561 return 1;
562 }
563 }
564 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
565 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
566
567 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
568 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
569 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
570 return 1;
571 DBGOUT(RXFILTER,
572 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
573 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
574 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
575 s->mac_reg[MTA + (f >> 5)]);
576
577 return 0;
578 }
579
580 static void
581 e1000_set_link_status(VLANClientState *vc)
582 {
583 E1000State *s = vc->opaque;
584 uint32_t old_status = s->mac_reg[STATUS];
585
586 if (vc->link_down)
587 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
588 else
589 s->mac_reg[STATUS] |= E1000_STATUS_LU;
590
591 if (s->mac_reg[STATUS] != old_status)
592 set_ics(s, 0, E1000_ICR_LSC);
593 }
594
595 static int
596 e1000_can_receive(void *opaque)
597 {
598 E1000State *s = opaque;
599
600 return (s->mac_reg[RCTL] & E1000_RCTL_EN);
601 }
602
603 static void
604 e1000_receive(void *opaque, const uint8_t *buf, int size)
605 {
606 E1000State *s = opaque;
607 struct e1000_rx_desc desc;
608 target_phys_addr_t base;
609 unsigned int n, rdt;
610 uint32_t rdh_start;
611 uint16_t vlan_special = 0;
612 uint8_t vlan_status = 0, vlan_offset = 0;
613
614 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
615 return;
616
617 if (size > s->rxbuf_size) {
618 DBGOUT(RX, "packet too large for buffers (%d > %d)\n", size,
619 s->rxbuf_size);
620 return;
621 }
622
623 if (!receive_filter(s, buf, size))
624 return;
625
626 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
627 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
628 memmove((void *)(buf + 4), buf, 12);
629 vlan_status = E1000_RXD_STAT_VP;
630 vlan_offset = 4;
631 size -= 4;
632 }
633
634 rdh_start = s->mac_reg[RDH];
635 size += 4; // for the header
636 do {
637 if (s->mac_reg[RDH] == s->mac_reg[RDT] && s->check_rxov) {
638 set_ics(s, 0, E1000_ICS_RXO);
639 return;
640 }
641 base = ((uint64_t)s->mac_reg[RDBAH] << 32) + s->mac_reg[RDBAL] +
642 sizeof(desc) * s->mac_reg[RDH];
643 cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
644 desc.special = vlan_special;
645 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
646 if (desc.buffer_addr) {
647 cpu_physical_memory_write(le64_to_cpu(desc.buffer_addr),
648 (void *)(buf + vlan_offset), size);
649 desc.length = cpu_to_le16(size);
650 desc.status |= E1000_RXD_STAT_EOP|E1000_RXD_STAT_IXSM;
651 } else // as per intel docs; skip descriptors with null buf addr
652 DBGOUT(RX, "Null RX descriptor!!\n");
653 cpu_physical_memory_write(base, (void *)&desc, sizeof(desc));
654
655 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
656 s->mac_reg[RDH] = 0;
657 s->check_rxov = 1;
658 /* see comment in start_xmit; same here */
659 if (s->mac_reg[RDH] == rdh_start) {
660 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
661 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
662 set_ics(s, 0, E1000_ICS_RXO);
663 return;
664 }
665 } while (desc.buffer_addr == 0);
666
667 s->mac_reg[GPRC]++;
668 s->mac_reg[TPR]++;
669 n = s->mac_reg[TORL];
670 if ((s->mac_reg[TORL] += size) < n)
671 s->mac_reg[TORH]++;
672
673 n = E1000_ICS_RXT0;
674 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
675 rdt += s->mac_reg[RDLEN] / sizeof(desc);
676 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
677 s->rxbuf_min_shift)
678 n |= E1000_ICS_RXDMT0;
679
680 set_ics(s, 0, n);
681 }
682
683 static uint32_t
684 mac_readreg(E1000State *s, int index)
685 {
686 return s->mac_reg[index];
687 }
688
689 static uint32_t
690 mac_icr_read(E1000State *s, int index)
691 {
692 uint32_t ret = s->mac_reg[ICR];
693
694 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
695 set_interrupt_cause(s, 0, 0);
696 return ret;
697 }
698
699 static uint32_t
700 mac_read_clr4(E1000State *s, int index)
701 {
702 uint32_t ret = s->mac_reg[index];
703
704 s->mac_reg[index] = 0;
705 return ret;
706 }
707
708 static uint32_t
709 mac_read_clr8(E1000State *s, int index)
710 {
711 uint32_t ret = s->mac_reg[index];
712
713 s->mac_reg[index] = 0;
714 s->mac_reg[index-1] = 0;
715 return ret;
716 }
717
718 static void
719 mac_writereg(E1000State *s, int index, uint32_t val)
720 {
721 s->mac_reg[index] = val;
722 }
723
724 static void
725 set_rdt(E1000State *s, int index, uint32_t val)
726 {
727 s->check_rxov = 0;
728 s->mac_reg[index] = val & 0xffff;
729 }
730
731 static void
732 set_16bit(E1000State *s, int index, uint32_t val)
733 {
734 s->mac_reg[index] = val & 0xffff;
735 }
736
737 static void
738 set_dlen(E1000State *s, int index, uint32_t val)
739 {
740 s->mac_reg[index] = val & 0xfff80;
741 }
742
743 static void
744 set_tctl(E1000State *s, int index, uint32_t val)
745 {
746 s->mac_reg[index] = val;
747 s->mac_reg[TDT] &= 0xffff;
748 start_xmit(s);
749 }
750
751 static void
752 set_icr(E1000State *s, int index, uint32_t val)
753 {
754 DBGOUT(INTERRUPT, "set_icr %x\n", val);
755 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
756 }
757
758 static void
759 set_imc(E1000State *s, int index, uint32_t val)
760 {
761 s->mac_reg[IMS] &= ~val;
762 set_ics(s, 0, 0);
763 }
764
765 static void
766 set_ims(E1000State *s, int index, uint32_t val)
767 {
768 s->mac_reg[IMS] |= val;
769 set_ics(s, 0, 0);
770 }
771
772 #define getreg(x) [x] = mac_readreg
773 static uint32_t (*macreg_readops[])(E1000State *, int) = {
774 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
775 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
776 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
777 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
778 getreg(RDH), getreg(RDT), getreg(VET),
779
780 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
781 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
782 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
783 [CRCERRS ... MPC] = &mac_readreg,
784 [RA ... RA+31] = &mac_readreg,
785 [MTA ... MTA+127] = &mac_readreg,
786 [VFTA ... VFTA+127] = &mac_readreg,
787 };
788 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
789
790 #define putreg(x) [x] = mac_writereg
791 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
792 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
793 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
794 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
795 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
796 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
797 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
798 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
799 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
800 [RA ... RA+31] = &mac_writereg,
801 [MTA ... MTA+127] = &mac_writereg,
802 [VFTA ... VFTA+127] = &mac_writereg,
803 };
804 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
805
806 static void
807 e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
808 {
809 E1000State *s = opaque;
810 unsigned int index = (addr & 0x1ffff) >> 2;
811
812 #ifdef TARGET_WORDS_BIGENDIAN
813 val = bswap32(val);
814 #endif
815 if (index < NWRITEOPS && macreg_writeops[index])
816 macreg_writeops[index](s, index, val);
817 else if (index < NREADOPS && macreg_readops[index])
818 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
819 else
820 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08x\n",
821 index<<2, val);
822 }
823
824 static void
825 e1000_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
826 {
827 // emulate hw without byte enables: no RMW
828 e1000_mmio_writel(opaque, addr & ~3,
829 (val & 0xffff) << (8*(addr & 3)));
830 }
831
832 static void
833 e1000_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
834 {
835 // emulate hw without byte enables: no RMW
836 e1000_mmio_writel(opaque, addr & ~3,
837 (val & 0xff) << (8*(addr & 3)));
838 }
839
840 static uint32_t
841 e1000_mmio_readl(void *opaque, target_phys_addr_t addr)
842 {
843 E1000State *s = opaque;
844 unsigned int index = (addr & 0x1ffff) >> 2;
845
846 if (index < NREADOPS && macreg_readops[index])
847 {
848 uint32_t val = macreg_readops[index](s, index);
849 #ifdef TARGET_WORDS_BIGENDIAN
850 val = bswap32(val);
851 #endif
852 return val;
853 }
854 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
855 return 0;
856 }
857
858 static uint32_t
859 e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
860 {
861 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
862 (8 * (addr & 3))) & 0xff;
863 }
864
865 static uint32_t
866 e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
867 {
868 return ((e1000_mmio_readl(opaque, addr & ~3)) >>
869 (8 * (addr & 3))) & 0xffff;
870 }
871
872 static const int mac_regtosave[] = {
873 CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS,
874 LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH,
875 RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN,
876 TDT, TORH, TORL, TOTH, TOTL, TPR, TPT, TXDCTL, WUFC,
877 VET,
878 };
879 enum { MAC_NSAVE = ARRAY_SIZE(mac_regtosave) };
880
881 static const struct {
882 int size;
883 int array0;
884 } mac_regarraystosave[] = { {32, RA}, {128, MTA}, {128, VFTA} };
885 enum { MAC_NARRAYS = ARRAY_SIZE(mac_regarraystosave) };
886
887 static void
888 nic_save(QEMUFile *f, void *opaque)
889 {
890 E1000State *s = (E1000State *)opaque;
891 int i, j;
892
893 pci_device_save(&s->dev, f);
894 qemu_put_be32(f, 0);
895 qemu_put_be32s(f, &s->rxbuf_size);
896 qemu_put_be32s(f, &s->rxbuf_min_shift);
897 qemu_put_be32s(f, &s->eecd_state.val_in);
898 qemu_put_be16s(f, &s->eecd_state.bitnum_in);
899 qemu_put_be16s(f, &s->eecd_state.bitnum_out);
900 qemu_put_be16s(f, &s->eecd_state.reading);
901 qemu_put_be32s(f, &s->eecd_state.old_eecd);
902 qemu_put_8s(f, &s->tx.ipcss);
903 qemu_put_8s(f, &s->tx.ipcso);
904 qemu_put_be16s(f, &s->tx.ipcse);
905 qemu_put_8s(f, &s->tx.tucss);
906 qemu_put_8s(f, &s->tx.tucso);
907 qemu_put_be16s(f, &s->tx.tucse);
908 qemu_put_be32s(f, &s->tx.paylen);
909 qemu_put_8s(f, &s->tx.hdr_len);
910 qemu_put_be16s(f, &s->tx.mss);
911 qemu_put_be16s(f, &s->tx.size);
912 qemu_put_be16s(f, &s->tx.tso_frames);
913 qemu_put_8s(f, &s->tx.sum_needed);
914 qemu_put_s8s(f, &s->tx.ip);
915 qemu_put_s8s(f, &s->tx.tcp);
916 qemu_put_buffer(f, s->tx.header, sizeof s->tx.header);
917 qemu_put_buffer(f, s->tx.data, sizeof s->tx.data);
918 for (i = 0; i < 64; i++)
919 qemu_put_be16s(f, s->eeprom_data + i);
920 for (i = 0; i < 0x20; i++)
921 qemu_put_be16s(f, s->phy_reg + i);
922 for (i = 0; i < MAC_NSAVE; i++)
923 qemu_put_be32s(f, s->mac_reg + mac_regtosave[i]);
924 for (i = 0; i < MAC_NARRAYS; i++)
925 for (j = 0; j < mac_regarraystosave[i].size; j++)
926 qemu_put_be32s(f,
927 s->mac_reg + mac_regarraystosave[i].array0 + j);
928 }
929
930 static int
931 nic_load(QEMUFile *f, void *opaque, int version_id)
932 {
933 E1000State *s = (E1000State *)opaque;
934 int i, j, ret;
935
936 if ((ret = pci_device_load(&s->dev, f)) < 0)
937 return ret;
938 if (version_id == 1)
939 qemu_get_sbe32s(f, &i); /* once some unused instance id */
940 qemu_get_be32(f); /* Ignored. Was mmio_base. */
941 qemu_get_be32s(f, &s->rxbuf_size);
942 qemu_get_be32s(f, &s->rxbuf_min_shift);
943 qemu_get_be32s(f, &s->eecd_state.val_in);
944 qemu_get_be16s(f, &s->eecd_state.bitnum_in);
945 qemu_get_be16s(f, &s->eecd_state.bitnum_out);
946 qemu_get_be16s(f, &s->eecd_state.reading);
947 qemu_get_be32s(f, &s->eecd_state.old_eecd);
948 qemu_get_8s(f, &s->tx.ipcss);
949 qemu_get_8s(f, &s->tx.ipcso);
950 qemu_get_be16s(f, &s->tx.ipcse);
951 qemu_get_8s(f, &s->tx.tucss);
952 qemu_get_8s(f, &s->tx.tucso);
953 qemu_get_be16s(f, &s->tx.tucse);
954 qemu_get_be32s(f, &s->tx.paylen);
955 qemu_get_8s(f, &s->tx.hdr_len);
956 qemu_get_be16s(f, &s->tx.mss);
957 qemu_get_be16s(f, &s->tx.size);
958 qemu_get_be16s(f, &s->tx.tso_frames);
959 qemu_get_8s(f, &s->tx.sum_needed);
960 qemu_get_s8s(f, &s->tx.ip);
961 qemu_get_s8s(f, &s->tx.tcp);
962 qemu_get_buffer(f, s->tx.header, sizeof s->tx.header);
963 qemu_get_buffer(f, s->tx.data, sizeof s->tx.data);
964 for (i = 0; i < 64; i++)
965 qemu_get_be16s(f, s->eeprom_data + i);
966 for (i = 0; i < 0x20; i++)
967 qemu_get_be16s(f, s->phy_reg + i);
968 for (i = 0; i < MAC_NSAVE; i++)
969 qemu_get_be32s(f, s->mac_reg + mac_regtosave[i]);
970 for (i = 0; i < MAC_NARRAYS; i++)
971 for (j = 0; j < mac_regarraystosave[i].size; j++)
972 qemu_get_be32s(f,
973 s->mac_reg + mac_regarraystosave[i].array0 + j);
974 return 0;
975 }
976
977 static const uint16_t e1000_eeprom_template[64] = {
978 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
979 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
980 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
981 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
982 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
983 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
984 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
985 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
986 };
987
988 static const uint16_t phy_reg_init[] = {
989 [PHY_CTRL] = 0x1140, [PHY_STATUS] = 0x796d, // link initially up
990 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
991 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
992 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
993 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
994 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
995 };
996
997 static const uint32_t mac_reg_init[] = {
998 [PBA] = 0x00100030,
999 [LEDCTL] = 0x602,
1000 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
1001 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
1002 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
1003 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
1004 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
1005 E1000_STATUS_LU,
1006 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
1007 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
1008 E1000_MANC_RMCP_EN,
1009 };
1010
1011 /* PCI interface */
1012
1013 static CPUWriteMemoryFunc *e1000_mmio_write[] = {
1014 e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
1015 };
1016
1017 static CPUReadMemoryFunc *e1000_mmio_read[] = {
1018 e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
1019 };
1020
1021 static void
1022 e1000_mmio_map(PCIDevice *pci_dev, int region_num,
1023 uint32_t addr, uint32_t size, int type)
1024 {
1025 E1000State *d = (E1000State *)pci_dev;
1026 int i;
1027 const uint32_t excluded_regs[] = {
1028 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1029 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1030 };
1031
1032
1033 DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
1034
1035 cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
1036 qemu_register_coalesced_mmio(addr, excluded_regs[0]);
1037
1038 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1039 qemu_register_coalesced_mmio(addr + excluded_regs[i] + 4,
1040 excluded_regs[i + 1] -
1041 excluded_regs[i] - 4);
1042 }
1043
1044 static void
1045 e1000_cleanup(VLANClientState *vc)
1046 {
1047 E1000State *d = vc->opaque;
1048
1049 unregister_savevm("e1000", d);
1050 }
1051
1052 static int
1053 pci_e1000_uninit(PCIDevice *dev)
1054 {
1055 E1000State *d = (E1000State *) dev;
1056
1057 cpu_unregister_io_memory(d->mmio_index);
1058
1059 return 0;
1060 }
1061
1062 PCIDevice *
1063 pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn)
1064 {
1065 E1000State *d;
1066 uint8_t *pci_conf;
1067 uint16_t checksum = 0;
1068 static const char info_str[] = "e1000";
1069 int i;
1070
1071 d = (E1000State *)pci_register_device(bus, "e1000",
1072 sizeof(E1000State), devfn, NULL, NULL);
1073
1074 if (!d)
1075 return NULL;
1076
1077 pci_conf = d->dev.config;
1078
1079 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
1080 pci_config_set_device_id(pci_conf, E1000_DEVID);
1081 *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407);
1082 *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010);
1083 pci_conf[0x08] = 0x03;
1084 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
1085 pci_conf[0x0c] = 0x10;
1086
1087 pci_conf[0x3d] = 1; // interrupt pin 0
1088
1089 d->mmio_index = cpu_register_io_memory(0, e1000_mmio_read,
1090 e1000_mmio_write, d);
1091
1092 pci_register_io_region((PCIDevice *)d, 0, PNPMMIO_SIZE,
1093 PCI_ADDRESS_SPACE_MEM, e1000_mmio_map);
1094
1095 pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE,
1096 PCI_ADDRESS_SPACE_IO, ioport_map);
1097
1098 memmove(d->eeprom_data, e1000_eeprom_template,
1099 sizeof e1000_eeprom_template);
1100 for (i = 0; i < 3; i++)
1101 d->eeprom_data[i] = (nd->macaddr[2*i+1]<<8) | nd->macaddr[2*i];
1102 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1103 checksum += d->eeprom_data[i];
1104 checksum = (uint16_t) EEPROM_SUM - checksum;
1105 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1106
1107 memset(d->phy_reg, 0, sizeof d->phy_reg);
1108 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
1109 memset(d->mac_reg, 0, sizeof d->mac_reg);
1110 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
1111 d->rxbuf_min_shift = 1;
1112 memset(&d->tx, 0, sizeof d->tx);
1113
1114 d->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
1115 e1000_receive, e1000_can_receive,
1116 e1000_cleanup, d);
1117 d->vc->link_status_changed = e1000_set_link_status;
1118
1119 qemu_format_nic_info_str(d->vc, nd->macaddr);
1120
1121 register_savevm(info_str, -1, 2, nic_save, nic_load, d);
1122 d->dev.unregister = pci_e1000_uninit;
1123
1124 return (PCIDevice *)d;
1125 }
Patches shipped by Fedora