hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "fdc.h"
  27 #include "pci.h"
  28 #include "block.h"
  29 #include "sysemu.h"
  30 #include "audio/audio.h"
  31 #include "net.h"
  32 #include "smbus.h"
  33 #include "boards.h"
  34 #include "console.h"
  35 #include "fw_cfg.h"
  36 #include "virtio-blk.h"
  37 #include "virtio-balloon.h"
  38 #include "virtio-console.h"
  39 #include "hpet_emul.h"
  40 #include "device-assignment.h"
  41
  42 #include "qemu-kvm.h"
  43
  44 /* output Bochs bios info messages */
  45 //#define DEBUG_BIOS
  46
  47 #define BIOS_FILENAME "bios.bin"
  48 #define VGABIOS_FILENAME "vgabios.bin"
  49 #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
  50 #define EXTBOOT_FILENAME "extboot.bin"
  51
  52 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  53
  54 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  55 #define ACPI_DATA_SIZE       0x10000
  56 #define BIOS_CFG_IOPORT 0x510
  57 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  58
  59 #define MAX_IDE_BUS 2
  60
  61 extern uint8_t *acpi_tables;
  62 extern size_t acpi_tables_len;
  63
  64 static fdctrl_t *floppy_controller;
  65 static RTCState *rtc_state;
  66 static PITState *pit;
  67 static IOAPICState *ioapic;
  68 static PCIDevice *i440fx_state;
  69
  70 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
  71 {
  72 }
  73
  74 /* MSDOS compatibility mode FPU exception support */
  75 static qemu_irq ferr_irq;
  76 /* XXX: add IGNNE support */
  77 void cpu_set_ferr(CPUX86State *s)
  78 {
  79     qemu_irq_raise(ferr_irq);
  80 }
  81
  82 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
  83 {
  84     qemu_irq_lower(ferr_irq);
  85 }
  86
  87 /* TSC handling */
  88 uint64_t cpu_get_tsc(CPUX86State *env)
  89 {
  90     /* Note: when using kqemu, it is more logical to return the host TSC
  91        because kqemu does not trap the RDTSC instruction for
  92        performance reasons */
  93 #ifdef USE_KQEMU
  94     if (env->kqemu_enabled) {
  95         return cpu_get_real_ticks();
  96     } else
  97 #endif
  98     {
  99         return cpu_get_ticks();
 100     }
 101 }
 102
 103 /* SMM support */
 104 void cpu_smm_update(CPUState *env)
 105 {
 106     if (i440fx_state && env == first_cpu)
 107         i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
 108 }
 109
 110
 111 /* IRQ handling */
 112 int cpu_get_pic_interrupt(CPUState *env)
 113 {
 114     int intno;
 115
 116     intno = apic_get_interrupt(env);
 117     if (intno >= 0) {
 118         /* set irq request if a PIC irq is still pending */
 119         /* XXX: improve that */
 120         pic_update_irq(isa_pic);
 121         return intno;
 122     }
 123     /* read the irq from the PIC */
 124     if (!apic_accept_pic_intr(env))
 125         return -1;
 126
 127     intno = pic_read_irq(isa_pic);
 128     return intno;
 129 }
 130
 131 static void pic_irq_request(void *opaque, int irq, int level)
 132 {
 133     CPUState *env = first_cpu;
 134
 135     if (env->apic_state) {
 136         while (env) {
 137             if (apic_accept_pic_intr(env))
 138                 apic_deliver_pic_intr(env, level);
 139             env = env->next_cpu;
 140         }
 141     } else {
 142         if (level)
 143             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 144         else
 145             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 146     }
 147 }
 148
 149 /* PC cmos mappings */
 150
 151 #define REG_EQUIPMENT_BYTE          0x14
 152
 153 static int cmos_get_fd_drive_type(int fd0)
 154 {
 155     int val;
 156
 157     switch (fd0) {
 158     case 0:
 159         /* 1.44 Mb 3"5 drive */
 160         val = 4;
 161         break;
 162     case 1:
 163         /* 2.88 Mb 3"5 drive */
 164         val = 5;
 165         break;
 166     case 2:
 167         /* 1.2 Mb 5"5 drive */
 168         val = 2;
 169         break;
 170     default:
 171         val = 0;
 172         break;
 173     }
 174     return val;
 175 }
 176
 177 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 178 {
 179     RTCState *s = rtc_state;
 180     int cylinders, heads, sectors;
 181     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 182     rtc_set_memory(s, type_ofs, 47);
 183     rtc_set_memory(s, info_ofs, cylinders);
 184     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 185     rtc_set_memory(s, info_ofs + 2, heads);
 186     rtc_set_memory(s, info_ofs + 3, 0xff);
 187     rtc_set_memory(s, info_ofs + 4, 0xff);
 188     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 189     rtc_set_memory(s, info_ofs + 6, cylinders);
 190     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 191     rtc_set_memory(s, info_ofs + 8, sectors);
 192 }
 193
 194 /* convert boot_device letter to something recognizable by the bios */
 195 static int boot_device2nibble(char boot_device)
 196 {
 197     switch(boot_device) {
 198     case 'a':
 199     case 'b':
 200         return 0x01; /* floppy boot */
 201     case 'c':
 202         return 0x02; /* hard drive boot */
 203     case 'd':
 204         return 0x03; /* CD-ROM boot */
 205     case 'n':
 206         return 0x04; /* Network boot */
 207     }
 208     return 0;
 209 }
 210
 211 /* copy/pasted from cmos_init, should be made a general function
 212  and used there as well */
 213 static int pc_boot_set(void *opaque, const char *boot_device)
 214 {
 215 #define PC_MAX_BOOT_DEVICES 3
 216     RTCState *s = (RTCState *)opaque;
 217     int nbds, bds[3] = { 0, };
 218     int i;
 219
 220     nbds = strlen(boot_device);
 221     if (nbds > PC_MAX_BOOT_DEVICES) {
 222         term_printf("Too many boot devices for PC\n");
 223         return(1);
 224     }
 225     for (i = 0; i < nbds; i++) {
 226         bds[i] = boot_device2nibble(boot_device[i]);
 227         if (bds[i] == 0) {
 228             term_printf("Invalid boot device for PC: '%c'\n",
 229                     boot_device[i]);
 230             return(1);
 231         }
 232     }
 233     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 234     rtc_set_memory(s, 0x38, (bds[2] << 4));
 235     return(0);
 236 }
 237
 238 /* hd_table must contain 4 block drivers */
 239 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 240                       const char *boot_device, BlockDriverState **hd_table)
 241 {
 242     RTCState *s = rtc_state;
 243     int nbds, bds[3] = { 0, };
 244     int val;
 245     int fd0, fd1, nb;
 246     int i;
 247
 248     /* various important CMOS locations needed by PC/Bochs bios */
 249
 250     /* memory size */
 251     val = 640; /* base memory in K */
 252     rtc_set_memory(s, 0x15, val);
 253     rtc_set_memory(s, 0x16, val >> 8);
 254
 255     val = (ram_size / 1024) - 1024;
 256     if (val > 65535)
 257         val = 65535;
 258     rtc_set_memory(s, 0x17, val);
 259     rtc_set_memory(s, 0x18, val >> 8);
 260     rtc_set_memory(s, 0x30, val);
 261     rtc_set_memory(s, 0x31, val >> 8);
 262
 263     if (above_4g_mem_size) {
 264         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 265         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 266         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 267     }
 268     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 269
 270     if (ram_size > (16 * 1024 * 1024))
 271         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 272     else
 273         val = 0;
 274     if (val > 65535)
 275         val = 65535;
 276     rtc_set_memory(s, 0x34, val);
 277     rtc_set_memory(s, 0x35, val >> 8);
 278
 279     /* set the number of CPU */
 280     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 281
 282     /* set boot devices, and disable floppy signature check if requested */
 283 #define PC_MAX_BOOT_DEVICES 3
 284     nbds = strlen(boot_device);
 285     if (nbds > PC_MAX_BOOT_DEVICES) {
 286         fprintf(stderr, "Too many boot devices for PC\n");
 287         exit(1);
 288     }
 289     for (i = 0; i < nbds; i++) {
 290         bds[i] = boot_device2nibble(boot_device[i]);
 291         if (bds[i] == 0) {
 292             fprintf(stderr, "Invalid boot device for PC: '%c'\n",
 293                     boot_device[i]);
 294             exit(1);
 295         }
 296     }
 297     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 298     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
 299
 300     /* floppy type */
 301
 302     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 303     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 304
 305     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 306     rtc_set_memory(s, 0x10, val);
 307
 308     val = 0;
 309     nb = 0;
 310     if (fd0 < 3)
 311         nb++;
 312     if (fd1 < 3)
 313         nb++;
 314     switch (nb) {
 315     case 0:
 316         break;
 317     case 1:
 318         val |= 0x01; /* 1 drive, ready for boot */
 319         break;
 320     case 2:
 321         val |= 0x41; /* 2 drives, ready for boot */
 322         break;
 323     }
 324     val |= 0x02; /* FPU is there */
 325     val |= 0x04; /* PS/2 mouse installed */
 326     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 327
 328     /* hard drives */
 329
 330     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 331     if (hd_table[0])
 332         cmos_init_hd(0x19, 0x1b, hd_table[0]);
 333     if (hd_table[1])
 334         cmos_init_hd(0x1a, 0x24, hd_table[1]);
 335
 336     val = 0;
 337     for (i = 0; i < 4; i++) {
 338         if (hd_table[i]) {
 339             int cylinders, heads, sectors, translation;
 340             /* NOTE: bdrv_get_geometry_hint() returns the physical
 341                 geometry.  It is always such that: 1 <= sects <= 63, 1
 342                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 343                 geometry can be different if a translation is done. */
 344             translation = bdrv_get_translation_hint(hd_table[i]);
 345             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 346                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 347                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 348                     /* No translation. */
 349                     translation = 0;
 350                 } else {
 351                     /* LBA translation. */
 352                     translation = 1;
 353                 }
 354             } else {
 355                 translation--;
 356             }
 357             val |= translation << (i * 2);
 358         }
 359     }
 360     rtc_set_memory(s, 0x39, val);
 361 }
 362
 363 void ioport_set_a20(int enable)
 364 {
 365     /* XXX: send to all CPUs ? */
 366     cpu_x86_set_a20(first_cpu, enable);
 367 }
 368
 369 int ioport_get_a20(void)
 370 {
 371     return ((first_cpu->a20_mask >> 20) & 1);
 372 }
 373
 374 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 375 {
 376     ioport_set_a20((val >> 1) & 1);
 377     /* XXX: bit 0 is fast reset */
 378 }
 379
 380 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 381 {
 382     return ioport_get_a20() << 1;
 383 }
 384
 385 /***********************************************************/
 386 /* Bochs BIOS debug ports */
 387
 388 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 389 {
 390     static const char shutdown_str[8] = "Shutdown";
 391     static int shutdown_index = 0;
 392
 393     switch(addr) {
 394         /* Bochs BIOS messages */
 395     case 0x400:
 396     case 0x401:
 397         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 398         exit(1);
 399     case 0x402:
 400     case 0x403:
 401 #ifdef DEBUG_BIOS
 402         fprintf(stderr, "%c", val);
 403 #endif
 404         break;
 405     case 0x8900:
 406         /* same as Bochs power off */
 407         if (val == shutdown_str[shutdown_index]) {
 408             shutdown_index++;
 409             if (shutdown_index == 8) {
 410                 shutdown_index = 0;
 411                 qemu_system_shutdown_request();
 412             }
 413         } else {
 414             shutdown_index = 0;
 415         }
 416         break;
 417
 418         /* LGPL'ed VGA BIOS messages */
 419     case 0x501:
 420     case 0x502:
 421         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 422         exit(1);
 423     case 0x500:
 424     case 0x503:
 425 #ifdef DEBUG_BIOS
 426         fprintf(stderr, "%c", val);
 427 #endif
 428         break;
 429     }
 430 }
 431
 432 static void bochs_bios_init(void)
 433 {
 434     void *fw_cfg;
 435
 436     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 437     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 438     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 439     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 440     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 441
 442     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 443     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 444     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 445     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 446
 447     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 448     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 449     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 450     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, acpi_tables, acpi_tables_len);
 451 }
 452
 453 /* Generate an initial boot sector which sets state and jump to
 454    a specified vector */
 455 static void generate_bootsect(uint8_t *option_rom,
 456                               uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
 457 {
 458     uint8_t rom[512], *p, *reloc;
 459     uint8_t sum;
 460     int i;
 461
 462     memset(rom, 0, sizeof(rom));
 463
 464     p = rom;
 465     /* Make sure we have an option rom signature */
 466     *p++ = 0x55;
 467     *p++ = 0xaa;
 468
 469     /* ROM size in sectors*/
 470     *p++ = 1;
 471
 472     /* Hook int19 */
 473
 474     *p++ = 0x50;                /* push ax */
 475     *p++ = 0x1e;                /* push ds */
 476     *p++ = 0x31; *p++ = 0xc0;   /* xor ax, ax */
 477     *p++ = 0x8e; *p++ = 0xd8;   /* mov ax, ds */
 478
 479     *p++ = 0xc7; *p++ = 0x06;   /* movvw _start,0x64 */
 480     *p++ = 0x64; *p++ = 0x00;
 481     reloc = p;
 482     *p++ = 0x00; *p++ = 0x00;
 483
 484     *p++ = 0x8c; *p++ = 0x0e;   /* mov cs,0x66 */
 485     *p++ = 0x66; *p++ = 0x00;
 486
 487     *p++ = 0x1f;                /* pop ds */
 488     *p++ = 0x58;                /* pop ax */
 489     *p++ = 0xcb;                /* lret */
 490
 491     /* Actual code */
 492     *reloc = (p - rom);
 493
 494     *p++ = 0xfa;                /* CLI */
 495     *p++ = 0xfc;                /* CLD */
 496
 497     for (i = 0; i < 6; i++) {
 498         if (i == 1)             /* Skip CS */
 499             continue;
 500
 501         *p++ = 0xb8;            /* MOV AX,imm16 */
 502         *p++ = segs[i];
 503         *p++ = segs[i] >> 8;
 504         *p++ = 0x8e;            /* MOV <seg>,AX */
 505         *p++ = 0xc0 + (i << 3);
 506     }
 507
 508     for (i = 0; i < 8; i++) {
 509         *p++ = 0x66;            /* 32-bit operand size */
 510         *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
 511         *p++ = gpr[i];
 512         *p++ = gpr[i] >> 8;
 513         *p++ = gpr[i] >> 16;
 514         *p++ = gpr[i] >> 24;
 515     }
 516
 517     *p++ = 0xea;                /* JMP FAR */
 518     *p++ = ip;                  /* IP */
 519     *p++ = ip >> 8;
 520     *p++ = segs[1];             /* CS */
 521     *p++ = segs[1] >> 8;
 522
 523     /* sign rom */
 524     sum = 0;
 525     for (i = 0; i < (sizeof(rom) - 1); i++)
 526         sum += rom[i];
 527     rom[sizeof(rom) - 1] = -sum;
 528
 529     memcpy(option_rom, rom, sizeof(rom));
 530 }
 531
 532 static long get_file_size(FILE *f)
 533 {
 534     long where, size;
 535
 536     /* XXX: on Unix systems, using fstat() probably makes more sense */
 537
 538     where = ftell(f);
 539     fseek(f, 0, SEEK_END);
 540     size = ftell(f);
 541     fseek(f, where, SEEK_SET);
 542
 543     return size;
 544 }
 545
 546 static void load_linux(uint8_t *option_rom,
 547                        const char *kernel_filename,
 548                        const char *initrd_filename,
 549                        const char *kernel_cmdline)
 550 {
 551     uint16_t protocol;
 552     uint32_t gpr[8];
 553     uint16_t seg[6];
 554     uint16_t real_seg;
 555     int setup_size, kernel_size, initrd_size, cmdline_size;
 556     uint32_t initrd_max;
 557     uint8_t header[1024];
 558     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr;
 559     FILE *f, *fi;
 560
 561     /* Align to 16 bytes as a paranoia measure */
 562     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 563
 564     /* load the kernel header */
 565     f = fopen(kernel_filename, "rb");
 566     if (!f || !(kernel_size = get_file_size(f)) ||
 567         fread(header, 1, 1024, f) != 1024) {
 568         fprintf(stderr, "qemu: could not load kernel '%s'\n",
 569                 kernel_filename);
 570         exit(1);
 571     }
 572
 573     /* kernel protocol version */
 574 #if 0
 575     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 576 #endif
 577     if (ldl_p(header+0x202) == 0x53726448)
 578         protocol = lduw_p(header+0x206);
 579     else
 580         protocol = 0;
 581
 582     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 583         /* Low kernel */
 584         real_addr    = 0x90000;
 585         cmdline_addr = 0x9a000 - cmdline_size;
 586         prot_addr    = 0x10000;
 587     } else if (protocol < 0x202) {
 588         /* High but ancient kernel */
 589         real_addr    = 0x90000;
 590         cmdline_addr = 0x9a000 - cmdline_size;
 591         prot_addr    = 0x100000;
 592     } else {
 593         /* High and recent kernel */
 594         real_addr    = 0x10000;
 595         cmdline_addr = 0x20000;
 596         prot_addr    = 0x100000;
 597     }
 598
 599 #if 0
 600     fprintf(stderr,
 601             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 602             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 603             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 604             real_addr,
 605             cmdline_addr,
 606             prot_addr);
 607 #endif
 608
 609     /* highest address for loading the initrd */
 610     if (protocol >= 0x203)
 611         initrd_max = ldl_p(header+0x22c);
 612     else
 613         initrd_max = 0x37ffffff;
 614
 615     if (initrd_max >= ram_size-ACPI_DATA_SIZE)
 616         initrd_max = ram_size-ACPI_DATA_SIZE-1;
 617
 618     /* kernel command line */
 619     pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
 620
 621     if (protocol >= 0x202) {
 622         stl_p(header+0x228, cmdline_addr);
 623     } else {
 624         stw_p(header+0x20, 0xA33F);
 625         stw_p(header+0x22, cmdline_addr-real_addr);
 626     }
 627
 628     /* loader type */
 629     /* High nybble = B reserved for Qemu; low nybble is revision number.
 630        If this code is substantially changed, you may want to consider
 631        incrementing the revision. */
 632     if (protocol >= 0x200)
 633         header[0x210] = 0xB0;
 634
 635     /* heap */
 636     if (protocol >= 0x201) {
 637         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 638         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 639     }
 640
 641     /* load initrd */
 642     if (initrd_filename) {
 643         if (protocol < 0x200) {
 644             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 645             exit(1);
 646         }
 647
 648         fi = fopen(initrd_filename, "rb");
 649         if (!fi) {
 650             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 651                     initrd_filename);
 652             exit(1);
 653         }
 654
 655         initrd_size = get_file_size(fi);
 656         initrd_addr = (initrd_max-initrd_size) & ~4095;
 657
 658         fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx
 659                 "\n", initrd_size, initrd_addr);
 660
 661         if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
 662             fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
 663                     initrd_filename);
 664             exit(1);
 665         }
 666         fclose(fi);
 667
 668         stl_p(header+0x218, initrd_addr);
 669         stl_p(header+0x21c, initrd_size);
 670     }
 671
 672     /* store the finalized header and load the rest of the kernel */
 673     cpu_physical_memory_write(real_addr, header, 1024);
 674
 675     setup_size = header[0x1f1];
 676     if (setup_size == 0)
 677         setup_size = 4;
 678
 679     setup_size = (setup_size+1)*512;
 680     kernel_size -= setup_size;  /* Size of protected-mode code */
 681
 682     if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
 683         !fread_targphys_ok(prot_addr, kernel_size, f)) {
 684         fprintf(stderr, "qemu: read error on kernel '%s'\n",
 685                 kernel_filename);
 686         exit(1);
 687     }
 688     fclose(f);
 689
 690     /* generate bootsector to set up the initial register state */
 691     real_seg = real_addr >> 4;
 692     seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
 693     seg[1] = real_seg+0x20;     /* CS */
 694     memset(gpr, 0, sizeof gpr);
 695     gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */
 696
 697     generate_bootsect(option_rom, gpr, seg, 0);
 698 }
 699
 700 static void main_cpu_reset(void *opaque)
 701 {
 702     CPUState *env = opaque;
 703     cpu_reset(env);
 704 }
 705
 706 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 707 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 708 static const int ide_irq[2] = { 14, 15 };
 709
 710 #define NE2000_NB_MAX 6
 711
 712 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
 713 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 714
 715 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 716 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 717
 718 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 719 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 720
 721 #ifdef HAS_AUDIO
 722 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 723 {
 724     struct soundhw *c;
 725     int audio_enabled = 0;
 726
 727     for (c = soundhw; !audio_enabled && c->name; ++c) {
 728         audio_enabled = c->enabled;
 729     }
 730
 731     if (audio_enabled) {
 732         AudioState *s;
 733
 734         s = AUD_init ();
 735         if (s) {
 736             for (c = soundhw; c->name; ++c) {
 737                 if (c->enabled) {
 738                     if (c->isa) {
 739                         c->init.init_isa (s, pic);
 740                     }
 741                     else {
 742                         if (pci_bus) {
 743                             c->init.init_pci (pci_bus, s);
 744                         }
 745                     }
 746                 }
 747             }
 748         }
 749     }
 750 }
 751 #endif
 752
 753 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 754 {
 755     static int nb_ne2k = 0;
 756
 757     if (nb_ne2k == NE2000_NB_MAX)
 758         return;
 759     isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
 760     nb_ne2k++;
 761 }
 762
 763 typedef struct rom_reset_data {
 764     uint8_t *data;
 765     target_phys_addr_t addr;
 766     unsigned size;
 767 } RomResetData;
 768
 769 static void option_rom_reset(void *_rrd)
 770 {
 771     RomResetData *rrd = _rrd;
 772
 773     cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
 774 }
 775
 776 static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
 777 {
 778     RomResetData *rrd = qemu_malloc(sizeof *rrd);
 779
 780     rrd->data = qemu_malloc(size);
 781     cpu_physical_memory_read(addr, rrd->data, size);
 782     rrd->addr = addr;
 783     rrd->size = size;
 784     qemu_register_reset(option_rom_reset, rrd);
 785 }
 786
 787 CPUState *pc_new_cpu(int cpu, const char *cpu_model, int pci_enabled)
 788 {
 789         CPUState *env = cpu_init(cpu_model);
 790         if (!env) {
 791             fprintf(stderr, "Unable to find x86 CPU definition\n");
 792             exit(1);
 793         }
 794         if (cpu != 0)
 795             env->halted = 1;
 796         if (smp_cpus > 1) {
 797             /* XXX: enable it in all cases */
 798             env->cpuid_features |= CPUID_APIC;
 799         }
 800         qemu_register_reset(main_cpu_reset, env);
 801         if (pci_enabled) {
 802             apic_init(env);
 803         }
 804         return env;
 805 }
 806
 807 /* PC hardware initialisation */
 808 static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
 809                      const char *boot_device,
 810                      const char *kernel_filename, const char *kernel_cmdline,
 811                      const char *initrd_filename,
 812                      int pci_enabled, const char *cpu_model)
 813 {
 814     char buf[1024];
 815     int ret, linux_boot, i;
 816     ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
 817     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 818     int bios_size, isa_bios_size, vga_bios_size;
 819     int pci_option_rom_offset;
 820     PCIBus *pci_bus;
 821     int piix3_devfn = -1;
 822     CPUState *env;
 823     qemu_irq *cpu_irq;
 824     qemu_irq *i8259;
 825     int index;
 826     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 827     BlockDriverState *fd[MAX_FD];
 828
 829     if (ram_size >= 0xe0000000 ) {
 830         above_4g_mem_size = ram_size - 0xe0000000;
 831         below_4g_mem_size = 0xe0000000;
 832     } else {
 833         below_4g_mem_size = ram_size;
 834     }
 835
 836     linux_boot = (kernel_filename != NULL);
 837
 838     /* init CPUs */
 839     if (cpu_model == NULL) {
 840 #ifdef TARGET_X86_64
 841         cpu_model = "qemu64";
 842 #else
 843         cpu_model = "qemu32";
 844 #endif
 845     }
 846
 847     for(i = 0; i < smp_cpus; i++) {
 848         env = pc_new_cpu(i, cpu_model, pci_enabled);
 849     }
 850
 851     vmport_init();
 852
 853     /* allocate RAM */
 854     ram_addr = qemu_ram_alloc(0xa0000);
 855     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 856
 857     /* Allocate, even though we won't register, so we don't break the
 858      * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
 859      * and some bios areas, which will be registered later
 860      */
 861     ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
 862     ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
 863     cpu_register_physical_memory(0x100000,
 864                  below_4g_mem_size - 0x100000,
 865                  ram_addr);
 866
 867     /* above 4giga memory allocation */
 868     if (above_4g_mem_size > 0) {
 869         if (hpagesize) {
 870             if (ram_addr & (hpagesize-1)) {
 871                 unsigned long aligned_addr;
 872                 aligned_addr = (ram_addr + hpagesize - 1) & ~(hpagesize-1);
 873                 qemu_ram_alloc(aligned_addr - ram_addr);
 874                 ram_addr = aligned_addr;
 875             }
 876         }
 877         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 878         cpu_register_physical_memory(0x100000000ULL,
 879                                      above_4g_mem_size,
 880                                      ram_addr);
 881     }
 882
 883     /* allocate VGA RAM */
 884     vga_ram_addr = qemu_ram_alloc(vga_ram_size);
 885
 886     /* BIOS load */
 887     if (bios_name == NULL)
 888         bios_name = BIOS_FILENAME;
 889     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 890     bios_size = get_image_size(buf);
 891     if (bios_size <= 0 ||
 892         (bios_size % 65536) != 0) {
 893         goto bios_error;
 894     }
 895     bios_offset = qemu_ram_alloc(bios_size);
 896     ret = load_image(buf, phys_ram_base + bios_offset);
 897     if (ret != bios_size) {
 898     bios_error:
 899         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
 900         exit(1);
 901     }
 902
 903     if (cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled) {
 904         /* VGA BIOS load */
 905         if (cirrus_vga_enabled) {
 906             snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME);
 907         } else {
 908             snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
 909         }
 910         vga_bios_size = get_image_size(buf);
 911         if (vga_bios_size <= 0 || vga_bios_size > 65536)
 912             goto vga_bios_error;
 913         vga_bios_offset = qemu_ram_alloc(65536);
 914
 915         ret = load_image(buf, phys_ram_base + vga_bios_offset);
 916         if (ret != vga_bios_size) {
 917 vga_bios_error:
 918             fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf);
 919             exit(1);
 920         }
 921
 922         /* setup basic memory access */
 923         cpu_register_physical_memory(0xc0000, 0x10000,
 924                                      vga_bios_offset | IO_MEM_ROM);
 925     }
 926
 927     /* map the last 128KB of the BIOS in ISA space */
 928     isa_bios_size = bios_size;
 929     if (isa_bios_size > (128 * 1024))
 930         isa_bios_size = 128 * 1024;
 931     cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
 932                                  IO_MEM_UNASSIGNED);
 933     /* kvm tpr optimization needs the bios accessible for write, at least to qemu itself */
 934     cpu_register_physical_memory(0x100000 - isa_bios_size,
 935                                  isa_bios_size,
 936                                  (bios_offset + bios_size - isa_bios_size) /* | IO_MEM_ROM */);
 937
 938     if (extboot_drive != -1) {
 939         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, EXTBOOT_FILENAME);
 940         option_rom[nb_option_roms++] = buf;
 941     }
 942
 943     {
 944         ram_addr_t option_rom_offset;
 945         int size, offset;
 946
 947         offset = 0;
 948         if (linux_boot) {
 949             option_rom_offset = qemu_ram_alloc(TARGET_PAGE_SIZE);
 950             load_linux(phys_ram_base + option_rom_offset,
 951                        kernel_filename, initrd_filename, kernel_cmdline);
 952             cpu_register_physical_memory(0xd0000, TARGET_PAGE_SIZE,
 953                                          option_rom_offset | IO_MEM_ROM);
 954             offset = TARGET_PAGE_SIZE;
 955         }
 956
 957         for (i = 0; i < nb_option_roms; i++) {
 958             size = get_image_size(option_rom[i]);
 959             if (size < 0) {
 960                 fprintf(stderr, "Could not load option rom '%s'\n",
 961                         option_rom[i]);
 962                 exit(1);
 963             }
 964             if (size > (0x10000 - offset))
 965                 goto option_rom_error;
 966             option_rom_offset = qemu_ram_alloc(size);
 967             ret = load_image(option_rom[i], phys_ram_base + option_rom_offset);
 968             if (ret != size) {
 969             option_rom_error:
 970                 fprintf(stderr, "Too many option ROMS\n");
 971                 exit(1);
 972             }
 973             size = (size + 4095) & ~4095;
 974     /* XXX: for DDIM support, "ROM space" should be writable during
 975        initialization, and (optionally) marked readonly by the BIOS
 976        before INT 19h.  See the PNPBIOS specification, appendix B.
 977        DDIM support is mandatory for proper PCI expansion ROM support. */
 978             cpu_register_physical_memory(0xd0000 + offset,
 979                                          size, option_rom_offset /* | IO_MEM_ROM */);
 980             option_rom_setup_reset(0xd0000 + offset, size);
 981             offset += size;
 982         }
 983         pci_option_rom_offset = offset;
 984     }
 985
 986     /* map all the bios at the top of memory */
 987     cpu_register_physical_memory((uint32_t)(-bios_size),
 988                                  bios_size, bios_offset | IO_MEM_ROM);
 989
 990     bochs_bios_init();
 991
 992     cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
 993     i8259 = i8259_init(cpu_irq[0]);
 994     ferr_irq = i8259[13];
 995
 996     if (pci_enabled) {
 997         pci_bus = i440fx_init(&i440fx_state, i8259);
 998         piix3_devfn = piix3_init(pci_bus, -1);
 999     } else {
1000         pci_bus = NULL;
1001     }
1002
1003     /* init basic PC hardware */
1004     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1005
1006     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1007
1008     if (cirrus_vga_enabled) {
1009         if (pci_enabled) {
1010             pci_cirrus_vga_init(pci_bus,
1011                                 phys_ram_base + vga_ram_addr,
1012                                 vga_ram_addr, vga_ram_size);
1013         } else {
1014             isa_cirrus_vga_init(phys_ram_base + vga_ram_addr,
1015                                 vga_ram_addr, vga_ram_size);
1016         }
1017     } else if (vmsvga_enabled) {
1018         if (pci_enabled)
1019             pci_vmsvga_init(pci_bus, phys_ram_base + vga_ram_addr,
1020                             vga_ram_addr, vga_ram_size);
1021         else
1022             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1023     } else if (std_vga_enabled) {
1024         if (pci_enabled) {
1025             pci_vga_init(pci_bus, phys_ram_base + vga_ram_addr,
1026                          vga_ram_addr, vga_ram_size, 0, 0);
1027         } else {
1028             isa_vga_init(phys_ram_base + vga_ram_addr,
1029                          vga_ram_addr, vga_ram_size);
1030         }
1031     }
1032
1033     rtc_state = rtc_init(0x70, i8259[8], 2000);
1034
1035     qemu_register_boot_set(pc_boot_set, rtc_state);
1036
1037     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1038     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1039
1040     if (pci_enabled) {
1041         ioapic = ioapic_init();
1042     }
1043 #ifdef USE_KVM_PIT
1044     if (kvm_enabled() && qemu_kvm_pit_in_kernel())
1045         pit = kvm_pit_init(0x40, i8259[0]);
1046     else
1047 #endif
1048         pit = pit_init(0x40, i8259[0]);
1049     pcspk_init(pit);
1050     if (!no_hpet) {
1051         hpet_init(i8259);
1052     }
1053     if (pci_enabled) {
1054         pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
1055     }
1056
1057     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1058         if (serial_hds[i]) {
1059             serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
1060                         serial_hds[i]);
1061         }
1062     }
1063
1064     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1065         if (parallel_hds[i]) {
1066             parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1067                           parallel_hds[i]);
1068         }
1069     }
1070
1071     for(i = 0; i < nb_nics; i++) {
1072         NICInfo *nd = &nd_table[i];
1073
1074         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1075             pc_init_ne2k_isa(nd, i8259);
1076         else
1077             pci_nic_init(pci_bus, nd, -1, "rtl8139");
1078     }
1079
1080     qemu_system_hot_add_init(cpu_model);
1081
1082     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1083         fprintf(stderr, "qemu: too many IDE bus\n");
1084         exit(1);
1085     }
1086
1087     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1088         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1089         if (index != -1)
1090             hd[i] = drives_table[index].bdrv;
1091         else
1092             hd[i] = NULL;
1093     }
1094
1095     if (pci_enabled) {
1096         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1097     } else {
1098         for(i = 0; i < MAX_IDE_BUS; i++) {
1099             isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1100                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1101         }
1102     }
1103
1104     i8042_init(i8259[1], i8259[12], 0x60);
1105     DMA_init(0);
1106 #ifdef HAS_AUDIO
1107     audio_init(pci_enabled ? pci_bus : NULL, i8259);
1108 #endif
1109
1110     for(i = 0; i < MAX_FD; i++) {
1111         index = drive_get_index(IF_FLOPPY, 0, i);
1112         if (index != -1)
1113             fd[i] = drives_table[index].bdrv;
1114         else
1115             fd[i] = NULL;
1116     }
1117     floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1118
1119     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1120
1121     if (pci_enabled && usb_enabled) {
1122         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1123     }
1124
1125     if (pci_enabled && acpi_enabled) {
1126         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1127         i2c_bus *smbus;
1128
1129         /* TODO: Populate SPD eeprom data.  */
1130         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1131         for (i = 0; i < 8; i++) {
1132             smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
1133         }
1134     }
1135
1136     if (i440fx_state) {
1137         i440fx_init_memory_mappings(i440fx_state);
1138     }
1139
1140     if (pci_enabled) {
1141         int max_bus;
1142         int bus, unit;
1143         void *scsi;
1144
1145         max_bus = drive_get_max_bus(IF_SCSI);
1146
1147         for (bus = 0; bus <= max_bus; bus++) {
1148             scsi = lsi_scsi_init(pci_bus, -1);
1149             for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
1150                 index = drive_get_index(IF_SCSI, bus, unit);
1151                 if (index == -1)
1152                     continue;
1153                 lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
1154             }
1155         }
1156     }
1157
1158     /* Add virtio block devices */
1159     if (pci_enabled) {
1160         int index;
1161         int unit_id = 0;
1162
1163         while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
1164             virtio_blk_init(pci_bus, drives_table[index].bdrv);
1165             unit_id++;
1166         }
1167     }
1168
1169     if (extboot_drive != -1) {
1170         DriveInfo *info = &drives_table[extboot_drive];
1171         int cyls, heads, secs;
1172
1173         if (info->type != IF_IDE && info->type != IF_VIRTIO) {
1174             bdrv_guess_geometry(info->bdrv, &cyls, &heads, &secs);
1175             bdrv_set_geometry_hint(info->bdrv, cyls, heads, secs);
1176         }
1177
1178         extboot_init(info->bdrv, 1);
1179     }
1180
1181     /* Add virtio balloon device */
1182     if (pci_enabled)
1183         virtio_balloon_init(pci_bus);
1184
1185     /* Add virtio console devices */
1186     if (pci_enabled) {
1187         for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1188             if (virtcon_hds[i])
1189                 virtio_console_init(pci_bus, virtcon_hds[i]);
1190         }
1191     }
1192
1193 #ifdef USE_KVM_DEVICE_ASSIGNMENT
1194     if (kvm_enabled()) {
1195         add_assigned_devices(pci_bus, assigned_devices, assigned_devices_index);
1196         assigned_dev_load_option_roms(pci_option_rom_offset);
1197     }
1198 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
1199 }
1200
1201 static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
1202                         const char *boot_device,
1203                         const char *kernel_filename,
1204                         const char *kernel_cmdline,
1205                         const char *initrd_filename,
1206                         const char *cpu_model)
1207 {
1208     pc_init1(ram_size, vga_ram_size, boot_device,
1209              kernel_filename, kernel_cmdline,
1210              initrd_filename, 1, cpu_model);
1211 }
1212
1213 static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
1214                         const char *boot_device,
1215                         const char *kernel_filename,
1216                         const char *kernel_cmdline,
1217                         const char *initrd_filename,
1218                         const char *cpu_model)
1219 {
1220     pc_init1(ram_size, vga_ram_size, boot_device,
1221              kernel_filename, kernel_cmdline,
1222              initrd_filename, 0, cpu_model);
1223 }
1224
1225 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1226    BIOS will read it and start S3 resume at POST Entry */
1227 void cmos_set_s3_resume(void)
1228 {
1229     if (rtc_state)
1230         rtc_set_memory(rtc_state, 0xF, 0xFE);
1231 }
1232
1233 QEMUMachine pc_machine = {
1234     .name = "pc",
1235     .desc = "Standard PC",
1236     .init = pc_init_pci,
1237     .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1238     .max_cpus = 255,
1239 };
1240
1241 QEMUMachine isapc_machine = {
1242     .name = "isapc",
1243     .desc = "ISA-only PC",
1244     .init = pc_init_isa,
1245     .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1246     .max_cpus = 1,
1247 };