exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 /* is_jmp field values */
  25 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  26 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  27 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  28 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  29
  30 struct TranslationBlock;
  31
  32 /* XXX: make safe guess about sizes */
  33 #define MAX_OP_PER_INSTR 64
  34 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  35 #define MAX_OPC_PARAM 10
  36 #define OPC_BUF_SIZE 512
  37 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  38
  39 /* Maximum size a TCG op can expand to.  This is complicated because a
  40    single op may require several host instructions and regirster reloads.
  41    For now take a wild guess at 128 bytes, which should allow at least
  42    a couple of fixup instructions per argument.  */
  43 #define TCG_MAX_OP_SIZE 128
  44
  45 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  46
  47 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  48 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  49 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  50 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  51 extern target_ulong gen_opc_jump_pc[2];
  52 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  53
  54 typedef void (GenOpFunc)(void);
  55 typedef void (GenOpFunc1)(long);
  56 typedef void (GenOpFunc2)(long, long);
  57 typedef void (GenOpFunc3)(long, long, long);
  58
  59 extern FILE *logfile;
  60 extern int loglevel;
  61
  62 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  63 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  64 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  65                  unsigned long searched_pc, int pc_pos, void *puc);
  66
  67 unsigned long code_gen_max_block_size(void);
  68 void cpu_gen_init(void);
  69 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  70                  int *gen_code_size_ptr);
  71 int cpu_restore_state(struct TranslationBlock *tb,
  72                       CPUState *env, unsigned long searched_pc,
  73                       void *puc);
  74 int cpu_restore_state_copy(struct TranslationBlock *tb,
  75                            CPUState *env, unsigned long searched_pc,
  76                            void *puc);
  77 void cpu_resume_from_signal(CPUState *env1, void *puc);
  78 void cpu_exec_init(CPUState *env);
  79 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  80 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
  81                                    int is_cpu_write_access);
  82 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  83 void tlb_flush_page(CPUState *env, target_ulong addr);
  84 void tlb_flush(CPUState *env, int flush_global);
  85 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
  86                       target_phys_addr_t paddr, int prot,
  87                       int mmu_idx, int is_softmmu);
  88 static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
  89                                target_phys_addr_t paddr, int prot,
  90                                int mmu_idx, int is_softmmu)
  91 {
  92     if (prot & PAGE_READ)
  93         prot |= PAGE_EXEC;
  94     return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
  95 }
  96
  97 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
  98
  99 #define CODE_GEN_PHYS_HASH_BITS     15
 100 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 101
 102 #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 103
 104 /* estimated block size for TB allocation */
 105 /* XXX: use a per code average code fragment size and modulate it
 106    according to the host CPU */
 107 #if defined(CONFIG_SOFTMMU)
 108 #define CODE_GEN_AVG_BLOCK_SIZE 128
 109 #else
 110 #define CODE_GEN_AVG_BLOCK_SIZE 64
 111 #endif
 112
 113 #if defined(__powerpc__) || defined(__x86_64__) || defined(__arm__)
 114 #define USE_DIRECT_JUMP
 115 #endif
 116 #if defined(__i386__) && !defined(_WIN32)
 117 #define USE_DIRECT_JUMP
 118 #endif
 119
 120 typedef struct TranslationBlock {
 121     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 122     target_ulong cs_base; /* CS base for this block */
 123     uint64_t flags; /* flags defining in which context the code was generated */
 124     uint16_t size;      /* size of target code for this block (1 <=
 125                            size <= TARGET_PAGE_SIZE) */
 126     uint16_t cflags;    /* compile flags */
 127 #define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
 128 #define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
 129 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 130
 131     uint8_t *tc_ptr;    /* pointer to the translated code */
 132     /* next matching tb for physical address. */
 133     struct TranslationBlock *phys_hash_next;
 134     /* first and second physical page containing code. The lower bit
 135        of the pointer tells the index in page_next[] */
 136     struct TranslationBlock *page_next[2];
 137     target_ulong page_addr[2];
 138
 139     /* the following data are used to directly call another TB from
 140        the code of this one. */
 141     uint16_t tb_next_offset[2]; /* offset of original jump target */
 142 #ifdef USE_DIRECT_JUMP
 143     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 144 #else
 145     unsigned long tb_next[2]; /* address of jump generated code */
 146 #endif
 147     /* list of TBs jumping to this one. This is a circular list using
 148        the two least significant bits of the pointers to tell what is
 149        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 150        jmp_first */
 151     struct TranslationBlock *jmp_next[2];
 152     struct TranslationBlock *jmp_first;
 153 } TranslationBlock;
 154
 155 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 156 {
 157     target_ulong tmp;
 158     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 159     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 160 }
 161
 162 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 163 {
 164     target_ulong tmp;
 165     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 166     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 167             | (tmp & TB_JMP_ADDR_MASK));
 168 }
 169
 170 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 171 {
 172     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 173 }
 174
 175 TranslationBlock *tb_alloc(target_ulong pc);
 176 void tb_flush(CPUState *env);
 177 void tb_link_phys(TranslationBlock *tb,
 178                   target_ulong phys_pc, target_ulong phys_page2);
 179
 180 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 181 extern uint8_t *code_gen_ptr;
 182 extern int code_gen_max_blocks;
 183
 184 #if defined(USE_DIRECT_JUMP)
 185
 186 #if defined(__powerpc__)
 187 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 188 {
 189     uint32_t val, *ptr;
 190     long disp = addr - jmp_addr;
 191
 192     ptr = (uint32_t *)jmp_addr;
 193     val = *ptr;
 194
 195     if ((disp << 6) >> 6 != disp) {
 196         uint16_t *p1;
 197
 198         p1 = (uint16_t *) ptr;
 199         *ptr = (val & ~0x03fffffc) | 4;
 200         p1[3] = addr >> 16;
 201         p1[5] = addr & 0xffff;
 202     } else {
 203         /* patch the branch destination */
 204         val = (val & ~0x03fffffc) | (disp & 0x03fffffc);
 205         *ptr = val;
 206     }
 207     /* flush icache */
 208     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 209     asm volatile ("sync" : : : "memory");
 210     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 211     asm volatile ("sync" : : : "memory");
 212     asm volatile ("isync" : : : "memory");
 213 }
 214 #elif defined(__i386__) || defined(__x86_64__)
 215 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 216 {
 217     /* patch the branch destination */
 218     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 219     /* no need to flush icache explicitly */
 220 }
 221 #elif defined(__arm__)
 222 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 223 {
 224     register unsigned long _beg __asm ("a1");
 225     register unsigned long _end __asm ("a2");
 226     register unsigned long _flg __asm ("a3");
 227
 228     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 229     *(uint32_t *)jmp_addr |= ((addr - (jmp_addr + 8)) >> 2) & 0xffffff;
 230
 231     /* flush icache */
 232     _beg = jmp_addr;
 233     _end = jmp_addr + 4;
 234     _flg = 0;
 235     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 236 }
 237 #endif
 238
 239 static inline void tb_set_jmp_target(TranslationBlock *tb,
 240                                      int n, unsigned long addr)
 241 {
 242     unsigned long offset;
 243
 244     offset = tb->tb_jmp_offset[n];
 245     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 246     offset = tb->tb_jmp_offset[n + 2];
 247     if (offset != 0xffff)
 248         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 249 }
 250
 251 #else
 252
 253 /* set the jump target */
 254 static inline void tb_set_jmp_target(TranslationBlock *tb,
 255                                      int n, unsigned long addr)
 256 {
 257     tb->tb_next[n] = addr;
 258 }
 259
 260 #endif
 261
 262 static inline void tb_add_jump(TranslationBlock *tb, int n,
 263                                TranslationBlock *tb_next)
 264 {
 265     /* NOTE: this test is only needed for thread safety */
 266     if (!tb->jmp_next[n]) {
 267         /* patch the native jump address */
 268         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 269
 270         /* add in TB jmp circular list */
 271         tb->jmp_next[n] = tb_next->jmp_first;
 272         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 273     }
 274 }
 275
 276 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 277
 278 #ifndef offsetof
 279 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 280 #endif
 281
 282 #if defined(_WIN32)
 283 #define ASM_DATA_SECTION ".section \".data\"\n"
 284 #define ASM_PREVIOUS_SECTION ".section .text\n"
 285 #elif defined(__APPLE__)
 286 #define ASM_DATA_SECTION ".data\n"
 287 #define ASM_PREVIOUS_SECTION ".text\n"
 288 #else
 289 #define ASM_DATA_SECTION ".section \".data\"\n"
 290 #define ASM_PREVIOUS_SECTION ".previous\n"
 291 #endif
 292
 293 #define ASM_OP_LABEL_NAME(n, opname) \
 294     ASM_NAME(__op_label) #n "." ASM_NAME(opname)
 295
 296 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 297 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 298 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 299
 300 #if defined(__hppa__)
 301
 302 typedef int spinlock_t[4];
 303
 304 #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }
 305
 306 static inline void resetlock (spinlock_t *p)
 307 {
 308     (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1;
 309 }
 310
 311 #else
 312
 313 typedef int spinlock_t;
 314
 315 #define SPIN_LOCK_UNLOCKED 0
 316
 317 static inline void resetlock (spinlock_t *p)
 318 {
 319     *p = SPIN_LOCK_UNLOCKED;
 320 }
 321
 322 #endif
 323
 324 #if defined(__powerpc__)
 325 static inline int testandset (int *p)
 326 {
 327     int ret;
 328     __asm__ __volatile__ (
 329                           "0:    lwarx %0,0,%1\n"
 330                           "      xor. %0,%3,%0\n"
 331                           "      bne 1f\n"
 332                           "      stwcx. %2,0,%1\n"
 333                           "      bne- 0b\n"
 334                           "1:    "
 335                           : "=&r" (ret)
 336                           : "r" (p), "r" (1), "r" (0)
 337                           : "cr0", "memory");
 338     return ret;
 339 }
 340 #elif defined(__i386__)
 341 static inline int testandset (int *p)
 342 {
 343     long int readval = 0;
 344
 345     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 346                           : "+m" (*p), "+a" (readval)
 347                           : "r" (1)
 348                           : "cc");
 349     return readval;
 350 }
 351 #elif defined(__x86_64__)
 352 static inline int testandset (int *p)
 353 {
 354     long int readval = 0;
 355
 356     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 357                           : "+m" (*p), "+a" (readval)
 358                           : "r" (1)
 359                           : "cc");
 360     return readval;
 361 }
 362 #elif defined(__s390__)
 363 static inline int testandset (int *p)
 364 {
 365     int ret;
 366
 367     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 368                           "   jl    0b"
 369                           : "=&d" (ret)
 370                           : "r" (1), "a" (p), "0" (*p)
 371                           : "cc", "memory" );
 372     return ret;
 373 }
 374 #elif defined(__alpha__)
 375 static inline int testandset (int *p)
 376 {
 377     int ret;
 378     unsigned long one;
 379
 380     __asm__ __volatile__ ("0:   mov 1,%2\n"
 381                           "     ldl_l %0,%1\n"
 382                           "     stl_c %2,%1\n"
 383                           "     beq %2,1f\n"
 384                           ".subsection 2\n"
 385                           "1:   br 0b\n"
 386                           ".previous"
 387                           : "=r" (ret), "=m" (*p), "=r" (one)
 388                           : "m" (*p));
 389     return ret;
 390 }
 391 #elif defined(__sparc__)
 392 static inline int testandset (int *p)
 393 {
 394         int ret;
 395
 396         __asm__ __volatile__("ldstub    [%1], %0"
 397                              : "=r" (ret)
 398                              : "r" (p)
 399                              : "memory");
 400
 401         return (ret ? 1 : 0);
 402 }
 403 #elif defined(__arm__)
 404 static inline int testandset (int *spinlock)
 405 {
 406     register unsigned int ret;
 407     __asm__ __volatile__("swp %0, %1, [%2]"
 408                          : "=r"(ret)
 409                          : "0"(1), "r"(spinlock));
 410
 411     return ret;
 412 }
 413 #elif defined(__mc68000)
 414 static inline int testandset (int *p)
 415 {
 416     char ret;
 417     __asm__ __volatile__("tas %1; sne %0"
 418                          : "=r" (ret)
 419                          : "m" (p)
 420                          : "cc","memory");
 421     return ret;
 422 }
 423 #elif defined(__hppa__)
 424
 425 /* Because malloc only guarantees 8-byte alignment for malloc'd data,
 426    and GCC only guarantees 8-byte alignment for stack locals, we can't
 427    be assured of 16-byte alignment for atomic lock data even if we
 428    specify "__attribute ((aligned(16)))" in the type declaration.  So,
 429    we use a struct containing an array of four ints for the atomic lock
 430    type and dynamically select the 16-byte aligned int from the array
 431    for the semaphore.  */
 432 #define __PA_LDCW_ALIGNMENT 16
 433 static inline void *ldcw_align (void *p) {
 434     unsigned long a = (unsigned long)p;
 435     a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
 436     return (void *)a;
 437 }
 438
 439 static inline int testandset (spinlock_t *p)
 440 {
 441     unsigned int ret;
 442     p = ldcw_align(p);
 443     __asm__ __volatile__("ldcw 0(%1),%0"
 444                          : "=r" (ret)
 445                          : "r" (p)
 446                          : "memory" );
 447     return !ret;
 448 }
 449
 450 #elif defined(__ia64)
 451
 452 #include "ia64intrin.h"
 453 static inline int testandset (int *p)
 454 {
 455     return (int)cmpxchg_acq(p,0,1);
 456 }
 457 #elif defined(__mips__)
 458 static inline int testandset (int *p)
 459 {
 460     int ret;
 461
 462     __asm__ __volatile__ (
 463         "       .set push               \n"
 464         "       .set noat               \n"
 465         "       .set mips2              \n"
 466         "1:     li      $1, 1           \n"
 467         "       ll      %0, %1          \n"
 468         "       sc      $1, %1          \n"
 469         "       beqz    $1, 1b          \n"
 470         "       .set pop                "
 471         : "=r" (ret), "+R" (*p)
 472         :
 473         : "memory");
 474
 475     return ret;
 476 }
 477 #else
 478 #error unimplemented CPU support
 479 #endif
 480
 481 #if defined(CONFIG_USER_ONLY)
 482 static inline void spin_lock(spinlock_t *lock)
 483 {
 484     while (testandset(lock));
 485 }
 486
 487 static inline void spin_unlock(spinlock_t *lock)
 488 {
 489     resetlock(lock);
 490 }
 491
 492 static inline int spin_trylock(spinlock_t *lock)
 493 {
 494     return !testandset(lock);
 495 }
 496 #else
 497 static inline void spin_lock(spinlock_t *lock)
 498 {
 499 }
 500
 501 static inline void spin_unlock(spinlock_t *lock)
 502 {
 503 }
 504
 505 static inline int spin_trylock(spinlock_t *lock)
 506 {
 507     return 1;
 508 }
 509 #endif
 510
 511 extern spinlock_t tb_lock;
 512
 513 extern int tb_invalidated_flag;
 514
 515 #if !defined(CONFIG_USER_ONLY)
 516
 517 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 518               void *retaddr);
 519
 520 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 521 #define MEMSUFFIX _code
 522 #define env cpu_single_env
 523
 524 #define DATA_SIZE 1
 525 #include "softmmu_header.h"
 526
 527 #define DATA_SIZE 2
 528 #include "softmmu_header.h"
 529
 530 #define DATA_SIZE 4
 531 #include "softmmu_header.h"
 532
 533 #define DATA_SIZE 8
 534 #include "softmmu_header.h"
 535
 536 #undef ACCESS_TYPE
 537 #undef MEMSUFFIX
 538 #undef env
 539
 540 #endif
 541
 542 #if defined(CONFIG_USER_ONLY)
 543 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 544 {
 545     return addr;
 546 }
 547 #else
 548 /* NOTE: this function can trigger an exception */
 549 /* NOTE2: the returned address is not exactly the physical address: it
 550    is the offset relative to phys_ram_base */
 551 static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr)
 552 {
 553     int mmu_idx, page_index, pd;
 554
 555     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 556     mmu_idx = cpu_mmu_index(env1);
 557     if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
 558                          (addr & TARGET_PAGE_MASK), 0)) {
 559         ldub_code(addr);
 560     }
 561     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 562     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 563 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 564         do_unassigned_access(addr, 0, 1, 0);
 565 #else
 566         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 567 #endif
 568     }
 569     return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base;
 570 }
 571 #endif
 572
 573 #ifdef USE_KQEMU
 574 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 575
 576 #define MSR_QPI_COMMBASE 0xfabe0010
 577
 578 int kqemu_init(CPUState *env);
 579 int kqemu_cpu_exec(CPUState *env);
 580 void kqemu_flush_page(CPUState *env, target_ulong addr);
 581 void kqemu_flush(CPUState *env, int global);
 582 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 583 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 584 void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
 585                         ram_addr_t phys_offset);
 586 void kqemu_cpu_interrupt(CPUState *env);
 587 void kqemu_record_dump(void);
 588
 589 extern uint32_t kqemu_comm_base;
 590
 591 static inline int kqemu_is_ok(CPUState *env)
 592 {
 593     return(env->kqemu_enabled &&
 594            (env->cr[0] & CR0_PE_MASK) &&
 595            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 596            (env->eflags & IF_MASK) &&
 597            !(env->eflags & VM_MASK) &&
 598            (env->kqemu_enabled == 2 ||
 599             ((env->hflags & HF_CPL_MASK) == 3 &&
 600              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 601 }
 602
 603 #endif