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Merge branch 'qemu-cvs'
[qemu-kvm/fedora.git] / hw / vga.c
blob79c682fb27dbc0bb7b91b292b1487f92cf7f119f
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "console.h"
26 #include "pc.h"
27 #include "pci.h"
28 #include "vga_int.h"
29 #include "pixel_ops.h"
30 #include "qemu-timer.h"
31 #include "kvm.h"
32 #include "qemu-kvm.h"
33
34 //#define DEBUG_VGA
35 //#define DEBUG_VGA_MEM
36 //#define DEBUG_VGA_REG
37
38 //#define DEBUG_BOCHS_VBE
39
40 /* force some bits to zero */
41 const uint8_t sr_mask[8] = {
42 (uint8_t)~0xfc,
43 (uint8_t)~0xc2,
44 (uint8_t)~0xf0,
45 (uint8_t)~0xc0,
46 (uint8_t)~0xf1,
47 (uint8_t)~0xff,
48 (uint8_t)~0xff,
49 (uint8_t)~0x00,
50 };
51
52 const uint8_t gr_mask[16] = {
53 (uint8_t)~0xf0, /* 0x00 */
54 (uint8_t)~0xf0, /* 0x01 */
55 (uint8_t)~0xf0, /* 0x02 */
56 (uint8_t)~0xe0, /* 0x03 */
57 (uint8_t)~0xfc, /* 0x04 */
58 (uint8_t)~0x84, /* 0x05 */
59 (uint8_t)~0xf0, /* 0x06 */
60 (uint8_t)~0xf0, /* 0x07 */
61 (uint8_t)~0x00, /* 0x08 */
62 (uint8_t)~0xff, /* 0x09 */
63 (uint8_t)~0xff, /* 0x0a */
64 (uint8_t)~0xff, /* 0x0b */
65 (uint8_t)~0xff, /* 0x0c */
66 (uint8_t)~0xff, /* 0x0d */
67 (uint8_t)~0xff, /* 0x0e */
68 (uint8_t)~0xff, /* 0x0f */
69 };
70
71 #define cbswap_32(__x) \
72 ((uint32_t)( \
73 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
74 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
75 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
76 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
77
78 #ifdef WORDS_BIGENDIAN
79 #define PAT(x) cbswap_32(x)
80 #else
81 #define PAT(x) (x)
82 #endif
83
84 #ifdef WORDS_BIGENDIAN
85 #define BIG 1
86 #else
87 #define BIG 0
88 #endif
89
90 #ifdef WORDS_BIGENDIAN
91 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
92 #else
93 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
94 #endif
95
96 static const uint32_t mask16[16] = {
97 PAT(0x00000000),
98 PAT(0x000000ff),
99 PAT(0x0000ff00),
100 PAT(0x0000ffff),
101 PAT(0x00ff0000),
102 PAT(0x00ff00ff),
103 PAT(0x00ffff00),
104 PAT(0x00ffffff),
105 PAT(0xff000000),
106 PAT(0xff0000ff),
107 PAT(0xff00ff00),
108 PAT(0xff00ffff),
109 PAT(0xffff0000),
110 PAT(0xffff00ff),
111 PAT(0xffffff00),
112 PAT(0xffffffff),
113 };
114
115 #undef PAT
116
117 #ifdef WORDS_BIGENDIAN
118 #define PAT(x) (x)
119 #else
120 #define PAT(x) cbswap_32(x)
121 #endif
122
123 static const uint32_t dmask16[16] = {
124 PAT(0x00000000),
125 PAT(0x000000ff),
126 PAT(0x0000ff00),
127 PAT(0x0000ffff),
128 PAT(0x00ff0000),
129 PAT(0x00ff00ff),
130 PAT(0x00ffff00),
131 PAT(0x00ffffff),
132 PAT(0xff000000),
133 PAT(0xff0000ff),
134 PAT(0xff00ff00),
135 PAT(0xff00ffff),
136 PAT(0xffff0000),
137 PAT(0xffff00ff),
138 PAT(0xffffff00),
139 PAT(0xffffffff),
140 };
141
142 static const uint32_t dmask4[4] = {
143 PAT(0x00000000),
144 PAT(0x0000ffff),
145 PAT(0xffff0000),
146 PAT(0xffffffff),
147 };
148
149 static uint32_t expand4[256];
150 static uint16_t expand2[256];
151 static uint8_t expand4to8[16];
152
153 static void vga_screen_dump(void *opaque, const char *filename);
154
155 static void vga_dumb_update_retrace_info(VGAState *s)
156 {
157 (void) s;
158 }
159
160 static void vga_precise_update_retrace_info(VGAState *s)
161 {
162 int htotal_chars;
163 int hretr_start_char;
164 int hretr_skew_chars;
165 int hretr_end_char;
166
167 int vtotal_lines;
168 int vretr_start_line;
169 int vretr_end_line;
170
171 int div2, sldiv2, dots;
172 int clocking_mode;
173 int clock_sel;
174 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
175 int64_t chars_per_sec;
176 struct vga_precise_retrace *r = &s->retrace_info.precise;
177
178 htotal_chars = s->cr[0x00] + 5;
179 hretr_start_char = s->cr[0x04];
180 hretr_skew_chars = (s->cr[0x05] >> 5) & 3;
181 hretr_end_char = s->cr[0x05] & 0x1f;
182
183 vtotal_lines = (s->cr[0x06]
184 | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2
185 ;
186 vretr_start_line = s->cr[0x10]
187 | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)
188 ;
189 vretr_end_line = s->cr[0x11] & 0xf;
190
191
192 div2 = (s->cr[0x17] >> 2) & 1;
193 sldiv2 = (s->cr[0x17] >> 3) & 1;
194
195 clocking_mode = (s->sr[0x01] >> 3) & 1;
196 clock_sel = (s->msr >> 2) & 3;
197 dots = (s->msr & 1) ? 8 : 9;
198
199 chars_per_sec = clk_hz[clock_sel] / dots;
200
201 htotal_chars <<= clocking_mode;
202
203 r->total_chars = vtotal_lines * htotal_chars;
204 if (r->freq) {
205 r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);
206 } else {
207 r->ticks_per_char = ticks_per_sec / chars_per_sec;
208 }
209
210 r->vstart = vretr_start_line;
211 r->vend = r->vstart + vretr_end_line + 1;
212
213 r->hstart = hretr_start_char + hretr_skew_chars;
214 r->hend = r->hstart + hretr_end_char + 1;
215 r->htotal = htotal_chars;
216
217 #if 0
218 printf (
219 "hz=%f\n"
220 "htotal = %d\n"
221 "hretr_start = %d\n"
222 "hretr_skew = %d\n"
223 "hretr_end = %d\n"
224 "vtotal = %d\n"
225 "vretr_start = %d\n"
226 "vretr_end = %d\n"
227 "div2 = %d sldiv2 = %d\n"
228 "clocking_mode = %d\n"
229 "clock_sel = %d %d\n"
230 "dots = %d\n"
231 "ticks/char = %lld\n"
232 "\n",
233 (double) ticks_per_sec / (r->ticks_per_char * r->total_chars),
234 htotal_chars,
235 hretr_start_char,
236 hretr_skew_chars,
237 hretr_end_char,
238 vtotal_lines,
239 vretr_start_line,
240 vretr_end_line,
241 div2, sldiv2,
242 clocking_mode,
243 clock_sel,
244 clk_hz[clock_sel],
245 dots,
246 r->ticks_per_char
247 );
248 #endif
249 }
250
251 static uint8_t vga_precise_retrace(VGAState *s)
252 {
253 struct vga_precise_retrace *r = &s->retrace_info.precise;
254 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
255
256 if (r->total_chars) {
257 int cur_line, cur_line_char, cur_char;
258 int64_t cur_tick;
259
260 cur_tick = qemu_get_clock(vm_clock);
261
262 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
263 cur_line = cur_char / r->htotal;
264
265 if (cur_line >= r->vstart && cur_line <= r->vend) {
266 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
267 } else {
268 cur_line_char = cur_char % r->htotal;
269 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
270 val |= ST01_DISP_ENABLE;
271 }
272 }
273
274 return val;
275 } else {
276 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
277 }
278 }
279
280 static uint8_t vga_dumb_retrace(VGAState *s)
281 {
282 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
283 }
284
285 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
286 {
287 VGAState *s = opaque;
288 int val, index;
289
290 /* check port range access depending on color/monochrome mode */
291 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
292 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
293 val = 0xff;
294 } else {
295 switch(addr) {
296 case 0x3c0:
297 if (s->ar_flip_flop == 0) {
298 val = s->ar_index;
299 } else {
300 val = 0;
301 }
302 break;
303 case 0x3c1:
304 index = s->ar_index & 0x1f;
305 if (index < 21)
306 val = s->ar[index];
307 else
308 val = 0;
309 break;
310 case 0x3c2:
311 val = s->st00;
312 break;
313 case 0x3c4:
314 val = s->sr_index;
315 break;
316 case 0x3c5:
317 val = s->sr[s->sr_index];
318 #ifdef DEBUG_VGA_REG
319 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
320 #endif
321 break;
322 case 0x3c7:
323 val = s->dac_state;
324 break;
325 case 0x3c8:
326 val = s->dac_write_index;
327 break;
328 case 0x3c9:
329 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
330 if (++s->dac_sub_index == 3) {
331 s->dac_sub_index = 0;
332 s->dac_read_index++;
333 }
334 break;
335 case 0x3ca:
336 val = s->fcr;
337 break;
338 case 0x3cc:
339 val = s->msr;
340 break;
341 case 0x3ce:
342 val = s->gr_index;
343 break;
344 case 0x3cf:
345 val = s->gr[s->gr_index];
346 #ifdef DEBUG_VGA_REG
347 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
348 #endif
349 break;
350 case 0x3b4:
351 case 0x3d4:
352 val = s->cr_index;
353 break;
354 case 0x3b5:
355 case 0x3d5:
356 val = s->cr[s->cr_index];
357 #ifdef DEBUG_VGA_REG
358 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
359 #endif
360 break;
361 case 0x3ba:
362 case 0x3da:
363 /* just toggle to fool polling */
364 val = s->st01 = s->retrace(s);
365 s->ar_flip_flop = 0;
366 break;
367 default:
368 val = 0x00;
369 break;
370 }
371 }
372 #if defined(DEBUG_VGA)
373 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
374 #endif
375 return val;
376 }
377
378 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
379 {
380 VGAState *s = opaque;
381 int index;
382
383 /* check port range access depending on color/monochrome mode */
384 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
385 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
386 return;
387
388 #ifdef DEBUG_VGA
389 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
390 #endif
391
392 switch(addr) {
393 case 0x3c0:
394 if (s->ar_flip_flop == 0) {
395 val &= 0x3f;
396 s->ar_index = val;
397 } else {
398 index = s->ar_index & 0x1f;
399 switch(index) {
400 case 0x00 ... 0x0f:
401 s->ar[index] = val & 0x3f;
402 break;
403 case 0x10:
404 s->ar[index] = val & ~0x10;
405 break;
406 case 0x11:
407 s->ar[index] = val;
408 break;
409 case 0x12:
410 s->ar[index] = val & ~0xc0;
411 break;
412 case 0x13:
413 s->ar[index] = val & ~0xf0;
414 break;
415 case 0x14:
416 s->ar[index] = val & ~0xf0;
417 break;
418 default:
419 break;
420 }
421 }
422 s->ar_flip_flop ^= 1;
423 break;
424 case 0x3c2:
425 s->msr = val & ~0x10;
426 s->update_retrace_info(s);
427 break;
428 case 0x3c4:
429 s->sr_index = val & 7;
430 break;
431 case 0x3c5:
432 #ifdef DEBUG_VGA_REG
433 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
434 #endif
435 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
436 if (s->sr_index == 1) s->update_retrace_info(s);
437 break;
438 case 0x3c7:
439 s->dac_read_index = val;
440 s->dac_sub_index = 0;
441 s->dac_state = 3;
442 break;
443 case 0x3c8:
444 s->dac_write_index = val;
445 s->dac_sub_index = 0;
446 s->dac_state = 0;
447 break;
448 case 0x3c9:
449 s->dac_cache[s->dac_sub_index] = val;
450 if (++s->dac_sub_index == 3) {
451 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
452 s->dac_sub_index = 0;
453 s->dac_write_index++;
454 }
455 break;
456 case 0x3ce:
457 s->gr_index = val & 0x0f;
458 break;
459 case 0x3cf:
460 #ifdef DEBUG_VGA_REG
461 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
462 #endif
463 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
464 break;
465 case 0x3b4:
466 case 0x3d4:
467 s->cr_index = val;
468 break;
469 case 0x3b5:
470 case 0x3d5:
471 #ifdef DEBUG_VGA_REG
472 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
473 #endif
474 /* handle CR0-7 protection */
475 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
476 /* can always write bit 4 of CR7 */
477 if (s->cr_index == 7)
478 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
479 return;
480 }
481 switch(s->cr_index) {
482 case 0x01: /* horizontal display end */
483 case 0x07:
484 case 0x09:
485 case 0x0c:
486 case 0x0d:
487 case 0x12: /* vertical display end */
488 s->cr[s->cr_index] = val;
489 break;
490 default:
491 s->cr[s->cr_index] = val;
492 break;
493 }
494
495 switch(s->cr_index) {
496 case 0x00:
497 case 0x04:
498 case 0x05:
499 case 0x06:
500 case 0x07:
501 case 0x11:
502 case 0x17:
503 s->update_retrace_info(s);
504 break;
505 }
506 break;
507 case 0x3ba:
508 case 0x3da:
509 s->fcr = val & 0x10;
510 break;
511 }
512 }
513
514 #ifdef CONFIG_BOCHS_VBE
515 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
516 {
517 VGAState *s = opaque;
518 uint32_t val;
519 val = s->vbe_index;
520 return val;
521 }
522
523 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
524 {
525 VGAState *s = opaque;
526 uint32_t val;
527
528 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
529 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
530 switch(s->vbe_index) {
531 /* XXX: do not hardcode ? */
532 case VBE_DISPI_INDEX_XRES:
533 val = VBE_DISPI_MAX_XRES;
534 break;
535 case VBE_DISPI_INDEX_YRES:
536 val = VBE_DISPI_MAX_YRES;
537 break;
538 case VBE_DISPI_INDEX_BPP:
539 val = VBE_DISPI_MAX_BPP;
540 break;
541 default:
542 val = s->vbe_regs[s->vbe_index];
543 break;
544 }
545 } else {
546 val = s->vbe_regs[s->vbe_index];
547 }
548 } else {
549 val = 0;
550 }
551 #ifdef DEBUG_BOCHS_VBE
552 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
553 #endif
554 return val;
555 }
556
557 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
558 {
559 VGAState *s = opaque;
560 s->vbe_index = val;
561 }
562
563 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
564 {
565 VGAState *s = opaque;
566
567 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
568 #ifdef DEBUG_BOCHS_VBE
569 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
570 #endif
571 switch(s->vbe_index) {
572 case VBE_DISPI_INDEX_ID:
573 if (val == VBE_DISPI_ID0 ||
574 val == VBE_DISPI_ID1 ||
575 val == VBE_DISPI_ID2 ||
576 val == VBE_DISPI_ID3 ||
577 val == VBE_DISPI_ID4) {
578 s->vbe_regs[s->vbe_index] = val;
579 }
580 break;
581 case VBE_DISPI_INDEX_XRES:
582 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
583 s->vbe_regs[s->vbe_index] = val;
584 }
585 break;
586 case VBE_DISPI_INDEX_YRES:
587 if (val <= VBE_DISPI_MAX_YRES) {
588 s->vbe_regs[s->vbe_index] = val;
589 }
590 break;
591 case VBE_DISPI_INDEX_BPP:
592 if (val == 0)
593 val = 8;
594 if (val == 4 || val == 8 || val == 15 ||
595 val == 16 || val == 24 || val == 32) {
596 s->vbe_regs[s->vbe_index] = val;
597 }
598 break;
599 case VBE_DISPI_INDEX_BANK:
600 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
601 val &= (s->vbe_bank_mask >> 2);
602 } else {
603 val &= s->vbe_bank_mask;
604 }
605 s->vbe_regs[s->vbe_index] = val;
606 s->bank_offset = (val << 16);
607 break;
608 case VBE_DISPI_INDEX_ENABLE:
609 if ((val & VBE_DISPI_ENABLED) &&
610 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
611 int h, shift_control;
612
613 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
614 s->vbe_regs[VBE_DISPI_INDEX_XRES];
615 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
616 s->vbe_regs[VBE_DISPI_INDEX_YRES];
617 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
618 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
619
620 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
621 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
622 else
623 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
624 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
625 s->vbe_start_addr = 0;
626
627 /* clear the screen (should be done in BIOS) */
628 if (!(val & VBE_DISPI_NOCLEARMEM)) {
629 memset(s->vram_ptr, 0,
630 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
631 }
632
633 /* we initialize the VGA graphic mode (should be done
634 in BIOS) */
635 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
636 s->cr[0x17] |= 3; /* no CGA modes */
637 s->cr[0x13] = s->vbe_line_offset >> 3;
638 /* width */
639 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
640 /* height (only meaningful if < 1024) */
641 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
642 s->cr[0x12] = h;
643 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
644 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
645 /* line compare to 1023 */
646 s->cr[0x18] = 0xff;
647 s->cr[0x07] |= 0x10;
648 s->cr[0x09] |= 0x40;
649
650 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
651 shift_control = 0;
652 s->sr[0x01] &= ~8; /* no double line */
653 } else {
654 shift_control = 2;
655 s->sr[4] |= 0x08; /* set chain 4 mode */
656 s->sr[2] |= 0x0f; /* activate all planes */
657 }
658 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
659 s->cr[0x09] &= ~0x9f; /* no double scan */
660 } else {
661 /* XXX: the bios should do that */
662 s->bank_offset = 0;
663 }
664 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
665 s->vbe_regs[s->vbe_index] = val;
666 break;
667 case VBE_DISPI_INDEX_VIRT_WIDTH:
668 {
669 int w, h, line_offset;
670
671 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
672 return;
673 w = val;
674 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
675 line_offset = w >> 1;
676 else
677 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
678 h = s->vram_size / line_offset;
679 /* XXX: support weird bochs semantics ? */
680 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
681 return;
682 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
683 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
684 s->vbe_line_offset = line_offset;
685 }
686 break;
687 case VBE_DISPI_INDEX_X_OFFSET:
688 case VBE_DISPI_INDEX_Y_OFFSET:
689 {
690 int x;
691 s->vbe_regs[s->vbe_index] = val;
692 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
693 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
694 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
695 s->vbe_start_addr += x >> 1;
696 else
697 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
698 s->vbe_start_addr >>= 2;
699 }
700 break;
701 default:
702 break;
703 }
704 }
705 }
706 #endif
707
708 /* called for accesses between 0xa0000 and 0xc0000 */
709 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
710 {
711 VGAState *s = opaque;
712 int memory_map_mode, plane;
713 uint32_t ret;
714
715 /* convert to VGA memory offset */
716 memory_map_mode = (s->gr[6] >> 2) & 3;
717 addr &= 0x1ffff;
718 switch(memory_map_mode) {
719 case 0:
720 break;
721 case 1:
722 if (addr >= 0x10000)
723 return 0xff;
724 addr += s->bank_offset;
725 break;
726 case 2:
727 addr -= 0x10000;
728 if (addr >= 0x8000)
729 return 0xff;
730 break;
731 default:
732 case 3:
733 addr -= 0x18000;
734 if (addr >= 0x8000)
735 return 0xff;
736 break;
737 }
738
739 if (s->sr[4] & 0x08) {
740 /* chain 4 mode : simplest access */
741 ret = s->vram_ptr[addr];
742 } else if (s->gr[5] & 0x10) {
743 /* odd/even mode (aka text mode mapping) */
744 plane = (s->gr[4] & 2) | (addr & 1);
745 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
746 } else {
747 /* standard VGA latched access */
748 s->latch = ((uint32_t *)s->vram_ptr)[addr];
749
750 if (!(s->gr[5] & 0x08)) {
751 /* read mode 0 */
752 plane = s->gr[4];
753 ret = GET_PLANE(s->latch, plane);
754 } else {
755 /* read mode 1 */
756 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
757 ret |= ret >> 16;
758 ret |= ret >> 8;
759 ret = (~ret) & 0xff;
760 }
761 }
762 return ret;
763 }
764
765 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
766 {
767 uint32_t v;
768 #ifdef TARGET_WORDS_BIGENDIAN
769 v = vga_mem_readb(opaque, addr) << 8;
770 v |= vga_mem_readb(opaque, addr + 1);
771 #else
772 v = vga_mem_readb(opaque, addr);
773 v |= vga_mem_readb(opaque, addr + 1) << 8;
774 #endif
775 return v;
776 }
777
778 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
779 {
780 uint32_t v;
781 #ifdef TARGET_WORDS_BIGENDIAN
782 v = vga_mem_readb(opaque, addr) << 24;
783 v |= vga_mem_readb(opaque, addr + 1) << 16;
784 v |= vga_mem_readb(opaque, addr + 2) << 8;
785 v |= vga_mem_readb(opaque, addr + 3);
786 #else
787 v = vga_mem_readb(opaque, addr);
788 v |= vga_mem_readb(opaque, addr + 1) << 8;
789 v |= vga_mem_readb(opaque, addr + 2) << 16;
790 v |= vga_mem_readb(opaque, addr + 3) << 24;
791 #endif
792 return v;
793 }
794
795 /* called for accesses between 0xa0000 and 0xc0000 */
796 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
797 {
798 VGAState *s = opaque;
799 int memory_map_mode, plane, write_mode, b, func_select, mask;
800 uint32_t write_mask, bit_mask, set_mask;
801
802 #ifdef DEBUG_VGA_MEM
803 printf("vga: [0x%x] = 0x%02x\n", addr, val);
804 #endif
805 /* convert to VGA memory offset */
806 memory_map_mode = (s->gr[6] >> 2) & 3;
807 addr &= 0x1ffff;
808 switch(memory_map_mode) {
809 case 0:
810 break;
811 case 1:
812 if (addr >= 0x10000)
813 return;
814 addr += s->bank_offset;
815 break;
816 case 2:
817 addr -= 0x10000;
818 if (addr >= 0x8000)
819 return;
820 break;
821 default:
822 case 3:
823 addr -= 0x18000;
824 if (addr >= 0x8000)
825 return;
826 break;
827 }
828
829 if (s->sr[4] & 0x08) {
830 /* chain 4 mode : simplest access */
831 plane = addr & 3;
832 mask = (1 << plane);
833 if (s->sr[2] & mask) {
834 s->vram_ptr[addr] = val;
835 #ifdef DEBUG_VGA_MEM
836 printf("vga: chain4: [0x%x]\n", addr);
837 #endif
838 s->plane_updated |= mask; /* only used to detect font change */
839 cpu_physical_memory_set_dirty(s->vram_offset + addr);
840 }
841 } else if (s->gr[5] & 0x10) {
842 /* odd/even mode (aka text mode mapping) */
843 plane = (s->gr[4] & 2) | (addr & 1);
844 mask = (1 << plane);
845 if (s->sr[2] & mask) {
846 addr = ((addr & ~1) << 1) | plane;
847 s->vram_ptr[addr] = val;
848 #ifdef DEBUG_VGA_MEM
849 printf("vga: odd/even: [0x%x]\n", addr);
850 #endif
851 s->plane_updated |= mask; /* only used to detect font change */
852 cpu_physical_memory_set_dirty(s->vram_offset + addr);
853 }
854 } else {
855 /* standard VGA latched access */
856 write_mode = s->gr[5] & 3;
857 switch(write_mode) {
858 default:
859 case 0:
860 /* rotate */
861 b = s->gr[3] & 7;
862 val = ((val >> b) | (val << (8 - b))) & 0xff;
863 val |= val << 8;
864 val |= val << 16;
865
866 /* apply set/reset mask */
867 set_mask = mask16[s->gr[1]];
868 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
869 bit_mask = s->gr[8];
870 break;
871 case 1:
872 val = s->latch;
873 goto do_write;
874 case 2:
875 val = mask16[val & 0x0f];
876 bit_mask = s->gr[8];
877 break;
878 case 3:
879 /* rotate */
880 b = s->gr[3] & 7;
881 val = (val >> b) | (val << (8 - b));
882
883 bit_mask = s->gr[8] & val;
884 val = mask16[s->gr[0]];
885 break;
886 }
887
888 /* apply logical operation */
889 func_select = s->gr[3] >> 3;
890 switch(func_select) {
891 case 0:
892 default:
893 /* nothing to do */
894 break;
895 case 1:
896 /* and */
897 val &= s->latch;
898 break;
899 case 2:
900 /* or */
901 val |= s->latch;
902 break;
903 case 3:
904 /* xor */
905 val ^= s->latch;
906 break;
907 }
908
909 /* apply bit mask */
910 bit_mask |= bit_mask << 8;
911 bit_mask |= bit_mask << 16;
912 val = (val & bit_mask) | (s->latch & ~bit_mask);
913
914 do_write:
915 /* mask data according to sr[2] */
916 mask = s->sr[2];
917 s->plane_updated |= mask; /* only used to detect font change */
918 write_mask = mask16[mask];
919 ((uint32_t *)s->vram_ptr)[addr] =
920 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
921 (val & write_mask);
922 #ifdef DEBUG_VGA_MEM
923 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
924 addr * 4, write_mask, val);
925 #endif
926 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
927 }
928 }
929
930 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
931 {
932 #ifdef TARGET_WORDS_BIGENDIAN
933 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
934 vga_mem_writeb(opaque, addr + 1, val & 0xff);
935 #else
936 vga_mem_writeb(opaque, addr, val & 0xff);
937 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
938 #endif
939 }
940
941 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
942 {
943 #ifdef TARGET_WORDS_BIGENDIAN
944 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
945 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
946 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
947 vga_mem_writeb(opaque, addr + 3, val & 0xff);
948 #else
949 vga_mem_writeb(opaque, addr, val & 0xff);
950 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
951 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
952 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
953 #endif
954 }
955
956 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
957 const uint8_t *font_ptr, int h,
958 uint32_t fgcol, uint32_t bgcol);
959 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
960 const uint8_t *font_ptr, int h,
961 uint32_t fgcol, uint32_t bgcol, int dup9);
962 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
963 const uint8_t *s, int width);
964
965 #define DEPTH 8
966 #include "vga_template.h"
967
968 #define DEPTH 15
969 #include "vga_template.h"
970
971 #define BGR_FORMAT
972 #define DEPTH 15
973 #include "vga_template.h"
974
975 #define DEPTH 16
976 #include "vga_template.h"
977
978 #define BGR_FORMAT
979 #define DEPTH 16
980 #include "vga_template.h"
981
982 #define DEPTH 32
983 #include "vga_template.h"
984
985 #define BGR_FORMAT
986 #define DEPTH 32
987 #include "vga_template.h"
988
989 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
990 {
991 unsigned int col;
992 col = rgb_to_pixel8(r, g, b);
993 col |= col << 8;
994 col |= col << 16;
995 return col;
996 }
997
998 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
999 {
1000 unsigned int col;
1001 col = rgb_to_pixel15(r, g, b);
1002 col |= col << 16;
1003 return col;
1004 }
1005
1006 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1007 unsigned int b)
1008 {
1009 unsigned int col;
1010 col = rgb_to_pixel15bgr(r, g, b);
1011 col |= col << 16;
1012 return col;
1013 }
1014
1015 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1016 {
1017 unsigned int col;
1018 col = rgb_to_pixel16(r, g, b);
1019 col |= col << 16;
1020 return col;
1021 }
1022
1023 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1024 unsigned int b)
1025 {
1026 unsigned int col;
1027 col = rgb_to_pixel16bgr(r, g, b);
1028 col |= col << 16;
1029 return col;
1030 }
1031
1032 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1033 {
1034 unsigned int col;
1035 col = rgb_to_pixel32(r, g, b);
1036 return col;
1037 }
1038
1039 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1040 {
1041 unsigned int col;
1042 col = rgb_to_pixel32bgr(r, g, b);
1043 return col;
1044 }
1045
1046 /* return true if the palette was modified */
1047 static int update_palette16(VGAState *s)
1048 {
1049 int full_update, i;
1050 uint32_t v, col, *palette;
1051
1052 full_update = 0;
1053 palette = s->last_palette;
1054 for(i = 0; i < 16; i++) {
1055 v = s->ar[i];
1056 if (s->ar[0x10] & 0x80)
1057 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1058 else
1059 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1060 v = v * 3;
1061 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1062 c6_to_8(s->palette[v + 1]),
1063 c6_to_8(s->palette[v + 2]));
1064 if (col != palette[i]) {
1065 full_update = 1;
1066 palette[i] = col;
1067 }
1068 }
1069 return full_update;
1070 }
1071
1072 /* return true if the palette was modified */
1073 static int update_palette256(VGAState *s)
1074 {
1075 int full_update, i;
1076 uint32_t v, col, *palette;
1077
1078 full_update = 0;
1079 palette = s->last_palette;
1080 v = 0;
1081 for(i = 0; i < 256; i++) {
1082 if (s->dac_8bit) {
1083 col = s->rgb_to_pixel(s->palette[v],
1084 s->palette[v + 1],
1085 s->palette[v + 2]);
1086 } else {
1087 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1088 c6_to_8(s->palette[v + 1]),
1089 c6_to_8(s->palette[v + 2]));
1090 }
1091 if (col != palette[i]) {
1092 full_update = 1;
1093 palette[i] = col;
1094 }
1095 v += 3;
1096 }
1097 return full_update;
1098 }
1099
1100 static void vga_get_offsets(VGAState *s,
1101 uint32_t *pline_offset,
1102 uint32_t *pstart_addr,
1103 uint32_t *pline_compare)
1104 {
1105 uint32_t start_addr, line_offset, line_compare;
1106 #ifdef CONFIG_BOCHS_VBE
1107 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1108 line_offset = s->vbe_line_offset;
1109 start_addr = s->vbe_start_addr;
1110 line_compare = 65535;
1111 } else
1112 #endif
1113 {
1114 /* compute line_offset in bytes */
1115 line_offset = s->cr[0x13];
1116 line_offset <<= 3;
1117
1118 /* starting address */
1119 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1120
1121 /* line compare */
1122 line_compare = s->cr[0x18] |
1123 ((s->cr[0x07] & 0x10) << 4) |
1124 ((s->cr[0x09] & 0x40) << 3);
1125 }
1126 *pline_offset = line_offset;
1127 *pstart_addr = start_addr;
1128 *pline_compare = line_compare;
1129 }
1130
1131 /* update start_addr and line_offset. Return TRUE if modified */
1132 static int update_basic_params(VGAState *s)
1133 {
1134 int full_update;
1135 uint32_t start_addr, line_offset, line_compare;
1136
1137 full_update = 0;
1138
1139 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1140
1141 if (line_offset != s->line_offset ||
1142 start_addr != s->start_addr ||
1143 line_compare != s->line_compare) {
1144 s->line_offset = line_offset;
1145 s->start_addr = start_addr;
1146 s->line_compare = line_compare;
1147 full_update = 1;
1148 }
1149 return full_update;
1150 }
1151
1152 #define NB_DEPTHS 7
1153
1154 static inline int get_depth_index(DisplayState *s)
1155 {
1156 switch(ds_get_bits_per_pixel(s)) {
1157 default:
1158 case 8:
1159 return 0;
1160 case 15:
1161 return 1;
1162 case 16:
1163 return 2;
1164 case 32:
1165 return 3;
1166 }
1167 }
1168
1169 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
1170 vga_draw_glyph8_8,
1171 vga_draw_glyph8_16,
1172 vga_draw_glyph8_16,
1173 vga_draw_glyph8_32,
1174 vga_draw_glyph8_32,
1175 vga_draw_glyph8_16,
1176 vga_draw_glyph8_16,
1177 };
1178
1179 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1180 vga_draw_glyph16_8,
1181 vga_draw_glyph16_16,
1182 vga_draw_glyph16_16,
1183 vga_draw_glyph16_32,
1184 vga_draw_glyph16_32,
1185 vga_draw_glyph16_16,
1186 vga_draw_glyph16_16,
1187 };
1188
1189 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1190 vga_draw_glyph9_8,
1191 vga_draw_glyph9_16,
1192 vga_draw_glyph9_16,
1193 vga_draw_glyph9_32,
1194 vga_draw_glyph9_32,
1195 vga_draw_glyph9_16,
1196 vga_draw_glyph9_16,
1197 };
1198
1199 static const uint8_t cursor_glyph[32 * 4] = {
1200 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1201 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1202 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1203 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1204 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1205 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1206 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1207 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1208 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1209 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1212 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1213 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1214 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1215 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1216 };
1217
1218 static void vga_get_text_resolution(VGAState *s, int *pwidth, int *pheight,
1219 int *pcwidth, int *pcheight)
1220 {
1221 int width, cwidth, height, cheight;
1222
1223 /* total width & height */
1224 cheight = (s->cr[9] & 0x1f) + 1;
1225 cwidth = 8;
1226 if (!(s->sr[1] & 0x01))
1227 cwidth = 9;
1228 if (s->sr[1] & 0x08)
1229 cwidth = 16; /* NOTE: no 18 pixel wide */
1230 width = (s->cr[0x01] + 1);
1231 if (s->cr[0x06] == 100) {
1232 /* ugly hack for CGA 160x100x16 - explain me the logic */
1233 height = 100;
1234 } else {
1235 height = s->cr[0x12] |
1236 ((s->cr[0x07] & 0x02) << 7) |
1237 ((s->cr[0x07] & 0x40) << 3);
1238 height = (height + 1) / cheight;
1239 }
1240
1241 *pwidth = width;
1242 *pheight = height;
1243 *pcwidth = cwidth;
1244 *pcheight = cheight;
1245 }
1246
1247 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1248
1249 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1250 rgb_to_pixel8_dup,
1251 rgb_to_pixel15_dup,
1252 rgb_to_pixel16_dup,
1253 rgb_to_pixel32_dup,
1254 rgb_to_pixel32bgr_dup,
1255 rgb_to_pixel15bgr_dup,
1256 rgb_to_pixel16bgr_dup,
1257 };
1258
1259 /*
1260 * Text mode update
1261 * Missing:
1262 * - double scan
1263 * - double width
1264 * - underline
1265 * - flashing
1266 */
1267 static void vga_draw_text(VGAState *s, int full_update)
1268 {
1269 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1270 int cx_min, cx_max, linesize, x_incr;
1271 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1272 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1273 const uint8_t *font_ptr, *font_base[2];
1274 int dup9, line_offset, depth_index;
1275 uint32_t *palette;
1276 uint32_t *ch_attr_ptr;
1277 vga_draw_glyph8_func *vga_draw_glyph8;
1278 vga_draw_glyph9_func *vga_draw_glyph9;
1279
1280 vga_dirty_log_stop(s);
1281
1282 /* compute font data address (in plane 2) */
1283 v = s->sr[3];
1284 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1285 if (offset != s->font_offsets[0]) {
1286 s->font_offsets[0] = offset;
1287 full_update = 1;
1288 }
1289 font_base[0] = s->vram_ptr + offset;
1290
1291 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1292 font_base[1] = s->vram_ptr + offset;
1293 if (offset != s->font_offsets[1]) {
1294 s->font_offsets[1] = offset;
1295 full_update = 1;
1296 }
1297 if (s->plane_updated & (1 << 2)) {
1298 /* if the plane 2 was modified since the last display, it
1299 indicates the font may have been modified */
1300 s->plane_updated = 0;
1301 full_update = 1;
1302 }
1303 full_update |= update_basic_params(s);
1304
1305 line_offset = s->line_offset;
1306 s1 = s->vram_ptr + (s->start_addr * 4);
1307
1308 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1309 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1310 if ((height * width) > CH_ATTR_SIZE) {
1311 /* better than nothing: exit if transient size is too big */
1312 return;
1313 }
1314
1315 if (width != s->last_width || height != s->last_height ||
1316 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1317 s->last_scr_width = width * cw;
1318 s->last_scr_height = height * cheight;
1319 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1320 s->last_depth = 0;
1321 s->last_width = width;
1322 s->last_height = height;
1323 s->last_ch = cheight;
1324 s->last_cw = cw;
1325 full_update = 1;
1326 }
1327 s->rgb_to_pixel =
1328 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1329 full_update |= update_palette16(s);
1330 palette = s->last_palette;
1331 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1332
1333 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1334 if (cursor_offset != s->cursor_offset ||
1335 s->cr[0xa] != s->cursor_start ||
1336 s->cr[0xb] != s->cursor_end) {
1337 /* if the cursor position changed, we update the old and new
1338 chars */
1339 if (s->cursor_offset < CH_ATTR_SIZE)
1340 s->last_ch_attr[s->cursor_offset] = -1;
1341 if (cursor_offset < CH_ATTR_SIZE)
1342 s->last_ch_attr[cursor_offset] = -1;
1343 s->cursor_offset = cursor_offset;
1344 s->cursor_start = s->cr[0xa];
1345 s->cursor_end = s->cr[0xb];
1346 }
1347 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1348
1349 depth_index = get_depth_index(s->ds);
1350 if (cw == 16)
1351 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1352 else
1353 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1354 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1355
1356 dest = ds_get_data(s->ds);
1357 linesize = ds_get_linesize(s->ds);
1358 ch_attr_ptr = s->last_ch_attr;
1359 for(cy = 0; cy < height; cy++) {
1360 d1 = dest;
1361 src = s1;
1362 cx_min = width;
1363 cx_max = -1;
1364 for(cx = 0; cx < width; cx++) {
1365 ch_attr = *(uint16_t *)src;
1366 if (full_update || ch_attr != *ch_attr_ptr) {
1367 if (cx < cx_min)
1368 cx_min = cx;
1369 if (cx > cx_max)
1370 cx_max = cx;
1371 *ch_attr_ptr = ch_attr;
1372 #ifdef WORDS_BIGENDIAN
1373 ch = ch_attr >> 8;
1374 cattr = ch_attr & 0xff;
1375 #else
1376 ch = ch_attr & 0xff;
1377 cattr = ch_attr >> 8;
1378 #endif
1379 font_ptr = font_base[(cattr >> 3) & 1];
1380 font_ptr += 32 * 4 * ch;
1381 bgcol = palette[cattr >> 4];
1382 fgcol = palette[cattr & 0x0f];
1383 if (cw != 9) {
1384 vga_draw_glyph8(d1, linesize,
1385 font_ptr, cheight, fgcol, bgcol);
1386 } else {
1387 dup9 = 0;
1388 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1389 dup9 = 1;
1390 vga_draw_glyph9(d1, linesize,
1391 font_ptr, cheight, fgcol, bgcol, dup9);
1392 }
1393 if (src == cursor_ptr &&
1394 !(s->cr[0x0a] & 0x20)) {
1395 int line_start, line_last, h;
1396 /* draw the cursor */
1397 line_start = s->cr[0x0a] & 0x1f;
1398 line_last = s->cr[0x0b] & 0x1f;
1399 /* XXX: check that */
1400 if (line_last > cheight - 1)
1401 line_last = cheight - 1;
1402 if (line_last >= line_start && line_start < cheight) {
1403 h = line_last - line_start + 1;
1404 d = d1 + linesize * line_start;
1405 if (cw != 9) {
1406 vga_draw_glyph8(d, linesize,
1407 cursor_glyph, h, fgcol, bgcol);
1408 } else {
1409 vga_draw_glyph9(d, linesize,
1410 cursor_glyph, h, fgcol, bgcol, 1);
1411 }
1412 }
1413 }
1414 }
1415 d1 += x_incr;
1416 src += 4;
1417 ch_attr_ptr++;
1418 }
1419 if (cx_max != -1) {
1420 dpy_update(s->ds, cx_min * cw, cy * cheight,
1421 (cx_max - cx_min + 1) * cw, cheight);
1422 }
1423 dest += linesize * cheight;
1424 s1 += line_offset;
1425 }
1426 }
1427
1428 enum {
1429 VGA_DRAW_LINE2,
1430 VGA_DRAW_LINE2D2,
1431 VGA_DRAW_LINE4,
1432 VGA_DRAW_LINE4D2,
1433 VGA_DRAW_LINE8D2,
1434 VGA_DRAW_LINE8,
1435 VGA_DRAW_LINE15,
1436 VGA_DRAW_LINE16,
1437 VGA_DRAW_LINE24,
1438 VGA_DRAW_LINE32,
1439 VGA_DRAW_LINE_NB,
1440 };
1441
1442 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1443 vga_draw_line2_8,
1444 vga_draw_line2_16,
1445 vga_draw_line2_16,
1446 vga_draw_line2_32,
1447 vga_draw_line2_32,
1448 vga_draw_line2_16,
1449 vga_draw_line2_16,
1450
1451 vga_draw_line2d2_8,
1452 vga_draw_line2d2_16,
1453 vga_draw_line2d2_16,
1454 vga_draw_line2d2_32,
1455 vga_draw_line2d2_32,
1456 vga_draw_line2d2_16,
1457 vga_draw_line2d2_16,
1458
1459 vga_draw_line4_8,
1460 vga_draw_line4_16,
1461 vga_draw_line4_16,
1462 vga_draw_line4_32,
1463 vga_draw_line4_32,
1464 vga_draw_line4_16,
1465 vga_draw_line4_16,
1466
1467 vga_draw_line4d2_8,
1468 vga_draw_line4d2_16,
1469 vga_draw_line4d2_16,
1470 vga_draw_line4d2_32,
1471 vga_draw_line4d2_32,
1472 vga_draw_line4d2_16,
1473 vga_draw_line4d2_16,
1474
1475 vga_draw_line8d2_8,
1476 vga_draw_line8d2_16,
1477 vga_draw_line8d2_16,
1478 vga_draw_line8d2_32,
1479 vga_draw_line8d2_32,
1480 vga_draw_line8d2_16,
1481 vga_draw_line8d2_16,
1482
1483 vga_draw_line8_8,
1484 vga_draw_line8_16,
1485 vga_draw_line8_16,
1486 vga_draw_line8_32,
1487 vga_draw_line8_32,
1488 vga_draw_line8_16,
1489 vga_draw_line8_16,
1490
1491 vga_draw_line15_8,
1492 vga_draw_line15_15,
1493 vga_draw_line15_16,
1494 vga_draw_line15_32,
1495 vga_draw_line15_32bgr,
1496 vga_draw_line15_15bgr,
1497 vga_draw_line15_16bgr,
1498
1499 vga_draw_line16_8,
1500 vga_draw_line16_15,
1501 vga_draw_line16_16,
1502 vga_draw_line16_32,
1503 vga_draw_line16_32bgr,
1504 vga_draw_line16_15bgr,
1505 vga_draw_line16_16bgr,
1506
1507 vga_draw_line24_8,
1508 vga_draw_line24_15,
1509 vga_draw_line24_16,
1510 vga_draw_line24_32,
1511 vga_draw_line24_32bgr,
1512 vga_draw_line24_15bgr,
1513 vga_draw_line24_16bgr,
1514
1515 vga_draw_line32_8,
1516 vga_draw_line32_15,
1517 vga_draw_line32_16,
1518 vga_draw_line32_32,
1519 vga_draw_line32_32bgr,
1520 vga_draw_line32_15bgr,
1521 vga_draw_line32_16bgr,
1522 };
1523
1524 static int vga_get_bpp(VGAState *s)
1525 {
1526 int ret;
1527 #ifdef CONFIG_BOCHS_VBE
1528 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1529 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1530 } else
1531 #endif
1532 {
1533 ret = 0;
1534 }
1535 return ret;
1536 }
1537
1538 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1539 {
1540 int width, height;
1541
1542 #ifdef CONFIG_BOCHS_VBE
1543 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1544 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1545 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1546 } else
1547 #endif
1548 {
1549 width = (s->cr[0x01] + 1) * 8;
1550 height = s->cr[0x12] |
1551 ((s->cr[0x07] & 0x02) << 7) |
1552 ((s->cr[0x07] & 0x40) << 3);
1553 height = (height + 1);
1554 }
1555 *pwidth = width;
1556 *pheight = height;
1557 }
1558
1559 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1560 {
1561 int y;
1562 if (y1 >= VGA_MAX_HEIGHT)
1563 return;
1564 if (y2 >= VGA_MAX_HEIGHT)
1565 y2 = VGA_MAX_HEIGHT;
1566 for(y = y1; y < y2; y++) {
1567 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1568 }
1569 }
1570
1571 static void vga_sync_dirty_bitmap(VGAState *s)
1572 {
1573 if (s->map_addr)
1574 cpu_physical_sync_dirty_bitmap(s->map_addr, s->map_end);
1575
1576 if (s->lfb_vram_mapped) {
1577 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa0000, 0xa8000);
1578 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa8000, 0xb0000);
1579 }
1580 vga_dirty_log_start(s);
1581 }
1582
1583 /*
1584 * graphic modes
1585 */
1586 static void vga_draw_graphic(VGAState *s, int full_update)
1587 {
1588 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1589 int width, height, shift_control, line_offset, bwidth, bits;
1590 int disp_width, multi_scan, multi_run;
1591 uint8_t *d;
1592 uint32_t v, addr1, addr;
1593 long page0, page1, page_min, page_max;
1594 vga_draw_line_func *vga_draw_line;
1595
1596 full_update |= update_basic_params(s);
1597
1598 if (!full_update)
1599 vga_sync_dirty_bitmap(s);
1600
1601 s->get_resolution(s, &width, &height);
1602 disp_width = width;
1603
1604 shift_control = (s->gr[0x05] >> 5) & 3;
1605 double_scan = (s->cr[0x09] >> 7);
1606 if (shift_control != 1) {
1607 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1608 } else {
1609 /* in CGA modes, multi_scan is ignored */
1610 /* XXX: is it correct ? */
1611 multi_scan = double_scan;
1612 }
1613 multi_run = multi_scan;
1614 if (shift_control != s->shift_control ||
1615 double_scan != s->double_scan) {
1616 full_update = 1;
1617 s->shift_control = shift_control;
1618 s->double_scan = double_scan;
1619 }
1620
1621 depth = s->get_bpp(s);
1622 if (s->line_offset != s->last_line_offset ||
1623 disp_width != s->last_width ||
1624 height != s->last_height ||
1625 s->last_depth != depth) {
1626 #if defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1627 if (depth == 16 || depth == 32) {
1628 #else
1629 if (depth == 32) {
1630 #endif
1631 if (is_graphic_console()) {
1632 qemu_free_displaysurface(s->ds->surface);
1633 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1634 s->line_offset,
1635 s->vram_ptr + (s->start_addr * 4));
1636 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1637 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
1638 #endif
1639 dpy_resize(s->ds);
1640 } else {
1641 qemu_console_resize(s->ds, disp_width, height);
1642 }
1643 } else {
1644 qemu_console_resize(s->ds, disp_width, height);
1645 }
1646 s->last_scr_width = disp_width;
1647 s->last_scr_height = height;
1648 s->last_width = disp_width;
1649 s->last_height = height;
1650 s->last_line_offset = s->line_offset;
1651 s->last_depth = depth;
1652 full_update = 1;
1653 } else if (is_graphic_console() && is_buffer_shared(s->ds->surface) &&
1654 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1655 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1656 dpy_setdata(s->ds);
1657 }
1658
1659 s->rgb_to_pixel =
1660 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1661
1662 if (shift_control == 0) {
1663 full_update |= update_palette16(s);
1664 if (s->sr[0x01] & 8) {
1665 v = VGA_DRAW_LINE4D2;
1666 disp_width <<= 1;
1667 } else {
1668 v = VGA_DRAW_LINE4;
1669 }
1670 bits = 4;
1671 } else if (shift_control == 1) {
1672 full_update |= update_palette16(s);
1673 if (s->sr[0x01] & 8) {
1674 v = VGA_DRAW_LINE2D2;
1675 disp_width <<= 1;
1676 } else {
1677 v = VGA_DRAW_LINE2;
1678 }
1679 bits = 4;
1680 } else {
1681 switch(s->get_bpp(s)) {
1682 default:
1683 case 0:
1684 full_update |= update_palette256(s);
1685 v = VGA_DRAW_LINE8D2;
1686 bits = 4;
1687 break;
1688 case 8:
1689 full_update |= update_palette256(s);
1690 v = VGA_DRAW_LINE8;
1691 bits = 8;
1692 break;
1693 case 15:
1694 v = VGA_DRAW_LINE15;
1695 bits = 16;
1696 break;
1697 case 16:
1698 v = VGA_DRAW_LINE16;
1699 bits = 16;
1700 break;
1701 case 24:
1702 v = VGA_DRAW_LINE24;
1703 bits = 24;
1704 break;
1705 case 32:
1706 v = VGA_DRAW_LINE32;
1707 bits = 32;
1708 break;
1709 }
1710 }
1711 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1712
1713 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
1714 s->cursor_invalidate(s);
1715
1716 line_offset = s->line_offset;
1717 #if 0
1718 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1719 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1720 #endif
1721 addr1 = (s->start_addr * 4);
1722 bwidth = (width * bits + 7) / 8;
1723 y_start = -1;
1724 page_min = 0x7fffffff;
1725 page_max = -1;
1726 d = ds_get_data(s->ds);
1727 linesize = ds_get_linesize(s->ds);
1728 y1 = 0;
1729 for(y = 0; y < height; y++) {
1730 addr = addr1;
1731 if (!(s->cr[0x17] & 1)) {
1732 int shift;
1733 /* CGA compatibility handling */
1734 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1735 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1736 }
1737 if (!(s->cr[0x17] & 2)) {
1738 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1739 }
1740 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1741 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1742 update = full_update |
1743 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1744 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1745 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1746 /* if wide line, can use another page */
1747 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1748 VGA_DIRTY_FLAG);
1749 }
1750 /* explicit invalidation for the hardware cursor */
1751 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1752 if (update) {
1753 if (y_start < 0)
1754 y_start = y;
1755 if (page0 < page_min)
1756 page_min = page0;
1757 if (page1 > page_max)
1758 page_max = page1;
1759 if (!(is_buffer_shared(s->ds->surface))) {
1760 vga_draw_line(s, d, s->vram_ptr + addr, width);
1761 if (s->cursor_draw_line)
1762 s->cursor_draw_line(s, d, y);
1763 }
1764 } else {
1765 if (y_start >= 0) {
1766 /* flush to display */
1767 dpy_update(s->ds, 0, y_start,
1768 disp_width, y - y_start);
1769 y_start = -1;
1770 }
1771 }
1772 if (!multi_run) {
1773 mask = (s->cr[0x17] & 3) ^ 3;
1774 if ((y1 & mask) == mask)
1775 addr1 += line_offset;
1776 y1++;
1777 multi_run = multi_scan;
1778 } else {
1779 multi_run--;
1780 }
1781 /* line compare acts on the displayed lines */
1782 if (y == s->line_compare)
1783 addr1 = 0;
1784 d += linesize;
1785 }
1786 if (y_start >= 0) {
1787 /* flush to display */
1788 dpy_update(s->ds, 0, y_start,
1789 disp_width, y - y_start);
1790 }
1791 /* reset modified pages */
1792 if (page_max != -1) {
1793 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1794 VGA_DIRTY_FLAG);
1795 }
1796 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1797 }
1798
1799 static void vga_draw_blank(VGAState *s, int full_update)
1800 {
1801 int i, w, val;
1802 uint8_t *d;
1803
1804 if (!full_update)
1805 return;
1806 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1807 return;
1808 vga_dirty_log_stop(s);
1809
1810 s->rgb_to_pixel =
1811 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1812 if (ds_get_bits_per_pixel(s->ds) == 8)
1813 val = s->rgb_to_pixel(0, 0, 0);
1814 else
1815 val = 0;
1816 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1817 d = ds_get_data(s->ds);
1818 for(i = 0; i < s->last_scr_height; i++) {
1819 memset(d, val, w);
1820 d += ds_get_linesize(s->ds);
1821 }
1822 dpy_update(s->ds, 0, 0,
1823 s->last_scr_width, s->last_scr_height);
1824 }
1825
1826 #define GMODE_TEXT 0
1827 #define GMODE_GRAPH 1
1828 #define GMODE_BLANK 2
1829
1830 static void vga_update_display(void *opaque)
1831 {
1832 VGAState *s = (VGAState *)opaque;
1833 int full_update, graphic_mode;
1834
1835 if (ds_get_bits_per_pixel(s->ds) == 0) {
1836 /* nothing to do */
1837 } else {
1838 full_update = 0;
1839 if (!(s->ar_index & 0x20)) {
1840 graphic_mode = GMODE_BLANK;
1841 } else {
1842 graphic_mode = s->gr[6] & 1;
1843 }
1844 if (graphic_mode != s->graphic_mode) {
1845 s->graphic_mode = graphic_mode;
1846 full_update = 1;
1847 }
1848 switch(graphic_mode) {
1849 case GMODE_TEXT:
1850 vga_draw_text(s, full_update);
1851 break;
1852 case GMODE_GRAPH:
1853 #ifdef TARGET_IA64
1854 full_update = 1;
1855 #endif
1856 vga_draw_graphic(s, full_update);
1857 break;
1858 case GMODE_BLANK:
1859 default:
1860 vga_draw_blank(s, full_update);
1861 break;
1862 }
1863 }
1864 }
1865
1866 /* force a full display refresh */
1867 static void vga_invalidate_display(void *opaque)
1868 {
1869 VGAState *s = (VGAState *)opaque;
1870
1871 s->last_width = -1;
1872 s->last_height = -1;
1873 }
1874
1875 void vga_reset(void *opaque)
1876 {
1877 VGAState *s = (VGAState *) opaque;
1878
1879 s->lfb_addr = 0;
1880 s->lfb_end = 0;
1881 s->map_addr = 0;
1882 s->map_end = 0;
1883 s->lfb_vram_mapped = 0;
1884 s->bios_offset = 0;
1885 s->bios_size = 0;
1886 s->sr_index = 0;
1887 memset(s->sr, '\0', sizeof(s->sr));
1888 s->gr_index = 0;
1889 memset(s->gr, '\0', sizeof(s->gr));
1890 s->ar_index = 0;
1891 memset(s->ar, '\0', sizeof(s->ar));
1892 s->ar_flip_flop = 0;
1893 s->cr_index = 0;
1894 memset(s->cr, '\0', sizeof(s->cr));
1895 s->msr = 0;
1896 s->fcr = 0;
1897 s->st00 = 0;
1898 s->st01 = 0;
1899 s->dac_state = 0;
1900 s->dac_sub_index = 0;
1901 s->dac_read_index = 0;
1902 s->dac_write_index = 0;
1903 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1904 s->dac_8bit = 0;
1905 memset(s->palette, '\0', sizeof(s->palette));
1906 s->bank_offset = 0;
1907 #ifdef CONFIG_BOCHS_VBE
1908 s->vbe_index = 0;
1909 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1910 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
1911 s->vbe_start_addr = 0;
1912 s->vbe_line_offset = 0;
1913 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1914 #endif
1915 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1916 s->graphic_mode = -1; /* force full update */
1917 s->shift_control = 0;
1918 s->double_scan = 0;
1919 s->line_offset = 0;
1920 s->line_compare = 0;
1921 s->start_addr = 0;
1922 s->plane_updated = 0;
1923 s->last_cw = 0;
1924 s->last_ch = 0;
1925 s->last_width = 0;
1926 s->last_height = 0;
1927 s->last_scr_width = 0;
1928 s->last_scr_height = 0;
1929 s->cursor_start = 0;
1930 s->cursor_end = 0;
1931 s->cursor_offset = 0;
1932 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1933 memset(s->last_palette, '\0', sizeof(s->last_palette));
1934 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1935 switch (vga_retrace_method) {
1936 case VGA_RETRACE_DUMB:
1937 break;
1938 case VGA_RETRACE_PRECISE:
1939 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1940 break;
1941 }
1942 }
1943
1944 #define TEXTMODE_X(x) ((x) % width)
1945 #define TEXTMODE_Y(x) ((x) / width)
1946 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1947 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1948 /* relay text rendering to the display driver
1949 * instead of doing a full vga_update_display() */
1950 static void vga_update_text(void *opaque, console_ch_t *chardata)
1951 {
1952 VGAState *s = (VGAState *) opaque;
1953 int graphic_mode, i, cursor_offset, cursor_visible;
1954 int cw, cheight, width, height, size, c_min, c_max;
1955 uint32_t *src;
1956 console_ch_t *dst, val;
1957 char msg_buffer[80];
1958 int full_update = 0;
1959
1960 if (!(s->ar_index & 0x20)) {
1961 graphic_mode = GMODE_BLANK;
1962 } else {
1963 graphic_mode = s->gr[6] & 1;
1964 }
1965 if (graphic_mode != s->graphic_mode) {
1966 s->graphic_mode = graphic_mode;
1967 full_update = 1;
1968 }
1969 if (s->last_width == -1) {
1970 s->last_width = 0;
1971 full_update = 1;
1972 }
1973
1974 switch (graphic_mode) {
1975 case GMODE_TEXT:
1976 /* TODO: update palette */
1977 full_update |= update_basic_params(s);
1978
1979 /* total width & height */
1980 cheight = (s->cr[9] & 0x1f) + 1;
1981 cw = 8;
1982 if (!(s->sr[1] & 0x01))
1983 cw = 9;
1984 if (s->sr[1] & 0x08)
1985 cw = 16; /* NOTE: no 18 pixel wide */
1986 width = (s->cr[0x01] + 1);
1987 if (s->cr[0x06] == 100) {
1988 /* ugly hack for CGA 160x100x16 - explain me the logic */
1989 height = 100;
1990 } else {
1991 height = s->cr[0x12] |
1992 ((s->cr[0x07] & 0x02) << 7) |
1993 ((s->cr[0x07] & 0x40) << 3);
1994 height = (height + 1) / cheight;
1995 }
1996
1997 size = (height * width);
1998 if (size > CH_ATTR_SIZE) {
1999 if (!full_update)
2000 return;
2001
2002 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2003 width, height);
2004 break;
2005 }
2006
2007 if (width != s->last_width || height != s->last_height ||
2008 cw != s->last_cw || cheight != s->last_ch) {
2009 s->last_scr_width = width * cw;
2010 s->last_scr_height = height * cheight;
2011 s->ds->surface->width = width;
2012 s->ds->surface->height = height;
2013 dpy_resize(s->ds);
2014 s->last_width = width;
2015 s->last_height = height;
2016 s->last_ch = cheight;
2017 s->last_cw = cw;
2018 full_update = 1;
2019 }
2020
2021 /* Update "hardware" cursor */
2022 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
2023 if (cursor_offset != s->cursor_offset ||
2024 s->cr[0xa] != s->cursor_start ||
2025 s->cr[0xb] != s->cursor_end || full_update) {
2026 cursor_visible = !(s->cr[0xa] & 0x20);
2027 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2028 dpy_cursor(s->ds,
2029 TEXTMODE_X(cursor_offset),
2030 TEXTMODE_Y(cursor_offset));
2031 else
2032 dpy_cursor(s->ds, -1, -1);
2033 s->cursor_offset = cursor_offset;
2034 s->cursor_start = s->cr[0xa];
2035 s->cursor_end = s->cr[0xb];
2036 }
2037
2038 src = (uint32_t *) s->vram_ptr + s->start_addr;
2039 dst = chardata;
2040
2041 if (full_update) {
2042 for (i = 0; i < size; src ++, dst ++, i ++)
2043 console_write_ch(dst, VMEM2CHTYPE(*src));
2044
2045 dpy_update(s->ds, 0, 0, width, height);
2046 } else {
2047 c_max = 0;
2048
2049 for (i = 0; i < size; src ++, dst ++, i ++) {
2050 console_write_ch(&val, VMEM2CHTYPE(*src));
2051 if (*dst != val) {
2052 *dst = val;
2053 c_max = i;
2054 break;
2055 }
2056 }
2057 c_min = i;
2058 for (; i < size; src ++, dst ++, i ++) {
2059 console_write_ch(&val, VMEM2CHTYPE(*src));
2060 if (*dst != val) {
2061 *dst = val;
2062 c_max = i;
2063 }
2064 }
2065
2066 if (c_min <= c_max) {
2067 i = TEXTMODE_Y(c_min);
2068 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2069 }
2070 }
2071
2072 return;
2073 case GMODE_GRAPH:
2074 if (!full_update)
2075 return;
2076
2077 s->get_resolution(s, &width, &height);
2078 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2079 width, height);
2080 break;
2081 case GMODE_BLANK:
2082 default:
2083 if (!full_update)
2084 return;
2085
2086 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2087 break;
2088 }
2089
2090 /* Display a message */
2091 s->last_width = 60;
2092 s->last_height = height = 3;
2093 dpy_cursor(s->ds, -1, -1);
2094 s->ds->surface->width = s->last_width;
2095 s->ds->surface->height = height;
2096 dpy_resize(s->ds);
2097
2098 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2099 console_write_ch(dst ++, ' ');
2100
2101 size = strlen(msg_buffer);
2102 width = (s->last_width - size) / 2;
2103 dst = chardata + s->last_width + width;
2104 for (i = 0; i < size; i ++)
2105 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2106
2107 dpy_update(s->ds, 0, 0, s->last_width, height);
2108 }
2109
2110 static CPUReadMemoryFunc *vga_mem_read[3] = {
2111 vga_mem_readb,
2112 vga_mem_readw,
2113 vga_mem_readl,
2114 };
2115
2116 static CPUWriteMemoryFunc *vga_mem_write[3] = {
2117 vga_mem_writeb,
2118 vga_mem_writew,
2119 vga_mem_writel,
2120 };
2121
2122 static void vga_save(QEMUFile *f, void *opaque)
2123 {
2124 VGAState *s = opaque;
2125 int i;
2126
2127 if (s->pci_dev)
2128 pci_device_save(s->pci_dev, f);
2129
2130 qemu_put_be32s(f, &s->latch);
2131 qemu_put_8s(f, &s->sr_index);
2132 qemu_put_buffer(f, s->sr, 8);
2133 qemu_put_8s(f, &s->gr_index);
2134 qemu_put_buffer(f, s->gr, 16);
2135 qemu_put_8s(f, &s->ar_index);
2136 qemu_put_buffer(f, s->ar, 21);
2137 qemu_put_be32(f, s->ar_flip_flop);
2138 qemu_put_8s(f, &s->cr_index);
2139 qemu_put_buffer(f, s->cr, 256);
2140 qemu_put_8s(f, &s->msr);
2141 qemu_put_8s(f, &s->fcr);
2142 qemu_put_byte(f, s->st00);
2143 qemu_put_8s(f, &s->st01);
2144
2145 qemu_put_8s(f, &s->dac_state);
2146 qemu_put_8s(f, &s->dac_sub_index);
2147 qemu_put_8s(f, &s->dac_read_index);
2148 qemu_put_8s(f, &s->dac_write_index);
2149 qemu_put_buffer(f, s->dac_cache, 3);
2150 qemu_put_buffer(f, s->palette, 768);
2151
2152 qemu_put_be32(f, s->bank_offset);
2153 #ifdef CONFIG_BOCHS_VBE
2154 qemu_put_byte(f, 1);
2155 qemu_put_be16s(f, &s->vbe_index);
2156 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2157 qemu_put_be16s(f, &s->vbe_regs[i]);
2158 qemu_put_be32s(f, &s->vbe_start_addr);
2159 qemu_put_be32s(f, &s->vbe_line_offset);
2160 qemu_put_be32s(f, &s->vbe_bank_mask);
2161 #else
2162 qemu_put_byte(f, 0);
2163 #endif
2164 }
2165
2166 static int vga_load(QEMUFile *f, void *opaque, int version_id)
2167 {
2168 VGAState *s = opaque;
2169 int is_vbe, i, ret;
2170
2171 if (version_id > 2)
2172 return -EINVAL;
2173
2174 if (s->pci_dev && version_id >= 2) {
2175 ret = pci_device_load(s->pci_dev, f);
2176 if (ret < 0)
2177 return ret;
2178 }
2179
2180 qemu_get_be32s(f, &s->latch);
2181 qemu_get_8s(f, &s->sr_index);
2182 qemu_get_buffer(f, s->sr, 8);
2183 qemu_get_8s(f, &s->gr_index);
2184 qemu_get_buffer(f, s->gr, 16);
2185 qemu_get_8s(f, &s->ar_index);
2186 qemu_get_buffer(f, s->ar, 21);
2187 s->ar_flip_flop=qemu_get_be32(f);
2188 qemu_get_8s(f, &s->cr_index);
2189 qemu_get_buffer(f, s->cr, 256);
2190 qemu_get_8s(f, &s->msr);
2191 qemu_get_8s(f, &s->fcr);
2192 qemu_get_8s(f, &s->st00);
2193 qemu_get_8s(f, &s->st01);
2194
2195 qemu_get_8s(f, &s->dac_state);
2196 qemu_get_8s(f, &s->dac_sub_index);
2197 qemu_get_8s(f, &s->dac_read_index);
2198 qemu_get_8s(f, &s->dac_write_index);
2199 qemu_get_buffer(f, s->dac_cache, 3);
2200 qemu_get_buffer(f, s->palette, 768);
2201
2202 s->bank_offset=qemu_get_be32(f);
2203 is_vbe = qemu_get_byte(f);
2204 #ifdef CONFIG_BOCHS_VBE
2205 if (!is_vbe)
2206 return -EINVAL;
2207 qemu_get_be16s(f, &s->vbe_index);
2208 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2209 qemu_get_be16s(f, &s->vbe_regs[i]);
2210 qemu_get_be32s(f, &s->vbe_start_addr);
2211 qemu_get_be32s(f, &s->vbe_line_offset);
2212 qemu_get_be32s(f, &s->vbe_bank_mask);
2213 #else
2214 if (is_vbe)
2215 return -EINVAL;
2216 #endif
2217
2218 /* force refresh */
2219 s->graphic_mode = -1;
2220 return 0;
2221 }
2222
2223 typedef struct PCIVGAState {
2224 PCIDevice dev;
2225 VGAState vga_state;
2226 } PCIVGAState;
2227
2228 static int s1, s2;
2229
2230 static void mark_dirty(target_phys_addr_t start, target_phys_addr_t len)
2231 {
2232 target_phys_addr_t end = start + len;
2233
2234 while (start < end) {
2235 cpu_physical_memory_set_dirty(cpu_get_physical_page_desc(start));
2236 start += TARGET_PAGE_SIZE;
2237 }
2238 }
2239
2240 void vga_dirty_log_start(VGAState *s)
2241 {
2242 if (kvm_enabled() && s->map_addr)
2243 if (!s1) {
2244 kvm_log_start(s->map_addr, s->map_end - s->map_addr);
2245 mark_dirty(s->map_addr, s->map_end - s->map_addr);
2246 s1 = 1;
2247 }
2248 if (kvm_enabled() && s->lfb_vram_mapped) {
2249 if (!s2) {
2250 kvm_log_start(isa_mem_base + 0xa0000, 0x8000);
2251 kvm_log_start(isa_mem_base + 0xa8000, 0x8000);
2252 mark_dirty(isa_mem_base + 0xa0000, 0x10000);
2253 }
2254 s2 = 1;
2255 }
2256 }
2257
2258 void vga_dirty_log_stop(VGAState *s)
2259 {
2260 if (kvm_enabled() && s->map_addr && s1)
2261 kvm_log_stop(s->map_addr, s->map_end - s->map_addr);
2262
2263 if (kvm_enabled() && s->lfb_vram_mapped && s2) {
2264 kvm_log_stop(isa_mem_base + 0xa0000, 0x8000);
2265 kvm_log_stop(isa_mem_base + 0xa8000, 0x8000);
2266 }
2267 s1 = s2 = 0;
2268 }
2269
2270 static void vga_map(PCIDevice *pci_dev, int region_num,
2271 uint32_t addr, uint32_t size, int type)
2272 {
2273 PCIVGAState *d = (PCIVGAState *)pci_dev;
2274 VGAState *s = &d->vga_state;
2275 if (region_num == PCI_ROM_SLOT) {
2276 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
2277 } else {
2278 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2279 }
2280
2281 s->map_addr = addr;
2282 s->map_end = addr + VGA_RAM_SIZE;
2283
2284 vga_dirty_log_start(s);
2285 }
2286
2287 #ifdef TARGET_IA64
2288 /* do the same job as vgabios before vgabios get ready - yeah */
2289 void vga_bios_init(VGAState *s)
2290 {
2291 uint8_t palette_model[192] = {
2292 0, 0, 0, 0, 0, 170, 0, 170,
2293 0, 0, 170, 170, 170, 0, 0, 170,
2294 0, 170, 170, 85, 0, 170, 170, 170,
2295 85, 85, 85, 85, 85, 255, 85, 255,
2296 85, 85, 255, 255, 255, 85, 85, 255,
2297 85, 255, 255, 255, 85, 255, 255, 255,
2298 0, 21, 0, 0, 21, 42, 0, 63,
2299 0, 0, 63, 42, 42, 21, 0, 42,
2300 21, 42, 42, 63, 0, 42, 63, 42,
2301 0, 21, 21, 0, 21, 63, 0, 63,
2302 21, 0, 63, 63, 42, 21, 21, 42,
2303 21, 63, 42, 63, 21, 42, 63, 63,
2304 21, 0, 0, 21, 0, 42, 21, 42,
2305 0, 21, 42, 42, 63, 0, 0, 63,
2306 0, 42, 63, 42, 0, 63, 42, 42,
2307 21, 0, 21, 21, 0, 63, 21, 42,
2308 21, 21, 42, 63, 63, 0, 21, 63,
2309 0, 63, 63, 42, 21, 63, 42, 63,
2310 21, 21, 0, 21, 21, 42, 21, 63,
2311 0, 21, 63, 42, 63, 21, 0, 63,
2312 21, 42, 63, 63, 0, 63, 63, 42,
2313 21, 21, 21, 21, 21, 63, 21, 63,
2314 21, 21, 63, 63, 63, 21, 21, 63,
2315 21, 63, 63, 63, 21, 63, 63, 63
2316 };
2317
2318 s->latch = 0;
2319
2320 s->sr_index = 3;
2321 s->sr[0] = 3;
2322 s->sr[1] = 0;
2323 s->sr[2] = 3;
2324 s->sr[3] = 0;
2325 s->sr[4] = 2;
2326 s->sr[5] = 0;
2327 s->sr[6] = 0;
2328 s->sr[7] = 0;
2329
2330 s->gr_index = 5;
2331 s->gr[0] = 0;
2332 s->gr[1] = 0;
2333 s->gr[2] = 0;
2334 s->gr[3] = 0;
2335 s->gr[4] = 0;
2336 s->gr[5] = 16;
2337 s->gr[6] = 14;
2338 s->gr[7] = 15;
2339 s->gr[8] = 255;
2340
2341 /* changed by out 0x03c0 */
2342 s->ar_index = 32;
2343 s->ar[0] = 0;
2344 s->ar[1] = 1;
2345 s->ar[2] = 2;
2346 s->ar[3] = 3;
2347 s->ar[4] = 4;
2348 s->ar[5] = 5;
2349 s->ar[6] = 6;
2350 s->ar[7] = 7;
2351 s->ar[8] = 8;
2352 s->ar[9] = 9;
2353 s->ar[10] = 10;
2354 s->ar[11] = 11;
2355 s->ar[12] = 12;
2356 s->ar[13] = 13;
2357 s->ar[14] = 14;
2358 s->ar[15] = 15;
2359 s->ar[16] = 12;
2360 s->ar[17] = 0;
2361 s->ar[18] = 15;
2362 s->ar[19] = 8;
2363 s->ar[20] = 0;
2364
2365 s->ar_flip_flop = 1;
2366
2367 s->cr_index = 15;
2368 s->cr[0] = 95;
2369 s->cr[1] = 79;
2370 s->cr[2] = 80;
2371 s->cr[3] = 130;
2372 s->cr[4] = 85;
2373 s->cr[5] = 129;
2374 s->cr[6] = 191;
2375 s->cr[7] = 31;
2376 s->cr[8] = 0;
2377 s->cr[9] = 79;
2378 s->cr[10] = 14;
2379 s->cr[11] = 15;
2380 s->cr[12] = 0;
2381 s->cr[13] = 0;
2382 s->cr[14] = 5;
2383 s->cr[15] = 160;
2384 s->cr[16] = 156;
2385 s->cr[17] = 142;
2386 s->cr[18] = 143;
2387 s->cr[19] = 40;
2388 s->cr[20] = 31;
2389 s->cr[21] = 150;
2390 s->cr[22] = 185;
2391 s->cr[23] = 163;
2392 s->cr[24] = 255;
2393
2394 s->msr = 103;
2395 s->fcr = 0;
2396 s->st00 = 0;
2397 s->st01 = 0;
2398
2399 /* dac_* & palette will be initialized by os through out 0x03c8 &
2400 * out 0c03c9(1:3) */
2401 s->dac_state = 0;
2402 s->dac_sub_index = 0;
2403 s->dac_read_index = 0;
2404 s->dac_write_index = 16;
2405 s->dac_cache[0] = 255;
2406 s->dac_cache[1] = 255;
2407 s->dac_cache[2] = 255;
2408
2409 /* palette */
2410 memcpy(s->palette, palette_model, 192);
2411
2412 s->bank_offset = 0;
2413 s->graphic_mode = -1;
2414
2415 /* TODO: add vbe support if enabled */
2416 }
2417 #endif
2418
2419 void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
2420 ram_addr_t vga_ram_offset, int vga_ram_size)
2421 {
2422 int i, j, v, b;
2423
2424 for(i = 0;i < 256; i++) {
2425 v = 0;
2426 for(j = 0; j < 8; j++) {
2427 v |= ((i >> j) & 1) << (j * 4);
2428 }
2429 expand4[i] = v;
2430
2431 v = 0;
2432 for(j = 0; j < 4; j++) {
2433 v |= ((i >> (2 * j)) & 3) << (j * 4);
2434 }
2435 expand2[i] = v;
2436 }
2437 for(i = 0; i < 16; i++) {
2438 v = 0;
2439 for(j = 0; j < 4; j++) {
2440 b = ((i >> j) & 1);
2441 v |= b << (2 * j);
2442 v |= b << (2 * j + 1);
2443 }
2444 expand4to8[i] = v;
2445 }
2446
2447 s->vram_ptr = vga_ram_base;
2448 s->vram_offset = vga_ram_offset;
2449 s->vram_size = vga_ram_size;
2450 s->get_bpp = vga_get_bpp;
2451 s->get_offsets = vga_get_offsets;
2452 s->get_resolution = vga_get_resolution;
2453 s->update = vga_update_display;
2454 s->invalidate = vga_invalidate_display;
2455 s->screen_dump = vga_screen_dump;
2456 s->text_update = vga_update_text;
2457 switch (vga_retrace_method) {
2458 case VGA_RETRACE_DUMB:
2459 s->retrace = vga_dumb_retrace;
2460 s->update_retrace_info = vga_dumb_update_retrace_info;
2461 break;
2462
2463 case VGA_RETRACE_PRECISE:
2464 s->retrace = vga_precise_retrace;
2465 s->update_retrace_info = vga_precise_update_retrace_info;
2466 break;
2467 }
2468 vga_reset(s);
2469 #ifdef TARGET_IA64
2470 vga_bios_init(s);
2471 #endif
2472 }
2473
2474 /* used by both ISA and PCI */
2475 void vga_init(VGAState *s)
2476 {
2477 int vga_io_memory;
2478
2479 qemu_register_reset(vga_reset, s);
2480 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2481
2482 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2483
2484 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2485 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2486 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2487 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2488
2489 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2490
2491 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2492 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2493 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2494 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2495 s->bank_offset = 0;
2496
2497 #ifdef CONFIG_BOCHS_VBE
2498 #if defined (TARGET_I386)
2499 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2500 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2501
2502 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2503 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2504
2505 /* old Bochs IO ports */
2506 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2507 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2508
2509 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2510 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2511 #else
2512 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2513 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2514
2515 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2516 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2517 #endif
2518 #endif /* CONFIG_BOCHS_VBE */
2519
2520 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2521 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2522 vga_io_memory);
2523 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2524 }
2525
2526 /* Memory mapped interface */
2527 static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
2528 {
2529 VGAState *s = opaque;
2530
2531 return vga_ioport_read(s, addr >> s->it_shift) & 0xff;
2532 }
2533
2534 static void vga_mm_writeb (void *opaque,
2535 target_phys_addr_t addr, uint32_t value)
2536 {
2537 VGAState *s = opaque;
2538
2539 vga_ioport_write(s, addr >> s->it_shift, value & 0xff);
2540 }
2541
2542 static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
2543 {
2544 VGAState *s = opaque;
2545
2546 return vga_ioport_read(s, addr >> s->it_shift) & 0xffff;
2547 }
2548
2549 static void vga_mm_writew (void *opaque,
2550 target_phys_addr_t addr, uint32_t value)
2551 {
2552 VGAState *s = opaque;
2553
2554 vga_ioport_write(s, addr >> s->it_shift, value & 0xffff);
2555 }
2556
2557 static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
2558 {
2559 VGAState *s = opaque;
2560
2561 return vga_ioport_read(s, addr >> s->it_shift);
2562 }
2563
2564 static void vga_mm_writel (void *opaque,
2565 target_phys_addr_t addr, uint32_t value)
2566 {
2567 VGAState *s = opaque;
2568
2569 vga_ioport_write(s, addr >> s->it_shift, value);
2570 }
2571
2572 static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
2573 &vga_mm_readb,
2574 &vga_mm_readw,
2575 &vga_mm_readl,
2576 };
2577
2578 static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
2579 &vga_mm_writeb,
2580 &vga_mm_writew,
2581 &vga_mm_writel,
2582 };
2583
2584 static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
2585 target_phys_addr_t ctrl_base, int it_shift)
2586 {
2587 int s_ioport_ctrl, vga_io_memory;
2588
2589 s->it_shift = it_shift;
2590 s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);
2591 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2592
2593 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2594
2595 cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
2596 s->bank_offset = 0;
2597 cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
2598 qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
2599 }
2600
2601 int isa_vga_init(uint8_t *vga_ram_base,
2602 unsigned long vga_ram_offset, int vga_ram_size)
2603 {
2604 VGAState *s;
2605
2606 s = qemu_mallocz(sizeof(VGAState));
2607 if (!s)
2608 return -1;
2609
2610 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2611 vga_init(s);
2612
2613 s->ds = graphic_console_init(s->update, s->invalidate,
2614 s->screen_dump, s->text_update, s);
2615
2616 #ifdef CONFIG_BOCHS_VBE
2617 /* XXX: use optimized standard vga accesses */
2618 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2619 vga_ram_size, vga_ram_offset);
2620 #endif
2621 return 0;
2622 }
2623
2624 int isa_vga_mm_init(uint8_t *vga_ram_base,
2625 unsigned long vga_ram_offset, int vga_ram_size,
2626 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
2627 int it_shift)
2628 {
2629 VGAState *s;
2630
2631 s = qemu_mallocz(sizeof(VGAState));
2632 if (!s)
2633 return -1;
2634
2635 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2636 vga_mm_init(s, vram_base, ctrl_base, it_shift);
2637
2638 s->ds = graphic_console_init(s->update, s->invalidate,
2639 s->screen_dump, s->text_update, s);
2640
2641 #ifdef CONFIG_BOCHS_VBE
2642 /* XXX: use optimized standard vga accesses */
2643 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2644 vga_ram_size, vga_ram_offset);
2645 #endif
2646 return 0;
2647 }
2648
2649 static void pci_vga_write_config(PCIDevice *d,
2650 uint32_t address, uint32_t val, int len)
2651 {
2652 PCIVGAState *pvs = container_of(d, PCIVGAState, dev);
2653 VGAState *s = &pvs->vga_state;
2654
2655 vga_dirty_log_stop(s);
2656 pci_default_write_config(d, address, val, len);
2657 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
2658 s->map_addr = 0;
2659 vga_dirty_log_start(s);
2660 }
2661
2662 int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
2663 unsigned long vga_ram_offset, int vga_ram_size,
2664 unsigned long vga_bios_offset, int vga_bios_size)
2665 {
2666 PCIVGAState *d;
2667 VGAState *s;
2668 uint8_t *pci_conf;
2669
2670 d = (PCIVGAState *)pci_register_device(bus, "VGA",
2671 sizeof(PCIVGAState),
2672 -1, NULL, pci_vga_write_config);
2673 if (!d)
2674 return -1;
2675 s = &d->vga_state;
2676
2677 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2678 vga_init(s);
2679
2680 s->ds = graphic_console_init(s->update, s->invalidate,
2681 s->screen_dump, s->text_update, s);
2682
2683 s->pci_dev = &d->dev;
2684
2685 pci_conf = d->dev.config;
2686 // dummy VGA (same as Bochs ID)
2687 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
2688 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
2689 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
2690 pci_conf[0x0e] = 0x00; // header_type
2691
2692 /* XXX: vga_ram_size must be a power of two */
2693 pci_register_io_region(&d->dev, 0, vga_ram_size,
2694 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2695 if (vga_bios_size != 0) {
2696 unsigned int bios_total_size;
2697 s->bios_offset = vga_bios_offset;
2698 s->bios_size = vga_bios_size;
2699 /* must be a power of two */
2700 bios_total_size = 1;
2701 while (bios_total_size < vga_bios_size)
2702 bios_total_size <<= 1;
2703 pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
2704 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2705 }
2706 return 0;
2707 }
2708
2709 /********************************************************/
2710 /* vga screen dump */
2711
2712 static void vga_save_dpy_update(DisplayState *s,
2713 int x, int y, int w, int h)
2714 {
2715 }
2716
2717 static void vga_save_dpy_resize(DisplayState *s)
2718 {
2719 }
2720
2721 static void vga_save_dpy_refresh(DisplayState *s)
2722 {
2723 }
2724
2725 int ppm_save(const char *filename, struct DisplaySurface *ds)
2726 {
2727 FILE *f;
2728 uint8_t *d, *d1;
2729 uint32_t v;
2730 int y, x;
2731 uint8_t r, g, b;
2732
2733 f = fopen(filename, "wb");
2734 if (!f)
2735 return -1;
2736 fprintf(f, "P6\n%d %d\n%d\n",
2737 ds->width, ds->height, 255);
2738 d1 = ds->data;
2739 for(y = 0; y < ds->height; y++) {
2740 d = d1;
2741 for(x = 0; x < ds->width; x++) {
2742 if (ds->pf.bits_per_pixel == 32)
2743 v = *(uint32_t *)d;
2744 else
2745 v = (uint32_t) (*(uint16_t *)d);
2746 r = ((v >> ds->pf.rshift) & ds->pf.rmax) * 256 /
2747 (ds->pf.rmax + 1);
2748 g = ((v >> ds->pf.gshift) & ds->pf.gmax) * 256 /
2749 (ds->pf.gmax + 1);
2750 b = ((v >> ds->pf.bshift) & ds->pf.bmax) * 256 /
2751 (ds->pf.bmax + 1);
2752 fputc(r, f);
2753 fputc(g, f);
2754 fputc(b, f);
2755 d += ds->pf.bytes_per_pixel;
2756 }
2757 d1 += ds->linesize;
2758 }
2759 fclose(f);
2760 return 0;
2761 }
2762
2763 static void vga_screen_dump_blank(VGAState *s, const char *filename)
2764 {
2765 FILE *f;
2766 unsigned int y, x, w, h;
2767
2768 w = s->last_scr_width * sizeof(uint32_t);
2769 h = s->last_scr_height;
2770
2771 f = fopen(filename, "wb");
2772 if (!f)
2773 return;
2774 fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
2775 for (y = 0; y < h; y++) {
2776 for (x = 0; x < w; x++) {
2777 fputc(0, f);
2778 }
2779 }
2780 fclose(f);
2781 }
2782
2783 static void vga_screen_dump_common(VGAState *s, const char *filename,
2784 int w, int h)
2785 {
2786 DisplayState *saved_ds, ds1, *ds = &ds1;
2787 DisplayChangeListener dcl;
2788
2789 /* XXX: this is a little hackish */
2790 vga_invalidate_display(s);
2791 saved_ds = s->ds;
2792
2793 memset(ds, 0, sizeof(DisplayState));
2794 memset(&dcl, 0, sizeof(DisplayChangeListener));
2795 dcl.dpy_update = vga_save_dpy_update;
2796 dcl.dpy_resize = vga_save_dpy_resize;
2797 dcl.dpy_refresh = vga_save_dpy_refresh;
2798 register_displaychangelistener(ds, &dcl);
2799 ds->surface = qemu_create_displaysurface(w, h, 32, 4 * w);
2800
2801 s->ds = ds;
2802 s->graphic_mode = -1;
2803 vga_update_display(s);
2804
2805 ppm_save(filename, ds->surface);
2806
2807 qemu_free_displaysurface(ds->surface);
2808 s->ds = saved_ds;
2809 }
2810
2811 static void vga_screen_dump_graphic(VGAState *s, const char *filename)
2812 {
2813 int w, h;
2814
2815 s->get_resolution(s, &w, &h);
2816 vga_screen_dump_common(s, filename, w, h);
2817 }
2818
2819 static void vga_screen_dump_text(VGAState *s, const char *filename)
2820 {
2821 int w, h, cwidth, cheight;
2822
2823 vga_get_text_resolution(s, &w, &h, &cwidth, &cheight);
2824 vga_screen_dump_common(s, filename, w * cwidth, h * cheight);
2825 }
2826
2827 /* save the vga display in a PPM image even if no display is
2828 available */
2829 static void vga_screen_dump(void *opaque, const char *filename)
2830 {
2831 VGAState *s = (VGAState *)opaque;
2832
2833 if (!(s->ar_index & 0x20))
2834 vga_screen_dump_blank(s, filename);
2835 else if (s->gr[6] & 1)
2836 vga_screen_dump_graphic(s, filename);
2837 else
2838 vga_screen_dump_text(s, filename);
2839 }
Patches shipped by Fedora