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Merge branch 'qemu-cvs'
[qemu-kvm/fedora.git] / hw / pc.c
blob8a52f4961afc14c1561b87db24cf6e36ad622a15
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pc.h"
26 #include "fdc.h"
27 #include "pci.h"
28 #include "block.h"
29 #include "sysemu.h"
30 #include "audio/audio.h"
31 #include "net.h"
32 #include "smbus.h"
33 #include "boards.h"
34 #include "console.h"
35 #include "fw_cfg.h"
36 #include "virtio-blk.h"
37 #include "virtio-balloon.h"
38 #include "virtio-console.h"
39 #include "hpet_emul.h"
40 #include "device-assignment.h"
41
42 #include "qemu-kvm.h"
43
44 /* output Bochs bios info messages */
45 //#define DEBUG_BIOS
46
47 #define BIOS_FILENAME "bios.bin"
48 #define VGABIOS_FILENAME "vgabios.bin"
49 #define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
50 #define EXTBOOT_FILENAME "extboot.bin"
51
52 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
53
54 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
55 #define ACPI_DATA_SIZE 0x10000
56 #define BIOS_CFG_IOPORT 0x510
57
58 #define MAX_IDE_BUS 2
59
60 static fdctrl_t *floppy_controller;
61 static RTCState *rtc_state;
62 static PITState *pit;
63 static IOAPICState *ioapic;
64 static PCIDevice *i440fx_state;
65
66 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
67 {
68 }
69
70 /* MSDOS compatibility mode FPU exception support */
71 static qemu_irq ferr_irq;
72 /* XXX: add IGNNE support */
73 void cpu_set_ferr(CPUX86State *s)
74 {
75 qemu_irq_raise(ferr_irq);
76 }
77
78 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
79 {
80 qemu_irq_lower(ferr_irq);
81 }
82
83 /* TSC handling */
84 uint64_t cpu_get_tsc(CPUX86State *env)
85 {
86 /* Note: when using kqemu, it is more logical to return the host TSC
87 because kqemu does not trap the RDTSC instruction for
88 performance reasons */
89 #ifdef USE_KQEMU
90 if (env->kqemu_enabled) {
91 return cpu_get_real_ticks();
92 } else
93 #endif
94 {
95 return cpu_get_ticks();
96 }
97 }
98
99 /* SMM support */
100 void cpu_smm_update(CPUState *env)
101 {
102 if (i440fx_state && env == first_cpu)
103 i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
104 }
105
106
107 /* IRQ handling */
108 int cpu_get_pic_interrupt(CPUState *env)
109 {
110 int intno;
111
112 intno = apic_get_interrupt(env);
113 if (intno >= 0) {
114 /* set irq request if a PIC irq is still pending */
115 /* XXX: improve that */
116 pic_update_irq(isa_pic);
117 return intno;
118 }
119 /* read the irq from the PIC */
120 if (!apic_accept_pic_intr(env))
121 return -1;
122
123 intno = pic_read_irq(isa_pic);
124 return intno;
125 }
126
127 static void pic_irq_request(void *opaque, int irq, int level)
128 {
129 CPUState *env = first_cpu;
130
131 if (env->apic_state) {
132 while (env) {
133 if (apic_accept_pic_intr(env))
134 apic_deliver_pic_intr(env, level);
135 env = env->next_cpu;
136 }
137 } else {
138 if (level)
139 cpu_interrupt(env, CPU_INTERRUPT_HARD);
140 else
141 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
142 }
143 }
144
145 /* PC cmos mappings */
146
147 #define REG_EQUIPMENT_BYTE 0x14
148
149 static int cmos_get_fd_drive_type(int fd0)
150 {
151 int val;
152
153 switch (fd0) {
154 case 0:
155 /* 1.44 Mb 3"5 drive */
156 val = 4;
157 break;
158 case 1:
159 /* 2.88 Mb 3"5 drive */
160 val = 5;
161 break;
162 case 2:
163 /* 1.2 Mb 5"5 drive */
164 val = 2;
165 break;
166 default:
167 val = 0;
168 break;
169 }
170 return val;
171 }
172
173 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
174 {
175 RTCState *s = rtc_state;
176 int cylinders, heads, sectors;
177 bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
178 rtc_set_memory(s, type_ofs, 47);
179 rtc_set_memory(s, info_ofs, cylinders);
180 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
181 rtc_set_memory(s, info_ofs + 2, heads);
182 rtc_set_memory(s, info_ofs + 3, 0xff);
183 rtc_set_memory(s, info_ofs + 4, 0xff);
184 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
185 rtc_set_memory(s, info_ofs + 6, cylinders);
186 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
187 rtc_set_memory(s, info_ofs + 8, sectors);
188 }
189
190 /* convert boot_device letter to something recognizable by the bios */
191 static int boot_device2nibble(char boot_device)
192 {
193 switch(boot_device) {
194 case 'a':
195 case 'b':
196 return 0x01; /* floppy boot */
197 case 'c':
198 return 0x02; /* hard drive boot */
199 case 'd':
200 return 0x03; /* CD-ROM boot */
201 case 'n':
202 return 0x04; /* Network boot */
203 }
204 return 0;
205 }
206
207 /* copy/pasted from cmos_init, should be made a general function
208 and used there as well */
209 static int pc_boot_set(void *opaque, const char *boot_device)
210 {
211 #define PC_MAX_BOOT_DEVICES 3
212 RTCState *s = (RTCState *)opaque;
213 int nbds, bds[3] = { 0, };
214 int i;
215
216 nbds = strlen(boot_device);
217 if (nbds > PC_MAX_BOOT_DEVICES) {
218 term_printf("Too many boot devices for PC\n");
219 return(1);
220 }
221 for (i = 0; i < nbds; i++) {
222 bds[i] = boot_device2nibble(boot_device[i]);
223 if (bds[i] == 0) {
224 term_printf("Invalid boot device for PC: '%c'\n",
225 boot_device[i]);
226 return(1);
227 }
228 }
229 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
230 rtc_set_memory(s, 0x38, (bds[2] << 4));
231 return(0);
232 }
233
234 /* hd_table must contain 4 block drivers */
235 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
236 const char *boot_device, BlockDriverState **hd_table)
237 {
238 RTCState *s = rtc_state;
239 int nbds, bds[3] = { 0, };
240 int val;
241 int fd0, fd1, nb;
242 int i;
243
244 /* various important CMOS locations needed by PC/Bochs bios */
245
246 /* memory size */
247 val = 640; /* base memory in K */
248 rtc_set_memory(s, 0x15, val);
249 rtc_set_memory(s, 0x16, val >> 8);
250
251 val = (ram_size / 1024) - 1024;
252 if (val > 65535)
253 val = 65535;
254 rtc_set_memory(s, 0x17, val);
255 rtc_set_memory(s, 0x18, val >> 8);
256 rtc_set_memory(s, 0x30, val);
257 rtc_set_memory(s, 0x31, val >> 8);
258
259 if (above_4g_mem_size) {
260 rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
261 rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
262 rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
263 }
264 rtc_set_memory(s, 0x5f, smp_cpus - 1);
265
266 if (ram_size > (16 * 1024 * 1024))
267 val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
268 else
269 val = 0;
270 if (val > 65535)
271 val = 65535;
272 rtc_set_memory(s, 0x34, val);
273 rtc_set_memory(s, 0x35, val >> 8);
274
275 /* set the number of CPU */
276 rtc_set_memory(s, 0x5f, smp_cpus - 1);
277
278 /* set boot devices, and disable floppy signature check if requested */
279 #define PC_MAX_BOOT_DEVICES 3
280 nbds = strlen(boot_device);
281 if (nbds > PC_MAX_BOOT_DEVICES) {
282 fprintf(stderr, "Too many boot devices for PC\n");
283 exit(1);
284 }
285 for (i = 0; i < nbds; i++) {
286 bds[i] = boot_device2nibble(boot_device[i]);
287 if (bds[i] == 0) {
288 fprintf(stderr, "Invalid boot device for PC: '%c'\n",
289 boot_device[i]);
290 exit(1);
291 }
292 }
293 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
294 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
295
296 /* floppy type */
297
298 fd0 = fdctrl_get_drive_type(floppy_controller, 0);
299 fd1 = fdctrl_get_drive_type(floppy_controller, 1);
300
301 val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
302 rtc_set_memory(s, 0x10, val);
303
304 val = 0;
305 nb = 0;
306 if (fd0 < 3)
307 nb++;
308 if (fd1 < 3)
309 nb++;
310 switch (nb) {
311 case 0:
312 break;
313 case 1:
314 val |= 0x01; /* 1 drive, ready for boot */
315 break;
316 case 2:
317 val |= 0x41; /* 2 drives, ready for boot */
318 break;
319 }
320 val |= 0x02; /* FPU is there */
321 val |= 0x04; /* PS/2 mouse installed */
322 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
323
324 /* hard drives */
325
326 rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
327 if (hd_table[0])
328 cmos_init_hd(0x19, 0x1b, hd_table[0]);
329 if (hd_table[1])
330 cmos_init_hd(0x1a, 0x24, hd_table[1]);
331
332 val = 0;
333 for (i = 0; i < 4; i++) {
334 if (hd_table[i]) {
335 int cylinders, heads, sectors, translation;
336 /* NOTE: bdrv_get_geometry_hint() returns the physical
337 geometry. It is always such that: 1 <= sects <= 63, 1
338 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
339 geometry can be different if a translation is done. */
340 translation = bdrv_get_translation_hint(hd_table[i]);
341 if (translation == BIOS_ATA_TRANSLATION_AUTO) {
342 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
343 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
344 /* No translation. */
345 translation = 0;
346 } else {
347 /* LBA translation. */
348 translation = 1;
349 }
350 } else {
351 translation--;
352 }
353 val |= translation << (i * 2);
354 }
355 }
356 rtc_set_memory(s, 0x39, val);
357 }
358
359 void ioport_set_a20(int enable)
360 {
361 /* XXX: send to all CPUs ? */
362 cpu_x86_set_a20(first_cpu, enable);
363 }
364
365 int ioport_get_a20(void)
366 {
367 return ((first_cpu->a20_mask >> 20) & 1);
368 }
369
370 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
371 {
372 ioport_set_a20((val >> 1) & 1);
373 /* XXX: bit 0 is fast reset */
374 }
375
376 static uint32_t ioport92_read(void *opaque, uint32_t addr)
377 {
378 return ioport_get_a20() << 1;
379 }
380
381 /***********************************************************/
382 /* Bochs BIOS debug ports */
383
384 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
385 {
386 static const char shutdown_str[8] = "Shutdown";
387 static int shutdown_index = 0;
388
389 switch(addr) {
390 /* Bochs BIOS messages */
391 case 0x400:
392 case 0x401:
393 fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
394 exit(1);
395 case 0x402:
396 case 0x403:
397 #ifdef DEBUG_BIOS
398 fprintf(stderr, "%c", val);
399 #endif
400 break;
401 case 0x8900:
402 /* same as Bochs power off */
403 if (val == shutdown_str[shutdown_index]) {
404 shutdown_index++;
405 if (shutdown_index == 8) {
406 shutdown_index = 0;
407 qemu_system_shutdown_request();
408 }
409 } else {
410 shutdown_index = 0;
411 }
412 break;
413
414 /* LGPL'ed VGA BIOS messages */
415 case 0x501:
416 case 0x502:
417 fprintf(stderr, "VGA BIOS panic, line %d\n", val);
418 exit(1);
419 case 0x500:
420 case 0x503:
421 #ifdef DEBUG_BIOS
422 fprintf(stderr, "%c", val);
423 #endif
424 break;
425 }
426 }
427
428 static void bochs_bios_init(void)
429 {
430 void *fw_cfg;
431
432 register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
433 register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
434 register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
435 register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
436 register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
437
438 register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
439 register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
440 register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
441 register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
442
443 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
444 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
445 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
446 }
447
448 /* Generate an initial boot sector which sets state and jump to
449 a specified vector */
450 static void generate_bootsect(uint8_t *option_rom,
451 uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
452 {
453 uint8_t rom[512], *p, *reloc;
454 uint8_t sum;
455 int i;
456
457 memset(rom, 0, sizeof(rom));
458
459 p = rom;
460 /* Make sure we have an option rom signature */
461 *p++ = 0x55;
462 *p++ = 0xaa;
463
464 /* ROM size in sectors*/
465 *p++ = 1;
466
467 /* Hook int19 */
468
469 *p++ = 0x50; /* push ax */
470 *p++ = 0x1e; /* push ds */
471 *p++ = 0x31; *p++ = 0xc0; /* xor ax, ax */
472 *p++ = 0x8e; *p++ = 0xd8; /* mov ax, ds */
473
474 *p++ = 0xc7; *p++ = 0x06; /* movvw _start,0x64 */
475 *p++ = 0x64; *p++ = 0x00;
476 reloc = p;
477 *p++ = 0x00; *p++ = 0x00;
478
479 *p++ = 0x8c; *p++ = 0x0e; /* mov cs,0x66 */
480 *p++ = 0x66; *p++ = 0x00;
481
482 *p++ = 0x1f; /* pop ds */
483 *p++ = 0x58; /* pop ax */
484 *p++ = 0xcb; /* lret */
485
486 /* Actual code */
487 *reloc = (p - rom);
488
489 *p++ = 0xfa; /* CLI */
490 *p++ = 0xfc; /* CLD */
491
492 for (i = 0; i < 6; i++) {
493 if (i == 1) /* Skip CS */
494 continue;
495
496 *p++ = 0xb8; /* MOV AX,imm16 */
497 *p++ = segs[i];
498 *p++ = segs[i] >> 8;
499 *p++ = 0x8e; /* MOV <seg>,AX */
500 *p++ = 0xc0 + (i << 3);
501 }
502
503 for (i = 0; i < 8; i++) {
504 *p++ = 0x66; /* 32-bit operand size */
505 *p++ = 0xb8 + i; /* MOV <reg>,imm32 */
506 *p++ = gpr[i];
507 *p++ = gpr[i] >> 8;
508 *p++ = gpr[i] >> 16;
509 *p++ = gpr[i] >> 24;
510 }
511
512 *p++ = 0xea; /* JMP FAR */
513 *p++ = ip; /* IP */
514 *p++ = ip >> 8;
515 *p++ = segs[1]; /* CS */
516 *p++ = segs[1] >> 8;
517
518 /* sign rom */
519 sum = 0;
520 for (i = 0; i < (sizeof(rom) - 1); i++)
521 sum += rom[i];
522 rom[sizeof(rom) - 1] = -sum;
523
524 memcpy(option_rom, rom, sizeof(rom));
525 }
526
527 static long get_file_size(FILE *f)
528 {
529 long where, size;
530
531 /* XXX: on Unix systems, using fstat() probably makes more sense */
532
533 where = ftell(f);
534 fseek(f, 0, SEEK_END);
535 size = ftell(f);
536 fseek(f, where, SEEK_SET);
537
538 return size;
539 }
540
541 static void load_linux(uint8_t *option_rom,
542 const char *kernel_filename,
543 const char *initrd_filename,
544 const char *kernel_cmdline)
545 {
546 uint16_t protocol;
547 uint32_t gpr[8];
548 uint16_t seg[6];
549 uint16_t real_seg;
550 int setup_size, kernel_size, initrd_size, cmdline_size;
551 uint32_t initrd_max;
552 uint8_t header[1024];
553 target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr;
554 FILE *f, *fi;
555
556 /* Align to 16 bytes as a paranoia measure */
557 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
558
559 /* load the kernel header */
560 f = fopen(kernel_filename, "rb");
561 if (!f || !(kernel_size = get_file_size(f)) ||
562 fread(header, 1, 1024, f) != 1024) {
563 fprintf(stderr, "qemu: could not load kernel '%s'\n",
564 kernel_filename);
565 exit(1);
566 }
567
568 /* kernel protocol version */
569 #if 0
570 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
571 #endif
572 if (ldl_p(header+0x202) == 0x53726448)
573 protocol = lduw_p(header+0x206);
574 else
575 protocol = 0;
576
577 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
578 /* Low kernel */
579 real_addr = 0x90000;
580 cmdline_addr = 0x9a000 - cmdline_size;
581 prot_addr = 0x10000;
582 } else if (protocol < 0x202) {
583 /* High but ancient kernel */
584 real_addr = 0x90000;
585 cmdline_addr = 0x9a000 - cmdline_size;
586 prot_addr = 0x100000;
587 } else {
588 /* High and recent kernel */
589 real_addr = 0x10000;
590 cmdline_addr = 0x20000;
591 prot_addr = 0x100000;
592 }
593
594 #if 0
595 fprintf(stderr,
596 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
597 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
598 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
599 real_addr,
600 cmdline_addr,
601 prot_addr);
602 #endif
603
604 /* highest address for loading the initrd */
605 if (protocol >= 0x203)
606 initrd_max = ldl_p(header+0x22c);
607 else
608 initrd_max = 0x37ffffff;
609
610 if (initrd_max >= ram_size-ACPI_DATA_SIZE)
611 initrd_max = ram_size-ACPI_DATA_SIZE-1;
612
613 /* kernel command line */
614 pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
615
616 if (protocol >= 0x202) {
617 stl_p(header+0x228, cmdline_addr);
618 } else {
619 stw_p(header+0x20, 0xA33F);
620 stw_p(header+0x22, cmdline_addr-real_addr);
621 }
622
623 /* loader type */
624 /* High nybble = B reserved for Qemu; low nybble is revision number.
625 If this code is substantially changed, you may want to consider
626 incrementing the revision. */
627 if (protocol >= 0x200)
628 header[0x210] = 0xB0;
629
630 /* heap */
631 if (protocol >= 0x201) {
632 header[0x211] |= 0x80; /* CAN_USE_HEAP */
633 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
634 }
635
636 /* load initrd */
637 if (initrd_filename) {
638 if (protocol < 0x200) {
639 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
640 exit(1);
641 }
642
643 fi = fopen(initrd_filename, "rb");
644 if (!fi) {
645 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
646 initrd_filename);
647 exit(1);
648 }
649
650 initrd_size = get_file_size(fi);
651 initrd_addr = (initrd_max-initrd_size) & ~4095;
652
653 fprintf(stderr, "qemu: loading initrd (%#x bytes) at 0x" TARGET_FMT_plx
654 "\n", initrd_size, initrd_addr);
655
656 if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
657 fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
658 initrd_filename);
659 exit(1);
660 }
661 fclose(fi);
662
663 stl_p(header+0x218, initrd_addr);
664 stl_p(header+0x21c, initrd_size);
665 }
666
667 /* store the finalized header and load the rest of the kernel */
668 cpu_physical_memory_write(real_addr, header, 1024);
669
670 setup_size = header[0x1f1];
671 if (setup_size == 0)
672 setup_size = 4;
673
674 setup_size = (setup_size+1)*512;
675 kernel_size -= setup_size; /* Size of protected-mode code */
676
677 if (!fread_targphys_ok(real_addr+1024, setup_size-1024, f) ||
678 !fread_targphys_ok(prot_addr, kernel_size, f)) {
679 fprintf(stderr, "qemu: read error on kernel '%s'\n",
680 kernel_filename);
681 exit(1);
682 }
683 fclose(f);
684
685 /* generate bootsector to set up the initial register state */
686 real_seg = real_addr >> 4;
687 seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
688 seg[1] = real_seg+0x20; /* CS */
689 memset(gpr, 0, sizeof gpr);
690 gpr[4] = cmdline_addr-real_addr-16; /* SP (-16 is paranoia) */
691
692 generate_bootsect(option_rom, gpr, seg, 0);
693 }
694
695 static void main_cpu_reset(void *opaque)
696 {
697 CPUState *env = opaque;
698 cpu_reset(env);
699 }
700
701 static const int ide_iobase[2] = { 0x1f0, 0x170 };
702 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
703 static const int ide_irq[2] = { 14, 15 };
704
705 #define NE2000_NB_MAX 6
706
707 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
708 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
709
710 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
711 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
712
713 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
714 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
715
716 #ifdef HAS_AUDIO
717 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
718 {
719 struct soundhw *c;
720 int audio_enabled = 0;
721
722 for (c = soundhw; !audio_enabled && c->name; ++c) {
723 audio_enabled = c->enabled;
724 }
725
726 if (audio_enabled) {
727 AudioState *s;
728
729 s = AUD_init ();
730 if (s) {
731 for (c = soundhw; c->name; ++c) {
732 if (c->enabled) {
733 if (c->isa) {
734 c->init.init_isa (s, pic);
735 }
736 else {
737 if (pci_bus) {
738 c->init.init_pci (pci_bus, s);
739 }
740 }
741 }
742 }
743 }
744 }
745 }
746 #endif
747
748 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
749 {
750 static int nb_ne2k = 0;
751
752 if (nb_ne2k == NE2000_NB_MAX)
753 return;
754 isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
755 nb_ne2k++;
756 }
757
758 typedef struct rom_reset_data {
759 uint8_t *data;
760 target_phys_addr_t addr;
761 unsigned size;
762 } RomResetData;
763
764 static void option_rom_reset(void *_rrd)
765 {
766 RomResetData *rrd = _rrd;
767
768 cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
769 }
770
771 static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
772 {
773 RomResetData *rrd = qemu_malloc(sizeof *rrd);
774
775 rrd->data = qemu_malloc(size);
776 cpu_physical_memory_read(addr, rrd->data, size);
777 rrd->addr = addr;
778 rrd->size = size;
779 qemu_register_reset(option_rom_reset, rrd);
780 }
781
782 CPUState *pc_new_cpu(int cpu, const char *cpu_model, int pci_enabled)
783 {
784 CPUState *env = cpu_init(cpu_model);
785 if (!env) {
786 fprintf(stderr, "Unable to find x86 CPU definition\n");
787 exit(1);
788 }
789 if (cpu != 0)
790 env->halted = 1;
791 if (smp_cpus > 1) {
792 /* XXX: enable it in all cases */
793 env->cpuid_features |= CPUID_APIC;
794 }
795 qemu_register_reset(main_cpu_reset, env);
796 if (pci_enabled) {
797 apic_init(env);
798 }
799 return env;
800 }
801
802 /* PC hardware initialisation */
803 static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
804 const char *boot_device,
805 const char *kernel_filename, const char *kernel_cmdline,
806 const char *initrd_filename,
807 int pci_enabled, const char *cpu_model)
808 {
809 char buf[1024];
810 int ret, linux_boot, i;
811 ram_addr_t ram_addr, vga_ram_addr, bios_offset, vga_bios_offset;
812 ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
813 int bios_size, isa_bios_size, vga_bios_size;
814 int pci_option_rom_offset;
815 PCIBus *pci_bus;
816 int piix3_devfn = -1;
817 CPUState *env;
818 qemu_irq *cpu_irq;
819 qemu_irq *i8259;
820 int index;
821 BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
822 BlockDriverState *fd[MAX_FD];
823
824 if (ram_size >= 0xe0000000 ) {
825 above_4g_mem_size = ram_size - 0xe0000000;
826 below_4g_mem_size = 0xe0000000;
827 } else {
828 below_4g_mem_size = ram_size;
829 }
830
831 linux_boot = (kernel_filename != NULL);
832
833 /* init CPUs */
834 if (cpu_model == NULL) {
835 #ifdef TARGET_X86_64
836 cpu_model = "qemu64";
837 #else
838 cpu_model = "qemu32";
839 #endif
840 }
841
842 for(i = 0; i < smp_cpus; i++) {
843 env = pc_new_cpu(i, cpu_model, pci_enabled);
844 }
845
846 vmport_init();
847
848 /* allocate RAM */
849 ram_addr = qemu_ram_alloc(0xa0000);
850 cpu_register_physical_memory(0, 0xa0000, ram_addr);
851
852 /* Allocate, even though we won't register, so we don't break the
853 * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
854 * and some bios areas, which will be registered later
855 */
856 ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
857 ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
858 cpu_register_physical_memory(0x100000,
859 below_4g_mem_size - 0x100000,
860 ram_addr);
861
862 /* above 4giga memory allocation */
863 if (above_4g_mem_size > 0) {
864 if (hpagesize) {
865 if (ram_addr & (hpagesize-1)) {
866 unsigned long aligned_addr;
867 aligned_addr = (ram_addr + hpagesize - 1) & ~(hpagesize-1);
868 qemu_ram_alloc(aligned_addr - ram_addr);
869 ram_addr = aligned_addr;
870 }
871 }
872 ram_addr = qemu_ram_alloc(above_4g_mem_size);
873 cpu_register_physical_memory(0x100000000ULL,
874 above_4g_mem_size,
875 ram_addr);
876 }
877
878 /* allocate VGA RAM */
879 vga_ram_addr = qemu_ram_alloc(vga_ram_size);
880
881 /* BIOS load */
882 if (bios_name == NULL)
883 bios_name = BIOS_FILENAME;
884 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
885 bios_size = get_image_size(buf);
886 if (bios_size <= 0 ||
887 (bios_size % 65536) != 0) {
888 goto bios_error;
889 }
890 bios_offset = qemu_ram_alloc(bios_size);
891 ret = load_image(buf, phys_ram_base + bios_offset);
892 if (ret != bios_size) {
893 bios_error:
894 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", buf);
895 exit(1);
896 }
897
898 if (cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled) {
899 /* VGA BIOS load */
900 if (cirrus_vga_enabled) {
901 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_CIRRUS_FILENAME);
902 } else {
903 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
904 }
905 vga_bios_size = get_image_size(buf);
906 if (vga_bios_size <= 0 || vga_bios_size > 65536)
907 goto vga_bios_error;
908 vga_bios_offset = qemu_ram_alloc(65536);
909
910 ret = load_image(buf, phys_ram_base + vga_bios_offset);
911 if (ret != vga_bios_size) {
912 vga_bios_error:
913 fprintf(stderr, "qemu: could not load VGA BIOS '%s'\n", buf);
914 exit(1);
915 }
916
917 /* setup basic memory access */
918 cpu_register_physical_memory(0xc0000, 0x10000,
919 vga_bios_offset | IO_MEM_ROM);
920 }
921
922 /* map the last 128KB of the BIOS in ISA space */
923 isa_bios_size = bios_size;
924 if (isa_bios_size > (128 * 1024))
925 isa_bios_size = 128 * 1024;
926 cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
927 IO_MEM_UNASSIGNED);
928 /* kvm tpr optimization needs the bios accessible for write, at least to qemu itself */
929 cpu_register_physical_memory(0x100000 - isa_bios_size,
930 isa_bios_size,
931 (bios_offset + bios_size - isa_bios_size) /* | IO_MEM_ROM */);
932
933 if (extboot_drive != -1) {
934 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, EXTBOOT_FILENAME);
935 option_rom[nb_option_roms++] = buf;
936 }
937
938 {
939 ram_addr_t option_rom_offset;
940 int size, offset;
941
942 offset = 0;
943 if (linux_boot) {
944 option_rom_offset = qemu_ram_alloc(TARGET_PAGE_SIZE);
945 load_linux(phys_ram_base + option_rom_offset,
946 kernel_filename, initrd_filename, kernel_cmdline);
947 cpu_register_physical_memory(0xd0000, TARGET_PAGE_SIZE,
948 option_rom_offset | IO_MEM_ROM);
949 offset = TARGET_PAGE_SIZE;
950 }
951
952 for (i = 0; i < nb_option_roms; i++) {
953 size = get_image_size(option_rom[i]);
954 if (size < 0) {
955 fprintf(stderr, "Could not load option rom '%s'\n",
956 option_rom[i]);
957 exit(1);
958 }
959 if (size > (0x10000 - offset))
960 goto option_rom_error;
961 option_rom_offset = qemu_ram_alloc(size);
962 ret = load_image(option_rom[i], phys_ram_base + option_rom_offset);
963 if (ret != size) {
964 option_rom_error:
965 fprintf(stderr, "Too many option ROMS\n");
966 exit(1);
967 }
968 size = (size + 4095) & ~4095;
969 /* XXX: for DDIM support, "ROM space" should be writable during
970 initialization, and (optionally) marked readonly by the BIOS
971 before INT 19h. See the PNPBIOS specification, appendix B.
972 DDIM support is mandatory for proper PCI expansion ROM support. */
973 cpu_register_physical_memory(0xd0000 + offset,
974 size, option_rom_offset /* | IO_MEM_ROM */);
975 option_rom_setup_reset(0xd0000 + offset, size);
976 offset += size;
977 }
978 pci_option_rom_offset = offset;
979 }
980
981 /* map all the bios at the top of memory */
982 cpu_register_physical_memory((uint32_t)(-bios_size),
983 bios_size, bios_offset | IO_MEM_ROM);
984
985 bochs_bios_init();
986
987 cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
988 i8259 = i8259_init(cpu_irq[0]);
989 ferr_irq = i8259[13];
990
991 if (pci_enabled) {
992 pci_bus = i440fx_init(&i440fx_state, i8259);
993 piix3_devfn = piix3_init(pci_bus, -1);
994 } else {
995 pci_bus = NULL;
996 }
997
998 /* init basic PC hardware */
999 register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1000
1001 register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1002
1003 if (cirrus_vga_enabled) {
1004 if (pci_enabled) {
1005 pci_cirrus_vga_init(pci_bus,
1006 phys_ram_base + vga_ram_addr,
1007 vga_ram_addr, vga_ram_size);
1008 } else {
1009 isa_cirrus_vga_init(phys_ram_base + vga_ram_addr,
1010 vga_ram_addr, vga_ram_size);
1011 }
1012 } else if (vmsvga_enabled) {
1013 if (pci_enabled)
1014 pci_vmsvga_init(pci_bus, phys_ram_base + vga_ram_addr,
1015 vga_ram_addr, vga_ram_size);
1016 else
1017 fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1018 } else if (std_vga_enabled) {
1019 if (pci_enabled) {
1020 pci_vga_init(pci_bus, phys_ram_base + vga_ram_addr,
1021 vga_ram_addr, vga_ram_size, 0, 0);
1022 } else {
1023 isa_vga_init(phys_ram_base + vga_ram_addr,
1024 vga_ram_addr, vga_ram_size);
1025 }
1026 }
1027
1028 rtc_state = rtc_init(0x70, i8259[8], 2000);
1029
1030 qemu_register_boot_set(pc_boot_set, rtc_state);
1031
1032 register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1033 register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1034
1035 if (pci_enabled) {
1036 ioapic = ioapic_init();
1037 }
1038 #ifdef USE_KVM_PIT
1039 if (kvm_enabled() && qemu_kvm_pit_in_kernel())
1040 pit = kvm_pit_init(0x40, i8259[0]);
1041 else
1042 #endif
1043 pit = pit_init(0x40, i8259[0]);
1044 pcspk_init(pit);
1045 if (!no_hpet) {
1046 hpet_init(i8259);
1047 }
1048 if (pci_enabled) {
1049 pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
1050 }
1051
1052 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1053 if (serial_hds[i]) {
1054 serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
1055 serial_hds[i]);
1056 }
1057 }
1058
1059 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1060 if (parallel_hds[i]) {
1061 parallel_init(parallel_io[i], i8259[parallel_irq[i]],
1062 parallel_hds[i]);
1063 }
1064 }
1065
1066 for(i = 0; i < nb_nics; i++) {
1067 NICInfo *nd = &nd_table[i];
1068
1069 if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1070 pc_init_ne2k_isa(nd, i8259);
1071 else
1072 pci_nic_init(pci_bus, nd, -1, "rtl8139");
1073 }
1074
1075 qemu_system_hot_add_init(cpu_model);
1076
1077 if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1078 fprintf(stderr, "qemu: too many IDE bus\n");
1079 exit(1);
1080 }
1081
1082 for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1083 index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1084 if (index != -1)
1085 hd[i] = drives_table[index].bdrv;
1086 else
1087 hd[i] = NULL;
1088 }
1089
1090 if (pci_enabled) {
1091 pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
1092 } else {
1093 for(i = 0; i < MAX_IDE_BUS; i++) {
1094 isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
1095 hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1096 }
1097 }
1098
1099 i8042_init(i8259[1], i8259[12], 0x60);
1100 DMA_init(0);
1101 #ifdef HAS_AUDIO
1102 audio_init(pci_enabled ? pci_bus : NULL, i8259);
1103 #endif
1104
1105 for(i = 0; i < MAX_FD; i++) {
1106 index = drive_get_index(IF_FLOPPY, 0, i);
1107 if (index != -1)
1108 fd[i] = drives_table[index].bdrv;
1109 else
1110 fd[i] = NULL;
1111 }
1112 floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
1113
1114 cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1115
1116 if (pci_enabled && usb_enabled) {
1117 usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1118 }
1119
1120 if (pci_enabled && acpi_enabled) {
1121 uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1122 i2c_bus *smbus;
1123
1124 /* TODO: Populate SPD eeprom data. */
1125 smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
1126 for (i = 0; i < 8; i++) {
1127 smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
1128 }
1129 }
1130
1131 if (i440fx_state) {
1132 i440fx_init_memory_mappings(i440fx_state);
1133 }
1134
1135 if (pci_enabled) {
1136 int max_bus;
1137 int bus, unit;
1138 void *scsi;
1139
1140 max_bus = drive_get_max_bus(IF_SCSI);
1141
1142 for (bus = 0; bus <= max_bus; bus++) {
1143 scsi = lsi_scsi_init(pci_bus, -1);
1144 for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
1145 index = drive_get_index(IF_SCSI, bus, unit);
1146 if (index == -1)
1147 continue;
1148 lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
1149 }
1150 }
1151 }
1152
1153 /* Add virtio block devices */
1154 if (pci_enabled) {
1155 int index;
1156 int unit_id = 0;
1157
1158 while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
1159 virtio_blk_init(pci_bus, drives_table[index].bdrv);
1160 unit_id++;
1161 }
1162 }
1163
1164 if (extboot_drive != -1) {
1165 DriveInfo *info = &drives_table[extboot_drive];
1166 int cyls, heads, secs;
1167
1168 if (info->type != IF_IDE && info->type != IF_VIRTIO) {
1169 bdrv_guess_geometry(info->bdrv, &cyls, &heads, &secs);
1170 bdrv_set_geometry_hint(info->bdrv, cyls, heads, secs);
1171 }
1172
1173 extboot_init(info->bdrv, 1);
1174 }
1175
1176 /* Add virtio balloon device */
1177 if (pci_enabled)
1178 virtio_balloon_init(pci_bus);
1179
1180 /* Add virtio console devices */
1181 if (pci_enabled) {
1182 for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1183 if (virtcon_hds[i])
1184 virtio_console_init(pci_bus, virtcon_hds[i]);
1185 }
1186 }
1187
1188 #ifdef USE_KVM_DEVICE_ASSIGNMENT
1189 if (kvm_enabled()) {
1190 add_assigned_devices(pci_bus, assigned_devices, assigned_devices_index);
1191 assigned_dev_load_option_roms(pci_option_rom_offset);
1192 }
1193 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
1194 }
1195
1196 static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
1197 const char *boot_device,
1198 const char *kernel_filename,
1199 const char *kernel_cmdline,
1200 const char *initrd_filename,
1201 const char *cpu_model)
1202 {
1203 pc_init1(ram_size, vga_ram_size, boot_device,
1204 kernel_filename, kernel_cmdline,
1205 initrd_filename, 1, cpu_model);
1206 }
1207
1208 static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
1209 const char *boot_device,
1210 const char *kernel_filename,
1211 const char *kernel_cmdline,
1212 const char *initrd_filename,
1213 const char *cpu_model)
1214 {
1215 pc_init1(ram_size, vga_ram_size, boot_device,
1216 kernel_filename, kernel_cmdline,
1217 initrd_filename, 0, cpu_model);
1218 }
1219
1220 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1221 BIOS will read it and start S3 resume at POST Entry */
1222 void cmos_set_s3_resume(void)
1223 {
1224 if (rtc_state)
1225 rtc_set_memory(rtc_state, 0xF, 0xFE);
1226 }
1227
1228 QEMUMachine pc_machine = {
1229 .name = "pc",
1230 .desc = "Standard PC",
1231 .init = pc_init_pci,
1232 .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1233 .max_cpus = 255,
1234 };
1235
1236 QEMUMachine isapc_machine = {
1237 .name = "isapc",
1238 .desc = "ISA-only PC",
1239 .init = pc_init_isa,
1240 .ram_require = VGA_RAM_SIZE + PC_MAX_BIOS_SIZE,
1241 .max_cpus = 1,
1242 };
Patches shipped by Fedora