2 * QEMU Cirrus CLGD 54xx VGA Emulator.
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
39 * - destination write mask support not complete (bits 5..7)
40 * - optimize linear mappings
41 * - optimize bitblt functions
44 //#define DEBUG_CIRRUS
45 //#define DEBUG_BITBLT
47 /***************************************
51 ***************************************/
53 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
178 #define PCI_DEVICE_CLGD5462 0x00d0
179 #define PCI_DEVICE_CLGD5465 0x00d6
181 // PCI 0x04: command(word), 0x06(word): status
182 #define PCI_COMMAND_IOACCESS 0x0001
183 #define PCI_COMMAND_MEMACCESS 0x0002
184 #define PCI_COMMAND_BUSMASTER 0x0004
185 #define PCI_COMMAND_SPECIALCYCLE 0x0008
186 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
187 #define PCI_COMMAND_PALETTESNOOPING 0x0020
188 #define PCI_COMMAND_PARITYDETECTION 0x0040
189 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
190 #define PCI_COMMAND_SERR 0x0100
191 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
192 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
193 #define PCI_CLASS_BASE_DISPLAY 0x03
194 // PCI 0x08, 0x00ff0000
195 #define PCI_CLASS_SUB_VGA 0x00
196 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
197 #define PCI_CLASS_HEADERTYPE_00h 0x00
198 // 0x10-0x3f (headertype 00h)
199 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
200 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
201 #define PCI_MAP_MEM 0x0
202 #define PCI_MAP_IO 0x1
203 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
204 #define PCI_MAP_IO_ADDR_MASK (~0x3)
205 #define PCI_MAP_MEMFLAGS_32BIT 0x0
206 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
207 #define PCI_MAP_MEMFLAGS_64BIT 0x4
208 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
209 // PCI 0x28: cardbus CIS pointer
210 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
211 // PCI 0x30: expansion ROM base address
212 #define PCI_ROMBIOS_ENABLED 0x1
213 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
214 // PCI 0x38: reserved
215 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
217 #define CIRRUS_PNPMMIO_SIZE 0x1000
220 /* I/O and memory hook */
221 #define CIRRUS_HOOK_NOT_HANDLED 0
222 #define CIRRUS_HOOK_HANDLED 1
224 #define ABS(a) ((signed)(a) > 0 ? a : -a)
226 #define BLTUNSAFE(s) \
228 ( /* check dst is within bounds */ \
229 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
230 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
233 ( /* check src is within bounds */ \
234 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
235 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
240 struct CirrusVGAState
;
241 typedef void (*cirrus_bitblt_rop_t
) (struct CirrusVGAState
*s
,
242 uint8_t * dst
, const uint8_t * src
,
243 int dstpitch
, int srcpitch
,
244 int bltwidth
, int bltheight
);
245 typedef void (*cirrus_fill_t
)(struct CirrusVGAState
*s
,
246 uint8_t *dst
, int dst_pitch
, int width
, int height
);
248 typedef struct CirrusVGAState
{
251 int cirrus_linear_io_addr
;
252 int cirrus_linear_bitblt_io_addr
;
253 int cirrus_mmio_io_addr
;
254 uint32_t cirrus_addr_mask
;
255 uint32_t linear_mmio_mask
;
256 uint8_t cirrus_shadow_gr0
;
257 uint8_t cirrus_shadow_gr1
;
258 uint8_t cirrus_hidden_dac_lockindex
;
259 uint8_t cirrus_hidden_dac_data
;
260 uint32_t cirrus_bank_base
[2];
261 uint32_t cirrus_bank_limit
[2];
262 uint8_t cirrus_hidden_palette
[48];
263 uint32_t hw_cursor_x
;
264 uint32_t hw_cursor_y
;
265 int cirrus_blt_pixelwidth
;
266 int cirrus_blt_width
;
267 int cirrus_blt_height
;
268 int cirrus_blt_dstpitch
;
269 int cirrus_blt_srcpitch
;
270 uint32_t cirrus_blt_fgcol
;
271 uint32_t cirrus_blt_bgcol
;
272 uint32_t cirrus_blt_dstaddr
;
273 uint32_t cirrus_blt_srcaddr
;
274 uint8_t cirrus_blt_mode
;
275 uint8_t cirrus_blt_modeext
;
276 cirrus_bitblt_rop_t cirrus_rop
;
277 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
278 uint8_t cirrus_bltbuf
[CIRRUS_BLTBUFSIZE
];
279 uint8_t *cirrus_srcptr
;
280 uint8_t *cirrus_srcptr_end
;
281 uint32_t cirrus_srccounter
;
282 /* hwcursor display state */
283 int last_hw_cursor_size
;
284 int last_hw_cursor_x
;
285 int last_hw_cursor_y
;
286 int last_hw_cursor_y_start
;
287 int last_hw_cursor_y_end
;
288 int real_vram_size
; /* XXX: suppress that */
289 CPUWriteMemoryFunc
**cirrus_linear_write
;
294 typedef struct PCICirrusVGAState
{
296 CirrusVGAState cirrus_vga
;
299 static uint8_t rop_to_index
[256];
301 /***************************************
305 ***************************************/
308 static void cirrus_bitblt_reset(CirrusVGAState
*s
);
309 static void cirrus_update_memory_access(CirrusVGAState
*s
);
311 /***************************************
315 ***************************************/
317 static void cirrus_bitblt_rop_nop(CirrusVGAState
*s
,
318 uint8_t *dst
,const uint8_t *src
,
319 int dstpitch
,int srcpitch
,
320 int bltwidth
,int bltheight
)
324 static void cirrus_bitblt_fill_nop(CirrusVGAState
*s
,
326 int dstpitch
, int bltwidth
,int bltheight
)
331 #define ROP_OP(d, s) d = 0
332 #include "cirrus_vga_rop.h"
334 #define ROP_NAME src_and_dst
335 #define ROP_OP(d, s) d = (s) & (d)
336 #include "cirrus_vga_rop.h"
338 #define ROP_NAME src_and_notdst
339 #define ROP_OP(d, s) d = (s) & (~(d))
340 #include "cirrus_vga_rop.h"
342 #define ROP_NAME notdst
343 #define ROP_OP(d, s) d = ~(d)
344 #include "cirrus_vga_rop.h"
347 #define ROP_OP(d, s) d = s
348 #include "cirrus_vga_rop.h"
351 #define ROP_OP(d, s) d = ~0
352 #include "cirrus_vga_rop.h"
354 #define ROP_NAME notsrc_and_dst
355 #define ROP_OP(d, s) d = (~(s)) & (d)
356 #include "cirrus_vga_rop.h"
358 #define ROP_NAME src_xor_dst
359 #define ROP_OP(d, s) d = (s) ^ (d)
360 #include "cirrus_vga_rop.h"
362 #define ROP_NAME src_or_dst
363 #define ROP_OP(d, s) d = (s) | (d)
364 #include "cirrus_vga_rop.h"
366 #define ROP_NAME notsrc_or_notdst
367 #define ROP_OP(d, s) d = (~(s)) | (~(d))
368 #include "cirrus_vga_rop.h"
370 #define ROP_NAME src_notxor_dst
371 #define ROP_OP(d, s) d = ~((s) ^ (d))
372 #include "cirrus_vga_rop.h"
374 #define ROP_NAME src_or_notdst
375 #define ROP_OP(d, s) d = (s) | (~(d))
376 #include "cirrus_vga_rop.h"
378 #define ROP_NAME notsrc
379 #define ROP_OP(d, s) d = (~(s))
380 #include "cirrus_vga_rop.h"
382 #define ROP_NAME notsrc_or_dst
383 #define ROP_OP(d, s) d = (~(s)) | (d)
384 #include "cirrus_vga_rop.h"
386 #define ROP_NAME notsrc_and_notdst
387 #define ROP_OP(d, s) d = (~(s)) & (~(d))
388 #include "cirrus_vga_rop.h"
390 static const cirrus_bitblt_rop_t cirrus_fwd_rop
[16] = {
391 cirrus_bitblt_rop_fwd_0
,
392 cirrus_bitblt_rop_fwd_src_and_dst
,
393 cirrus_bitblt_rop_nop
,
394 cirrus_bitblt_rop_fwd_src_and_notdst
,
395 cirrus_bitblt_rop_fwd_notdst
,
396 cirrus_bitblt_rop_fwd_src
,
397 cirrus_bitblt_rop_fwd_1
,
398 cirrus_bitblt_rop_fwd_notsrc_and_dst
,
399 cirrus_bitblt_rop_fwd_src_xor_dst
,
400 cirrus_bitblt_rop_fwd_src_or_dst
,
401 cirrus_bitblt_rop_fwd_notsrc_or_notdst
,
402 cirrus_bitblt_rop_fwd_src_notxor_dst
,
403 cirrus_bitblt_rop_fwd_src_or_notdst
,
404 cirrus_bitblt_rop_fwd_notsrc
,
405 cirrus_bitblt_rop_fwd_notsrc_or_dst
,
406 cirrus_bitblt_rop_fwd_notsrc_and_notdst
,
409 static const cirrus_bitblt_rop_t cirrus_bkwd_rop
[16] = {
410 cirrus_bitblt_rop_bkwd_0
,
411 cirrus_bitblt_rop_bkwd_src_and_dst
,
412 cirrus_bitblt_rop_nop
,
413 cirrus_bitblt_rop_bkwd_src_and_notdst
,
414 cirrus_bitblt_rop_bkwd_notdst
,
415 cirrus_bitblt_rop_bkwd_src
,
416 cirrus_bitblt_rop_bkwd_1
,
417 cirrus_bitblt_rop_bkwd_notsrc_and_dst
,
418 cirrus_bitblt_rop_bkwd_src_xor_dst
,
419 cirrus_bitblt_rop_bkwd_src_or_dst
,
420 cirrus_bitblt_rop_bkwd_notsrc_or_notdst
,
421 cirrus_bitblt_rop_bkwd_src_notxor_dst
,
422 cirrus_bitblt_rop_bkwd_src_or_notdst
,
423 cirrus_bitblt_rop_bkwd_notsrc
,
424 cirrus_bitblt_rop_bkwd_notsrc_or_dst
,
425 cirrus_bitblt_rop_bkwd_notsrc_and_notdst
,
428 #define TRANSP_ROP(name) {\
432 #define TRANSP_NOP(func) {\
437 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop
[16][2] = {
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0
),
439 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst
),
440 TRANSP_NOP(cirrus_bitblt_rop_nop
),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst
),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst
),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src
),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1
),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst
),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst
),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst
),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst
),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst
),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst
),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc
),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst
),
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst
),
456 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop
[16][2] = {
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0
),
458 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst
),
459 TRANSP_NOP(cirrus_bitblt_rop_nop
),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst
),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst
),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src
),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1
),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst
),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst
),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst
),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst
),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst
),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst
),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc
),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst
),
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst
),
475 #define ROP2(name) {\
482 #define ROP_NOP2(func) {\
489 static const cirrus_bitblt_rop_t cirrus_patternfill
[16][4] = {
490 ROP2(cirrus_patternfill_0
),
491 ROP2(cirrus_patternfill_src_and_dst
),
492 ROP_NOP2(cirrus_bitblt_rop_nop
),
493 ROP2(cirrus_patternfill_src_and_notdst
),
494 ROP2(cirrus_patternfill_notdst
),
495 ROP2(cirrus_patternfill_src
),
496 ROP2(cirrus_patternfill_1
),
497 ROP2(cirrus_patternfill_notsrc_and_dst
),
498 ROP2(cirrus_patternfill_src_xor_dst
),
499 ROP2(cirrus_patternfill_src_or_dst
),
500 ROP2(cirrus_patternfill_notsrc_or_notdst
),
501 ROP2(cirrus_patternfill_src_notxor_dst
),
502 ROP2(cirrus_patternfill_src_or_notdst
),
503 ROP2(cirrus_patternfill_notsrc
),
504 ROP2(cirrus_patternfill_notsrc_or_dst
),
505 ROP2(cirrus_patternfill_notsrc_and_notdst
),
508 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp
[16][4] = {
509 ROP2(cirrus_colorexpand_transp_0
),
510 ROP2(cirrus_colorexpand_transp_src_and_dst
),
511 ROP_NOP2(cirrus_bitblt_rop_nop
),
512 ROP2(cirrus_colorexpand_transp_src_and_notdst
),
513 ROP2(cirrus_colorexpand_transp_notdst
),
514 ROP2(cirrus_colorexpand_transp_src
),
515 ROP2(cirrus_colorexpand_transp_1
),
516 ROP2(cirrus_colorexpand_transp_notsrc_and_dst
),
517 ROP2(cirrus_colorexpand_transp_src_xor_dst
),
518 ROP2(cirrus_colorexpand_transp_src_or_dst
),
519 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst
),
520 ROP2(cirrus_colorexpand_transp_src_notxor_dst
),
521 ROP2(cirrus_colorexpand_transp_src_or_notdst
),
522 ROP2(cirrus_colorexpand_transp_notsrc
),
523 ROP2(cirrus_colorexpand_transp_notsrc_or_dst
),
524 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst
),
527 static const cirrus_bitblt_rop_t cirrus_colorexpand
[16][4] = {
528 ROP2(cirrus_colorexpand_0
),
529 ROP2(cirrus_colorexpand_src_and_dst
),
530 ROP_NOP2(cirrus_bitblt_rop_nop
),
531 ROP2(cirrus_colorexpand_src_and_notdst
),
532 ROP2(cirrus_colorexpand_notdst
),
533 ROP2(cirrus_colorexpand_src
),
534 ROP2(cirrus_colorexpand_1
),
535 ROP2(cirrus_colorexpand_notsrc_and_dst
),
536 ROP2(cirrus_colorexpand_src_xor_dst
),
537 ROP2(cirrus_colorexpand_src_or_dst
),
538 ROP2(cirrus_colorexpand_notsrc_or_notdst
),
539 ROP2(cirrus_colorexpand_src_notxor_dst
),
540 ROP2(cirrus_colorexpand_src_or_notdst
),
541 ROP2(cirrus_colorexpand_notsrc
),
542 ROP2(cirrus_colorexpand_notsrc_or_dst
),
543 ROP2(cirrus_colorexpand_notsrc_and_notdst
),
546 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp
[16][4] = {
547 ROP2(cirrus_colorexpand_pattern_transp_0
),
548 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst
),
549 ROP_NOP2(cirrus_bitblt_rop_nop
),
550 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst
),
551 ROP2(cirrus_colorexpand_pattern_transp_notdst
),
552 ROP2(cirrus_colorexpand_pattern_transp_src
),
553 ROP2(cirrus_colorexpand_pattern_transp_1
),
554 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst
),
555 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst
),
556 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst
),
557 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst
),
558 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst
),
559 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst
),
560 ROP2(cirrus_colorexpand_pattern_transp_notsrc
),
561 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst
),
562 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst
),
565 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern
[16][4] = {
566 ROP2(cirrus_colorexpand_pattern_0
),
567 ROP2(cirrus_colorexpand_pattern_src_and_dst
),
568 ROP_NOP2(cirrus_bitblt_rop_nop
),
569 ROP2(cirrus_colorexpand_pattern_src_and_notdst
),
570 ROP2(cirrus_colorexpand_pattern_notdst
),
571 ROP2(cirrus_colorexpand_pattern_src
),
572 ROP2(cirrus_colorexpand_pattern_1
),
573 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst
),
574 ROP2(cirrus_colorexpand_pattern_src_xor_dst
),
575 ROP2(cirrus_colorexpand_pattern_src_or_dst
),
576 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst
),
577 ROP2(cirrus_colorexpand_pattern_src_notxor_dst
),
578 ROP2(cirrus_colorexpand_pattern_src_or_notdst
),
579 ROP2(cirrus_colorexpand_pattern_notsrc
),
580 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst
),
581 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst
),
584 static const cirrus_fill_t cirrus_fill
[16][4] = {
586 ROP2(cirrus_fill_src_and_dst
),
587 ROP_NOP2(cirrus_bitblt_fill_nop
),
588 ROP2(cirrus_fill_src_and_notdst
),
589 ROP2(cirrus_fill_notdst
),
590 ROP2(cirrus_fill_src
),
592 ROP2(cirrus_fill_notsrc_and_dst
),
593 ROP2(cirrus_fill_src_xor_dst
),
594 ROP2(cirrus_fill_src_or_dst
),
595 ROP2(cirrus_fill_notsrc_or_notdst
),
596 ROP2(cirrus_fill_src_notxor_dst
),
597 ROP2(cirrus_fill_src_or_notdst
),
598 ROP2(cirrus_fill_notsrc
),
599 ROP2(cirrus_fill_notsrc_or_dst
),
600 ROP2(cirrus_fill_notsrc_and_notdst
),
603 static inline void cirrus_bitblt_fgcol(CirrusVGAState
*s
)
606 switch (s
->cirrus_blt_pixelwidth
) {
608 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
;
611 color
= s
->cirrus_shadow_gr1
| (s
->gr
[0x11] << 8);
612 s
->cirrus_blt_fgcol
= le16_to_cpu(color
);
615 s
->cirrus_blt_fgcol
= s
->cirrus_shadow_gr1
|
616 (s
->gr
[0x11] << 8) | (s
->gr
[0x13] << 16);
620 color
= s
->cirrus_shadow_gr1
| (s
->gr
[0x11] << 8) |
621 (s
->gr
[0x13] << 16) | (s
->gr
[0x15] << 24);
622 s
->cirrus_blt_fgcol
= le32_to_cpu(color
);
627 static inline void cirrus_bitblt_bgcol(CirrusVGAState
*s
)
630 switch (s
->cirrus_blt_pixelwidth
) {
632 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
;
635 color
= s
->cirrus_shadow_gr0
| (s
->gr
[0x10] << 8);
636 s
->cirrus_blt_bgcol
= le16_to_cpu(color
);
639 s
->cirrus_blt_bgcol
= s
->cirrus_shadow_gr0
|
640 (s
->gr
[0x10] << 8) | (s
->gr
[0x12] << 16);
644 color
= s
->cirrus_shadow_gr0
| (s
->gr
[0x10] << 8) |
645 (s
->gr
[0x12] << 16) | (s
->gr
[0x14] << 24);
646 s
->cirrus_blt_bgcol
= le32_to_cpu(color
);
651 static void cirrus_invalidate_region(CirrusVGAState
* s
, int off_begin
,
652 int off_pitch
, int bytesperline
,
659 for (y
= 0; y
< lines
; y
++) {
661 off_cur_end
= (off_cur
+ bytesperline
) & s
->cirrus_addr_mask
;
662 off_cur
&= TARGET_PAGE_MASK
;
663 while (off_cur
< off_cur_end
) {
664 cpu_physical_memory_set_dirty(s
->vram_offset
+ off_cur
);
665 off_cur
+= TARGET_PAGE_SIZE
;
667 off_begin
+= off_pitch
;
671 static int cirrus_bitblt_common_patterncopy(CirrusVGAState
* s
,
676 dst
= s
->vram_ptr
+ (s
->cirrus_blt_dstaddr
& s
->cirrus_addr_mask
);
681 (*s
->cirrus_rop
) (s
, dst
, src
,
682 s
->cirrus_blt_dstpitch
, 0,
683 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
684 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
685 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
686 s
->cirrus_blt_height
);
692 static int cirrus_bitblt_solidfill(CirrusVGAState
*s
, int blt_rop
)
694 cirrus_fill_t rop_func
;
698 rop_func
= cirrus_fill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
699 rop_func(s
, s
->vram_ptr
+ (s
->cirrus_blt_dstaddr
& s
->cirrus_addr_mask
),
700 s
->cirrus_blt_dstpitch
,
701 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
702 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
703 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
704 s
->cirrus_blt_height
);
705 cirrus_bitblt_reset(s
);
709 /***************************************
711 * bitblt (video-to-video)
713 ***************************************/
715 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState
* s
)
717 return cirrus_bitblt_common_patterncopy(s
,
718 s
->vram_ptr
+ ((s
->cirrus_blt_srcaddr
& ~7) &
719 s
->cirrus_addr_mask
));
722 static void cirrus_do_copy(CirrusVGAState
*s
, int dst
, int src
, int w
, int h
)
730 depth
= s
->get_bpp((VGAState
*)s
) / 8;
731 s
->get_resolution((VGAState
*)s
, &width
, &height
);
734 sx
= (src
% (width
* depth
)) / depth
;
735 sy
= (src
/ (width
* depth
));
736 dx
= (dst
% (width
*depth
)) / depth
;
737 dy
= (dst
/ (width
* depth
));
739 /* normalize width */
742 /* if we're doing a backward copy, we have to adjust
743 our x/y to be the upper left corner (instead of the lower
745 if (s
->cirrus_blt_dstpitch
< 0) {
746 sx
-= (s
->cirrus_blt_width
/ depth
) - 1;
747 dx
-= (s
->cirrus_blt_width
/ depth
) - 1;
748 sy
-= s
->cirrus_blt_height
- 1;
749 dy
-= s
->cirrus_blt_height
- 1;
752 /* are we in the visible portion of memory? */
753 if (sx
>= 0 && sy
>= 0 && dx
>= 0 && dy
>= 0 &&
754 (sx
+ w
) <= width
&& (sy
+ h
) <= height
&&
755 (dx
+ w
) <= width
&& (dy
+ h
) <= height
) {
759 /* make to sure only copy if it's a plain copy ROP */
760 if (*s
->cirrus_rop
!= cirrus_bitblt_rop_fwd_src
&&
761 *s
->cirrus_rop
!= cirrus_bitblt_rop_bkwd_src
)
764 /* we have to flush all pending changes so that the copy
765 is generated at the appropriate moment in time */
769 (*s
->cirrus_rop
) (s
, s
->vram_ptr
+
770 (s
->cirrus_blt_dstaddr
& s
->cirrus_addr_mask
),
772 (s
->cirrus_blt_srcaddr
& s
->cirrus_addr_mask
),
773 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_srcpitch
,
774 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
777 qemu_console_copy(s
->ds
,
779 s
->cirrus_blt_width
/ depth
,
780 s
->cirrus_blt_height
);
782 /* we don't have to notify the display that this portion has
783 changed since qemu_console_copy implies this */
786 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
,
787 s
->cirrus_blt_dstpitch
, s
->cirrus_blt_width
,
788 s
->cirrus_blt_height
);
791 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState
* s
)
796 cirrus_do_copy(s
, s
->cirrus_blt_dstaddr
- s
->start_addr
,
797 s
->cirrus_blt_srcaddr
- s
->start_addr
,
798 s
->cirrus_blt_width
, s
->cirrus_blt_height
);
803 /***************************************
805 * bitblt (cpu-to-video)
807 ***************************************/
809 static void cirrus_bitblt_cputovideo_next(CirrusVGAState
* s
)
814 if (s
->cirrus_srccounter
> 0) {
815 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
816 cirrus_bitblt_common_patterncopy(s
, s
->cirrus_bltbuf
);
818 s
->cirrus_srccounter
= 0;
819 cirrus_bitblt_reset(s
);
821 /* at least one scan line */
823 (*s
->cirrus_rop
)(s
, s
->vram_ptr
+
824 (s
->cirrus_blt_dstaddr
& s
->cirrus_addr_mask
),
825 s
->cirrus_bltbuf
, 0, 0, s
->cirrus_blt_width
, 1);
826 cirrus_invalidate_region(s
, s
->cirrus_blt_dstaddr
, 0,
827 s
->cirrus_blt_width
, 1);
828 s
->cirrus_blt_dstaddr
+= s
->cirrus_blt_dstpitch
;
829 s
->cirrus_srccounter
-= s
->cirrus_blt_srcpitch
;
830 if (s
->cirrus_srccounter
<= 0)
832 /* more bytes than needed can be transfered because of
833 word alignment, so we keep them for the next line */
834 /* XXX: keep alignment to speed up transfer */
835 end_ptr
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
836 copy_count
= s
->cirrus_srcptr_end
- end_ptr
;
837 memmove(s
->cirrus_bltbuf
, end_ptr
, copy_count
);
838 s
->cirrus_srcptr
= s
->cirrus_bltbuf
+ copy_count
;
839 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
840 } while (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
);
845 /***************************************
849 ***************************************/
851 static void cirrus_bitblt_reset(CirrusVGAState
* s
)
856 ~(CIRRUS_BLT_START
| CIRRUS_BLT_BUSY
| CIRRUS_BLT_FIFOUSED
);
857 need_update
= s
->cirrus_srcptr
!= &s
->cirrus_bltbuf
[0]
858 || s
->cirrus_srcptr_end
!= &s
->cirrus_bltbuf
[0];
859 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
860 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
861 s
->cirrus_srccounter
= 0;
864 cirrus_update_memory_access(s
);
867 static int cirrus_bitblt_cputovideo(CirrusVGAState
* s
)
871 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_MEMSYSSRC
;
872 s
->cirrus_srcptr
= &s
->cirrus_bltbuf
[0];
873 s
->cirrus_srcptr_end
= &s
->cirrus_bltbuf
[0];
875 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
876 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
877 s
->cirrus_blt_srcpitch
= 8;
879 /* XXX: check for 24 bpp */
880 s
->cirrus_blt_srcpitch
= 8 * 8 * s
->cirrus_blt_pixelwidth
;
882 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
;
884 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
885 w
= s
->cirrus_blt_width
/ s
->cirrus_blt_pixelwidth
;
886 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_DWORDGRANULARITY
)
887 s
->cirrus_blt_srcpitch
= ((w
+ 31) >> 5);
889 s
->cirrus_blt_srcpitch
= ((w
+ 7) >> 3);
891 /* always align input size to 32 bits */
892 s
->cirrus_blt_srcpitch
= (s
->cirrus_blt_width
+ 3) & ~3;
894 s
->cirrus_srccounter
= s
->cirrus_blt_srcpitch
* s
->cirrus_blt_height
;
896 s
->cirrus_srcptr
= s
->cirrus_bltbuf
;
897 s
->cirrus_srcptr_end
= s
->cirrus_bltbuf
+ s
->cirrus_blt_srcpitch
;
898 cirrus_update_memory_access(s
);
902 static int cirrus_bitblt_videotocpu(CirrusVGAState
* s
)
906 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
911 static int cirrus_bitblt_videotovideo(CirrusVGAState
* s
)
915 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
916 ret
= cirrus_bitblt_videotovideo_patterncopy(s
);
918 ret
= cirrus_bitblt_videotovideo_copy(s
);
921 cirrus_bitblt_reset(s
);
925 static void cirrus_bitblt_start(CirrusVGAState
* s
)
929 s
->gr
[0x31] |= CIRRUS_BLT_BUSY
;
931 s
->cirrus_blt_width
= (s
->gr
[0x20] | (s
->gr
[0x21] << 8)) + 1;
932 s
->cirrus_blt_height
= (s
->gr
[0x22] | (s
->gr
[0x23] << 8)) + 1;
933 s
->cirrus_blt_dstpitch
= (s
->gr
[0x24] | (s
->gr
[0x25] << 8));
934 s
->cirrus_blt_srcpitch
= (s
->gr
[0x26] | (s
->gr
[0x27] << 8));
935 s
->cirrus_blt_dstaddr
=
936 (s
->gr
[0x28] | (s
->gr
[0x29] << 8) | (s
->gr
[0x2a] << 16));
937 s
->cirrus_blt_srcaddr
=
938 (s
->gr
[0x2c] | (s
->gr
[0x2d] << 8) | (s
->gr
[0x2e] << 16));
939 s
->cirrus_blt_mode
= s
->gr
[0x30];
940 s
->cirrus_blt_modeext
= s
->gr
[0x33];
941 blt_rop
= s
->gr
[0x32];
944 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
947 s
->cirrus_blt_modeext
,
949 s
->cirrus_blt_height
,
950 s
->cirrus_blt_dstpitch
,
951 s
->cirrus_blt_srcpitch
,
952 s
->cirrus_blt_dstaddr
,
953 s
->cirrus_blt_srcaddr
,
957 switch (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PIXELWIDTHMASK
) {
958 case CIRRUS_BLTMODE_PIXELWIDTH8
:
959 s
->cirrus_blt_pixelwidth
= 1;
961 case CIRRUS_BLTMODE_PIXELWIDTH16
:
962 s
->cirrus_blt_pixelwidth
= 2;
964 case CIRRUS_BLTMODE_PIXELWIDTH24
:
965 s
->cirrus_blt_pixelwidth
= 3;
967 case CIRRUS_BLTMODE_PIXELWIDTH32
:
968 s
->cirrus_blt_pixelwidth
= 4;
972 printf("cirrus: bitblt - pixel width is unknown\n");
976 s
->cirrus_blt_mode
&= ~CIRRUS_BLTMODE_PIXELWIDTHMASK
;
979 cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSSRC
|
980 CIRRUS_BLTMODE_MEMSYSDEST
))
981 == (CIRRUS_BLTMODE_MEMSYSSRC
| CIRRUS_BLTMODE_MEMSYSDEST
)) {
983 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
988 if ((s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_SOLIDFILL
) &&
989 (s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_MEMSYSDEST
|
990 CIRRUS_BLTMODE_TRANSPARENTCOMP
|
991 CIRRUS_BLTMODE_PATTERNCOPY
|
992 CIRRUS_BLTMODE_COLOREXPAND
)) ==
993 (CIRRUS_BLTMODE_PATTERNCOPY
| CIRRUS_BLTMODE_COLOREXPAND
)) {
994 cirrus_bitblt_fgcol(s
);
995 cirrus_bitblt_solidfill(s
, blt_rop
);
997 if ((s
->cirrus_blt_mode
& (CIRRUS_BLTMODE_COLOREXPAND
|
998 CIRRUS_BLTMODE_PATTERNCOPY
)) ==
999 CIRRUS_BLTMODE_COLOREXPAND
) {
1001 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1002 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
1003 cirrus_bitblt_bgcol(s
);
1005 cirrus_bitblt_fgcol(s
);
1006 s
->cirrus_rop
= cirrus_colorexpand_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1008 cirrus_bitblt_fgcol(s
);
1009 cirrus_bitblt_bgcol(s
);
1010 s
->cirrus_rop
= cirrus_colorexpand
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1012 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_PATTERNCOPY
) {
1013 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_COLOREXPAND
) {
1014 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1015 if (s
->cirrus_blt_modeext
& CIRRUS_BLTMODEEXT_COLOREXPINV
)
1016 cirrus_bitblt_bgcol(s
);
1018 cirrus_bitblt_fgcol(s
);
1019 s
->cirrus_rop
= cirrus_colorexpand_pattern_transp
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1021 cirrus_bitblt_fgcol(s
);
1022 cirrus_bitblt_bgcol(s
);
1023 s
->cirrus_rop
= cirrus_colorexpand_pattern
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1026 s
->cirrus_rop
= cirrus_patternfill
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1029 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_TRANSPARENTCOMP
) {
1030 if (s
->cirrus_blt_pixelwidth
> 2) {
1031 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1034 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
1035 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
1036 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
1037 s
->cirrus_rop
= cirrus_bkwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1039 s
->cirrus_rop
= cirrus_fwd_transp_rop
[rop_to_index
[blt_rop
]][s
->cirrus_blt_pixelwidth
- 1];
1042 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_BACKWARDS
) {
1043 s
->cirrus_blt_dstpitch
= -s
->cirrus_blt_dstpitch
;
1044 s
->cirrus_blt_srcpitch
= -s
->cirrus_blt_srcpitch
;
1045 s
->cirrus_rop
= cirrus_bkwd_rop
[rop_to_index
[blt_rop
]];
1047 s
->cirrus_rop
= cirrus_fwd_rop
[rop_to_index
[blt_rop
]];
1051 // setup bitblt engine.
1052 if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSSRC
) {
1053 if (!cirrus_bitblt_cputovideo(s
))
1055 } else if (s
->cirrus_blt_mode
& CIRRUS_BLTMODE_MEMSYSDEST
) {
1056 if (!cirrus_bitblt_videotocpu(s
))
1059 if (!cirrus_bitblt_videotovideo(s
))
1065 cirrus_bitblt_reset(s
);
1068 static void cirrus_write_bitblt(CirrusVGAState
* s
, unsigned reg_value
)
1072 old_value
= s
->gr
[0x31];
1073 s
->gr
[0x31] = reg_value
;
1075 if (((old_value
& CIRRUS_BLT_RESET
) != 0) &&
1076 ((reg_value
& CIRRUS_BLT_RESET
) == 0)) {
1077 cirrus_bitblt_reset(s
);
1078 } else if (((old_value
& CIRRUS_BLT_START
) == 0) &&
1079 ((reg_value
& CIRRUS_BLT_START
) != 0)) {
1080 cirrus_bitblt_start(s
);
1085 /***************************************
1089 ***************************************/
1091 static void cirrus_get_offsets(VGAState
*s1
,
1092 uint32_t *pline_offset
,
1093 uint32_t *pstart_addr
,
1094 uint32_t *pline_compare
)
1096 CirrusVGAState
* s
= (CirrusVGAState
*)s1
;
1097 uint32_t start_addr
, line_offset
, line_compare
;
1099 line_offset
= s
->cr
[0x13]
1100 | ((s
->cr
[0x1b] & 0x10) << 4);
1102 *pline_offset
= line_offset
;
1104 start_addr
= (s
->cr
[0x0c] << 8)
1106 | ((s
->cr
[0x1b] & 0x01) << 16)
1107 | ((s
->cr
[0x1b] & 0x0c) << 15)
1108 | ((s
->cr
[0x1d] & 0x80) << 12);
1109 *pstart_addr
= start_addr
;
1111 line_compare
= s
->cr
[0x18] |
1112 ((s
->cr
[0x07] & 0x10) << 4) |
1113 ((s
->cr
[0x09] & 0x40) << 3);
1114 *pline_compare
= line_compare
;
1117 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState
* s
)
1121 switch (s
->cirrus_hidden_dac_data
& 0xf) {
1124 break; /* Sierra HiColor */
1127 break; /* XGA HiColor */
1130 printf("cirrus: invalid DAC value %x in 16bpp\n",
1131 (s
->cirrus_hidden_dac_data
& 0xf));
1139 static int cirrus_get_bpp(VGAState
*s1
)
1141 CirrusVGAState
* s
= (CirrusVGAState
*)s1
;
1144 if ((s
->sr
[0x07] & 0x01) != 0) {
1146 switch (s
->sr
[0x07] & CIRRUS_SR7_BPP_MASK
) {
1147 case CIRRUS_SR7_BPP_8
:
1150 case CIRRUS_SR7_BPP_16_DOUBLEVCLK
:
1151 ret
= cirrus_get_bpp16_depth(s
);
1153 case CIRRUS_SR7_BPP_24
:
1156 case CIRRUS_SR7_BPP_16
:
1157 ret
= cirrus_get_bpp16_depth(s
);
1159 case CIRRUS_SR7_BPP_32
:
1164 printf("cirrus: unknown bpp - sr7=%x\n", s
->sr
[0x7]);
1177 static void cirrus_get_resolution(VGAState
*s
, int *pwidth
, int *pheight
)
1181 width
= (s
->cr
[0x01] + 1) * 8;
1182 height
= s
->cr
[0x12] |
1183 ((s
->cr
[0x07] & 0x02) << 7) |
1184 ((s
->cr
[0x07] & 0x40) << 3);
1185 height
= (height
+ 1);
1186 /* interlace support */
1187 if (s
->cr
[0x1a] & 0x01)
1188 height
= height
* 2;
1193 /***************************************
1197 ***************************************/
1199 static void cirrus_update_bank_ptr(CirrusVGAState
* s
, unsigned bank_index
)
1204 if ((s
->gr
[0x0b] & 0x01) != 0) /* dual bank */
1205 offset
= s
->gr
[0x09 + bank_index
];
1206 else /* single bank */
1207 offset
= s
->gr
[0x09];
1209 if ((s
->gr
[0x0b] & 0x20) != 0)
1214 if (s
->real_vram_size
<= offset
)
1217 limit
= s
->real_vram_size
- offset
;
1219 if (((s
->gr
[0x0b] & 0x01) == 0) && (bank_index
!= 0)) {
1220 if (limit
> 0x8000) {
1229 /* Thinking about changing bank base? First, drop the dirty bitmap information
1230 * on the current location, otherwise we lose this pointer forever */
1231 if (s
->lfb_vram_mapped
) {
1232 target_phys_addr_t base_addr
= isa_mem_base
+ 0xa0000 + bank_index
* 0x8000;
1233 cpu_physical_sync_dirty_bitmap(base_addr
, base_addr
+ 0x8000);
1235 s
->cirrus_bank_base
[bank_index
] = offset
;
1236 s
->cirrus_bank_limit
[bank_index
] = limit
;
1238 s
->cirrus_bank_base
[bank_index
] = 0;
1239 s
->cirrus_bank_limit
[bank_index
] = 0;
1243 /***************************************
1245 * I/O access between 0x3c4-0x3c5
1247 ***************************************/
1250 cirrus_hook_read_sr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1252 switch (reg_index
) {
1253 case 0x00: // Standard VGA
1254 case 0x01: // Standard VGA
1255 case 0x02: // Standard VGA
1256 case 0x03: // Standard VGA
1257 case 0x04: // Standard VGA
1258 return CIRRUS_HOOK_NOT_HANDLED
;
1259 case 0x06: // Unlock Cirrus extensions
1260 *reg_value
= s
->sr
[reg_index
];
1265 case 0x70: // Graphics Cursor X
1269 case 0xf0: // Graphics Cursor X
1270 *reg_value
= s
->sr
[0x10];
1275 case 0x71: // Graphics Cursor Y
1279 case 0xf1: // Graphics Cursor Y
1280 *reg_value
= s
->sr
[0x11];
1283 case 0x07: // Extended Sequencer Mode
1284 case 0x08: // EEPROM Control
1285 case 0x09: // Scratch Register 0
1286 case 0x0a: // Scratch Register 1
1287 case 0x0b: // VCLK 0
1288 case 0x0c: // VCLK 1
1289 case 0x0d: // VCLK 2
1290 case 0x0e: // VCLK 3
1291 case 0x0f: // DRAM Control
1292 case 0x12: // Graphics Cursor Attribute
1293 case 0x13: // Graphics Cursor Pattern Address
1294 case 0x14: // Scratch Register 2
1295 case 0x15: // Scratch Register 3
1296 case 0x16: // Performance Tuning Register
1297 case 0x17: // Configuration Readback and Extended Control
1298 case 0x18: // Signature Generator Control
1299 case 0x19: // Signal Generator Result
1300 case 0x1a: // Signal Generator Result
1301 case 0x1b: // VCLK 0 Denominator & Post
1302 case 0x1c: // VCLK 1 Denominator & Post
1303 case 0x1d: // VCLK 2 Denominator & Post
1304 case 0x1e: // VCLK 3 Denominator & Post
1305 case 0x1f: // BIOS Write Enable and MCLK select
1307 printf("cirrus: handled inport sr_index %02x\n", reg_index
);
1309 *reg_value
= s
->sr
[reg_index
];
1313 printf("cirrus: inport sr_index %02x\n", reg_index
);
1319 return CIRRUS_HOOK_HANDLED
;
1323 cirrus_hook_write_sr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1325 switch (reg_index
) {
1326 case 0x00: // Standard VGA
1327 case 0x01: // Standard VGA
1328 case 0x02: // Standard VGA
1329 case 0x03: // Standard VGA
1330 case 0x04: // Standard VGA
1331 return CIRRUS_HOOK_NOT_HANDLED
;
1332 case 0x06: // Unlock Cirrus extensions
1334 if (reg_value
== 0x12) {
1335 s
->sr
[reg_index
] = 0x12;
1337 s
->sr
[reg_index
] = 0x0f;
1343 case 0x70: // Graphics Cursor X
1347 case 0xf0: // Graphics Cursor X
1348 s
->sr
[0x10] = reg_value
;
1349 s
->hw_cursor_x
= (reg_value
<< 3) | (reg_index
>> 5);
1354 case 0x71: // Graphics Cursor Y
1358 case 0xf1: // Graphics Cursor Y
1359 s
->sr
[0x11] = reg_value
;
1360 s
->hw_cursor_y
= (reg_value
<< 3) | (reg_index
>> 5);
1362 case 0x07: // Extended Sequencer Mode
1363 cirrus_update_memory_access(s
);
1364 case 0x08: // EEPROM Control
1365 case 0x09: // Scratch Register 0
1366 case 0x0a: // Scratch Register 1
1367 case 0x0b: // VCLK 0
1368 case 0x0c: // VCLK 1
1369 case 0x0d: // VCLK 2
1370 case 0x0e: // VCLK 3
1371 case 0x0f: // DRAM Control
1372 case 0x12: // Graphics Cursor Attribute
1373 case 0x13: // Graphics Cursor Pattern Address
1374 case 0x14: // Scratch Register 2
1375 case 0x15: // Scratch Register 3
1376 case 0x16: // Performance Tuning Register
1377 case 0x18: // Signature Generator Control
1378 case 0x19: // Signature Generator Result
1379 case 0x1a: // Signature Generator Result
1380 case 0x1b: // VCLK 0 Denominator & Post
1381 case 0x1c: // VCLK 1 Denominator & Post
1382 case 0x1d: // VCLK 2 Denominator & Post
1383 case 0x1e: // VCLK 3 Denominator & Post
1384 case 0x1f: // BIOS Write Enable and MCLK select
1385 s
->sr
[reg_index
] = reg_value
;
1387 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1388 reg_index
, reg_value
);
1390 if (reg_index
== 0x07)
1391 cirrus_update_memory_access(s
);
1393 case 0x17: // Configuration Readback and Extended Control
1394 s
->sr
[reg_index
] = (s
->sr
[reg_index
] & 0x38) | (reg_value
& 0xc7);
1395 cirrus_update_memory_access(s
);
1399 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index
,
1405 return CIRRUS_HOOK_HANDLED
;
1408 /***************************************
1410 * I/O access at 0x3c6
1412 ***************************************/
1414 static void cirrus_read_hidden_dac(CirrusVGAState
* s
, int *reg_value
)
1417 if (++s
->cirrus_hidden_dac_lockindex
== 5) {
1418 *reg_value
= s
->cirrus_hidden_dac_data
;
1419 s
->cirrus_hidden_dac_lockindex
= 0;
1423 static void cirrus_write_hidden_dac(CirrusVGAState
* s
, int reg_value
)
1425 if (s
->cirrus_hidden_dac_lockindex
== 4) {
1426 s
->cirrus_hidden_dac_data
= reg_value
;
1427 #if defined(DEBUG_CIRRUS)
1428 printf("cirrus: outport hidden DAC, value %02x\n", reg_value
);
1431 s
->cirrus_hidden_dac_lockindex
= 0;
1434 /***************************************
1436 * I/O access at 0x3c9
1438 ***************************************/
1440 static int cirrus_hook_read_palette(CirrusVGAState
* s
, int *reg_value
)
1442 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
))
1443 return CIRRUS_HOOK_NOT_HANDLED
;
1445 s
->cirrus_hidden_palette
[(s
->dac_read_index
& 0x0f) * 3 +
1447 if (++s
->dac_sub_index
== 3) {
1448 s
->dac_sub_index
= 0;
1449 s
->dac_read_index
++;
1451 return CIRRUS_HOOK_HANDLED
;
1454 static int cirrus_hook_write_palette(CirrusVGAState
* s
, int reg_value
)
1456 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_HIDDENPEL
))
1457 return CIRRUS_HOOK_NOT_HANDLED
;
1458 s
->dac_cache
[s
->dac_sub_index
] = reg_value
;
1459 if (++s
->dac_sub_index
== 3) {
1460 memcpy(&s
->cirrus_hidden_palette
[(s
->dac_write_index
& 0x0f) * 3],
1462 /* XXX update cursor */
1463 s
->dac_sub_index
= 0;
1464 s
->dac_write_index
++;
1466 return CIRRUS_HOOK_HANDLED
;
1469 /***************************************
1471 * I/O access between 0x3ce-0x3cf
1473 ***************************************/
1476 cirrus_hook_read_gr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1478 switch (reg_index
) {
1479 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1480 *reg_value
= s
->cirrus_shadow_gr0
;
1481 return CIRRUS_HOOK_HANDLED
;
1482 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1483 *reg_value
= s
->cirrus_shadow_gr1
;
1484 return CIRRUS_HOOK_HANDLED
;
1485 case 0x02: // Standard VGA
1486 case 0x03: // Standard VGA
1487 case 0x04: // Standard VGA
1488 case 0x06: // Standard VGA
1489 case 0x07: // Standard VGA
1490 case 0x08: // Standard VGA
1491 return CIRRUS_HOOK_NOT_HANDLED
;
1492 case 0x05: // Standard VGA, Cirrus extended mode
1497 if (reg_index
< 0x3a) {
1498 *reg_value
= s
->gr
[reg_index
];
1501 printf("cirrus: inport gr_index %02x\n", reg_index
);
1506 return CIRRUS_HOOK_HANDLED
;
1510 cirrus_hook_write_gr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1512 #if defined(DEBUG_BITBLT) && 0
1513 printf("gr%02x: %02x\n", reg_index
, reg_value
);
1515 switch (reg_index
) {
1516 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1517 s
->cirrus_shadow_gr0
= reg_value
;
1518 return CIRRUS_HOOK_NOT_HANDLED
;
1519 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1520 s
->cirrus_shadow_gr1
= reg_value
;
1521 return CIRRUS_HOOK_NOT_HANDLED
;
1522 case 0x02: // Standard VGA
1523 case 0x03: // Standard VGA
1524 case 0x04: // Standard VGA
1525 case 0x06: // Standard VGA
1526 case 0x07: // Standard VGA
1527 case 0x08: // Standard VGA
1528 return CIRRUS_HOOK_NOT_HANDLED
;
1529 case 0x05: // Standard VGA, Cirrus extended mode
1530 s
->gr
[reg_index
] = reg_value
& 0x7f;
1531 cirrus_update_memory_access(s
);
1533 case 0x09: // bank offset #0
1534 case 0x0A: // bank offset #1
1535 s
->gr
[reg_index
] = reg_value
;
1536 cirrus_update_bank_ptr(s
, 0);
1537 cirrus_update_bank_ptr(s
, 1);
1538 cirrus_update_memory_access(s
);
1541 s
->gr
[reg_index
] = reg_value
;
1542 cirrus_update_bank_ptr(s
, 0);
1543 cirrus_update_bank_ptr(s
, 1);
1544 cirrus_update_memory_access(s
);
1546 case 0x10: // BGCOLOR 0x0000ff00
1547 case 0x11: // FGCOLOR 0x0000ff00
1548 case 0x12: // BGCOLOR 0x00ff0000
1549 case 0x13: // FGCOLOR 0x00ff0000
1550 case 0x14: // BGCOLOR 0xff000000
1551 case 0x15: // FGCOLOR 0xff000000
1552 case 0x20: // BLT WIDTH 0x0000ff
1553 case 0x22: // BLT HEIGHT 0x0000ff
1554 case 0x24: // BLT DEST PITCH 0x0000ff
1555 case 0x26: // BLT SRC PITCH 0x0000ff
1556 case 0x28: // BLT DEST ADDR 0x0000ff
1557 case 0x29: // BLT DEST ADDR 0x00ff00
1558 case 0x2c: // BLT SRC ADDR 0x0000ff
1559 case 0x2d: // BLT SRC ADDR 0x00ff00
1560 case 0x2f: // BLT WRITEMASK
1561 case 0x30: // BLT MODE
1562 case 0x32: // RASTER OP
1563 case 0x33: // BLT MODEEXT
1564 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1565 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1566 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1567 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1568 s
->gr
[reg_index
] = reg_value
;
1570 case 0x21: // BLT WIDTH 0x001f00
1571 case 0x23: // BLT HEIGHT 0x001f00
1572 case 0x25: // BLT DEST PITCH 0x001f00
1573 case 0x27: // BLT SRC PITCH 0x001f00
1574 s
->gr
[reg_index
] = reg_value
& 0x1f;
1576 case 0x2a: // BLT DEST ADDR 0x3f0000
1577 s
->gr
[reg_index
] = reg_value
& 0x3f;
1578 /* if auto start mode, starts bit blt now */
1579 if (s
->gr
[0x31] & CIRRUS_BLT_AUTOSTART
) {
1580 cirrus_bitblt_start(s
);
1583 case 0x2e: // BLT SRC ADDR 0x3f0000
1584 s
->gr
[reg_index
] = reg_value
& 0x3f;
1586 case 0x31: // BLT STATUS/START
1587 cirrus_write_bitblt(s
, reg_value
);
1591 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index
,
1597 return CIRRUS_HOOK_HANDLED
;
1600 /***************************************
1602 * I/O access between 0x3d4-0x3d5
1604 ***************************************/
1607 cirrus_hook_read_cr(CirrusVGAState
* s
, unsigned reg_index
, int *reg_value
)
1609 switch (reg_index
) {
1610 case 0x00: // Standard VGA
1611 case 0x01: // Standard VGA
1612 case 0x02: // Standard VGA
1613 case 0x03: // Standard VGA
1614 case 0x04: // Standard VGA
1615 case 0x05: // Standard VGA
1616 case 0x06: // Standard VGA
1617 case 0x07: // Standard VGA
1618 case 0x08: // Standard VGA
1619 case 0x09: // Standard VGA
1620 case 0x0a: // Standard VGA
1621 case 0x0b: // Standard VGA
1622 case 0x0c: // Standard VGA
1623 case 0x0d: // Standard VGA
1624 case 0x0e: // Standard VGA
1625 case 0x0f: // Standard VGA
1626 case 0x10: // Standard VGA
1627 case 0x11: // Standard VGA
1628 case 0x12: // Standard VGA
1629 case 0x13: // Standard VGA
1630 case 0x14: // Standard VGA
1631 case 0x15: // Standard VGA
1632 case 0x16: // Standard VGA
1633 case 0x17: // Standard VGA
1634 case 0x18: // Standard VGA
1635 return CIRRUS_HOOK_NOT_HANDLED
;
1636 case 0x24: // Attribute Controller Toggle Readback (R)
1637 *reg_value
= (s
->ar_flip_flop
<< 7);
1639 case 0x19: // Interlace End
1640 case 0x1a: // Miscellaneous Control
1641 case 0x1b: // Extended Display Control
1642 case 0x1c: // Sync Adjust and Genlock
1643 case 0x1d: // Overlay Extended Control
1644 case 0x22: // Graphics Data Latches Readback (R)
1645 case 0x25: // Part Status
1646 case 0x27: // Part ID (R)
1647 *reg_value
= s
->cr
[reg_index
];
1649 case 0x26: // Attribute Controller Index Readback (R)
1650 *reg_value
= s
->ar_index
& 0x3f;
1654 printf("cirrus: inport cr_index %02x\n", reg_index
);
1660 return CIRRUS_HOOK_HANDLED
;
1664 cirrus_hook_write_cr(CirrusVGAState
* s
, unsigned reg_index
, int reg_value
)
1666 switch (reg_index
) {
1667 case 0x00: // Standard VGA
1668 case 0x01: // Standard VGA
1669 case 0x02: // Standard VGA
1670 case 0x03: // Standard VGA
1671 case 0x04: // Standard VGA
1672 case 0x05: // Standard VGA
1673 case 0x06: // Standard VGA
1674 case 0x07: // Standard VGA
1675 case 0x08: // Standard VGA
1676 case 0x09: // Standard VGA
1677 case 0x0a: // Standard VGA
1678 case 0x0b: // Standard VGA
1679 case 0x0c: // Standard VGA
1680 case 0x0d: // Standard VGA
1681 case 0x0e: // Standard VGA
1682 case 0x0f: // Standard VGA
1683 case 0x10: // Standard VGA
1684 case 0x11: // Standard VGA
1685 case 0x12: // Standard VGA
1686 case 0x13: // Standard VGA
1687 case 0x14: // Standard VGA
1688 case 0x15: // Standard VGA
1689 case 0x16: // Standard VGA
1690 case 0x17: // Standard VGA
1691 case 0x18: // Standard VGA
1692 return CIRRUS_HOOK_NOT_HANDLED
;
1693 case 0x19: // Interlace End
1694 case 0x1a: // Miscellaneous Control
1695 case 0x1b: // Extended Display Control
1696 case 0x1c: // Sync Adjust and Genlock
1697 case 0x1d: // Overlay Extended Control
1698 s
->cr
[reg_index
] = reg_value
;
1700 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1701 reg_index
, reg_value
);
1704 case 0x22: // Graphics Data Latches Readback (R)
1705 case 0x24: // Attribute Controller Toggle Readback (R)
1706 case 0x26: // Attribute Controller Index Readback (R)
1707 case 0x27: // Part ID (R)
1709 case 0x25: // Part Status
1712 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index
,
1718 return CIRRUS_HOOK_HANDLED
;
1721 /***************************************
1723 * memory-mapped I/O (bitblt)
1725 ***************************************/
1727 static uint8_t cirrus_mmio_blt_read(CirrusVGAState
* s
, unsigned address
)
1732 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1733 cirrus_hook_read_gr(s
, 0x00, &value
);
1735 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1736 cirrus_hook_read_gr(s
, 0x10, &value
);
1738 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1739 cirrus_hook_read_gr(s
, 0x12, &value
);
1741 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1742 cirrus_hook_read_gr(s
, 0x14, &value
);
1744 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1745 cirrus_hook_read_gr(s
, 0x01, &value
);
1747 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1748 cirrus_hook_read_gr(s
, 0x11, &value
);
1750 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1751 cirrus_hook_read_gr(s
, 0x13, &value
);
1753 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1754 cirrus_hook_read_gr(s
, 0x15, &value
);
1756 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1757 cirrus_hook_read_gr(s
, 0x20, &value
);
1759 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1760 cirrus_hook_read_gr(s
, 0x21, &value
);
1762 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1763 cirrus_hook_read_gr(s
, 0x22, &value
);
1765 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1766 cirrus_hook_read_gr(s
, 0x23, &value
);
1768 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1769 cirrus_hook_read_gr(s
, 0x24, &value
);
1771 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1772 cirrus_hook_read_gr(s
, 0x25, &value
);
1774 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1775 cirrus_hook_read_gr(s
, 0x26, &value
);
1777 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1778 cirrus_hook_read_gr(s
, 0x27, &value
);
1780 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1781 cirrus_hook_read_gr(s
, 0x28, &value
);
1783 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1784 cirrus_hook_read_gr(s
, 0x29, &value
);
1786 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1787 cirrus_hook_read_gr(s
, 0x2a, &value
);
1789 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1790 cirrus_hook_read_gr(s
, 0x2c, &value
);
1792 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1793 cirrus_hook_read_gr(s
, 0x2d, &value
);
1795 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1796 cirrus_hook_read_gr(s
, 0x2e, &value
);
1798 case CIRRUS_MMIO_BLTWRITEMASK
:
1799 cirrus_hook_read_gr(s
, 0x2f, &value
);
1801 case CIRRUS_MMIO_BLTMODE
:
1802 cirrus_hook_read_gr(s
, 0x30, &value
);
1804 case CIRRUS_MMIO_BLTROP
:
1805 cirrus_hook_read_gr(s
, 0x32, &value
);
1807 case CIRRUS_MMIO_BLTMODEEXT
:
1808 cirrus_hook_read_gr(s
, 0x33, &value
);
1810 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1811 cirrus_hook_read_gr(s
, 0x34, &value
);
1813 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1814 cirrus_hook_read_gr(s
, 0x35, &value
);
1816 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1817 cirrus_hook_read_gr(s
, 0x38, &value
);
1819 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1820 cirrus_hook_read_gr(s
, 0x39, &value
);
1822 case CIRRUS_MMIO_BLTSTATUS
:
1823 cirrus_hook_read_gr(s
, 0x31, &value
);
1827 printf("cirrus: mmio read - address 0x%04x\n", address
);
1832 return (uint8_t) value
;
1835 static void cirrus_mmio_blt_write(CirrusVGAState
* s
, unsigned address
,
1839 case (CIRRUS_MMIO_BLTBGCOLOR
+ 0):
1840 cirrus_hook_write_gr(s
, 0x00, value
);
1842 case (CIRRUS_MMIO_BLTBGCOLOR
+ 1):
1843 cirrus_hook_write_gr(s
, 0x10, value
);
1845 case (CIRRUS_MMIO_BLTBGCOLOR
+ 2):
1846 cirrus_hook_write_gr(s
, 0x12, value
);
1848 case (CIRRUS_MMIO_BLTBGCOLOR
+ 3):
1849 cirrus_hook_write_gr(s
, 0x14, value
);
1851 case (CIRRUS_MMIO_BLTFGCOLOR
+ 0):
1852 cirrus_hook_write_gr(s
, 0x01, value
);
1854 case (CIRRUS_MMIO_BLTFGCOLOR
+ 1):
1855 cirrus_hook_write_gr(s
, 0x11, value
);
1857 case (CIRRUS_MMIO_BLTFGCOLOR
+ 2):
1858 cirrus_hook_write_gr(s
, 0x13, value
);
1860 case (CIRRUS_MMIO_BLTFGCOLOR
+ 3):
1861 cirrus_hook_write_gr(s
, 0x15, value
);
1863 case (CIRRUS_MMIO_BLTWIDTH
+ 0):
1864 cirrus_hook_write_gr(s
, 0x20, value
);
1866 case (CIRRUS_MMIO_BLTWIDTH
+ 1):
1867 cirrus_hook_write_gr(s
, 0x21, value
);
1869 case (CIRRUS_MMIO_BLTHEIGHT
+ 0):
1870 cirrus_hook_write_gr(s
, 0x22, value
);
1872 case (CIRRUS_MMIO_BLTHEIGHT
+ 1):
1873 cirrus_hook_write_gr(s
, 0x23, value
);
1875 case (CIRRUS_MMIO_BLTDESTPITCH
+ 0):
1876 cirrus_hook_write_gr(s
, 0x24, value
);
1878 case (CIRRUS_MMIO_BLTDESTPITCH
+ 1):
1879 cirrus_hook_write_gr(s
, 0x25, value
);
1881 case (CIRRUS_MMIO_BLTSRCPITCH
+ 0):
1882 cirrus_hook_write_gr(s
, 0x26, value
);
1884 case (CIRRUS_MMIO_BLTSRCPITCH
+ 1):
1885 cirrus_hook_write_gr(s
, 0x27, value
);
1887 case (CIRRUS_MMIO_BLTDESTADDR
+ 0):
1888 cirrus_hook_write_gr(s
, 0x28, value
);
1890 case (CIRRUS_MMIO_BLTDESTADDR
+ 1):
1891 cirrus_hook_write_gr(s
, 0x29, value
);
1893 case (CIRRUS_MMIO_BLTDESTADDR
+ 2):
1894 cirrus_hook_write_gr(s
, 0x2a, value
);
1896 case (CIRRUS_MMIO_BLTDESTADDR
+ 3):
1899 case (CIRRUS_MMIO_BLTSRCADDR
+ 0):
1900 cirrus_hook_write_gr(s
, 0x2c, value
);
1902 case (CIRRUS_MMIO_BLTSRCADDR
+ 1):
1903 cirrus_hook_write_gr(s
, 0x2d, value
);
1905 case (CIRRUS_MMIO_BLTSRCADDR
+ 2):
1906 cirrus_hook_write_gr(s
, 0x2e, value
);
1908 case CIRRUS_MMIO_BLTWRITEMASK
:
1909 cirrus_hook_write_gr(s
, 0x2f, value
);
1911 case CIRRUS_MMIO_BLTMODE
:
1912 cirrus_hook_write_gr(s
, 0x30, value
);
1914 case CIRRUS_MMIO_BLTROP
:
1915 cirrus_hook_write_gr(s
, 0x32, value
);
1917 case CIRRUS_MMIO_BLTMODEEXT
:
1918 cirrus_hook_write_gr(s
, 0x33, value
);
1920 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 0):
1921 cirrus_hook_write_gr(s
, 0x34, value
);
1923 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR
+ 1):
1924 cirrus_hook_write_gr(s
, 0x35, value
);
1926 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 0):
1927 cirrus_hook_write_gr(s
, 0x38, value
);
1929 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK
+ 1):
1930 cirrus_hook_write_gr(s
, 0x39, value
);
1932 case CIRRUS_MMIO_BLTSTATUS
:
1933 cirrus_hook_write_gr(s
, 0x31, value
);
1937 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1944 /***************************************
1948 * assume TARGET_PAGE_SIZE >= 16
1950 ***************************************/
1952 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState
* s
,
1958 unsigned val
= mem_value
;
1961 dst
= s
->vram_ptr
+ (offset
&= s
->cirrus_addr_mask
);
1962 for (x
= 0; x
< 8; x
++) {
1964 *dst
= s
->cirrus_shadow_gr1
;
1965 } else if (mode
== 5) {
1966 *dst
= s
->cirrus_shadow_gr0
;
1971 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
);
1972 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
+ 7);
1975 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState
* s
,
1981 unsigned val
= mem_value
;
1984 dst
= s
->vram_ptr
+ (offset
&= s
->cirrus_addr_mask
);
1985 for (x
= 0; x
< 8; x
++) {
1987 *dst
= s
->cirrus_shadow_gr1
;
1988 *(dst
+ 1) = s
->gr
[0x11];
1989 } else if (mode
== 5) {
1990 *dst
= s
->cirrus_shadow_gr0
;
1991 *(dst
+ 1) = s
->gr
[0x10];
1996 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
);
1997 cpu_physical_memory_set_dirty(s
->vram_offset
+ offset
+ 15);
2000 /***************************************
2002 * memory access between 0xa0000-0xbffff
2004 ***************************************/
2006 static uint32_t cirrus_vga_mem_readb(void *opaque
, target_phys_addr_t addr
)
2008 CirrusVGAState
*s
= opaque
;
2009 unsigned bank_index
;
2010 unsigned bank_offset
;
2013 if ((s
->sr
[0x07] & 0x01) == 0) {
2014 return vga_mem_readb(s
, addr
);
2019 if (addr
< 0x10000) {
2020 /* XXX handle bitblt */
2022 bank_index
= addr
>> 15;
2023 bank_offset
= addr
& 0x7fff;
2024 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2025 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2026 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2028 } else if (s
->gr
[0x0B] & 0x02) {
2031 bank_offset
&= s
->cirrus_addr_mask
;
2032 val
= *(s
->vram_ptr
+ bank_offset
);
2035 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2036 /* memory-mapped I/O */
2038 if ((s
->sr
[0x17] & 0x44) == 0x04) {
2039 val
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2044 printf("cirrus: mem_readb %06x\n", addr
);
2050 static uint32_t cirrus_vga_mem_readw(void *opaque
, target_phys_addr_t addr
)
2053 #ifdef TARGET_WORDS_BIGENDIAN
2054 v
= cirrus_vga_mem_readb(opaque
, addr
) << 8;
2055 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1);
2057 v
= cirrus_vga_mem_readb(opaque
, addr
);
2058 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 8;
2063 static uint32_t cirrus_vga_mem_readl(void *opaque
, target_phys_addr_t addr
)
2066 #ifdef TARGET_WORDS_BIGENDIAN
2067 v
= cirrus_vga_mem_readb(opaque
, addr
) << 24;
2068 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 16;
2069 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 2) << 8;
2070 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 3);
2072 v
= cirrus_vga_mem_readb(opaque
, addr
);
2073 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 1) << 8;
2074 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 2) << 16;
2075 v
|= cirrus_vga_mem_readb(opaque
, addr
+ 3) << 24;
2080 static void cirrus_vga_mem_writeb(void *opaque
, target_phys_addr_t addr
,
2083 CirrusVGAState
*s
= opaque
;
2084 unsigned bank_index
;
2085 unsigned bank_offset
;
2088 if ((s
->sr
[0x07] & 0x01) == 0) {
2089 vga_mem_writeb(s
, addr
, mem_value
);
2095 if (addr
< 0x10000) {
2096 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2098 *s
->cirrus_srcptr
++ = (uint8_t) mem_value
;
2099 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2100 cirrus_bitblt_cputovideo_next(s
);
2104 bank_index
= addr
>> 15;
2105 bank_offset
= addr
& 0x7fff;
2106 if (bank_offset
< s
->cirrus_bank_limit
[bank_index
]) {
2107 bank_offset
+= s
->cirrus_bank_base
[bank_index
];
2108 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2110 } else if (s
->gr
[0x0B] & 0x02) {
2113 bank_offset
&= s
->cirrus_addr_mask
;
2114 mode
= s
->gr
[0x05] & 0x7;
2115 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2116 *(s
->vram_ptr
+ bank_offset
) = mem_value
;
2117 cpu_physical_memory_set_dirty(s
->vram_offset
+
2120 if ((s
->gr
[0x0B] & 0x14) != 0x14) {
2121 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
,
2125 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
,
2132 } else if (addr
>= 0x18000 && addr
< 0x18100) {
2133 /* memory-mapped I/O */
2134 if ((s
->sr
[0x17] & 0x44) == 0x04) {
2135 cirrus_mmio_blt_write(s
, addr
& 0xff, mem_value
);
2139 printf("cirrus: mem_writeb %06x value %02x\n", addr
, mem_value
);
2144 static void cirrus_vga_mem_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
2146 #ifdef TARGET_WORDS_BIGENDIAN
2147 cirrus_vga_mem_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2148 cirrus_vga_mem_writeb(opaque
, addr
+ 1, val
& 0xff);
2150 cirrus_vga_mem_writeb(opaque
, addr
, val
& 0xff);
2151 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2155 static void cirrus_vga_mem_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
2157 #ifdef TARGET_WORDS_BIGENDIAN
2158 cirrus_vga_mem_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2159 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2160 cirrus_vga_mem_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2161 cirrus_vga_mem_writeb(opaque
, addr
+ 3, val
& 0xff);
2163 cirrus_vga_mem_writeb(opaque
, addr
, val
& 0xff);
2164 cirrus_vga_mem_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2165 cirrus_vga_mem_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2166 cirrus_vga_mem_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2170 static CPUReadMemoryFunc
*cirrus_vga_mem_read
[3] = {
2171 cirrus_vga_mem_readb
,
2172 cirrus_vga_mem_readw
,
2173 cirrus_vga_mem_readl
,
2176 static CPUWriteMemoryFunc
*cirrus_vga_mem_write
[3] = {
2177 cirrus_vga_mem_writeb
,
2178 cirrus_vga_mem_writew
,
2179 cirrus_vga_mem_writel
,
2182 /***************************************
2186 ***************************************/
2188 static inline void invalidate_cursor1(CirrusVGAState
*s
)
2190 if (s
->last_hw_cursor_size
) {
2191 vga_invalidate_scanlines((VGAState
*)s
,
2192 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_start
,
2193 s
->last_hw_cursor_y
+ s
->last_hw_cursor_y_end
);
2197 static inline void cirrus_cursor_compute_yrange(CirrusVGAState
*s
)
2201 int y
, y_min
, y_max
;
2203 src
= s
->vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2204 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2205 src
+= (s
->sr
[0x13] & 0x3c) * 256;
2208 for(y
= 0; y
< 64; y
++) {
2209 content
= ((uint32_t *)src
)[0] |
2210 ((uint32_t *)src
)[1] |
2211 ((uint32_t *)src
)[2] |
2212 ((uint32_t *)src
)[3];
2222 src
+= (s
->sr
[0x13] & 0x3f) * 256;
2225 for(y
= 0; y
< 32; y
++) {
2226 content
= ((uint32_t *)src
)[0] |
2227 ((uint32_t *)(src
+ 128))[0];
2237 if (y_min
> y_max
) {
2238 s
->last_hw_cursor_y_start
= 0;
2239 s
->last_hw_cursor_y_end
= 0;
2241 s
->last_hw_cursor_y_start
= y_min
;
2242 s
->last_hw_cursor_y_end
= y_max
+ 1;
2246 /* NOTE: we do not currently handle the cursor bitmap change, so we
2247 update the cursor only if it moves. */
2248 static void cirrus_cursor_invalidate(VGAState
*s1
)
2250 CirrusVGAState
*s
= (CirrusVGAState
*)s1
;
2253 if (!s
->sr
[0x12] & CIRRUS_CURSOR_SHOW
) {
2256 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
)
2261 /* invalidate last cursor and new cursor if any change */
2262 if (s
->last_hw_cursor_size
!= size
||
2263 s
->last_hw_cursor_x
!= s
->hw_cursor_x
||
2264 s
->last_hw_cursor_y
!= s
->hw_cursor_y
) {
2266 invalidate_cursor1(s
);
2268 s
->last_hw_cursor_size
= size
;
2269 s
->last_hw_cursor_x
= s
->hw_cursor_x
;
2270 s
->last_hw_cursor_y
= s
->hw_cursor_y
;
2271 /* compute the real cursor min and max y */
2272 cirrus_cursor_compute_yrange(s
);
2273 invalidate_cursor1(s
);
2277 static void cirrus_cursor_draw_line(VGAState
*s1
, uint8_t *d1
, int scr_y
)
2279 CirrusVGAState
*s
= (CirrusVGAState
*)s1
;
2280 int w
, h
, bpp
, x1
, x2
, poffset
;
2281 unsigned int color0
, color1
;
2282 const uint8_t *palette
, *src
;
2285 if (!(s
->sr
[0x12] & CIRRUS_CURSOR_SHOW
))
2287 /* fast test to see if the cursor intersects with the scan line */
2288 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2293 if (scr_y
< s
->hw_cursor_y
||
2294 scr_y
>= (s
->hw_cursor_y
+ h
))
2297 src
= s
->vram_ptr
+ s
->real_vram_size
- 16 * 1024;
2298 if (s
->sr
[0x12] & CIRRUS_CURSOR_LARGE
) {
2299 src
+= (s
->sr
[0x13] & 0x3c) * 256;
2300 src
+= (scr_y
- s
->hw_cursor_y
) * 16;
2302 content
= ((uint32_t *)src
)[0] |
2303 ((uint32_t *)src
)[1] |
2304 ((uint32_t *)src
)[2] |
2305 ((uint32_t *)src
)[3];
2307 src
+= (s
->sr
[0x13] & 0x3f) * 256;
2308 src
+= (scr_y
- s
->hw_cursor_y
) * 4;
2310 content
= ((uint32_t *)src
)[0] |
2311 ((uint32_t *)(src
+ 128))[0];
2313 /* if nothing to draw, no need to continue */
2318 x1
= s
->hw_cursor_x
;
2319 if (x1
>= s
->last_scr_width
)
2321 x2
= s
->hw_cursor_x
+ w
;
2322 if (x2
> s
->last_scr_width
)
2323 x2
= s
->last_scr_width
;
2325 palette
= s
->cirrus_hidden_palette
;
2326 color0
= s
->rgb_to_pixel(c6_to_8(palette
[0x0 * 3]),
2327 c6_to_8(palette
[0x0 * 3 + 1]),
2328 c6_to_8(palette
[0x0 * 3 + 2]));
2329 color1
= s
->rgb_to_pixel(c6_to_8(palette
[0xf * 3]),
2330 c6_to_8(palette
[0xf * 3 + 1]),
2331 c6_to_8(palette
[0xf * 3 + 2]));
2332 bpp
= ((ds_get_bits_per_pixel(s
->ds
) + 7) >> 3);
2334 switch(ds_get_bits_per_pixel(s
->ds
)) {
2338 vga_draw_cursor_line_8(d1
, src
, poffset
, w
, color0
, color1
, 0xff);
2341 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0x7fff);
2344 vga_draw_cursor_line_16(d1
, src
, poffset
, w
, color0
, color1
, 0xffff);
2347 vga_draw_cursor_line_32(d1
, src
, poffset
, w
, color0
, color1
, 0xffffff);
2352 /***************************************
2356 ***************************************/
2358 static uint32_t cirrus_linear_readb(void *opaque
, target_phys_addr_t addr
)
2360 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2363 addr
&= s
->cirrus_addr_mask
;
2365 if (((s
->sr
[0x17] & 0x44) == 0x44) &&
2366 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2367 /* memory-mapped I/O */
2368 ret
= cirrus_mmio_blt_read(s
, addr
& 0xff);
2370 /* XXX handle bitblt */
2374 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2376 } else if (s
->gr
[0x0B] & 0x02) {
2379 addr
&= s
->cirrus_addr_mask
;
2380 ret
= *(s
->vram_ptr
+ addr
);
2386 static uint32_t cirrus_linear_readw(void *opaque
, target_phys_addr_t addr
)
2389 #ifdef TARGET_WORDS_BIGENDIAN
2390 v
= cirrus_linear_readb(opaque
, addr
) << 8;
2391 v
|= cirrus_linear_readb(opaque
, addr
+ 1);
2393 v
= cirrus_linear_readb(opaque
, addr
);
2394 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 8;
2399 static uint32_t cirrus_linear_readl(void *opaque
, target_phys_addr_t addr
)
2402 #ifdef TARGET_WORDS_BIGENDIAN
2403 v
= cirrus_linear_readb(opaque
, addr
) << 24;
2404 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 16;
2405 v
|= cirrus_linear_readb(opaque
, addr
+ 2) << 8;
2406 v
|= cirrus_linear_readb(opaque
, addr
+ 3);
2408 v
= cirrus_linear_readb(opaque
, addr
);
2409 v
|= cirrus_linear_readb(opaque
, addr
+ 1) << 8;
2410 v
|= cirrus_linear_readb(opaque
, addr
+ 2) << 16;
2411 v
|= cirrus_linear_readb(opaque
, addr
+ 3) << 24;
2416 static void cirrus_linear_writeb(void *opaque
, target_phys_addr_t addr
,
2419 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2422 addr
&= s
->cirrus_addr_mask
;
2424 if (((s
->sr
[0x17] & 0x44) == 0x44) &&
2425 ((addr
& s
->linear_mmio_mask
) == s
->linear_mmio_mask
)) {
2426 /* memory-mapped I/O */
2427 cirrus_mmio_blt_write(s
, addr
& 0xff, val
);
2428 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2430 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2431 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2432 cirrus_bitblt_cputovideo_next(s
);
2436 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2438 } else if (s
->gr
[0x0B] & 0x02) {
2441 addr
&= s
->cirrus_addr_mask
;
2443 mode
= s
->gr
[0x05] & 0x7;
2444 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2445 *(s
->vram_ptr
+ addr
) = (uint8_t) val
;
2446 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2448 if ((s
->gr
[0x0B] & 0x14) != 0x14) {
2449 cirrus_mem_writeb_mode4and5_8bpp(s
, mode
, addr
, val
);
2451 cirrus_mem_writeb_mode4and5_16bpp(s
, mode
, addr
, val
);
2457 static void cirrus_linear_writew(void *opaque
, target_phys_addr_t addr
,
2460 #ifdef TARGET_WORDS_BIGENDIAN
2461 cirrus_linear_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2462 cirrus_linear_writeb(opaque
, addr
+ 1, val
& 0xff);
2464 cirrus_linear_writeb(opaque
, addr
, val
& 0xff);
2465 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2469 static void cirrus_linear_writel(void *opaque
, target_phys_addr_t addr
,
2472 #ifdef TARGET_WORDS_BIGENDIAN
2473 cirrus_linear_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2474 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2475 cirrus_linear_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2476 cirrus_linear_writeb(opaque
, addr
+ 3, val
& 0xff);
2478 cirrus_linear_writeb(opaque
, addr
, val
& 0xff);
2479 cirrus_linear_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2480 cirrus_linear_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2481 cirrus_linear_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2486 static CPUReadMemoryFunc
*cirrus_linear_read
[3] = {
2487 cirrus_linear_readb
,
2488 cirrus_linear_readw
,
2489 cirrus_linear_readl
,
2492 static CPUWriteMemoryFunc
*cirrus_linear_write
[3] = {
2493 cirrus_linear_writeb
,
2494 cirrus_linear_writew
,
2495 cirrus_linear_writel
,
2498 static void cirrus_linear_mem_writeb(void *opaque
, target_phys_addr_t addr
,
2501 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2503 addr
&= s
->cirrus_addr_mask
;
2504 *(s
->vram_ptr
+ addr
) = val
;
2505 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2508 static void cirrus_linear_mem_writew(void *opaque
, target_phys_addr_t addr
,
2511 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2513 addr
&= s
->cirrus_addr_mask
;
2514 cpu_to_le16w((uint16_t *)(s
->vram_ptr
+ addr
), val
);
2515 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2518 static void cirrus_linear_mem_writel(void *opaque
, target_phys_addr_t addr
,
2521 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2523 addr
&= s
->cirrus_addr_mask
;
2524 cpu_to_le32w((uint32_t *)(s
->vram_ptr
+ addr
), val
);
2525 cpu_physical_memory_set_dirty(s
->vram_offset
+ addr
);
2528 /***************************************
2530 * system to screen memory access
2532 ***************************************/
2535 static uint32_t cirrus_linear_bitblt_readb(void *opaque
, target_phys_addr_t addr
)
2539 /* XXX handle bitblt */
2544 static uint32_t cirrus_linear_bitblt_readw(void *opaque
, target_phys_addr_t addr
)
2547 #ifdef TARGET_WORDS_BIGENDIAN
2548 v
= cirrus_linear_bitblt_readb(opaque
, addr
) << 8;
2549 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1);
2551 v
= cirrus_linear_bitblt_readb(opaque
, addr
);
2552 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 8;
2557 static uint32_t cirrus_linear_bitblt_readl(void *opaque
, target_phys_addr_t addr
)
2560 #ifdef TARGET_WORDS_BIGENDIAN
2561 v
= cirrus_linear_bitblt_readb(opaque
, addr
) << 24;
2562 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 16;
2563 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 2) << 8;
2564 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 3);
2566 v
= cirrus_linear_bitblt_readb(opaque
, addr
);
2567 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 1) << 8;
2568 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 2) << 16;
2569 v
|= cirrus_linear_bitblt_readb(opaque
, addr
+ 3) << 24;
2574 static void cirrus_linear_bitblt_writeb(void *opaque
, target_phys_addr_t addr
,
2577 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2579 if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2581 *s
->cirrus_srcptr
++ = (uint8_t) val
;
2582 if (s
->cirrus_srcptr
>= s
->cirrus_srcptr_end
) {
2583 cirrus_bitblt_cputovideo_next(s
);
2588 static void cirrus_linear_bitblt_writew(void *opaque
, target_phys_addr_t addr
,
2591 #ifdef TARGET_WORDS_BIGENDIAN
2592 cirrus_linear_bitblt_writeb(opaque
, addr
, (val
>> 8) & 0xff);
2593 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, val
& 0xff);
2595 cirrus_linear_bitblt_writeb(opaque
, addr
, val
& 0xff);
2596 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2600 static void cirrus_linear_bitblt_writel(void *opaque
, target_phys_addr_t addr
,
2603 #ifdef TARGET_WORDS_BIGENDIAN
2604 cirrus_linear_bitblt_writeb(opaque
, addr
, (val
>> 24) & 0xff);
2605 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
2606 cirrus_linear_bitblt_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
2607 cirrus_linear_bitblt_writeb(opaque
, addr
+ 3, val
& 0xff);
2609 cirrus_linear_bitblt_writeb(opaque
, addr
, val
& 0xff);
2610 cirrus_linear_bitblt_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
2611 cirrus_linear_bitblt_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
2612 cirrus_linear_bitblt_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
2617 static CPUReadMemoryFunc
*cirrus_linear_bitblt_read
[3] = {
2618 cirrus_linear_bitblt_readb
,
2619 cirrus_linear_bitblt_readw
,
2620 cirrus_linear_bitblt_readl
,
2623 static CPUWriteMemoryFunc
*cirrus_linear_bitblt_write
[3] = {
2624 cirrus_linear_bitblt_writeb
,
2625 cirrus_linear_bitblt_writew
,
2626 cirrus_linear_bitblt_writel
,
2629 static void map_linear_vram(CirrusVGAState
*s
)
2631 vga_dirty_log_stop((VGAState
*)s
);
2633 vga_dirty_log_stop((VGAState
*)s
);
2634 if (!s
->map_addr
&& s
->lfb_addr
&& s
->lfb_end
) {
2635 s
->map_addr
= s
->lfb_addr
;
2636 s
->map_end
= s
->lfb_end
;
2637 cpu_register_physical_memory(s
->map_addr
, s
->map_end
- s
->map_addr
, s
->vram_offset
);
2644 s
->lfb_vram_mapped
= 0;
2646 cpu_register_physical_memory(isa_mem_base
+ 0xa0000, 0x8000,
2647 (s
->vram_offset
+ s
->cirrus_bank_base
[0]) | IO_MEM_UNASSIGNED
);
2648 cpu_register_physical_memory(isa_mem_base
+ 0xa8000, 0x8000,
2649 (s
->vram_offset
+ s
->cirrus_bank_base
[1]) | IO_MEM_UNASSIGNED
);
2650 if (!(s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
)
2651 && !((s
->sr
[0x07] & 0x01) == 0)
2652 && !((s
->gr
[0x0B] & 0x14) == 0x14)
2653 && !(s
->gr
[0x0B] & 0x02)) {
2655 cpu_register_physical_memory(isa_mem_base
+ 0xa0000, 0x8000,
2656 (s
->vram_offset
+ s
->cirrus_bank_base
[0]) | IO_MEM_RAM
);
2657 cpu_register_physical_memory(isa_mem_base
+ 0xa8000, 0x8000,
2658 (s
->vram_offset
+ s
->cirrus_bank_base
[1]) | IO_MEM_RAM
);
2660 s
->lfb_vram_mapped
= 1;
2663 cpu_register_physical_memory(isa_mem_base
+ 0xa0000, 0x20000,
2668 vga_dirty_log_start((VGAState
*)s
);
2671 static void unmap_linear_vram(CirrusVGAState
*s
)
2673 vga_dirty_log_stop((VGAState
*)s
);
2674 if (s
->map_addr
&& s
->lfb_addr
&& s
->lfb_end
)
2675 s
->map_addr
= s
->map_end
= 0;
2677 cpu_register_physical_memory(isa_mem_base
+ 0xa0000, 0x20000,
2680 vga_dirty_log_start((VGAState
*)s
);
2683 /* Compute the memory access functions */
2684 static void cirrus_update_memory_access(CirrusVGAState
*s
)
2688 if ((s
->sr
[0x17] & 0x44) == 0x44) {
2690 } else if (s
->cirrus_srcptr
!= s
->cirrus_srcptr_end
) {
2693 if ((s
->gr
[0x0B] & 0x14) == 0x14) {
2695 } else if (s
->gr
[0x0B] & 0x02) {
2699 mode
= s
->gr
[0x05] & 0x7;
2700 if (mode
< 4 || mode
> 5 || ((s
->gr
[0x0B] & 0x4) == 0)) {
2702 s
->cirrus_linear_write
[0] = cirrus_linear_mem_writeb
;
2703 s
->cirrus_linear_write
[1] = cirrus_linear_mem_writew
;
2704 s
->cirrus_linear_write
[2] = cirrus_linear_mem_writel
;
2707 unmap_linear_vram(s
);
2708 s
->cirrus_linear_write
[0] = cirrus_linear_writeb
;
2709 s
->cirrus_linear_write
[1] = cirrus_linear_writew
;
2710 s
->cirrus_linear_write
[2] = cirrus_linear_writel
;
2718 static uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
2720 CirrusVGAState
*s
= opaque
;
2723 /* check port range access depending on color/monochrome mode */
2724 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
))
2725 || (addr
>= 0x3d0 && addr
<= 0x3df
2726 && !(s
->msr
& MSR_COLOR_EMULATION
))) {
2731 if (s
->ar_flip_flop
== 0) {
2738 index
= s
->ar_index
& 0x1f;
2751 if (cirrus_hook_read_sr(s
, s
->sr_index
, &val
))
2753 val
= s
->sr
[s
->sr_index
];
2754 #ifdef DEBUG_VGA_REG
2755 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
2759 cirrus_read_hidden_dac(s
, &val
);
2765 val
= s
->dac_write_index
;
2766 s
->cirrus_hidden_dac_lockindex
= 0;
2769 if (cirrus_hook_read_palette(s
, &val
))
2771 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
2772 if (++s
->dac_sub_index
== 3) {
2773 s
->dac_sub_index
= 0;
2774 s
->dac_read_index
++;
2787 if (cirrus_hook_read_gr(s
, s
->gr_index
, &val
))
2789 val
= s
->gr
[s
->gr_index
];
2790 #ifdef DEBUG_VGA_REG
2791 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
2800 if (cirrus_hook_read_cr(s
, s
->cr_index
, &val
))
2802 val
= s
->cr
[s
->cr_index
];
2803 #ifdef DEBUG_VGA_REG
2804 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
2809 /* just toggle to fool polling */
2810 val
= s
->st01
= s
->retrace((VGAState
*) s
);
2811 s
->ar_flip_flop
= 0;
2818 #if defined(DEBUG_VGA)
2819 printf("VGA: read addr=0x%04x data=0x%02x\n", addr
, val
);
2824 static void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
2826 CirrusVGAState
*s
= opaque
;
2829 /* check port range access depending on color/monochrome mode */
2830 if ((addr
>= 0x3b0 && addr
<= 0x3bf && (s
->msr
& MSR_COLOR_EMULATION
))
2831 || (addr
>= 0x3d0 && addr
<= 0x3df
2832 && !(s
->msr
& MSR_COLOR_EMULATION
)))
2836 printf("VGA: write addr=0x%04x data=0x%02x\n", addr
, val
);
2841 if (s
->ar_flip_flop
== 0) {
2845 index
= s
->ar_index
& 0x1f;
2848 s
->ar
[index
] = val
& 0x3f;
2851 s
->ar
[index
] = val
& ~0x10;
2857 s
->ar
[index
] = val
& ~0xc0;
2860 s
->ar
[index
] = val
& ~0xf0;
2863 s
->ar
[index
] = val
& ~0xf0;
2869 s
->ar_flip_flop
^= 1;
2872 s
->msr
= val
& ~0x10;
2873 s
->update_retrace_info((VGAState
*) s
);
2879 if (cirrus_hook_write_sr(s
, s
->sr_index
, val
))
2881 #ifdef DEBUG_VGA_REG
2882 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
2884 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
2885 if (s
->sr_index
== 1) s
->update_retrace_info((VGAState
*) s
);
2888 cirrus_write_hidden_dac(s
, val
);
2891 s
->dac_read_index
= val
;
2892 s
->dac_sub_index
= 0;
2896 s
->dac_write_index
= val
;
2897 s
->dac_sub_index
= 0;
2901 if (cirrus_hook_write_palette(s
, val
))
2903 s
->dac_cache
[s
->dac_sub_index
] = val
;
2904 if (++s
->dac_sub_index
== 3) {
2905 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
2906 s
->dac_sub_index
= 0;
2907 s
->dac_write_index
++;
2914 if (cirrus_hook_write_gr(s
, s
->gr_index
, val
))
2916 #ifdef DEBUG_VGA_REG
2917 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
2919 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
2927 if (cirrus_hook_write_cr(s
, s
->cr_index
, val
))
2929 #ifdef DEBUG_VGA_REG
2930 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
2932 /* handle CR0-7 protection */
2933 if ((s
->cr
[0x11] & 0x80) && s
->cr_index
<= 7) {
2934 /* can always write bit 4 of CR7 */
2935 if (s
->cr_index
== 7)
2936 s
->cr
[7] = (s
->cr
[7] & ~0x10) | (val
& 0x10);
2939 switch (s
->cr_index
) {
2940 case 0x01: /* horizontal display end */
2945 case 0x12: /* vertical display end */
2946 s
->cr
[s
->cr_index
] = val
;
2950 s
->cr
[s
->cr_index
] = val
;
2954 switch(s
->cr_index
) {
2962 s
->update_retrace_info((VGAState
*) s
);
2968 s
->fcr
= val
& 0x10;
2973 /***************************************
2975 * memory-mapped I/O access
2977 ***************************************/
2979 static uint32_t cirrus_mmio_readb(void *opaque
, target_phys_addr_t addr
)
2981 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
2983 addr
&= CIRRUS_PNPMMIO_SIZE
- 1;
2985 if (addr
>= 0x100) {
2986 return cirrus_mmio_blt_read(s
, addr
- 0x100);
2988 return vga_ioport_read(s
, addr
+ 0x3c0);
2992 static uint32_t cirrus_mmio_readw(void *opaque
, target_phys_addr_t addr
)
2995 #ifdef TARGET_WORDS_BIGENDIAN
2996 v
= cirrus_mmio_readb(opaque
, addr
) << 8;
2997 v
|= cirrus_mmio_readb(opaque
, addr
+ 1);
2999 v
= cirrus_mmio_readb(opaque
, addr
);
3000 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 8;
3005 static uint32_t cirrus_mmio_readl(void *opaque
, target_phys_addr_t addr
)
3008 #ifdef TARGET_WORDS_BIGENDIAN
3009 v
= cirrus_mmio_readb(opaque
, addr
) << 24;
3010 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 16;
3011 v
|= cirrus_mmio_readb(opaque
, addr
+ 2) << 8;
3012 v
|= cirrus_mmio_readb(opaque
, addr
+ 3);
3014 v
= cirrus_mmio_readb(opaque
, addr
);
3015 v
|= cirrus_mmio_readb(opaque
, addr
+ 1) << 8;
3016 v
|= cirrus_mmio_readb(opaque
, addr
+ 2) << 16;
3017 v
|= cirrus_mmio_readb(opaque
, addr
+ 3) << 24;
3022 static void cirrus_mmio_writeb(void *opaque
, target_phys_addr_t addr
,
3025 CirrusVGAState
*s
= (CirrusVGAState
*) opaque
;
3027 addr
&= CIRRUS_PNPMMIO_SIZE
- 1;
3029 if (addr
>= 0x100) {
3030 cirrus_mmio_blt_write(s
, addr
- 0x100, val
);
3032 vga_ioport_write(s
, addr
+ 0x3c0, val
);
3036 static void cirrus_mmio_writew(void *opaque
, target_phys_addr_t addr
,
3039 #ifdef TARGET_WORDS_BIGENDIAN
3040 cirrus_mmio_writeb(opaque
, addr
, (val
>> 8) & 0xff);
3041 cirrus_mmio_writeb(opaque
, addr
+ 1, val
& 0xff);
3043 cirrus_mmio_writeb(opaque
, addr
, val
& 0xff);
3044 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
3048 static void cirrus_mmio_writel(void *opaque
, target_phys_addr_t addr
,
3051 #ifdef TARGET_WORDS_BIGENDIAN
3052 cirrus_mmio_writeb(opaque
, addr
, (val
>> 24) & 0xff);
3053 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 16) & 0xff);
3054 cirrus_mmio_writeb(opaque
, addr
+ 2, (val
>> 8) & 0xff);
3055 cirrus_mmio_writeb(opaque
, addr
+ 3, val
& 0xff);
3057 cirrus_mmio_writeb(opaque
, addr
, val
& 0xff);
3058 cirrus_mmio_writeb(opaque
, addr
+ 1, (val
>> 8) & 0xff);
3059 cirrus_mmio_writeb(opaque
, addr
+ 2, (val
>> 16) & 0xff);
3060 cirrus_mmio_writeb(opaque
, addr
+ 3, (val
>> 24) & 0xff);
3065 static CPUReadMemoryFunc
*cirrus_mmio_read
[3] = {
3071 static CPUWriteMemoryFunc
*cirrus_mmio_write
[3] = {
3077 /* load/save state */
3079 static void cirrus_vga_save(QEMUFile
*f
, void *opaque
)
3081 CirrusVGAState
*s
= opaque
;
3084 pci_device_save(s
->pci_dev
, f
);
3086 qemu_put_be32s(f
, &s
->latch
);
3087 qemu_put_8s(f
, &s
->sr_index
);
3088 qemu_put_buffer(f
, s
->sr
, 256);
3089 qemu_put_8s(f
, &s
->gr_index
);
3090 qemu_put_8s(f
, &s
->cirrus_shadow_gr0
);
3091 qemu_put_8s(f
, &s
->cirrus_shadow_gr1
);
3092 qemu_put_buffer(f
, s
->gr
+ 2, 254);
3093 qemu_put_8s(f
, &s
->ar_index
);
3094 qemu_put_buffer(f
, s
->ar
, 21);
3095 qemu_put_be32(f
, s
->ar_flip_flop
);
3096 qemu_put_8s(f
, &s
->cr_index
);
3097 qemu_put_buffer(f
, s
->cr
, 256);
3098 qemu_put_8s(f
, &s
->msr
);
3099 qemu_put_8s(f
, &s
->fcr
);
3100 qemu_put_8s(f
, &s
->st00
);
3101 qemu_put_8s(f
, &s
->st01
);
3103 qemu_put_8s(f
, &s
->dac_state
);
3104 qemu_put_8s(f
, &s
->dac_sub_index
);
3105 qemu_put_8s(f
, &s
->dac_read_index
);
3106 qemu_put_8s(f
, &s
->dac_write_index
);
3107 qemu_put_buffer(f
, s
->dac_cache
, 3);
3108 qemu_put_buffer(f
, s
->palette
, 768);
3110 qemu_put_be32(f
, s
->bank_offset
);
3112 qemu_put_8s(f
, &s
->cirrus_hidden_dac_lockindex
);
3113 qemu_put_8s(f
, &s
->cirrus_hidden_dac_data
);
3115 qemu_put_be32s(f
, &s
->hw_cursor_x
);
3116 qemu_put_be32s(f
, &s
->hw_cursor_y
);
3117 /* XXX: we do not save the bitblt state - we assume we do not save
3118 the state when the blitter is active */
3121 static int cirrus_vga_load(QEMUFile
*f
, void *opaque
, int version_id
)
3123 CirrusVGAState
*s
= opaque
;
3129 if (s
->pci_dev
&& version_id
>= 2) {
3130 ret
= pci_device_load(s
->pci_dev
, f
);
3135 qemu_get_be32s(f
, &s
->latch
);
3136 qemu_get_8s(f
, &s
->sr_index
);
3137 qemu_get_buffer(f
, s
->sr
, 256);
3138 qemu_get_8s(f
, &s
->gr_index
);
3139 qemu_get_8s(f
, &s
->cirrus_shadow_gr0
);
3140 qemu_get_8s(f
, &s
->cirrus_shadow_gr1
);
3141 s
->gr
[0x00] = s
->cirrus_shadow_gr0
& 0x0f;
3142 s
->gr
[0x01] = s
->cirrus_shadow_gr1
& 0x0f;
3143 qemu_get_buffer(f
, s
->gr
+ 2, 254);
3144 qemu_get_8s(f
, &s
->ar_index
);
3145 qemu_get_buffer(f
, s
->ar
, 21);
3146 s
->ar_flip_flop
=qemu_get_be32(f
);
3147 qemu_get_8s(f
, &s
->cr_index
);
3148 qemu_get_buffer(f
, s
->cr
, 256);
3149 qemu_get_8s(f
, &s
->msr
);
3150 qemu_get_8s(f
, &s
->fcr
);
3151 qemu_get_8s(f
, &s
->st00
);
3152 qemu_get_8s(f
, &s
->st01
);
3154 qemu_get_8s(f
, &s
->dac_state
);
3155 qemu_get_8s(f
, &s
->dac_sub_index
);
3156 qemu_get_8s(f
, &s
->dac_read_index
);
3157 qemu_get_8s(f
, &s
->dac_write_index
);
3158 qemu_get_buffer(f
, s
->dac_cache
, 3);
3159 qemu_get_buffer(f
, s
->palette
, 768);
3161 s
->bank_offset
=qemu_get_be32(f
);
3163 qemu_get_8s(f
, &s
->cirrus_hidden_dac_lockindex
);
3164 qemu_get_8s(f
, &s
->cirrus_hidden_dac_data
);
3166 qemu_get_be32s(f
, &s
->hw_cursor_x
);
3167 qemu_get_be32s(f
, &s
->hw_cursor_y
);
3169 cirrus_update_memory_access(s
);
3171 s
->graphic_mode
= -1;
3172 cirrus_update_bank_ptr(s
, 0);
3173 cirrus_update_bank_ptr(s
, 1);
3177 /***************************************
3181 ***************************************/
3183 static void cirrus_reset(void *opaque
)
3185 CirrusVGAState
*s
= opaque
;
3188 unmap_linear_vram(s
);
3190 if (s
->device_id
== CIRRUS_ID_CLGD5446
) {
3191 /* 4MB 64 bit memory config, always PCI */
3192 s
->sr
[0x1F] = 0x2d; // MemClock
3193 s
->gr
[0x18] = 0x0f; // fastest memory configuration
3196 s
->sr
[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3198 s
->sr
[0x1F] = 0x22; // MemClock
3199 s
->sr
[0x0F] = CIRRUS_MEMSIZE_2M
;
3200 s
->sr
[0x17] = s
->bustype
;
3201 s
->sr
[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3203 s
->cr
[0x27] = s
->device_id
;
3205 /* Win2K seems to assume that the pattern buffer is at 0xff
3207 memset(s
->vram_ptr
, 0xff, s
->real_vram_size
);
3209 s
->cirrus_hidden_dac_lockindex
= 5;
3210 s
->cirrus_hidden_dac_data
= 0;
3213 static void cirrus_init_common(CirrusVGAState
* s
, int device_id
, int is_pci
)
3220 for(i
= 0;i
< 256; i
++)
3221 rop_to_index
[i
] = CIRRUS_ROP_NOP_INDEX
; /* nop rop */
3222 rop_to_index
[CIRRUS_ROP_0
] = 0;
3223 rop_to_index
[CIRRUS_ROP_SRC_AND_DST
] = 1;
3224 rop_to_index
[CIRRUS_ROP_NOP
] = 2;
3225 rop_to_index
[CIRRUS_ROP_SRC_AND_NOTDST
] = 3;
3226 rop_to_index
[CIRRUS_ROP_NOTDST
] = 4;
3227 rop_to_index
[CIRRUS_ROP_SRC
] = 5;
3228 rop_to_index
[CIRRUS_ROP_1
] = 6;
3229 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_DST
] = 7;
3230 rop_to_index
[CIRRUS_ROP_SRC_XOR_DST
] = 8;
3231 rop_to_index
[CIRRUS_ROP_SRC_OR_DST
] = 9;
3232 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_NOTDST
] = 10;
3233 rop_to_index
[CIRRUS_ROP_SRC_NOTXOR_DST
] = 11;
3234 rop_to_index
[CIRRUS_ROP_SRC_OR_NOTDST
] = 12;
3235 rop_to_index
[CIRRUS_ROP_NOTSRC
] = 13;
3236 rop_to_index
[CIRRUS_ROP_NOTSRC_OR_DST
] = 14;
3237 rop_to_index
[CIRRUS_ROP_NOTSRC_AND_NOTDST
] = 15;
3238 s
->device_id
= device_id
;
3240 s
->bustype
= CIRRUS_BUSTYPE_PCI
;
3242 s
->bustype
= CIRRUS_BUSTYPE_ISA
;
3245 register_ioport_write(0x3c0, 16, 1, vga_ioport_write
, s
);
3247 register_ioport_write(0x3b4, 2, 1, vga_ioport_write
, s
);
3248 register_ioport_write(0x3d4, 2, 1, vga_ioport_write
, s
);
3249 register_ioport_write(0x3ba, 1, 1, vga_ioport_write
, s
);
3250 register_ioport_write(0x3da, 1, 1, vga_ioport_write
, s
);
3252 register_ioport_read(0x3c0, 16, 1, vga_ioport_read
, s
);
3254 register_ioport_read(0x3b4, 2, 1, vga_ioport_read
, s
);
3255 register_ioport_read(0x3d4, 2, 1, vga_ioport_read
, s
);
3256 register_ioport_read(0x3ba, 1, 1, vga_ioport_read
, s
);
3257 register_ioport_read(0x3da, 1, 1, vga_ioport_read
, s
);
3259 s
->vga_io_memory
= cpu_register_io_memory(0, cirrus_vga_mem_read
,
3260 cirrus_vga_mem_write
, s
);
3261 cpu_register_physical_memory(isa_mem_base
+ 0x000a0000, 0x20000,
3263 qemu_register_coalesced_mmio(isa_mem_base
+ 0x000a0000, 0x20000);
3265 /* I/O handler for LFB */
3266 s
->cirrus_linear_io_addr
=
3267 cpu_register_io_memory(0, cirrus_linear_read
, cirrus_linear_write
, s
);
3268 s
->cirrus_linear_write
= cpu_get_io_memory_write(s
->cirrus_linear_io_addr
);
3270 /* I/O handler for LFB */
3271 s
->cirrus_linear_bitblt_io_addr
=
3272 cpu_register_io_memory(0, cirrus_linear_bitblt_read
,
3273 cirrus_linear_bitblt_write
, s
);
3275 /* I/O handler for memory-mapped I/O */
3276 s
->cirrus_mmio_io_addr
=
3277 cpu_register_io_memory(0, cirrus_mmio_read
, cirrus_mmio_write
, s
);
3280 (s
->device_id
== CIRRUS_ID_CLGD5446
) ? 4096 * 1024 : 2048 * 1024;
3282 /* XXX: s->vram_size must be a power of two */
3283 s
->cirrus_addr_mask
= s
->real_vram_size
- 1;
3284 s
->linear_mmio_mask
= s
->real_vram_size
- 256;
3286 s
->get_bpp
= cirrus_get_bpp
;
3287 s
->get_offsets
= cirrus_get_offsets
;
3288 s
->get_resolution
= cirrus_get_resolution
;
3289 s
->cursor_invalidate
= cirrus_cursor_invalidate
;
3290 s
->cursor_draw_line
= cirrus_cursor_draw_line
;
3292 qemu_register_reset(cirrus_reset
, s
);
3294 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save
, cirrus_vga_load
, s
);
3297 /***************************************
3301 ***************************************/
3303 void isa_cirrus_vga_init(uint8_t *vga_ram_base
,
3304 ram_addr_t vga_ram_offset
, int vga_ram_size
)
3308 s
= qemu_mallocz(sizeof(CirrusVGAState
));
3310 vga_common_init((VGAState
*)s
,
3311 vga_ram_base
, vga_ram_offset
, vga_ram_size
);
3312 cirrus_init_common(s
, CIRRUS_ID_CLGD5430
, 0);
3313 s
->ds
= graphic_console_init(s
->update
, s
->invalidate
,
3314 s
->screen_dump
, s
->text_update
, s
);
3315 /* XXX ISA-LFB support */
3318 /***************************************
3322 ***************************************/
3324 static void cirrus_pci_lfb_map(PCIDevice
*d
, int region_num
,
3325 uint32_t addr
, uint32_t size
, int type
)
3327 CirrusVGAState
*s
= &((PCICirrusVGAState
*)d
)->cirrus_vga
;
3329 vga_dirty_log_stop((VGAState
*)s
);
3331 /* XXX: add byte swapping apertures */
3332 cpu_register_physical_memory(addr
, s
->vram_size
,
3333 s
->cirrus_linear_io_addr
);
3334 cpu_register_physical_memory(addr
+ 0x1000000, 0x400000,
3335 s
->cirrus_linear_bitblt_io_addr
);
3337 s
->map_addr
= s
->map_end
= 0;
3338 s
->lfb_addr
= addr
& TARGET_PAGE_MASK
;
3339 s
->lfb_end
= ((addr
+ VGA_RAM_SIZE
) + TARGET_PAGE_SIZE
- 1) & TARGET_PAGE_MASK
;
3340 /* account for overflow */
3341 if (s
->lfb_end
< addr
+ VGA_RAM_SIZE
)
3342 s
->lfb_end
= addr
+ VGA_RAM_SIZE
;
3344 vga_dirty_log_start((VGAState
*)s
);
3347 static void cirrus_pci_mmio_map(PCIDevice
*d
, int region_num
,
3348 uint32_t addr
, uint32_t size
, int type
)
3350 CirrusVGAState
*s
= &((PCICirrusVGAState
*)d
)->cirrus_vga
;
3352 cpu_register_physical_memory(addr
, CIRRUS_PNPMMIO_SIZE
,
3353 s
->cirrus_mmio_io_addr
);
3356 static void pci_cirrus_write_config(PCIDevice
*d
,
3357 uint32_t address
, uint32_t val
, int len
)
3359 PCICirrusVGAState
*pvs
= container_of(d
, PCICirrusVGAState
, dev
);
3360 CirrusVGAState
*s
= &pvs
->cirrus_vga
;
3362 vga_dirty_log_stop((VGAState
*)s
);
3364 pci_default_write_config(d
, address
, val
, len
);
3365 if (s
->map_addr
&& pvs
->dev
.io_regions
[0].addr
== -1)
3367 cirrus_update_memory_access(s
);
3369 vga_dirty_log_start((VGAState
*)s
);
3372 void pci_cirrus_vga_init(PCIBus
*bus
, uint8_t *vga_ram_base
,
3373 ram_addr_t vga_ram_offset
, int vga_ram_size
)
3375 PCICirrusVGAState
*d
;
3380 device_id
= CIRRUS_ID_CLGD5446
;
3382 /* setup PCI configuration registers */
3383 d
= (PCICirrusVGAState
*)pci_register_device(bus
, "Cirrus VGA",
3384 sizeof(PCICirrusVGAState
),
3385 -1, NULL
, pci_cirrus_write_config
);
3386 pci_conf
= d
->dev
.config
;
3387 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_CIRRUS
);
3388 pci_config_set_device_id(pci_conf
, device_id
);
3389 pci_conf
[0x04] = PCI_COMMAND_IOACCESS
| PCI_COMMAND_MEMACCESS
;
3390 pci_config_set_class(pci_conf
, PCI_CLASS_DISPLAY_VGA
);
3391 pci_conf
[0x0e] = PCI_CLASS_HEADERTYPE_00h
;
3395 vga_common_init((VGAState
*)s
,
3396 vga_ram_base
, vga_ram_offset
, vga_ram_size
);
3397 cirrus_init_common(s
, device_id
, 1);
3399 s
->ds
= graphic_console_init(s
->update
, s
->invalidate
,
3400 s
->screen_dump
, s
->text_update
, s
);
3402 s
->pci_dev
= (PCIDevice
*)d
;
3404 /* setup memory space */
3406 /* memory #1 memory-mapped I/O */
3407 /* XXX: s->vram_size must be a power of two */
3408 pci_register_io_region((PCIDevice
*)d
, 0, 0x2000000,
3409 PCI_ADDRESS_SPACE_MEM_PREFETCH
, cirrus_pci_lfb_map
);
3410 if (device_id
== CIRRUS_ID_CLGD5446
) {
3411 pci_register_io_region((PCIDevice
*)d
, 1, CIRRUS_PNPMMIO_SIZE
,
3412 PCI_ADDRESS_SPACE_MEM
, cirrus_pci_mmio_map
);