hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  18  */
  19 #include "hw.h"
  20 #include "pc.h"
  21 #include "pci.h"
  22 #include "qemu-timer.h"
  23 #include "sysemu.h"
  24 #include "i2c.h"
  25 #include "smbus.h"
  26 #include "kvm.h"
  27 #include "qemu-kvm.h"
  28 #include "string.h"
  29
  30 //#define DEBUG
  31
  32 /* i82731AB (PIIX4) compatible power management function */
  33 #define PM_FREQ 3579545
  34
  35 #define ACPI_DBG_IO_ADDR  0xb044
  36
  37 typedef struct PIIX4PMState {
  38     PCIDevice dev;
  39     uint16_t pmsts;
  40     uint16_t pmen;
  41     uint16_t pmcntrl;
  42     uint8_t apmc;
  43     uint8_t apms;
  44     QEMUTimer *tmr_timer;
  45     int64_t tmr_overflow_time;
  46     i2c_bus *smbus;
  47     uint8_t smb_stat;
  48     uint8_t smb_ctl;
  49     uint8_t smb_cmd;
  50     uint8_t smb_addr;
  51     uint8_t smb_data0;
  52     uint8_t smb_data1;
  53     uint8_t smb_data[32];
  54     uint8_t smb_index;
  55     qemu_irq irq;
  56 } PIIX4PMState;
  57
  58 #define RSM_STS (1 << 15)
  59 #define PWRBTN_STS (1 << 8)
  60 #define RTC_EN (1 << 10)
  61 #define PWRBTN_EN (1 << 8)
  62 #define GBL_EN (1 << 5)
  63 #define TMROF_EN (1 << 0)
  64
  65 #define SCI_EN (1 << 0)
  66
  67 #define SUS_EN (1 << 13)
  68
  69 #define ACPI_ENABLE 0xf1
  70 #define ACPI_DISABLE 0xf0
  71
  72 #define SMBHSTSTS 0x00
  73 #define SMBHSTCNT 0x02
  74 #define SMBHSTCMD 0x03
  75 #define SMBHSTADD 0x04
  76 #define SMBHSTDAT0 0x05
  77 #define SMBHSTDAT1 0x06
  78 #define SMBBLKDAT 0x07
  79
  80 static PIIX4PMState *pm_state;
  81
  82 static uint32_t get_pmtmr(PIIX4PMState *s)
  83 {
  84     uint32_t d;
  85     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  86     return d & 0xffffff;
  87 }
  88
  89 static int get_pmsts(PIIX4PMState *s)
  90 {
  91     int64_t d;
  92     int pmsts;
  93     pmsts = s->pmsts;
  94     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  95     if (d >= s->tmr_overflow_time)
  96         s->pmsts |= TMROF_EN;
  97     return s->pmsts;
  98 }
  99
 100 static void pm_update_sci(PIIX4PMState *s)
 101 {
 102     int sci_level, pmsts;
 103     int64_t expire_time;
 104
 105     pmsts = get_pmsts(s);
 106     sci_level = (((pmsts & s->pmen) &
 107                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
 108     qemu_set_irq(s->irq, sci_level);
 109     /* schedule a timer interruption if needed */
 110     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 111         expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
 112         qemu_mod_timer(s->tmr_timer, expire_time);
 113     } else {
 114         qemu_del_timer(s->tmr_timer);
 115     }
 116 }
 117
 118 static void pm_tmr_timer(void *opaque)
 119 {
 120     PIIX4PMState *s = opaque;
 121     pm_update_sci(s);
 122 }
 123
 124 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 125 {
 126     PIIX4PMState *s = opaque;
 127     addr &= 0x3f;
 128     switch(addr) {
 129     case 0x00:
 130         {
 131             int64_t d;
 132             int pmsts;
 133             pmsts = get_pmsts(s);
 134             if (pmsts & val & TMROF_EN) {
 135                 /* if TMRSTS is reset, then compute the new overflow time */
 136                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
 137                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 138             }
 139             s->pmsts &= ~val;
 140             pm_update_sci(s);
 141         }
 142         break;
 143     case 0x02:
 144         s->pmen = val;
 145         pm_update_sci(s);
 146         break;
 147     case 0x04:
 148         {
 149             int sus_typ;
 150             s->pmcntrl = val & ~(SUS_EN);
 151             if (val & SUS_EN) {
 152                 /* change suspend type */
 153                 sus_typ = (val >> 10) & 7;
 154                 switch(sus_typ) {
 155                 case 0: /* soft power off */
 156                     qemu_system_shutdown_request();
 157                     break;
 158                 case 1:
 159                     /* RSM_STS should be set on resume. Pretend that resume
 160                        was caused by power button */
 161                     s->pmsts |= (RSM_STS | PWRBTN_STS);
 162                     qemu_system_reset_request();
 163 #if defined(TARGET_I386)
 164                     cmos_set_s3_resume();
 165 #endif
 166                 default:
 167                     break;
 168                 }
 169             }
 170         }
 171         break;
 172     default:
 173         break;
 174     }
 175 #ifdef DEBUG
 176     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 177 #endif
 178 }
 179
 180 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 181 {
 182     PIIX4PMState *s = opaque;
 183     uint32_t val;
 184
 185     addr &= 0x3f;
 186     switch(addr) {
 187     case 0x00:
 188         val = get_pmsts(s);
 189         break;
 190     case 0x02:
 191         val = s->pmen;
 192         break;
 193     case 0x04:
 194         val = s->pmcntrl;
 195         break;
 196     default:
 197         val = 0;
 198         break;
 199     }
 200 #ifdef DEBUG
 201     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 202 #endif
 203     return val;
 204 }
 205
 206 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 207 {
 208     //    PIIX4PMState *s = opaque;
 209     addr &= 0x3f;
 210 #ifdef DEBUG
 211     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 212 #endif
 213 }
 214
 215 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 216 {
 217     PIIX4PMState *s = opaque;
 218     uint32_t val;
 219
 220     addr &= 0x3f;
 221     switch(addr) {
 222     case 0x08:
 223         val = get_pmtmr(s);
 224         break;
 225     default:
 226         val = 0;
 227         break;
 228     }
 229 #ifdef DEBUG
 230     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 231 #endif
 232     return val;
 233 }
 234
 235 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
 236 {
 237     PIIX4PMState *s = opaque;
 238     addr &= 1;
 239 #ifdef DEBUG
 240     printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
 241 #endif
 242     if (addr == 0) {
 243         s->apmc = val;
 244
 245         /* ACPI specs 3.0, 4.7.2.5 */
 246         if (val == ACPI_ENABLE) {
 247             s->pmcntrl |= SCI_EN;
 248         } else if (val == ACPI_DISABLE) {
 249             s->pmcntrl &= ~SCI_EN;
 250         }
 251
 252         if (s->dev.config[0x5b] & (1 << 1)) {
 253             cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
 254         }
 255     } else {
 256         s->apms = val;
 257     }
 258 }
 259
 260 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
 261 {
 262     PIIX4PMState *s = opaque;
 263     uint32_t val;
 264
 265     addr &= 1;
 266     if (addr == 0) {
 267         val = s->apmc;
 268     } else {
 269         val = s->apms;
 270     }
 271 #ifdef DEBUG
 272     printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
 273 #endif
 274     return val;
 275 }
 276
 277 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 278 {
 279 #if defined(DEBUG)
 280     printf("ACPI: DBG: 0x%08x\n", val);
 281 #endif
 282 }
 283
 284 static void smb_transaction(PIIX4PMState *s)
 285 {
 286     uint8_t prot = (s->smb_ctl >> 2) & 0x07;
 287     uint8_t read = s->smb_addr & 0x01;
 288     uint8_t cmd = s->smb_cmd;
 289     uint8_t addr = s->smb_addr >> 1;
 290     i2c_bus *bus = s->smbus;
 291
 292 #ifdef DEBUG
 293     printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
 294 #endif
 295     switch(prot) {
 296     case 0x0:
 297         smbus_quick_command(bus, addr, read);
 298         break;
 299     case 0x1:
 300         if (read) {
 301             s->smb_data0 = smbus_receive_byte(bus, addr);
 302         } else {
 303             smbus_send_byte(bus, addr, cmd);
 304         }
 305         break;
 306     case 0x2:
 307         if (read) {
 308             s->smb_data0 = smbus_read_byte(bus, addr, cmd);
 309         } else {
 310             smbus_write_byte(bus, addr, cmd, s->smb_data0);
 311         }
 312         break;
 313     case 0x3:
 314         if (read) {
 315             uint16_t val;
 316             val = smbus_read_word(bus, addr, cmd);
 317             s->smb_data0 = val;
 318             s->smb_data1 = val >> 8;
 319         } else {
 320             smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
 321         }
 322         break;
 323     case 0x5:
 324         if (read) {
 325             s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
 326         } else {
 327             smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
 328         }
 329         break;
 330     default:
 331         goto error;
 332     }
 333     return;
 334
 335   error:
 336     s->smb_stat |= 0x04;
 337 }
 338
 339 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
 340 {
 341     PIIX4PMState *s = opaque;
 342     addr &= 0x3f;
 343 #ifdef DEBUG
 344     printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
 345 #endif
 346     switch(addr) {
 347     case SMBHSTSTS:
 348         s->smb_stat = 0;
 349         s->smb_index = 0;
 350         break;
 351     case SMBHSTCNT:
 352         s->smb_ctl = val;
 353         if (val & 0x40)
 354             smb_transaction(s);
 355         break;
 356     case SMBHSTCMD:
 357         s->smb_cmd = val;
 358         break;
 359     case SMBHSTADD:
 360         s->smb_addr = val;
 361         break;
 362     case SMBHSTDAT0:
 363         s->smb_data0 = val;
 364         break;
 365     case SMBHSTDAT1:
 366         s->smb_data1 = val;
 367         break;
 368     case SMBBLKDAT:
 369         s->smb_data[s->smb_index++] = val;
 370         if (s->smb_index > 31)
 371             s->smb_index = 0;
 372         break;
 373     default:
 374         break;
 375     }
 376 }
 377
 378 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
 379 {
 380     PIIX4PMState *s = opaque;
 381     uint32_t val;
 382
 383     addr &= 0x3f;
 384     switch(addr) {
 385     case SMBHSTSTS:
 386         val = s->smb_stat;
 387         break;
 388     case SMBHSTCNT:
 389         s->smb_index = 0;
 390         val = s->smb_ctl & 0x1f;
 391         break;
 392     case SMBHSTCMD:
 393         val = s->smb_cmd;
 394         break;
 395     case SMBHSTADD:
 396         val = s->smb_addr;
 397         break;
 398     case SMBHSTDAT0:
 399         val = s->smb_data0;
 400         break;
 401     case SMBHSTDAT1:
 402         val = s->smb_data1;
 403         break;
 404     case SMBBLKDAT:
 405         val = s->smb_data[s->smb_index++];
 406         if (s->smb_index > 31)
 407             s->smb_index = 0;
 408         break;
 409     default:
 410         val = 0;
 411         break;
 412     }
 413 #ifdef DEBUG
 414     printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
 415 #endif
 416     return val;
 417 }
 418
 419 static void pm_io_space_update(PIIX4PMState *s)
 420 {
 421     uint32_t pm_io_base;
 422
 423     if (s->dev.config[0x80] & 1) {
 424         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 425         pm_io_base &= 0xffc0;
 426
 427         /* XXX: need to improve memory and ioport allocation */
 428 #if defined(DEBUG)
 429         printf("PM: mapping to 0x%x\n", pm_io_base);
 430 #endif
 431         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 432         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 433         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 434         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 435     }
 436 }
 437
 438 static void pm_write_config(PCIDevice *d,
 439                             uint32_t address, uint32_t val, int len)
 440 {
 441     pci_default_write_config(d, address, val, len);
 442     if (address == 0x80)
 443         pm_io_space_update((PIIX4PMState *)d);
 444 }
 445
 446 static void pm_save(QEMUFile* f,void *opaque)
 447 {
 448     PIIX4PMState *s = opaque;
 449
 450     pci_device_save(&s->dev, f);
 451
 452     qemu_put_be16s(f, &s->pmsts);
 453     qemu_put_be16s(f, &s->pmen);
 454     qemu_put_be16s(f, &s->pmcntrl);
 455     qemu_put_8s(f, &s->apmc);
 456     qemu_put_8s(f, &s->apms);
 457     qemu_put_timer(f, s->tmr_timer);
 458     qemu_put_be64(f, s->tmr_overflow_time);
 459 }
 460
 461 static int pm_load(QEMUFile* f,void* opaque,int version_id)
 462 {
 463     PIIX4PMState *s = opaque;
 464     int ret;
 465
 466     if (version_id > 1)
 467         return -EINVAL;
 468
 469     ret = pci_device_load(&s->dev, f);
 470     if (ret < 0)
 471         return ret;
 472
 473     qemu_get_be16s(f, &s->pmsts);
 474     qemu_get_be16s(f, &s->pmen);
 475     qemu_get_be16s(f, &s->pmcntrl);
 476     qemu_get_8s(f, &s->apmc);
 477     qemu_get_8s(f, &s->apms);
 478     qemu_get_timer(f, s->tmr_timer);
 479     s->tmr_overflow_time=qemu_get_be64(f);
 480
 481     pm_io_space_update(s);
 482
 483     return 0;
 484 }
 485
 486 static void piix4_reset(void *opaque)
 487 {
 488         PIIX4PMState *s = opaque;
 489         uint8_t *pci_conf = s->dev.config;
 490
 491         pci_conf[0x58] = 0;
 492         pci_conf[0x59] = 0;
 493         pci_conf[0x5a] = 0;
 494         pci_conf[0x5b] = 0;
 495 }
 496
 497 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 498                        qemu_irq sci_irq)
 499 {
 500     PIIX4PMState *s;
 501     uint8_t *pci_conf;
 502
 503     s = (PIIX4PMState *)pci_register_device(bus,
 504                                          "PM", sizeof(PIIX4PMState),
 505                                          devfn, NULL, pm_write_config);
 506     pm_state = s;
 507     pci_conf = s->dev.config;
 508     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 509     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 510     pci_conf[0x06] = 0x80;
 511     pci_conf[0x07] = 0x02;
 512     pci_conf[0x08] = 0x03; // revision number
 513     pci_conf[0x09] = 0x00;
 514     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 515     pci_conf[0x0e] = 0x00; // header_type
 516     pci_conf[0x3d] = 0x01; // interrupt pin 1
 517
 518     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 519
 520 #if defined(TARGET_IA64)
 521     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 522     pci_conf[0x41] = 0x1f;
 523     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 524     s->pmcntrl = SCI_EN;
 525 #endif
 526
 527     register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
 528     register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
 529
 530     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 531
 532     if (kvm_enabled()) {
 533         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 534          * support SMM mode. */
 535         pci_conf[0x5B] = 0x02;
 536     }
 537
 538     /* XXX: which specification is used ? The i82731AB has different
 539        mappings */
 540     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 541     pci_conf[0x63] = 0x60;
 542     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 543         (serial_hds[1] != NULL ? 0x90 : 0);
 544
 545     pci_conf[0x90] = smb_io_base | 1;
 546     pci_conf[0x91] = smb_io_base >> 8;
 547     pci_conf[0xd2] = 0x09;
 548     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
 549     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
 550
 551     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 552
 553     register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
 554
 555     s->smbus = i2c_init_bus();
 556     s->irq = sci_irq;
 557     qemu_register_reset(piix4_reset, s);
 558
 559     return s->smbus;
 560 }
 561
 562 #if defined(TARGET_I386)
 563 void qemu_system_powerdown(void)
 564 {
 565     if (!pm_state) {
 566         qemu_system_shutdown_request();
 567     } else if (pm_state->pmen & PWRBTN_EN) {
 568         pm_state->pmsts |= PWRBTN_EN;
 569         pm_update_sci(pm_state);
 570     }
 571 }
 572 #endif
 573 #define GPE_BASE 0xafe0
 574 #define PROC_BASE 0xaf00
 575 #define PCI_BASE 0xae00
 576 #define PCI_EJ_BASE 0xae08
 577
 578 struct gpe_regs {
 579     uint16_t sts; /* status */
 580     uint16_t en;  /* enabled */
 581     uint8_t up;
 582     uint8_t down;
 583 };
 584
 585 struct pci_status {
 586     uint32_t up;
 587     uint32_t down;
 588 };
 589
 590 static struct gpe_regs gpe;
 591 static struct pci_status pci0_status;
 592
 593 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 594 {
 595     uint32_t val = 0;
 596     struct gpe_regs *g = opaque;
 597     switch (addr) {
 598         case PROC_BASE:
 599             val = g->up;
 600             break;
 601         case PROC_BASE + 1:
 602             val = g->down;
 603             break;
 604
 605         case GPE_BASE:
 606             val = g->sts & 0xFF;
 607             break;
 608         case GPE_BASE + 1:
 609             val =  (g->sts >> 8) & 0xFF;
 610             break;
 611         case GPE_BASE + 2:
 612             val =  g->en & 0xFF;
 613             break;
 614         case GPE_BASE + 3:
 615             val =  (g->en >> 8) & 0xFF;
 616             break;
 617         default:
 618             break;
 619     }
 620
 621 #if defined(DEBUG)
 622     printf("gpe read %x == %x\n", addr, val);
 623 #endif
 624     return val;
 625 }
 626
 627 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 628 {
 629     struct gpe_regs *g = opaque;
 630     switch (addr) {
 631         case PROC_BASE:
 632             g->up = val;
 633             break;
 634         case PROC_BASE + 1:
 635             g->down = val;
 636             break;
 637
 638         case GPE_BASE:
 639             g->sts = (g->sts & ~0xFFFF) | (val & 0xFFFF);
 640             break;
 641         case GPE_BASE + 1:
 642             g->sts = (g->sts & 0xFFFF) | (val << 8);
 643             break;
 644         case GPE_BASE + 2:
 645             g->en = (g->en & ~0xFFFF) | (val & 0xFFFF);
 646             break;
 647         case GPE_BASE + 3:
 648             g->en = (g->en & 0xFFFF) | (val << 8);
 649             break;
 650         default:
 651             break;
 652    }
 653
 654 #if defined(DEBUG)
 655     printf("gpe write %x <== %d\n", addr, val);
 656 #endif
 657 }
 658
 659 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 660 {
 661     uint32_t val = 0;
 662     struct pci_status *g = opaque;
 663     switch (addr) {
 664         case PCI_BASE:
 665             val = g->up;
 666             break;
 667         case PCI_BASE + 4:
 668             val = g->down;
 669             break;
 670         default:
 671             break;
 672     }
 673
 674 #if defined(DEBUG)
 675     printf("pcihotplug read %x == %x\n", addr, val);
 676 #endif
 677     return val;
 678 }
 679
 680 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 681 {
 682     struct pci_status *g = opaque;
 683     switch (addr) {
 684         case PCI_BASE:
 685             g->up = val;
 686             break;
 687         case PCI_BASE + 4:
 688             g->down = val;
 689             break;
 690    }
 691
 692 #if defined(DEBUG)
 693     printf("pcihotplug write %x <== %d\n", addr, val);
 694 #endif
 695 }
 696
 697 static uint32_t pciej_read(void *opaque, uint32_t addr)
 698 {
 699 #if defined(DEBUG)
 700     printf("pciej read %x\n", addr);
 701 #endif
 702     return 0;
 703 }
 704
 705 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 706 {
 707     int slot = ffs(val) - 1;
 708
 709     device_hot_remove_success(0, slot);
 710
 711 #if defined(DEBUG)
 712     printf("pciej write %x <== %d\n", addr, val);
 713 #endif
 714 }
 715
 716 static const char *model;
 717
 718 void qemu_system_hot_add_init(const char *cpu_model)
 719 {
 720     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 721     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 722
 723     register_ioport_write(PROC_BASE, 4, 1, gpe_writeb, &gpe);
 724     register_ioport_read(PROC_BASE, 4, 1,  gpe_readb, &gpe);
 725
 726     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 727     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 728
 729     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
 730     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, NULL);
 731
 732     model = cpu_model;
 733 }
 734
 735 static void enable_processor(struct gpe_regs *g, int cpu)
 736 {
 737     g->sts |= 1;
 738     g->en |= 1;
 739     g->up |= (1 << cpu);
 740 }
 741
 742 static void disable_processor(struct gpe_regs *g, int cpu)
 743 {
 744     g->sts |= 1;
 745     g->en |= 1;
 746     g->down |= (1 << cpu);
 747 }
 748
 749 #if defined(TARGET_I386) || defined(TARGET_X86_64)
 750 #ifdef USE_KVM
 751 static CPUState *qemu_kvm_cpu_env(int index)
 752 {
 753     CPUState *penv;
 754
 755     penv = first_cpu;
 756
 757     while (penv) {
 758         if (penv->cpu_index == index)
 759             return penv;
 760         penv = (CPUState *)penv->next_cpu;
 761     }
 762
 763     return NULL;
 764 }
 765 #endif
 766
 767
 768 void qemu_system_cpu_hot_add(int cpu, int state)
 769 {
 770     CPUState *env;
 771
 772     if (state
 773 #ifdef USE_KVM
 774         && (!qemu_kvm_cpu_env(cpu))
 775 #endif
 776     ) {
 777         env = pc_new_cpu(cpu, model, 1);
 778         if (!env) {
 779             fprintf(stderr, "cpu %d creation failed\n", cpu);
 780             return;
 781         }
 782 #ifdef USE_KVM
 783         kvm_init_vcpu(env);
 784 #endif
 785     }
 786
 787     qemu_set_irq(pm_state->irq, 1);
 788     gpe.up = 0;
 789     gpe.down = 0;
 790     if (state)
 791         enable_processor(&gpe, cpu);
 792     else
 793         disable_processor(&gpe, cpu);
 794     qemu_set_irq(pm_state->irq, 0);
 795 }
 796 #endif
 797
 798 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 799 {
 800     g->sts |= 2;
 801     g->en |= 2;
 802     p->up |= (1 << slot);
 803 }
 804
 805 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 806 {
 807     g->sts |= 2;
 808     g->en |= 2;
 809     p->down |= (1 << slot);
 810 }
 811
 812 void qemu_system_device_hot_add(int pcibus, int slot, int state)
 813 {
 814     qemu_set_irq(pm_state->irq, 1);
 815     pci0_status.up = 0;
 816     pci0_status.down = 0;
 817     if (state)
 818         enable_device(&pci0_status, &gpe, slot);
 819     else
 820         disable_device(&pci0_status, &gpe, slot);
 821     qemu_set_irq(pm_state->irq, 0);
 822 }