2 * qemu/kvm integration, x86 specific code
4 * Copyright (C) 2006-2008 Qumranet Technologies
6 * Licensed under the terms of the GNU GPL version 2 or higher.
10 #include "config-host.h"
20 #include <sys/utsname.h>
21 #include <linux/kvm_para.h>
23 #define MSR_IA32_TSC 0x10
25 static struct kvm_msr_list
*kvm_msr_list
;
26 extern unsigned int kvm_shadow_memory
;
27 static int kvm_has_msr_star
;
28 static int kvm_has_vm_hsave_pa
;
30 static int lm_capable_kernel
;
32 int kvm_qemu_create_memory_alias(uint64_t phys_start
,
36 return kvm_create_memory_alias(kvm_context
, phys_start
, len
, target_phys
);
39 int kvm_qemu_destroy_memory_alias(uint64_t phys_start
)
41 return kvm_destroy_memory_alias(kvm_context
, phys_start
);
44 int kvm_arch_qemu_create_context(void)
47 struct utsname utsname
;
50 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
52 if (kvm_shadow_memory
)
53 kvm_set_shadow_pages(kvm_context
, kvm_shadow_memory
);
55 kvm_msr_list
= kvm_get_msr_list(kvm_context
);
58 for (i
= 0; i
< kvm_msr_list
->nmsrs
; ++i
) {
59 if (kvm_msr_list
->indices
[i
] == MSR_STAR
)
61 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
)
62 kvm_has_vm_hsave_pa
= 1;
68 static void set_msr_entry(struct kvm_msr_entry
*entry
, uint32_t index
,
75 /* returns 0 on success, non-0 on failure */
76 static int get_msr_entry(struct kvm_msr_entry
*entry
, CPUState
*env
)
78 switch (entry
->index
) {
79 case MSR_IA32_SYSENTER_CS
:
80 env
->sysenter_cs
= entry
->data
;
82 case MSR_IA32_SYSENTER_ESP
:
83 env
->sysenter_esp
= entry
->data
;
85 case MSR_IA32_SYSENTER_EIP
:
86 env
->sysenter_eip
= entry
->data
;
89 env
->star
= entry
->data
;
93 env
->cstar
= entry
->data
;
95 case MSR_KERNELGSBASE
:
96 env
->kernelgsbase
= entry
->data
;
99 env
->fmask
= entry
->data
;
102 env
->lstar
= entry
->data
;
106 env
->tsc
= entry
->data
;
108 case MSR_VM_HSAVE_PA
:
109 env
->vm_hsave
= entry
->data
;
112 printf("Warning unknown msr index 0x%x\n", entry
->index
);
124 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
126 lhs
->selector
= rhs
->selector
;
127 lhs
->base
= rhs
->base
;
128 lhs
->limit
= rhs
->limit
;
140 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
142 unsigned flags
= rhs
->flags
;
143 lhs
->selector
= rhs
->selector
;
144 lhs
->base
= rhs
->base
;
145 lhs
->limit
= rhs
->limit
;
146 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
147 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
148 lhs
->dpl
= rhs
->selector
& 3;
149 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
150 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
151 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
152 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
153 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
157 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
159 lhs
->selector
= rhs
->selector
;
160 lhs
->base
= rhs
->base
;
161 lhs
->limit
= rhs
->limit
;
163 (rhs
->type
<< DESC_TYPE_SHIFT
)
164 | (rhs
->present
* DESC_P_MASK
)
165 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
166 | (rhs
->db
<< DESC_B_SHIFT
)
167 | (rhs
->s
* DESC_S_MASK
)
168 | (rhs
->l
<< DESC_L_SHIFT
)
169 | (rhs
->g
* DESC_G_MASK
)
170 | (rhs
->avl
* DESC_AVL_MASK
);
173 void kvm_arch_load_regs(CPUState
*env
)
175 struct kvm_regs regs
;
177 struct kvm_sregs sregs
;
178 struct kvm_msr_entry msrs
[MSR_COUNT
];
181 regs
.rax
= env
->regs
[R_EAX
];
182 regs
.rbx
= env
->regs
[R_EBX
];
183 regs
.rcx
= env
->regs
[R_ECX
];
184 regs
.rdx
= env
->regs
[R_EDX
];
185 regs
.rsi
= env
->regs
[R_ESI
];
186 regs
.rdi
= env
->regs
[R_EDI
];
187 regs
.rsp
= env
->regs
[R_ESP
];
188 regs
.rbp
= env
->regs
[R_EBP
];
190 regs
.r8
= env
->regs
[8];
191 regs
.r9
= env
->regs
[9];
192 regs
.r10
= env
->regs
[10];
193 regs
.r11
= env
->regs
[11];
194 regs
.r12
= env
->regs
[12];
195 regs
.r13
= env
->regs
[13];
196 regs
.r14
= env
->regs
[14];
197 regs
.r15
= env
->regs
[15];
200 regs
.rflags
= env
->eflags
;
203 kvm_set_regs(kvm_context
, env
->cpu_index
, ®s
);
205 memset(&fpu
, 0, sizeof fpu
);
206 fpu
.fsw
= env
->fpus
& ~(7 << 11);
207 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
209 for (i
= 0; i
< 8; ++i
)
210 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
211 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
212 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
213 fpu
.mxcsr
= env
->mxcsr
;
214 kvm_set_fpu(kvm_context
, env
->cpu_index
, &fpu
);
216 memcpy(sregs
.interrupt_bitmap
, env
->interrupt_bitmap
, sizeof(sregs
.interrupt_bitmap
));
218 if ((env
->eflags
& VM_MASK
)) {
219 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
220 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
221 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
222 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
223 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
224 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
226 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
227 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
228 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
229 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
230 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
231 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
233 if (env
->cr
[0] & CR0_PE_MASK
) {
234 /* force ss cpl to cs cpl */
235 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
236 (sregs
.cs
.selector
& 3);
237 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
241 set_seg(&sregs
.tr
, &env
->tr
);
242 set_seg(&sregs
.ldt
, &env
->ldt
);
244 sregs
.idt
.limit
= env
->idt
.limit
;
245 sregs
.idt
.base
= env
->idt
.base
;
246 sregs
.gdt
.limit
= env
->gdt
.limit
;
247 sregs
.gdt
.base
= env
->gdt
.base
;
249 sregs
.cr0
= env
->cr
[0];
250 sregs
.cr2
= env
->cr
[2];
251 sregs
.cr3
= env
->cr
[3];
252 sregs
.cr4
= env
->cr
[4];
254 sregs
.cr8
= cpu_get_apic_tpr(env
);
255 sregs
.apic_base
= cpu_get_apic_base(env
);
257 sregs
.efer
= env
->efer
;
259 kvm_set_sregs(kvm_context
, env
->cpu_index
, &sregs
);
263 /* Remember to increase MSR_COUNT if you add new registers below */
264 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
265 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
266 set_msr_entry(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
267 if (kvm_has_msr_star
)
268 set_msr_entry(&msrs
[n
++], MSR_STAR
, env
->star
);
269 if (kvm_has_vm_hsave_pa
)
270 set_msr_entry(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
272 if (lm_capable_kernel
) {
273 set_msr_entry(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
274 set_msr_entry(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
275 set_msr_entry(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
276 set_msr_entry(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
280 rc
= kvm_set_msrs(kvm_context
, env
->cpu_index
, msrs
, n
);
282 perror("kvm_set_msrs FAILED");
285 void kvm_load_tsc(CPUState
*env
)
288 struct kvm_msr_entry msr
;
290 set_msr_entry(&msr
, MSR_IA32_TSC
, env
->tsc
);
292 rc
= kvm_set_msrs(kvm_context
, env
->cpu_index
, &msr
, 1);
294 perror("kvm_set_tsc FAILED.\n");
297 void kvm_save_mpstate(CPUState
*env
)
299 #ifdef KVM_CAP_MP_STATE
301 struct kvm_mp_state mp_state
;
303 r
= kvm_get_mpstate(kvm_context
, env
->cpu_index
, &mp_state
);
307 env
->mp_state
= mp_state
.mp_state
;
311 void kvm_load_mpstate(CPUState
*env
)
313 #ifdef KVM_CAP_MP_STATE
314 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
317 * -1 indicates that the host did not support GET_MP_STATE ioctl,
320 if (env
->mp_state
!= -1)
321 kvm_set_mpstate(kvm_context
, env
->cpu_index
, &mp_state
);
325 void kvm_arch_save_regs(CPUState
*env
)
327 struct kvm_regs regs
;
329 struct kvm_sregs sregs
;
330 struct kvm_msr_entry msrs
[MSR_COUNT
];
334 kvm_get_regs(kvm_context
, env
->cpu_index
, ®s
);
336 env
->regs
[R_EAX
] = regs
.rax
;
337 env
->regs
[R_EBX
] = regs
.rbx
;
338 env
->regs
[R_ECX
] = regs
.rcx
;
339 env
->regs
[R_EDX
] = regs
.rdx
;
340 env
->regs
[R_ESI
] = regs
.rsi
;
341 env
->regs
[R_EDI
] = regs
.rdi
;
342 env
->regs
[R_ESP
] = regs
.rsp
;
343 env
->regs
[R_EBP
] = regs
.rbp
;
345 env
->regs
[8] = regs
.r8
;
346 env
->regs
[9] = regs
.r9
;
347 env
->regs
[10] = regs
.r10
;
348 env
->regs
[11] = regs
.r11
;
349 env
->regs
[12] = regs
.r12
;
350 env
->regs
[13] = regs
.r13
;
351 env
->regs
[14] = regs
.r14
;
352 env
->regs
[15] = regs
.r15
;
355 env
->eflags
= regs
.rflags
;
358 kvm_get_fpu(kvm_context
, env
->cpu_index
, &fpu
);
359 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
362 for (i
= 0; i
< 8; ++i
)
363 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
364 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
365 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
366 env
->mxcsr
= fpu
.mxcsr
;
368 kvm_get_sregs(kvm_context
, env
->cpu_index
, &sregs
);
370 memcpy(env
->interrupt_bitmap
, sregs
.interrupt_bitmap
, sizeof(env
->interrupt_bitmap
));
372 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
373 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
374 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
375 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
376 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
377 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
379 get_seg(&env
->tr
, &sregs
.tr
);
380 get_seg(&env
->ldt
, &sregs
.ldt
);
382 env
->idt
.limit
= sregs
.idt
.limit
;
383 env
->idt
.base
= sregs
.idt
.base
;
384 env
->gdt
.limit
= sregs
.gdt
.limit
;
385 env
->gdt
.base
= sregs
.gdt
.base
;
387 env
->cr
[0] = sregs
.cr0
;
388 env
->cr
[2] = sregs
.cr2
;
389 env
->cr
[3] = sregs
.cr3
;
390 env
->cr
[4] = sregs
.cr4
;
392 cpu_set_apic_base(env
, sregs
.apic_base
);
394 env
->efer
= sregs
.efer
;
395 //cpu_set_apic_tpr(env, sregs.cr8);
397 #define HFLAG_COPY_MASK ~( \
398 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
399 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
400 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
401 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
405 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
406 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
407 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
408 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
409 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
410 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
411 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
413 if (env
->efer
& MSR_EFER_LMA
) {
414 hflags
|= HF_LMA_MASK
;
417 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
418 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
420 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
421 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
422 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
423 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
424 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
425 (env
->eflags
& VM_MASK
) ||
426 !(hflags
& HF_CS32_MASK
)) {
427 hflags
|= HF_ADDSEG_MASK
;
429 hflags
|= ((env
->segs
[R_DS
].base
|
430 env
->segs
[R_ES
].base
|
431 env
->segs
[R_SS
].base
) != 0) <<
435 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
439 /* Remember to increase MSR_COUNT if you add new registers below */
440 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
441 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
442 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
443 if (kvm_has_msr_star
)
444 msrs
[n
++].index
= MSR_STAR
;
445 msrs
[n
++].index
= MSR_IA32_TSC
;
446 if (kvm_has_vm_hsave_pa
)
447 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
449 if (lm_capable_kernel
) {
450 msrs
[n
++].index
= MSR_CSTAR
;
451 msrs
[n
++].index
= MSR_KERNELGSBASE
;
452 msrs
[n
++].index
= MSR_FMASK
;
453 msrs
[n
++].index
= MSR_LSTAR
;
456 rc
= kvm_get_msrs(kvm_context
, env
->cpu_index
, msrs
, n
);
458 perror("kvm_get_msrs FAILED");
461 n
= rc
; /* actual number of MSRs */
462 for (i
=0 ; i
<n
; i
++) {
463 if (get_msr_entry(&msrs
[i
], env
))
469 static void do_cpuid_ent(struct kvm_cpuid_entry2
*e
, uint32_t function
,
470 uint32_t count
, CPUState
*env
)
472 env
->regs
[R_EAX
] = function
;
473 env
->regs
[R_ECX
] = count
;
474 qemu_kvm_cpuid_on_env(env
);
475 e
->function
= function
;
478 e
->eax
= env
->regs
[R_EAX
];
479 e
->ebx
= env
->regs
[R_EBX
];
480 e
->ecx
= env
->regs
[R_ECX
];
481 e
->edx
= env
->regs
[R_EDX
];
484 struct kvm_para_features
{
487 } para_features
[] = {
488 #ifdef KVM_CAP_CLOCKSOURCE
489 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
491 #ifdef KVM_CAP_NOP_IO_DELAY
492 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
494 #ifdef KVM_CAP_PV_MMU
495 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
497 #ifdef KVM_CAP_CR3_CACHE
498 { KVM_CAP_CR3_CACHE
, KVM_FEATURE_CR3_CACHE
},
503 static int get_para_features(kvm_context_t kvm_context
)
507 for (i
= 0; i
< ARRAY_SIZE(para_features
)-1; i
++) {
508 if (kvm_check_extension(kvm_context
, para_features
[i
].cap
))
509 features
|= (1 << para_features
[i
].feature
);
515 int kvm_arch_qemu_init_env(CPUState
*cenv
)
517 struct kvm_cpuid_entry2 cpuid_ent
[100];
518 #ifdef KVM_CPUID_SIGNATURE
519 struct kvm_cpuid_entry2
*pv_ent
;
520 uint32_t signature
[3];
524 uint32_t i
, j
, limit
;
528 #ifdef KVM_CPUID_SIGNATURE
529 /* Paravirtualization CPUIDs */
530 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
531 pv_ent
= &cpuid_ent
[cpuid_nent
++];
532 memset(pv_ent
, 0, sizeof(*pv_ent
));
533 pv_ent
->function
= KVM_CPUID_SIGNATURE
;
535 pv_ent
->ebx
= signature
[0];
536 pv_ent
->ecx
= signature
[1];
537 pv_ent
->edx
= signature
[2];
539 pv_ent
= &cpuid_ent
[cpuid_nent
++];
540 memset(pv_ent
, 0, sizeof(*pv_ent
));
541 pv_ent
->function
= KVM_CPUID_FEATURES
;
542 pv_ent
->eax
= get_para_features(kvm_context
);
545 copy
.regs
[R_EAX
] = 0;
546 qemu_kvm_cpuid_on_env(©
);
547 limit
= copy
.regs
[R_EAX
];
549 for (i
= 0; i
<= limit
; ++i
) {
550 if (i
== 4 || i
== 0xb || i
== 0xd) {
552 do_cpuid_ent(&cpuid_ent
[cpuid_nent
], i
, j
, ©
);
554 cpuid_ent
[cpuid_nent
].flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
555 cpuid_ent
[cpuid_nent
].index
= j
;
559 if (i
== 4 && copy
.regs
[R_EAX
] == 0)
561 if (i
== 0xb && !(copy
.regs
[R_ECX
] & 0xff00))
563 if (i
== 0xd && copy
.regs
[R_EAX
] == 0)
567 do_cpuid_ent(&cpuid_ent
[cpuid_nent
++], i
, 0, ©
);
570 copy
.regs
[R_EAX
] = 0x80000000;
571 qemu_kvm_cpuid_on_env(©
);
572 limit
= copy
.regs
[R_EAX
];
574 for (i
= 0x80000000; i
<= limit
; ++i
)
575 do_cpuid_ent(&cpuid_ent
[cpuid_nent
++], i
, 0, ©
);
577 kvm_setup_cpuid2(kvm_context
, cenv
->cpu_index
, cpuid_nent
, cpuid_ent
);
581 int kvm_arch_halt(void *opaque
, int vcpu
)
583 CPUState
*env
= cpu_single_env
;
585 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
586 (env
->eflags
& IF_MASK
)) &&
587 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
589 env
->exception_index
= EXCP_HLT
;
594 void kvm_arch_pre_kvm_run(void *opaque
, CPUState
*env
)
596 if (!kvm_irqchip_in_kernel(kvm_context
))
597 kvm_set_cr8(kvm_context
, env
->cpu_index
, cpu_get_apic_tpr(env
));
600 void kvm_arch_post_kvm_run(void *opaque
, CPUState
*env
)
602 int vcpu
= env
->cpu_index
;
604 cpu_single_env
= env
;
606 env
->eflags
= kvm_get_interrupt_flag(kvm_context
, vcpu
)
607 ? env
->eflags
| IF_MASK
: env
->eflags
& ~IF_MASK
;
609 cpu_set_apic_tpr(env
, kvm_get_cr8(kvm_context
, vcpu
));
610 cpu_set_apic_base(env
, kvm_get_apic_base(kvm_context
, vcpu
));
613 int kvm_arch_has_work(CPUState
*env
)
615 if (((env
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_EXIT
)) &&
616 (env
->eflags
& IF_MASK
)) ||
617 (env
->interrupt_request
& CPU_INTERRUPT_NMI
))
622 int kvm_arch_try_push_interrupts(void *opaque
)
624 CPUState
*env
= cpu_single_env
;
627 if (kvm_is_ready_for_interrupt_injection(kvm_context
, env
->cpu_index
) &&
628 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
629 (env
->eflags
& IF_MASK
)) {
630 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
631 irq
= cpu_get_pic_interrupt(env
);
633 r
= kvm_inject_irq(kvm_context
, env
->cpu_index
, irq
);
635 printf("cpu %d fail inject %x\n", env
->cpu_index
, irq
);
639 return (env
->interrupt_request
& CPU_INTERRUPT_HARD
) != 0;
642 #ifdef KVM_CAP_USER_NMI
643 void kvm_arch_push_nmi(void *opaque
)
645 CPUState
*env
= cpu_single_env
;
648 if (likely(!(env
->interrupt_request
& CPU_INTERRUPT_NMI
)))
651 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
652 r
= kvm_inject_nmi(kvm_context
, env
->cpu_index
);
654 printf("cpu %d fail inject NMI\n", env
->cpu_index
);
656 #endif /* KVM_CAP_USER_NMI */
658 void kvm_arch_update_regs_for_sipi(CPUState
*env
)
660 SegmentCache cs
= env
->segs
[R_CS
];
662 kvm_arch_save_regs(env
);
663 env
->segs
[R_CS
] = cs
;
665 kvm_arch_load_regs(env
);
668 int handle_tpr_access(void *opaque
, int vcpu
,
669 uint64_t rip
, int is_write
)
671 kvm_tpr_access_report(cpu_single_env
, rip
, is_write
);
675 void kvm_arch_cpu_reset(CPUState
*env
)
677 kvm_arch_load_regs(env
);
678 if (env
->cpu_index
!= 0) {
679 if (kvm_irqchip_in_kernel(kvm_context
)) {
680 #ifdef KVM_CAP_MP_STATE
681 kvm_reset_mpstate(kvm_context
, env
->cpu_index
);
684 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
686 env
->exception_index
= EXCP_HLT
;
691 int kvm_arch_insert_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
695 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
696 cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 1))
701 int kvm_arch_remove_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
705 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
706 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1))
711 #ifdef KVM_CAP_SET_GUEST_DEBUG
718 static int nb_hw_breakpoint
;
720 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
724 for (n
= 0; n
< nb_hw_breakpoint
; n
++)
725 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
726 (hw_breakpoint
[n
].len
== len
|| len
== -1))
731 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
732 target_ulong len
, int type
)
735 case GDB_BREAKPOINT_HW
:
738 case GDB_WATCHPOINT_WRITE
:
739 case GDB_WATCHPOINT_ACCESS
:
746 if (addr
& (len
- 1))
757 if (nb_hw_breakpoint
== 4)
760 if (find_hw_breakpoint(addr
, len
, type
) >= 0)
763 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
764 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
765 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
771 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
772 target_ulong len
, int type
)
776 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
781 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
786 void kvm_arch_remove_all_hw_breakpoints(void)
788 nb_hw_breakpoint
= 0;
791 static CPUWatchpoint hw_watchpoint
;
793 int kvm_arch_debug(struct kvm_debug_exit_arch
*arch_info
)
798 if (arch_info
->exception
== 1) {
799 if (arch_info
->dr6
& (1 << 14)) {
800 if (cpu_single_env
->singlestep_enabled
)
803 for (n
= 0; n
< 4; n
++)
804 if (arch_info
->dr6
& (1 << n
))
805 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
811 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
812 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
813 hw_watchpoint
.flags
= BP_MEM_WRITE
;
817 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
818 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
819 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
823 } else if (kvm_find_sw_breakpoint(arch_info
->pc
))
827 kvm_update_guest_debug(cpu_single_env
,
828 (arch_info
->exception
== 1) ?
829 KVM_GUESTDBG_INJECT_DB
: KVM_GUESTDBG_INJECT_BP
);
834 void kvm_arch_update_guest_debug(CPUState
*env
, struct kvm_guest_debug
*dbg
)
836 const uint8_t type_code
[] = {
837 [GDB_BREAKPOINT_HW
] = 0x0,
838 [GDB_WATCHPOINT_WRITE
] = 0x1,
839 [GDB_WATCHPOINT_ACCESS
] = 0x3
841 const uint8_t len_code
[] = {
842 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
846 if (!TAILQ_EMPTY(&kvm_sw_breakpoints
))
847 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
849 if (nb_hw_breakpoint
> 0) {
850 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
851 dbg
->arch
.debugreg
[7] = 0x0600;
852 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
853 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
854 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
855 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
856 (len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
862 void kvm_arch_do_ioperm(void *_data
)
864 struct ioperm_data
*data
= _data
;
865 ioperm(data
->start_port
, data
->num
, data
->turn_on
);
868 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
871 return kvm_get_supported_cpuid(kvm_context
, function
, reg
);