Make it obvious that pci_nic_init() can't fail
[qemu-kvm/fedora.git] / softmmu_template.h
blob018d7fe756799ce51141fa4b5dbceac0312a3f0c
1 /*
2 * Software MMU support
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #define DATA_SIZE (1 << SHIFT)
21 #if DATA_SIZE == 8
22 #define SUFFIX q
23 #define USUFFIX q
24 #define DATA_TYPE uint64_t
25 #elif DATA_SIZE == 4
26 #define SUFFIX l
27 #define USUFFIX l
28 #define DATA_TYPE uint32_t
29 #elif DATA_SIZE == 2
30 #define SUFFIX w
31 #define USUFFIX uw
32 #define DATA_TYPE uint16_t
33 #elif DATA_SIZE == 1
34 #define SUFFIX b
35 #define USUFFIX ub
36 #define DATA_TYPE uint8_t
37 #else
38 #error unsupported data size
39 #endif
41 #ifdef SOFTMMU_CODE_ACCESS
42 #define READ_ACCESS_TYPE 2
43 #define ADDR_READ addr_code
44 #else
45 #define READ_ACCESS_TYPE 0
46 #define ADDR_READ addr_read
47 #endif
49 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
50 int mmu_idx,
51 void *retaddr);
52 static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
53 target_ulong addr,
54 void *retaddr)
56 DATA_TYPE res;
57 int index;
58 index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
59 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
60 env->mem_io_pc = (unsigned long)retaddr;
61 if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
62 && !can_do_io(env)) {
63 cpu_io_recompile(env, retaddr);
66 env->mem_io_vaddr = addr;
67 #if SHIFT <= 2
68 res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
69 #else
70 #ifdef TARGET_WORDS_BIGENDIAN
71 res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
72 res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
73 #else
74 res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
75 res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
76 #endif
77 #endif /* SHIFT > 2 */
78 #ifdef CONFIG_KQEMU
79 env->last_io_time = cpu_get_time_fast();
80 #endif
81 return res;
84 /* handle all cases except unaligned access which span two pages */
85 DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
86 int mmu_idx)
88 DATA_TYPE res;
89 int index;
90 target_ulong tlb_addr;
91 target_phys_addr_t addend;
92 void *retaddr;
94 /* test if there is match for unaligned or IO access */
95 /* XXX: could done more in memory macro in a non portable way */
96 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
97 redo:
98 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
99 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
100 if (tlb_addr & ~TARGET_PAGE_MASK) {
101 /* IO access */
102 if ((addr & (DATA_SIZE - 1)) != 0)
103 goto do_unaligned_access;
104 retaddr = GETPC();
105 addend = env->iotlb[mmu_idx][index];
106 res = glue(io_read, SUFFIX)(addend, addr, retaddr);
107 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
108 /* slow unaligned access (it spans two pages or IO) */
109 do_unaligned_access:
110 retaddr = GETPC();
111 #ifdef ALIGNED_ONLY
112 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
113 #endif
114 res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
115 mmu_idx, retaddr);
116 } else {
117 /* unaligned/aligned access in the same page */
118 #ifdef ALIGNED_ONLY
119 if ((addr & (DATA_SIZE - 1)) != 0) {
120 retaddr = GETPC();
121 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
123 #endif
124 addend = env->tlb_table[mmu_idx][index].addend;
125 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
127 } else {
128 /* the page is not in the TLB : fill it */
129 retaddr = GETPC();
130 #ifdef ALIGNED_ONLY
131 if ((addr & (DATA_SIZE - 1)) != 0)
132 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
133 #endif
134 tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
135 goto redo;
137 return res;
140 /* handle all unaligned cases */
141 static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
142 int mmu_idx,
143 void *retaddr)
145 DATA_TYPE res, res1, res2;
146 int index, shift;
147 target_phys_addr_t addend;
148 target_ulong tlb_addr, addr1, addr2;
150 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
151 redo:
152 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
153 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
154 if (tlb_addr & ~TARGET_PAGE_MASK) {
155 /* IO access */
156 if ((addr & (DATA_SIZE - 1)) != 0)
157 goto do_unaligned_access;
158 retaddr = GETPC();
159 addend = env->iotlb[mmu_idx][index];
160 res = glue(io_read, SUFFIX)(addend, addr, retaddr);
161 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
162 do_unaligned_access:
163 /* slow unaligned access (it spans two pages) */
164 addr1 = addr & ~(DATA_SIZE - 1);
165 addr2 = addr1 + DATA_SIZE;
166 res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
167 mmu_idx, retaddr);
168 res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
169 mmu_idx, retaddr);
170 shift = (addr & (DATA_SIZE - 1)) * 8;
171 #ifdef TARGET_WORDS_BIGENDIAN
172 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
173 #else
174 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
175 #endif
176 res = (DATA_TYPE)res;
177 } else {
178 /* unaligned/aligned access in the same page */
179 addend = env->tlb_table[mmu_idx][index].addend;
180 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
182 } else {
183 /* the page is not in the TLB : fill it */
184 tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
185 goto redo;
187 return res;
190 #ifndef SOFTMMU_CODE_ACCESS
192 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
193 DATA_TYPE val,
194 int mmu_idx,
195 void *retaddr);
197 static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
198 DATA_TYPE val,
199 target_ulong addr,
200 void *retaddr)
202 int index;
203 index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
204 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
205 if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
206 && !can_do_io(env)) {
207 cpu_io_recompile(env, retaddr);
210 env->mem_io_vaddr = addr;
211 env->mem_io_pc = (unsigned long)retaddr;
212 #if SHIFT <= 2
213 io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
214 #else
215 #ifdef TARGET_WORDS_BIGENDIAN
216 io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
217 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
218 #else
219 io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
220 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
221 #endif
222 #endif /* SHIFT > 2 */
223 #ifdef CONFIG_KQEMU
224 env->last_io_time = cpu_get_time_fast();
225 #endif
228 void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
229 DATA_TYPE val,
230 int mmu_idx)
232 target_phys_addr_t addend;
233 target_ulong tlb_addr;
234 void *retaddr;
235 int index;
237 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
238 redo:
239 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
240 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
241 if (tlb_addr & ~TARGET_PAGE_MASK) {
242 /* IO access */
243 if ((addr & (DATA_SIZE - 1)) != 0)
244 goto do_unaligned_access;
245 retaddr = GETPC();
246 addend = env->iotlb[mmu_idx][index];
247 glue(io_write, SUFFIX)(addend, val, addr, retaddr);
248 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
249 do_unaligned_access:
250 retaddr = GETPC();
251 #ifdef ALIGNED_ONLY
252 do_unaligned_access(addr, 1, mmu_idx, retaddr);
253 #endif
254 glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
255 mmu_idx, retaddr);
256 } else {
257 /* aligned/unaligned access in the same page */
258 #ifdef ALIGNED_ONLY
259 if ((addr & (DATA_SIZE - 1)) != 0) {
260 retaddr = GETPC();
261 do_unaligned_access(addr, 1, mmu_idx, retaddr);
263 #endif
264 addend = env->tlb_table[mmu_idx][index].addend;
265 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
267 } else {
268 /* the page is not in the TLB : fill it */
269 retaddr = GETPC();
270 #ifdef ALIGNED_ONLY
271 if ((addr & (DATA_SIZE - 1)) != 0)
272 do_unaligned_access(addr, 1, mmu_idx, retaddr);
273 #endif
274 tlb_fill(addr, 1, mmu_idx, retaddr);
275 goto redo;
279 /* handles all unaligned cases */
280 static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
281 DATA_TYPE val,
282 int mmu_idx,
283 void *retaddr)
285 target_phys_addr_t addend;
286 target_ulong tlb_addr;
287 int index, i;
289 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
290 redo:
291 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
292 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
293 if (tlb_addr & ~TARGET_PAGE_MASK) {
294 /* IO access */
295 if ((addr & (DATA_SIZE - 1)) != 0)
296 goto do_unaligned_access;
297 addend = env->iotlb[mmu_idx][index];
298 glue(io_write, SUFFIX)(addend, val, addr, retaddr);
299 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
300 do_unaligned_access:
301 /* XXX: not efficient, but simple */
302 /* Note: relies on the fact that tlb_fill() does not remove the
303 * previous page from the TLB cache. */
304 for(i = DATA_SIZE - 1; i >= 0; i--) {
305 #ifdef TARGET_WORDS_BIGENDIAN
306 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
307 mmu_idx, retaddr);
308 #else
309 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
310 mmu_idx, retaddr);
311 #endif
313 } else {
314 /* aligned/unaligned access in the same page */
315 addend = env->tlb_table[mmu_idx][index].addend;
316 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
318 } else {
319 /* the page is not in the TLB : fill it */
320 tlb_fill(addr, 1, mmu_idx, retaddr);
321 goto redo;
325 #endif /* !defined(SOFTMMU_CODE_ACCESS) */
327 #undef READ_ACCESS_TYPE
328 #undef SHIFT
329 #undef DATA_TYPE
330 #undef SUFFIX
331 #undef USUFFIX
332 #undef DATA_SIZE
333 #undef ADDR_READ