hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29 #include "pc.h"
  30 #include "qemu-kvm.h"
  31 #include "device-assignment.h"
  32
  33 //#define DEBUG_PCI
  34 #ifdef DEBUG_PCI
  35 # define PCI_DPRINTF(format, ...)       printf(format, __VA_ARGS__)
  36 #else
  37 # define PCI_DPRINTF(format, ...)       do { } while (0)
  38 #endif
  39
  40 struct PCIBus {
  41     BusState qbus;
  42     int bus_num;
  43     int devfn_min;
  44     pci_set_irq_fn set_irq;
  45     pci_map_irq_fn map_irq;
  46     uint32_t config_reg; /* XXX: suppress */
  47     /* low level pic */
  48     SetIRQFunc *low_set_irq;
  49     qemu_irq *irq_opaque;
  50     PCIDevice *devices[256];
  51     PCIDevice *parent_dev;
  52     PCIBus *next;
  53     /* The bus IRQ state is the logical OR of the connected devices.
  54        Keep a count of the number of devices with raised IRQs.  */
  55     int nirq;
  56     int *irq_count;
  57 };
  58
  59 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  60
  61 static struct BusInfo pci_bus_info = {
  62     .name       = "PCI",
  63     .size       = sizeof(PCIBus),
  64     .print_dev  = pcibus_dev_print,
  65     .props      = (Property[]) {
  66         {
  67             .name   = "devfn",
  68             .info   = &qdev_prop_uint32,
  69             .offset = offsetof(PCIDevice, devfn),
  70             .defval = (uint32_t[]) { -1 },
  71         },
  72         {/* end of list */}
  73     }
  74 };
  75
  76 static void pci_update_mappings(PCIDevice *d);
  77 static void pci_set_irq(void *opaque, int irq_num, int level);
  78
  79 target_phys_addr_t pci_mem_base;
  80 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  81 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  82 static PCIBus *first_bus;
  83
  84 static void pcibus_save(QEMUFile *f, void *opaque)
  85 {
  86     PCIBus *bus = (PCIBus *)opaque;
  87     int i;
  88
  89     qemu_put_be32(f, bus->nirq);
  90     for (i = 0; i < bus->nirq; i++)
  91         qemu_put_be32(f, bus->irq_count[i]);
  92 }
  93
  94 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  95 {
  96     PCIBus *bus = (PCIBus *)opaque;
  97     int i, nirq;
  98
  99     if (version_id != 1)
 100         return -EINVAL;
 101
 102     nirq = qemu_get_be32(f);
 103     if (bus->nirq != nirq) {
 104         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
 105                 nirq, bus->nirq);
 106         return -EINVAL;
 107     }
 108
 109     for (i = 0; i < nirq; i++)
 110         bus->irq_count[i] = qemu_get_be32(f);
 111
 112     return 0;
 113 }
 114
 115 static void pci_bus_reset(void *opaque)
 116 {
 117     PCIBus *bus = (PCIBus *)opaque;
 118     int i;
 119
 120     for (i = 0; i < bus->nirq; i++) {
 121         bus->irq_count[i] = 0;
 122     }
 123     for (i = 0; i < 256; i++) {
 124         if (bus->devices[i])
 125             memset(bus->devices[i]->irq_state, 0,
 126                    sizeof(bus->devices[i]->irq_state));
 127     }
 128 }
 129
 130 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 131                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 132                          qemu_irq *pic, int devfn_min, int nirq)
 133 {
 134     PCIBus *bus;
 135     static int nbus = 0;
 136
 137     bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
 138     bus->set_irq = set_irq;
 139     bus->map_irq = map_irq;
 140     bus->irq_opaque = pic;
 141     bus->devfn_min = devfn_min;
 142     bus->nirq = nirq;
 143     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 144     bus->next = first_bus;
 145     first_bus = bus;
 146     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 147     qemu_register_reset(pci_bus_reset, bus);
 148     return bus;
 149 }
 150
 151 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 152 {
 153     PCIBus *bus;
 154
 155     bus = qemu_mallocz(sizeof(PCIBus));
 156     bus->map_irq = map_irq;
 157     bus->parent_dev = dev;
 158     bus->next = dev->bus->next;
 159     dev->bus->next = bus;
 160     return bus;
 161 }
 162
 163 int pci_bus_num(PCIBus *s)
 164 {
 165     return s->bus_num;
 166 }
 167
 168 void pci_device_save(PCIDevice *s, QEMUFile *f)
 169 {
 170     int i;
 171
 172     qemu_put_be32(f, 2); /* PCI device version */
 173     qemu_put_buffer(f, s->config, 256);
 174     for (i = 0; i < 4; i++)
 175         qemu_put_be32(f, s->irq_state[i]);
 176 }
 177
 178 int pci_device_load(PCIDevice *s, QEMUFile *f)
 179 {
 180     uint8_t config[PCI_CONFIG_SPACE_SIZE];
 181     uint32_t version_id;
 182     int i;
 183
 184     version_id = qemu_get_be32(f);
 185     if (version_id > 2)
 186         return -EINVAL;
 187     qemu_get_buffer(f, config, sizeof config);
 188     for (i = 0; i < sizeof config; ++i)
 189         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
 190             return -EINVAL;
 191     memcpy(s->config, config, sizeof config);
 192
 193     pci_update_mappings(s);
 194
 195     if (version_id >= 2)
 196         for (i = 0; i < 4; i ++)
 197             s->irq_state[i] = qemu_get_be32(f);
 198     return 0;
 199 }
 200
 201 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 202 {
 203     uint16_t *id;
 204
 205     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 206     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 207     id[1] = cpu_to_le16(pci_default_sub_device_id);
 208     return 0;
 209 }
 210
 211 /*
 212  * Parse pci address in qemu command
 213  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 214  */
 215 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 216 {
 217     const char *p;
 218     char *e;
 219     unsigned long val;
 220     unsigned long dom = 0, bus = 0;
 221     unsigned slot = 0;
 222
 223     p = addr;
 224     val = strtoul(p, &e, 16);
 225     if (e == p)
 226         return -1;
 227     if (*e == ':') {
 228         bus = val;
 229         p = e + 1;
 230         val = strtoul(p, &e, 16);
 231         if (e == p)
 232             return -1;
 233         if (*e == ':') {
 234             dom = bus;
 235             bus = val;
 236             p = e + 1;
 237             val = strtoul(p, &e, 16);
 238             if (e == p)
 239                 return -1;
 240         }
 241     }
 242
 243     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 244         return -1;
 245
 246     slot = val;
 247
 248     if (*e)
 249         return -1;
 250
 251     /* Note: QEMU doesn't implement domains other than 0 */
 252     if (dom != 0 || pci_find_bus(bus) == NULL)
 253         return -1;
 254
 255     *domp = dom;
 256     *busp = bus;
 257     *slotp = slot;
 258     return 0;
 259 }
 260
 261 /*
 262  * Parse device bdf in device assignment command:
 263  *
 264  * -pcidevice host=bus:dev.func
 265  *
 266  * Parse <bus>:<slot>.<func> return -1 on error
 267  */
 268 int pci_parse_host_devaddr(const char *addr, int *busp,
 269                            int *slotp, int *funcp)
 270 {
 271     const char *p;
 272     char *e;
 273     int val;
 274     int bus = 0, slot = 0, func = 0;
 275
 276     p = addr;
 277     val = strtoul(p, &e, 16);
 278     if (e == p)
 279         return -1;
 280     if (*e == ':') {
 281         bus = val;
 282         p = e + 1;
 283         val = strtoul(p, &e, 16);
 284         if (e == p)
 285             return -1;
 286         if (*e == '.') {
 287             slot = val;
 288             p = e + 1;
 289             val = strtoul(p, &e, 16);
 290             if (e == p)
 291                 return -1;
 292             func = val;
 293         } else
 294             return -1;
 295     } else
 296         return -1;
 297
 298     if (bus > 0xff || slot > 0x1f || func > 0x7)
 299         return -1;
 300
 301     if (*e)
 302         return -1;
 303
 304     *busp = bus;
 305     *slotp = slot;
 306     *funcp = func;
 307     return 0;
 308 }
 309
 310 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 311                      unsigned *slotp)
 312 {
 313     /* strip legacy tag */
 314     if (!strncmp(addr, "pci_addr=", 9)) {
 315         addr += 9;
 316     }
 317     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 318         monitor_printf(mon, "Invalid pci address\n");
 319         return -1;
 320     }
 321     return 0;
 322 }
 323
 324 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 325 {
 326     int dom, bus;
 327     unsigned slot;
 328
 329     if (!devaddr) {
 330         *devfnp = -1;
 331         return pci_find_bus(0);
 332     }
 333
 334     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 335         return NULL;
 336     }
 337
 338     *devfnp = slot << 3;
 339     return pci_find_bus(bus);
 340 }
 341
 342 static void pci_init_cmask(PCIDevice *dev)
 343 {
 344     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 345     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 346     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 347     dev->cmask[PCI_REVISION_ID] = 0xff;
 348     dev->cmask[PCI_CLASS_PROG] = 0xff;
 349     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 350     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 351     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 352 }
 353
 354 static void pci_init_wmask(PCIDevice *dev)
 355 {
 356     int i;
 357     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 358     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 359     dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 360                               | PCI_COMMAND_MASTER;
 361     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
 362         dev->wmask[i] = 0xff;
 363 }
 364
 365 /* -1 for devfn means auto assign */
 366 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 367                                          const char *name, int devfn,
 368                                          PCIConfigReadFunc *config_read,
 369                                          PCIConfigWriteFunc *config_write)
 370 {
 371     if (devfn < 0) {
 372         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 373             if (!bus->devices[devfn])
 374                 goto found;
 375         }
 376         return NULL;
 377     found: ;
 378     } else if (bus->devices[devfn]) {
 379         return NULL;
 380     }
 381     pci_dev->bus = bus;
 382     pci_dev->devfn = devfn;
 383     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 384     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 385     pci_set_default_subsystem_id(pci_dev);
 386     pci_init_cmask(pci_dev);
 387     pci_init_wmask(pci_dev);
 388
 389     if (!config_read)
 390         config_read = pci_default_read_config;
 391     if (!config_write)
 392         config_write = pci_default_write_config;
 393     pci_dev->config_read = config_read;
 394     pci_dev->config_write = config_write;
 395     bus->devices[devfn] = pci_dev;
 396     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 397     return pci_dev;
 398 }
 399
 400 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 401                                int instance_size, int devfn,
 402                                PCIConfigReadFunc *config_read,
 403                                PCIConfigWriteFunc *config_write)
 404 {
 405     PCIDevice *pci_dev;
 406
 407     pci_dev = qemu_mallocz(instance_size);
 408     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 409                                      config_read, config_write);
 410     return pci_dev;
 411 }
 412 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 413 {
 414     return addr + pci_mem_base;
 415 }
 416
 417 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 418 {
 419     PCIIORegion *r;
 420     int i;
 421
 422     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 423         r = &pci_dev->io_regions[i];
 424         if (!r->size || r->addr == -1)
 425             continue;
 426         if (r->type == PCI_ADDRESS_SPACE_IO) {
 427             isa_unassign_ioport(r->addr, r->size);
 428         } else {
 429             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 430                                                      r->size,
 431                                                      IO_MEM_UNASSIGNED);
 432         }
 433     }
 434 }
 435
 436 int pci_unregister_device(PCIDevice *pci_dev, int assigned)
 437 {
 438     int ret = 0;
 439
 440     if (pci_dev->unregister)
 441         ret = pci_dev->unregister(pci_dev);
 442     if (ret)
 443         return ret;
 444
 445     pci_unregister_io_regions(pci_dev);
 446
 447     qemu_free_irqs(pci_dev->irq);
 448     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 449
 450     if (assigned)
 451         qemu_free(pci_dev);
 452     else
 453         qdev_free(&pci_dev->qdev);
 454     return 0;
 455 }
 456
 457 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 458                             uint32_t size, int type,
 459                             PCIMapIORegionFunc *map_func)
 460 {
 461     PCIIORegion *r;
 462     uint32_t addr;
 463     uint32_t wmask;
 464
 465     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 466         return;
 467
 468     if (size & (size-1)) {
 469         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 470                     "type=0x%x, size=0x%x\n", type, size);
 471         exit(1);
 472     }
 473
 474     r = &pci_dev->io_regions[region_num];
 475     r->addr = -1;
 476     r->size = size;
 477     r->type = type;
 478     r->map_func = map_func;
 479
 480     wmask = ~(size - 1);
 481     if (region_num == PCI_ROM_SLOT) {
 482         addr = 0x30;
 483         /* ROM enable bit is writeable */
 484         wmask |= 1;
 485     } else {
 486         addr = 0x10 + region_num * 4;
 487     }
 488     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 489     *(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
 490     *(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
 491 }
 492
 493 static void pci_update_mappings(PCIDevice *d)
 494 {
 495     PCIIORegion *r;
 496     int cmd, i;
 497     uint32_t last_addr, new_addr, config_ofs;
 498
 499     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 500     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 501         r = &d->io_regions[i];
 502         if (i == PCI_ROM_SLOT) {
 503             config_ofs = 0x30;
 504         } else {
 505             config_ofs = 0x10 + i * 4;
 506         }
 507         if (r->size != 0) {
 508             if (r->type & PCI_ADDRESS_SPACE_IO) {
 509                 if (cmd & PCI_COMMAND_IO) {
 510                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 511                                                          config_ofs));
 512                     new_addr = new_addr & ~(r->size - 1);
 513                     last_addr = new_addr + r->size - 1;
 514                     /* NOTE: we have only 64K ioports on PC */
 515                     if (last_addr <= new_addr || new_addr == 0 ||
 516                         last_addr >= 0x10000) {
 517                         new_addr = -1;
 518                     }
 519                 } else {
 520                     new_addr = -1;
 521                 }
 522             } else {
 523                 if (cmd & PCI_COMMAND_MEMORY) {
 524                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 525                                                          config_ofs));
 526                     /* the ROM slot has a specific enable bit */
 527                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 528                         goto no_mem_map;
 529                     new_addr = new_addr & ~(r->size - 1);
 530                     last_addr = new_addr + r->size - 1;
 531                     /* NOTE: we do not support wrapping */
 532                     /* XXX: as we cannot support really dynamic
 533                        mappings, we handle specific values as invalid
 534                        mappings. */
 535                     if (last_addr <= new_addr || new_addr == 0 ||
 536                         last_addr == -1) {
 537                         new_addr = -1;
 538                     }
 539                 } else {
 540                 no_mem_map:
 541                     new_addr = -1;
 542                 }
 543             }
 544             /* now do the real mapping */
 545             if (new_addr != r->addr) {
 546                 if (r->addr != -1) {
 547                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 548                         int class;
 549                         /* NOTE: specific hack for IDE in PC case:
 550                            only one byte must be mapped. */
 551                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 552                         if (class == 0x0101 && r->size == 4) {
 553                             isa_unassign_ioport(r->addr + 2, 1);
 554                         } else {
 555                             isa_unassign_ioport(r->addr, r->size);
 556                         }
 557                     } else {
 558                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 559                                                      r->size,
 560                                                      IO_MEM_UNASSIGNED);
 561                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 562                     }
 563                 }
 564                 r->addr = new_addr;
 565                 if (r->addr != -1) {
 566                     r->map_func(d, i, r->addr, r->size, r->type);
 567                 }
 568             }
 569         }
 570     }
 571 }
 572
 573 static uint32_t pci_read_config(PCIDevice *d,
 574                                 uint32_t address, int len)
 575 {
 576     uint32_t val;
 577
 578     switch(len) {
 579     default:
 580     case 4:
 581         if (address <= 0xfc) {
 582             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 583             break;
 584         }
 585         /* fall through */
 586     case 2:
 587         if (address <= 0xfe) {
 588             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 589             break;
 590         }
 591         /* fall through */
 592     case 1:
 593         val = d->config[address];
 594         break;
 595     }
 596     return val;
 597 }
 598
 599 static void pci_write_config(PCIDevice *pci_dev,
 600                              uint32_t address, uint32_t val, int len)
 601 {
 602     int i;
 603     for (i = 0; i < len; i++) {
 604         pci_dev->config[address + i] = val & 0xff;
 605         val >>= 8;
 606     }
 607 }
 608
 609 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len)
 610 {
 611     if (pci_dev->cap.supported && address >= pci_dev->cap.start &&
 612             (address + len) < pci_dev->cap.start + pci_dev->cap.length)
 613         return 1;
 614     return 0;
 615 }
 616
 617 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 618                                      uint32_t address, int len)
 619 {
 620     return pci_read_config(pci_dev, address, len);
 621 }
 622
 623 void pci_default_cap_write_config(PCIDevice *pci_dev,
 624                                   uint32_t address, uint32_t val, int len)
 625 {
 626     pci_write_config(pci_dev, address, val, len);
 627 }
 628
 629 uint32_t pci_default_read_config(PCIDevice *d,
 630                                  uint32_t address, int len)
 631 {
 632     if (pci_access_cap_config(d, address, len))
 633         return d->cap.config_read(d, address, len);
 634
 635     return pci_read_config(d, address, len);
 636 }
 637
 638 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 639 {
 640     uint8_t orig[PCI_CONFIG_SPACE_SIZE];
 641     int i;
 642
 643     if (pci_access_cap_config(d, addr, l)) {
 644         d->cap.config_write(d, addr, val, l);
 645         return;
 646     }
 647
 648     /* not efficient, but simple */
 649     memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
 650     for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
 651         uint8_t wmask = d->wmask[addr];
 652         d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
 653     }
 654
 655 #ifdef USE_KVM_DEVICE_ASSIGNMENT
 656     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel() &&
 657         addr >= PIIX_CONFIG_IRQ_ROUTE &&
 658         addr < PIIX_CONFIG_IRQ_ROUTE + 4)
 659         assigned_dev_update_irqs();
 660 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
 661
 662     if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
 663         || ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
 664             & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
 665         pci_update_mappings(d);
 666
 667 }
 668
 669 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 670 {
 671     PCIBus *s = opaque;
 672     PCIDevice *pci_dev;
 673     int config_addr, bus_num;
 674
 675 #if 0
 676     PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
 677                 addr, val, len);
 678 #endif
 679     bus_num = (addr >> 16) & 0xff;
 680     while (s && s->bus_num != bus_num)
 681         s = s->next;
 682     if (!s)
 683         return;
 684     pci_dev = s->devices[(addr >> 8) & 0xff];
 685     if (!pci_dev)
 686         return;
 687     config_addr = addr & 0xff;
 688     PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 689                 pci_dev->name, config_addr, val, len);
 690     pci_dev->config_write(pci_dev, config_addr, val, len);
 691 }
 692
 693 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 694 {
 695     PCIBus *s = opaque;
 696     PCIDevice *pci_dev;
 697     int config_addr, bus_num;
 698     uint32_t val;
 699
 700     bus_num = (addr >> 16) & 0xff;
 701     while (s && s->bus_num != bus_num)
 702         s= s->next;
 703     if (!s)
 704         goto fail;
 705     pci_dev = s->devices[(addr >> 8) & 0xff];
 706     if (!pci_dev) {
 707     fail:
 708         switch(len) {
 709         case 1:
 710             val = 0xff;
 711             break;
 712         case 2:
 713             val = 0xffff;
 714             break;
 715         default:
 716         case 4:
 717             val = 0xffffffff;
 718             break;
 719         }
 720         goto the_end;
 721     }
 722     config_addr = addr & 0xff;
 723     val = pci_dev->config_read(pci_dev, config_addr, len);
 724     PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 725                 pci_dev->name, config_addr, val, len);
 726  the_end:
 727 #if 0
 728     PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
 729                 addr, val, len);
 730 #endif
 731     return val;
 732 }
 733
 734 /***********************************************************/
 735 /* generic PCI irq support */
 736
 737 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 738 static void pci_set_irq(void *opaque, int irq_num, int level)
 739 {
 740     PCIDevice *pci_dev = (PCIDevice *)opaque;
 741     PCIBus *bus;
 742     int change;
 743
 744     change = level - pci_dev->irq_state[irq_num];
 745     if (!change)
 746         return;
 747
 748     pci_dev->irq_state[irq_num] = level;
 749
 750 #if defined(TARGET_IA64)
 751     ioapic_set_irq(pci_dev, irq_num, level);
 752 #endif
 753
 754     for (;;) {
 755         bus = pci_dev->bus;
 756         irq_num = bus->map_irq(pci_dev, irq_num);
 757         if (bus->set_irq)
 758             break;
 759         pci_dev = bus->parent_dev;
 760     }
 761     bus->irq_count[irq_num] += change;
 762     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 763 }
 764
 765 int pci_map_irq(PCIDevice *pci_dev, int pin)
 766 {
 767     return pci_dev->bus->map_irq(pci_dev, pin);
 768 }
 769
 770 /***********************************************************/
 771 /* monitor info on PCI */
 772
 773 typedef struct {
 774     uint16_t class;
 775     const char *desc;
 776 } pci_class_desc;
 777
 778 static const pci_class_desc pci_class_descriptions[] =
 779 {
 780     { 0x0100, "SCSI controller"},
 781     { 0x0101, "IDE controller"},
 782     { 0x0102, "Floppy controller"},
 783     { 0x0103, "IPI controller"},
 784     { 0x0104, "RAID controller"},
 785     { 0x0106, "SATA controller"},
 786     { 0x0107, "SAS controller"},
 787     { 0x0180, "Storage controller"},
 788     { 0x0200, "Ethernet controller"},
 789     { 0x0201, "Token Ring controller"},
 790     { 0x0202, "FDDI controller"},
 791     { 0x0203, "ATM controller"},
 792     { 0x0280, "Network controller"},
 793     { 0x0300, "VGA controller"},
 794     { 0x0301, "XGA controller"},
 795     { 0x0302, "3D controller"},
 796     { 0x0380, "Display controller"},
 797     { 0x0400, "Video controller"},
 798     { 0x0401, "Audio controller"},
 799     { 0x0402, "Phone"},
 800     { 0x0480, "Multimedia controller"},
 801     { 0x0500, "RAM controller"},
 802     { 0x0501, "Flash controller"},
 803     { 0x0580, "Memory controller"},
 804     { 0x0600, "Host bridge"},
 805     { 0x0601, "ISA bridge"},
 806     { 0x0602, "EISA bridge"},
 807     { 0x0603, "MC bridge"},
 808     { 0x0604, "PCI bridge"},
 809     { 0x0605, "PCMCIA bridge"},
 810     { 0x0606, "NUBUS bridge"},
 811     { 0x0607, "CARDBUS bridge"},
 812     { 0x0608, "RACEWAY bridge"},
 813     { 0x0680, "Bridge"},
 814     { 0x0c03, "USB controller"},
 815     { 0, NULL}
 816 };
 817
 818 static void pci_info_device(PCIDevice *d)
 819 {
 820     Monitor *mon = cur_mon;
 821     int i, class;
 822     PCIIORegion *r;
 823     const pci_class_desc *desc;
 824
 825     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 826                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 827     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 828     monitor_printf(mon, "    ");
 829     desc = pci_class_descriptions;
 830     while (desc->desc && class != desc->class)
 831         desc++;
 832     if (desc->desc) {
 833         monitor_printf(mon, "%s", desc->desc);
 834     } else {
 835         monitor_printf(mon, "Class %04x", class);
 836     }
 837     monitor_printf(mon, ": PCI device %04x:%04x\n",
 838            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 839            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 840
 841     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 842         monitor_printf(mon, "      IRQ %d.\n",
 843                        d->config[PCI_INTERRUPT_LINE]);
 844     }
 845     if (class == 0x0604) {
 846         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 847     }
 848     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 849         r = &d->io_regions[i];
 850         if (r->size != 0) {
 851             monitor_printf(mon, "      BAR%d: ", i);
 852             if (r->type & PCI_ADDRESS_SPACE_IO) {
 853                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 854                                r->addr, r->addr + r->size - 1);
 855             } else {
 856                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 857                                r->addr, r->addr + r->size - 1);
 858             }
 859         }
 860     }
 861     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
 862     if (class == 0x0604 && d->config[0x19] != 0) {
 863         pci_for_each_device(d->config[0x19], pci_info_device);
 864     }
 865 }
 866
 867 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 868 {
 869     PCIBus *bus = first_bus;
 870     PCIDevice *d;
 871     int devfn;
 872
 873     while (bus && bus->bus_num != bus_num)
 874         bus = bus->next;
 875     if (bus) {
 876         for(devfn = 0; devfn < 256; devfn++) {
 877             d = bus->devices[devfn];
 878             if (d)
 879                 fn(d);
 880         }
 881     }
 882 }
 883
 884 void pci_info(Monitor *mon)
 885 {
 886     pci_for_each_device(0, pci_info_device);
 887 }
 888
 889 PCIDevice *pci_create(const char *name, const char *devaddr)
 890 {
 891     PCIBus *bus;
 892     int devfn;
 893     DeviceState *dev;
 894
 895     bus = pci_get_bus_devfn(&devfn, devaddr);
 896     if (!bus) {
 897         fprintf(stderr, "Invalid PCI device address %s for device %s\n",
 898                 devaddr, name);
 899         exit(1);
 900     }
 901
 902     dev = qdev_create(&bus->qbus, name);
 903     qdev_prop_set_uint32(dev, "devfn", devfn);
 904     return (PCIDevice *)dev;
 905 }
 906
 907 static const char * const pci_nic_models[] = {
 908     "ne2k_pci",
 909     "i82551",
 910     "i82557b",
 911     "i82559er",
 912     "rtl8139",
 913     "e1000",
 914     "pcnet",
 915     "virtio",
 916     NULL
 917 };
 918
 919 static const char * const pci_nic_names[] = {
 920     "ne2k_pci",
 921     "i82551",
 922     "i82557b",
 923     "i82559er",
 924     "rtl8139",
 925     "e1000",
 926     "pcnet",
 927     "virtio-net-pci",
 928     NULL
 929 };
 930
 931 /* Initialize a PCI NIC.  */
 932 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 933                         const char *default_devaddr)
 934 {
 935     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
 936     PCIDevice *pci_dev;
 937     DeviceState *dev;
 938     int i;
 939
 940     i = qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 941     pci_dev = pci_create(pci_nic_names[i], devaddr);
 942     dev = &pci_dev->qdev;
 943     if (nd->id)
 944         dev->id = qemu_strdup(nd->id);
 945     dev->nd = nd;
 946     qdev_init(dev);
 947     nd->private = dev;
 948     return pci_dev;
 949 }
 950
 951 typedef struct {
 952     PCIDevice dev;
 953     PCIBus *bus;
 954 } PCIBridge;
 955
 956 static void pci_bridge_write_config(PCIDevice *d,
 957                              uint32_t address, uint32_t val, int len)
 958 {
 959     PCIBridge *s = (PCIBridge *)d;
 960
 961     pci_default_write_config(d, address, val, len);
 962     s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
 963 }
 964
 965 PCIBus *pci_find_bus(int bus_num)
 966 {
 967     PCIBus *bus = first_bus;
 968
 969     while (bus && bus->bus_num != bus_num)
 970         bus = bus->next;
 971
 972     return bus;
 973 }
 974
 975 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 976 {
 977     PCIBus *bus = pci_find_bus(bus_num);
 978
 979     if (!bus)
 980         return NULL;
 981
 982     return bus->devices[PCI_DEVFN(slot, function)];
 983 }
 984
 985 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 986                         pci_map_irq_fn map_irq, const char *name)
 987 {
 988     PCIBridge *s;
 989     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 990                                          devfn, NULL, pci_bridge_write_config);
 991
 992     pci_config_set_vendor_id(s->dev.config, vid);
 993     pci_config_set_device_id(s->dev.config, did);
 994
 995     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 996     s->dev.config[0x05] = 0x00;
 997     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 998     s->dev.config[0x07] = 0x00; // status = fast devsel
 999     s->dev.config[0x08] = 0x00; // revision
1000     s->dev.config[0x09] = 0x00; // programming i/f
1001     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
1002     s->dev.config[0x0D] = 0x10; // latency_timer
1003     s->dev.config[PCI_HEADER_TYPE] =
1004         PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
1005     s->dev.config[0x1E] = 0xa0; // secondary status
1006
1007     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
1008     return s->bus;
1009 }
1010
1011 static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1012 {
1013     PCIDevice *pci_dev = (PCIDevice *)qdev;
1014     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1015     PCIBus *bus;
1016     int devfn;
1017
1018     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1019     devfn = pci_dev->devfn;
1020     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1021                                      info->config_read, info->config_write);
1022     assert(pci_dev);
1023     info->init(pci_dev);
1024 }
1025
1026 void pci_qdev_register(PCIDeviceInfo *info)
1027 {
1028     info->qdev.init = pci_qdev_init;
1029     info->qdev.bus_info = &pci_bus_info;
1030     qdev_register(&info->qdev);
1031 }
1032
1033 void pci_qdev_register_many(PCIDeviceInfo *info)
1034 {
1035     while (info->qdev.name) {
1036         pci_qdev_register(info);
1037         info++;
1038     }
1039 }
1040
1041 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1042 {
1043     DeviceState *dev;
1044
1045     dev = qdev_create(&bus->qbus, name);
1046     qdev_prop_set_uint32(dev, "devfn", devfn);
1047     qdev_init(dev);
1048
1049     return (PCIDevice *)dev;
1050 }
1051
1052 int pci_enable_capability_support(PCIDevice *pci_dev,
1053                                   uint32_t config_start,
1054                                   PCICapConfigReadFunc *config_read,
1055                                   PCICapConfigWriteFunc *config_write,
1056                                   PCICapConfigInitFunc *config_init)
1057 {
1058     if (!pci_dev)
1059         return -ENODEV;
1060
1061     pci_dev->config[0x06] |= 0x10; // status = capabilities
1062
1063     if (config_start == 0)
1064         pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR;
1065     else if (config_start >= 0x40 && config_start < 0xff)
1066         pci_dev->cap.start = config_start;
1067     else
1068         return -EINVAL;
1069
1070     if (config_read)
1071         pci_dev->cap.config_read = config_read;
1072     else
1073         pci_dev->cap.config_read = pci_default_cap_read_config;
1074     if (config_write)
1075         pci_dev->cap.config_write = config_write;
1076     else
1077         pci_dev->cap.config_write = pci_default_cap_write_config;
1078     pci_dev->cap.supported = 1;
1079     pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start;
1080     return config_init(pci_dev);
1081 }
1082
1083 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1084 {
1085     int offset = PCI_CONFIG_HEADER_SIZE;
1086     int i;
1087     for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
1088         if (pdev->used[i])
1089             offset = i + 1;
1090         else if (i - offset + 1 == size)
1091             return offset;
1092     return 0;
1093 }
1094
1095 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1096                                         uint8_t *prev_p)
1097 {
1098     uint8_t next, prev;
1099
1100     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1101         return 0;
1102
1103     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1104          prev = next + PCI_CAP_LIST_NEXT)
1105         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1106             break;
1107
1108     if (prev_p)
1109         *prev_p = prev;
1110     return next;
1111 }
1112
1113 /* Reserve space and add capability to the linked list in pci config space */
1114 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1115 {
1116     uint8_t offset = pci_find_space(pdev, size);
1117     uint8_t *config = pdev->config + offset;
1118     if (!offset)
1119         return -ENOSPC;
1120     config[PCI_CAP_LIST_ID] = cap_id;
1121     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1122     pdev->config[PCI_CAPABILITY_LIST] = offset;
1123     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1124     memset(pdev->used + offset, 0xFF, size);
1125     /* Make capability read-only by default */
1126     memset(pdev->wmask + offset, 0, size);
1127     /* Check capability by default */
1128     memset(pdev->cmask + offset, 0xFF, size);
1129     return offset;
1130 }
1131
1132 /* Unlink capability from the pci config space. */
1133 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1134 {
1135     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1136     if (!offset)
1137         return;
1138     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1139     /* Make capability writeable again */
1140     memset(pdev->wmask + offset, 0xff, size);
1141     /* Clear cmask as device-specific registers can't be checked */
1142     memset(pdev->cmask + offset, 0, size);
1143     memset(pdev->used + offset, 0, size);
1144
1145     if (!pdev->config[PCI_CAPABILITY_LIST])
1146         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1147 }
1148
1149 /* Reserve space for capability at a known offset (to call after load). */
1150 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1151 {
1152     memset(pdev->used + offset, 0xff, size);
1153 }
1154
1155 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1156 {
1157     return pci_find_capability_list(pdev, cap_id, NULL);
1158 }
1159
1160 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1161 {
1162     PCIDevice *d = (PCIDevice *)dev;
1163     const pci_class_desc *desc;
1164     char ctxt[64];
1165     PCIIORegion *r;
1166     int i, class;
1167
1168     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1169     desc = pci_class_descriptions;
1170     while (desc->desc && class != desc->class)
1171         desc++;
1172     if (desc->desc) {
1173         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1174     } else {
1175         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1176     }
1177
1178     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1179                    "pci id %04x:%04x (sub %04x:%04x)\n",
1180                    indent, "", ctxt,
1181                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
1182                    le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1183                    le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
1184                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
1185                    le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
1186     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1187         r = &d->io_regions[i];
1188         if (!r->size)
1189             continue;
1190         monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
1191                        i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
1192                        r->addr, r->addr + r->size - 1);
1193     }
1194 }