hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7 #include "memory.h"
   8 #include "dma.h"
   9 #include "kvm.h"
  10
  11 /* PCI includes legacy ISA access.  */
  12 #include "isa.h"
  13
  14 #include "pcie.h"
  15
  16 /* PCI bus */
  17
  18 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  21 #define PCI_SLOT_MAX            32
  22 #define PCI_FUNC_MAX            8
  23
  24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  25 #include "pci_ids.h"
  26
  27 /* QEMU-specific Vendor and Device ID definitions */
  28
  29 /* IBM (0x1014) */
  30 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  31 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  32
  33 /* Hitachi (0x1054) */
  34 #define PCI_VENDOR_ID_HITACHI            0x1054
  35 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  36
  37 /* Apple (0x106b) */
  38 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  42 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  43
  44 /* Realtek (0x10ec) */
  45 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  46
  47 /* Xilinx (0x10ee) */
  48 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  49
  50 /* Marvell (0x11ab) */
  51 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  52
  53 /* QEMU/Bochs VGA (0x1234) */
  54 #define PCI_VENDOR_ID_QEMU               0x1234
  55 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  56
  57 /* VMWare (0x15ad) */
  58 #define PCI_VENDOR_ID_VMWARE             0x15ad
  59 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  60 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  61 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  62 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  63 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  64
  65 /* Intel (0x8086) */
  66 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  67 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  68 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  69
  70 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  71 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  72 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  73 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  74
  75 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  76 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  77 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  78 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  79
  80 #define FMT_PCIBUS                      PRIx64
  81
  82 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  83                                 uint32_t address, uint32_t data, int len);
  84 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  85                                    uint32_t address, int len);
  86 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  87                                 pcibus_t addr, pcibus_t size, int type);
  88 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  89
  90 typedef struct PCIIORegion {
  91     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  92 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  93     pcibus_t size;
  94     uint8_t type;
  95     MemoryRegion *memory;
  96     MemoryRegion *address_space;
  97 } PCIIORegion;
  98
  99 #define PCI_ROM_SLOT 6
 100 #define PCI_NUM_REGIONS 7
 101
 102 #include "pci_regs.h"
 103
 104 /* PCI HEADER_TYPE */
 105 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 106
 107 /* Size of the standard PCI config header */
 108 #define PCI_CONFIG_HEADER_SIZE 0x40
 109 /* Size of the standard PCI config space */
 110 #define PCI_CONFIG_SPACE_SIZE 0x100
 111 /* Size of the standart PCIe config space: 4KB */
 112 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 113
 114 #define PCI_NUM_PINS 4 /* A-D */
 115
 116 /* Bits in cap_present field. */
 117 enum {
 118     QEMU_PCI_CAP_MSI = 0x1,
 119     QEMU_PCI_CAP_MSIX = 0x2,
 120     QEMU_PCI_CAP_EXPRESS = 0x4,
 121
 122     /* multifunction capable device */
 123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 124     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 125
 126     /* command register SERR bit enabled */
 127 #define QEMU_PCI_CAP_SERR_BITNR 4
 128     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 129 };
 130
 131 typedef int (*msix_mask_notifier_func)(PCIDevice *, unsigned vector,
 132                                        int masked);
 133
 134 #define TYPE_PCI_DEVICE "pci-device"
 135 #define PCI_DEVICE(obj) \
 136      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 137 #define PCI_DEVICE_CLASS(klass) \
 138      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 139 #define PCI_DEVICE_GET_CLASS(obj) \
 140      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 141
 142 typedef struct PCIDeviceClass {
 143     DeviceClass parent_class;
 144
 145     int (*init)(PCIDevice *dev);
 146     PCIUnregisterFunc *exit;
 147     PCIConfigReadFunc *config_read;
 148     PCIConfigWriteFunc *config_write;
 149
 150     uint16_t vendor_id;
 151     uint16_t device_id;
 152     uint8_t revision;
 153     uint16_t class_id;
 154     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 155     uint16_t subsystem_id;              /* only for header type = 0 */
 156
 157     /*
 158      * pci-to-pci bridge or normal device.
 159      * This doesn't mean pci host switch.
 160      * When card bus bridge is supported, this would be enhanced.
 161      */
 162     int is_bridge;
 163
 164     /* pcie stuff */
 165     int is_express;   /* is this device pci express? */
 166
 167     /* device isn't hot-pluggable */
 168     int no_hotplug;
 169
 170     /* rom bar */
 171     const char *romfile;
 172 } PCIDeviceClass;
 173
 174 struct PCIDevice {
 175     DeviceState qdev;
 176     /* PCI config space */
 177     uint8_t *config;
 178
 179     /* Used to enable config checks on load. Note that writable bits are
 180      * never checked even if set in cmask. */
 181     uint8_t *cmask;
 182
 183     /* Used to implement R/W bytes */
 184     uint8_t *wmask;
 185
 186     /* Used to implement RW1C(Write 1 to Clear) bytes */
 187     uint8_t *w1cmask;
 188
 189     /* Used to allocate config space for capabilities. */
 190     uint8_t *used;
 191
 192     /* the following fields are read only */
 193     PCIBus *bus;
 194     uint32_t devfn;
 195     char name[64];
 196     PCIIORegion io_regions[PCI_NUM_REGIONS];
 197
 198     /* do not access the following fields */
 199     PCIConfigReadFunc *config_read;
 200     PCIConfigWriteFunc *config_write;
 201
 202     /* IRQ objects for the INTA-INTD pins.  */
 203     qemu_irq *irq;
 204
 205     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 206     uint8_t irq_state;
 207
 208     /* Capability bits */
 209     uint32_t cap_present;
 210
 211     /* Offset of MSI-X capability in config space */
 212     uint8_t msix_cap;
 213
 214     /* MSI-X entries */
 215     int msix_entries_nr;
 216
 217     /* Space to store MSIX table */
 218     uint8_t *msix_table_page;
 219     /* MMIO index used to map MSIX table and pending bit entries. */
 220     MemoryRegion msix_mmio;
 221     /* Reference-count for entries actually in use by driver. */
 222     unsigned *msix_entry_used;
 223     /* Region including the MSI-X table */
 224     uint32_t msix_bar_size;
 225     /* MSIX function mask set or MSIX disabled */
 226     bool msix_function_masked;
 227     /* Version id needed for VMState */
 228     int32_t version_id;
 229
 230     /* Offset of MSI capability in config space */
 231     uint8_t msi_cap;
 232
 233     /* PCI Express */
 234     PCIExpressDevice exp;
 235
 236     /* Location of option rom */
 237     char *romfile;
 238     bool has_rom;
 239     MemoryRegion rom;
 240     uint32_t rom_bar;
 241
 242     /* MSI entries */
 243     int msi_entries_nr;
 244     struct KVMMsiMessage *msi_irq_entries;
 245
 246     /* How much space does an MSIX table need. */
 247     /* The spec requires giving the table structure
 248      * a 4K aligned region all by itself. Align it to
 249      * target pages so that drivers can do passthrough
 250      * on the rest of the region. */
 251     target_phys_addr_t msix_page_size;
 252
 253     KVMMsiMessage *msix_irq_entries;
 254
 255     msix_mask_notifier_func msix_mask_notifier;
 256 };
 257
 258 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 259                       uint8_t attr, MemoryRegion *memory);
 260 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 261
 262 int pci_map_irq(PCIDevice *pci_dev, int pin);
 263
 264 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 265                        uint8_t offset, uint8_t size);
 266
 267 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 268
 269 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 270
 271
 272 uint32_t pci_default_read_config(PCIDevice *d,
 273                                  uint32_t address, int len);
 274 void pci_default_write_config(PCIDevice *d,
 275                               uint32_t address, uint32_t val, int len);
 276 void pci_device_save(PCIDevice *s, QEMUFile *f);
 277 int pci_device_load(PCIDevice *s, QEMUFile *f);
 278 MemoryRegion *pci_address_space(PCIDevice *dev);
 279 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 280
 281 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 282 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 283
 284 typedef enum {
 285     PCI_HOTPLUG_DISABLED,
 286     PCI_HOTPLUG_ENABLED,
 287     PCI_COLDPLUG_ENABLED,
 288 } PCIHotplugState;
 289
 290 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 291                               PCIHotplugState state);
 292 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 293                          const char *name,
 294                          MemoryRegion *address_space_mem,
 295                          MemoryRegion *address_space_io,
 296                          uint8_t devfn_min);
 297 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 298                     MemoryRegion *address_space_mem,
 299                     MemoryRegion *address_space_io,
 300                     uint8_t devfn_min);
 301 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 302                   void *irq_opaque, int nirq);
 303 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 304 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 305 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 306                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 307                          void *irq_opaque,
 308                          MemoryRegion *address_space_mem,
 309                          MemoryRegion *address_space_io,
 310                          uint8_t devfn_min, int nirq);
 311 void pci_device_reset(PCIDevice *dev);
 312 void pci_bus_reset(PCIBus *bus);
 313
 314 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 315                         const char *default_devaddr);
 316 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 317                                const char *default_devaddr);
 318 int pci_bus_num(PCIBus *s);
 319 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 320 PCIBus *pci_find_root_bus(int domain);
 321 int pci_find_domain(const PCIBus *bus);
 322 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 323 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 324 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 325 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 326
 327 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
 328                       unsigned int *slotp, unsigned int *funcp);
 329 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 330                      unsigned *slotp);
 331
 332 int pci_parse_host_devaddr(const char *addr, int *segp, int *busp,
 333                            int *slotp, int *funcp);
 334
 335 void pci_device_deassert_intx(PCIDevice *dev);
 336
 337 static inline void
 338 pci_set_byte(uint8_t *config, uint8_t val)
 339 {
 340     *config = val;
 341 }
 342
 343 static inline uint8_t
 344 pci_get_byte(const uint8_t *config)
 345 {
 346     return *config;
 347 }
 348
 349 static inline void
 350 pci_set_word(uint8_t *config, uint16_t val)
 351 {
 352     cpu_to_le16wu((uint16_t *)config, val);
 353 }
 354
 355 static inline uint16_t
 356 pci_get_word(const uint8_t *config)
 357 {
 358     return le16_to_cpupu((const uint16_t *)config);
 359 }
 360
 361 static inline void
 362 pci_set_long(uint8_t *config, uint32_t val)
 363 {
 364     cpu_to_le32wu((uint32_t *)config, val);
 365 }
 366
 367 static inline uint32_t
 368 pci_get_long(const uint8_t *config)
 369 {
 370     return le32_to_cpupu((const uint32_t *)config);
 371 }
 372
 373 static inline void
 374 pci_set_quad(uint8_t *config, uint64_t val)
 375 {
 376     cpu_to_le64w((uint64_t *)config, val);
 377 }
 378
 379 static inline uint64_t
 380 pci_get_quad(const uint8_t *config)
 381 {
 382     return le64_to_cpup((const uint64_t *)config);
 383 }
 384
 385 static inline void
 386 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 387 {
 388     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 389 }
 390
 391 static inline void
 392 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 393 {
 394     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 395 }
 396
 397 static inline void
 398 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 399 {
 400     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 401 }
 402
 403 static inline void
 404 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 405 {
 406     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 407 }
 408
 409 static inline void
 410 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 411 {
 412     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 413 }
 414
 415 static inline void
 416 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 417 {
 418     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 419 }
 420
 421 /*
 422  * helper functions to do bit mask operation on configuration space.
 423  * Just to set bit, use test-and-set and discard returned value.
 424  * Just to clear bit, use test-and-clear and discard returned value.
 425  * NOTE: They aren't atomic.
 426  */
 427 static inline uint8_t
 428 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 429 {
 430     uint8_t val = pci_get_byte(config);
 431     pci_set_byte(config, val & ~mask);
 432     return val & mask;
 433 }
 434
 435 static inline uint8_t
 436 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 437 {
 438     uint8_t val = pci_get_byte(config);
 439     pci_set_byte(config, val | mask);
 440     return val & mask;
 441 }
 442
 443 static inline uint16_t
 444 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 445 {
 446     uint16_t val = pci_get_word(config);
 447     pci_set_word(config, val & ~mask);
 448     return val & mask;
 449 }
 450
 451 static inline uint16_t
 452 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 453 {
 454     uint16_t val = pci_get_word(config);
 455     pci_set_word(config, val | mask);
 456     return val & mask;
 457 }
 458
 459 static inline uint32_t
 460 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 461 {
 462     uint32_t val = pci_get_long(config);
 463     pci_set_long(config, val & ~mask);
 464     return val & mask;
 465 }
 466
 467 static inline uint32_t
 468 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 469 {
 470     uint32_t val = pci_get_long(config);
 471     pci_set_long(config, val | mask);
 472     return val & mask;
 473 }
 474
 475 static inline uint64_t
 476 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 477 {
 478     uint64_t val = pci_get_quad(config);
 479     pci_set_quad(config, val & ~mask);
 480     return val & mask;
 481 }
 482
 483 static inline uint64_t
 484 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 485 {
 486     uint64_t val = pci_get_quad(config);
 487     pci_set_quad(config, val | mask);
 488     return val & mask;
 489 }
 490
 491 void pci_qdev_register(DeviceInfo *info);
 492
 493 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 494                                     const char *name);
 495 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 496                                            bool multifunction,
 497                                            const char *name);
 498 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 499 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 500
 501 static inline int pci_is_express(const PCIDevice *d)
 502 {
 503     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 504 }
 505
 506 static inline uint32_t pci_config_size(const PCIDevice *d)
 507 {
 508     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 509 }
 510
 511 /* DMA access functions */
 512 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 513                              void *buf, dma_addr_t len, DMADirection dir)
 514 {
 515     cpu_physical_memory_rw(addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
 516     return 0;
 517 }
 518
 519 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 520                                void *buf, dma_addr_t len)
 521 {
 522     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 523 }
 524
 525 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 526                                 const void *buf, dma_addr_t len)
 527 {
 528     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 529 }
 530
 531 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 532     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 533                                                    dma_addr_t addr)     \
 534     {                                                                   \
 535         return ld##_l##_phys(addr);                                     \
 536     }                                                                   \
 537     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 538                           dma_addr_t addr, uint##_bits##_t val)         \
 539     {                                                                   \
 540         st##_s##_phys(addr, val);                                       \
 541     }
 542
 543 PCI_DMA_DEFINE_LDST(ub, b, 8);
 544 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 545 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 546 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 547 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 548 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 549 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 550
 551 #undef PCI_DMA_DEFINE_LDST
 552
 553 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 554                                 dma_addr_t *plen, DMADirection dir)
 555 {
 556     target_phys_addr_t len = *plen;
 557     void *buf;
 558
 559     buf = cpu_physical_memory_map(addr, &len, dir == DMA_DIRECTION_FROM_DEVICE);
 560     *plen = len;
 561     return buf;
 562 }
 563
 564 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 565                                  DMADirection dir, dma_addr_t access_len)
 566 {
 567     cpu_physical_memory_unmap(buffer, len, dir == DMA_DIRECTION_FROM_DEVICE,
 568                               access_len);
 569 }
 570
 571 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 572                                        int alloc_hint)
 573 {
 574     qemu_sglist_init(qsg, alloc_hint);
 575 }
 576
 577 extern const VMStateDescription vmstate_pci_device;
 578
 579 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 580     .name       = (stringify(_field)),                               \
 581     .size       = sizeof(PCIDevice),                                 \
 582     .vmsd       = &vmstate_pci_device,                               \
 583     .flags      = VMS_STRUCT,                                        \
 584     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 585 }
 586
 587 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 588     .name       = (stringify(_field)),                               \
 589     .size       = sizeof(PCIDevice),                                 \
 590     .vmsd       = &vmstate_pci_device,                               \
 591     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 592     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 593 }
 594
 595 #endif