4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
34 #include "device-assignment.h"
36 #include "qmp-commands.h"
41 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
43 # define PCI_DPRINTF(format, ...) do { } while (0)
46 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
47 static char *pcibus_get_dev_path(DeviceState
*dev
);
48 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
49 static int pcibus_reset(BusState
*qbus
);
51 struct BusInfo pci_bus_info
= {
53 .size
= sizeof(PCIBus
),
54 .print_dev
= pcibus_dev_print
,
55 .get_dev_path
= pcibus_get_dev_path
,
56 .get_fw_dev_path
= pcibus_get_fw_dev_path
,
57 .reset
= pcibus_reset
,
58 .props
= (Property
[]) {
59 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
60 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
61 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
62 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
63 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
64 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
65 QEMU_PCI_CAP_SERR_BITNR
, true),
66 DEFINE_PROP_END_OF_LIST()
70 static void pci_update_mappings(PCIDevice
*d
);
71 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
72 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
);
73 static void pci_del_option_rom(PCIDevice
*pdev
);
75 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
76 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
81 QLIST_ENTRY(PCIHostBus
) next
;
83 static QLIST_HEAD(, PCIHostBus
) host_buses
;
85 static const VMStateDescription vmstate_pcibus
= {
88 .minimum_version_id
= 1,
89 .minimum_version_id_old
= 1,
90 .fields
= (VMStateField
[]) {
91 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
92 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
96 static int pci_bar(PCIDevice
*d
, int reg
)
100 if (reg
!= PCI_ROM_SLOT
)
101 return PCI_BASE_ADDRESS_0
+ reg
* 4;
103 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
104 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
107 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
109 return (d
->irq_state
>> irq_num
) & 0x1;
112 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
114 d
->irq_state
&= ~(0x1 << irq_num
);
115 d
->irq_state
|= level
<< irq_num
;
118 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
123 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
126 pci_dev
= bus
->parent_dev
;
128 bus
->irq_count
[irq_num
] += change
;
129 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
132 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
134 assert(irq_num
>= 0);
135 assert(irq_num
< bus
->nirq
);
136 return !!bus
->irq_count
[irq_num
];
139 /* Update interrupt status bit in config space on interrupt
141 static void pci_update_irq_status(PCIDevice
*dev
)
143 if (dev
->irq_state
) {
144 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
146 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
150 void pci_device_deassert_intx(PCIDevice
*dev
)
153 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
154 qemu_set_irq(dev
->irq
[i
], 0);
159 * This function is called on #RST and FLR.
160 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
162 void pci_device_reset(PCIDevice
*dev
)
166 qdev_reset_all(&dev
->qdev
);
169 pci_update_irq_status(dev
);
170 pci_device_deassert_intx(dev
);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
173 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
174 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
175 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
176 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
177 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
178 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
179 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
180 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
181 PCIIORegion
*region
= &dev
->io_regions
[r
];
186 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
187 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
188 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
190 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
193 pci_update_mappings(dev
);
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
200 void pci_bus_reset(PCIBus
*bus
)
204 for (i
= 0; i
< bus
->nirq
; i
++) {
205 bus
->irq_count
[i
] = 0;
207 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
208 if (bus
->devices
[i
]) {
209 pci_device_reset(bus
->devices
[i
]);
214 static int pcibus_reset(BusState
*qbus
)
216 pci_bus_reset(DO_UPCAST(PCIBus
, qbus
, qbus
));
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
223 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
225 struct PCIHostBus
*host
;
226 host
= g_malloc0(sizeof(*host
));
227 host
->domain
= domain
;
229 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
232 PCIBus
*pci_find_root_bus(int domain
)
234 struct PCIHostBus
*host
;
236 QLIST_FOREACH(host
, &host_buses
, next
) {
237 if (host
->domain
== domain
) {
245 int pci_find_domain(const PCIBus
*bus
)
248 struct PCIHostBus
*host
;
250 /* obtain root bus */
251 while ((d
= bus
->parent_dev
) != NULL
) {
255 QLIST_FOREACH(host
, &host_buses
, next
) {
256 if (host
->bus
== bus
) {
261 abort(); /* should not be reached */
265 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
267 MemoryRegion
*address_space_mem
,
268 MemoryRegion
*address_space_io
,
271 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
272 assert(PCI_FUNC(devfn_min
) == 0);
273 bus
->devfn_min
= devfn_min
;
274 bus
->address_space_mem
= address_space_mem
;
275 bus
->address_space_io
= address_space_io
;
278 QLIST_INIT(&bus
->child
);
279 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
281 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
284 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
285 MemoryRegion
*address_space_mem
,
286 MemoryRegion
*address_space_io
,
291 bus
= g_malloc0(sizeof(*bus
));
292 bus
->qbus
.qdev_allocated
= 1;
293 pci_bus_new_inplace(bus
, parent
, name
, address_space_mem
,
294 address_space_io
, devfn_min
);
298 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
299 void *irq_opaque
, int nirq
)
301 bus
->set_irq
= set_irq
;
302 bus
->map_irq
= map_irq
;
303 bus
->irq_opaque
= irq_opaque
;
305 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
308 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
310 bus
->qbus
.allow_hotplug
= 1;
311 bus
->hotplug
= hotplug
;
312 bus
->hotplug_qdev
= qdev
;
315 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
316 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
318 MemoryRegion
*address_space_mem
,
319 MemoryRegion
*address_space_io
,
320 uint8_t devfn_min
, int nirq
)
324 bus
= pci_bus_new(parent
, name
, address_space_mem
,
325 address_space_io
, devfn_min
);
326 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
330 int pci_bus_num(PCIBus
*s
)
333 return 0; /* pci host bridge */
334 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
337 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
339 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
343 assert(size
== pci_config_size(s
));
344 config
= g_malloc(size
);
346 qemu_get_buffer(f
, config
, size
);
347 for (i
= 0; i
< size
; ++i
) {
348 if ((config
[i
] ^ s
->config
[i
]) &
349 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
354 memcpy(s
->config
, config
, size
);
356 pci_update_mappings(s
);
363 /* just put buffer */
364 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
366 const uint8_t **v
= pv
;
367 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
368 qemu_put_buffer(f
, *v
, size
);
371 static VMStateInfo vmstate_info_pci_config
= {
372 .name
= "pci config",
373 .get
= get_pci_config_device
,
374 .put
= put_pci_config_device
,
377 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
379 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
380 uint32_t irq_state
[PCI_NUM_PINS
];
382 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
383 irq_state
[i
] = qemu_get_be32(f
);
384 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
385 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
391 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
392 pci_set_irq_state(s
, i
, irq_state
[i
]);
398 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
401 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
403 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
404 qemu_put_be32(f
, pci_irq_state(s
, i
));
408 static VMStateInfo vmstate_info_pci_irq_state
= {
409 .name
= "pci irq state",
410 .get
= get_pci_irq_state
,
411 .put
= put_pci_irq_state
,
414 const VMStateDescription vmstate_pci_device
= {
417 .minimum_version_id
= 1,
418 .minimum_version_id_old
= 1,
419 .fields
= (VMStateField
[]) {
420 VMSTATE_INT32_LE(version_id
, PCIDevice
),
421 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
422 vmstate_info_pci_config
,
423 PCI_CONFIG_SPACE_SIZE
),
424 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
425 vmstate_info_pci_irq_state
,
426 PCI_NUM_PINS
* sizeof(int32_t)),
427 VMSTATE_END_OF_LIST()
431 const VMStateDescription vmstate_pcie_device
= {
434 .minimum_version_id
= 1,
435 .minimum_version_id_old
= 1,
436 .fields
= (VMStateField
[]) {
437 VMSTATE_INT32_LE(version_id
, PCIDevice
),
438 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
439 vmstate_info_pci_config
,
440 PCIE_CONFIG_SPACE_SIZE
),
441 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
442 vmstate_info_pci_irq_state
,
443 PCI_NUM_PINS
* sizeof(int32_t)),
444 VMSTATE_END_OF_LIST()
448 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
450 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
453 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
455 /* Clear interrupt status bit: it is implicit
456 * in irq_state which we are saving.
457 * This makes us compatible with old devices
458 * which never set or clear this bit. */
459 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
460 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
461 /* Restore the interrupt status bit. */
462 pci_update_irq_status(s
);
465 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
468 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
469 /* Restore the interrupt status bit. */
470 pci_update_irq_status(s
);
474 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
476 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
477 pci_default_sub_vendor_id
);
478 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
479 pci_default_sub_device_id
);
483 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
484 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
486 int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
487 unsigned int *slotp
, unsigned int *funcp
)
492 unsigned long dom
= 0, bus
= 0;
493 unsigned int slot
= 0;
494 unsigned int func
= 0;
497 val
= strtoul(p
, &e
, 16);
503 val
= strtoul(p
, &e
, 16);
510 val
= strtoul(p
, &e
, 16);
523 val
= strtoul(p
, &e
, 16);
530 /* if funcp == NULL func is 0 */
531 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
537 /* Note: QEMU doesn't implement domains other than 0 */
538 if (!pci_find_bus(pci_find_root_bus(dom
), bus
))
550 * Parse device seg and bdf in device assignment command:
552 * -pcidevice host=[seg:]bus:dev.func
554 * Parse [seg:]<bus>:<slot>.<func> return -1 on error
556 int pci_parse_host_devaddr(const char *addr
, int *segp
, int *busp
,
557 int *slotp
, int *funcp
)
562 int seg
= 0, bus
= 0, slot
= 0, func
= 0;
564 /* parse optional seg */
575 if (val
<= 0 || val
> 2)
580 val
= strtoul(p
, &e
, 16);
592 val
= strtoul(p
, &e
, 16);
598 val
= strtoul(p
, &e
, 16);
604 val
= strtoul(p
, &e
, 16);
613 if (seg
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 0x7)
626 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
629 /* strip legacy tag */
630 if (!strncmp(addr
, "pci_addr=", 9)) {
633 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
, NULL
)) {
634 monitor_printf(mon
, "Invalid pci address\n");
640 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
647 return pci_find_bus(pci_find_root_bus(0), 0);
650 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
654 *devfnp
= PCI_DEVFN(slot
, 0);
655 return pci_find_bus(pci_find_root_bus(dom
), bus
);
658 static void pci_init_cmask(PCIDevice
*dev
)
660 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
661 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
662 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
663 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
664 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
665 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
666 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
667 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
670 static void pci_init_wmask(PCIDevice
*dev
)
672 int config_size
= pci_config_size(dev
);
674 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
675 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
676 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
677 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
678 PCI_COMMAND_INTX_DISABLE
);
679 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
680 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
683 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
684 config_size
- PCI_CONFIG_HEADER_SIZE
);
687 static void pci_init_w1cmask(PCIDevice
*dev
)
690 * Note: It's okay to set w1cmask even for readonly bits as
691 * long as their value is hardwired to 0.
693 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
694 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
695 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
696 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
699 static void pci_init_wmask_bridge(PCIDevice
*d
)
701 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
702 PCI_SEC_LETENCY_TIMER */
703 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
706 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
707 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
708 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
709 PCI_MEMORY_RANGE_MASK
& 0xffff);
710 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
711 PCI_MEMORY_RANGE_MASK
& 0xffff);
712 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
713 PCI_PREF_RANGE_MASK
& 0xffff);
714 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
715 PCI_PREF_RANGE_MASK
& 0xffff);
717 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
718 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
720 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
721 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
722 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
723 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
724 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
725 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
726 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
727 PCI_BRIDGE_CTL_PARITY
|
728 PCI_BRIDGE_CTL_SERR
|
731 PCI_BRIDGE_CTL_VGA_16BIT
|
732 PCI_BRIDGE_CTL_MASTER_ABORT
|
733 PCI_BRIDGE_CTL_BUS_RESET
|
734 PCI_BRIDGE_CTL_FAST_BACK
|
735 PCI_BRIDGE_CTL_DISCARD
|
736 PCI_BRIDGE_CTL_SEC_DISCARD
|
737 PCI_BRIDGE_CTL_DISCARD_SERR
);
738 /* Below does not do anything as we never set this bit, put here for
740 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
741 PCI_BRIDGE_CTL_DISCARD_STATUS
);
744 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
746 uint8_t slot
= PCI_SLOT(dev
->devfn
);
749 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
750 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
754 * multifunction bit is interpreted in two ways as follows.
755 * - all functions must set the bit to 1.
757 * - function 0 must set the bit, but the rest function (> 0)
758 * is allowed to leave the bit to 0.
759 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
761 * So OS (at least Linux) checks the bit of only function 0,
762 * and doesn't see the bit of function > 0.
764 * The below check allows both interpretation.
766 if (PCI_FUNC(dev
->devfn
)) {
767 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
768 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
769 /* function 0 should set multifunction bit */
770 error_report("PCI: single function device can't be populated "
771 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
777 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
780 /* function 0 indicates single function, so function > 0 must be NULL */
781 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
782 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
783 error_report("PCI: %x.0 indicates single function, "
784 "but %x.%x is already populated.",
792 static void pci_config_alloc(PCIDevice
*pci_dev
)
794 int config_size
= pci_config_size(pci_dev
);
796 pci_dev
->config
= g_malloc0(config_size
);
797 pci_dev
->cmask
= g_malloc0(config_size
);
798 pci_dev
->wmask
= g_malloc0(config_size
);
799 pci_dev
->w1cmask
= g_malloc0(config_size
);
800 pci_dev
->used
= g_malloc0(config_size
);
803 static void pci_config_free(PCIDevice
*pci_dev
)
805 g_free(pci_dev
->config
);
806 g_free(pci_dev
->cmask
);
807 g_free(pci_dev
->wmask
);
808 g_free(pci_dev
->w1cmask
);
809 g_free(pci_dev
->used
);
812 /* -1 for devfn means auto assign */
813 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
814 const char *name
, int devfn
)
816 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
817 PCIConfigReadFunc
*config_read
= pc
->config_read
;
818 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
821 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
822 devfn
+= PCI_FUNC_MAX
) {
823 if (!bus
->devices
[devfn
])
826 error_report("PCI: no slot/function available for %s, all in use", name
);
829 } else if (bus
->devices
[devfn
]) {
830 error_report("PCI: slot %d function %d not available for %s, in use by %s",
831 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
835 pci_dev
->devfn
= devfn
;
836 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
837 pci_dev
->irq_state
= 0;
838 pci_config_alloc(pci_dev
);
840 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
841 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
842 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
843 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
845 if (!pc
->is_bridge
) {
846 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
847 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
848 pc
->subsystem_vendor_id
);
849 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
852 pci_set_default_subsystem_id(pci_dev
);
855 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
856 assert(!pc
->subsystem_vendor_id
);
857 assert(!pc
->subsystem_id
);
859 pci_init_cmask(pci_dev
);
860 pci_init_wmask(pci_dev
);
861 pci_init_w1cmask(pci_dev
);
863 pci_init_wmask_bridge(pci_dev
);
865 if (pci_init_multifunction(bus
, pci_dev
)) {
866 pci_config_free(pci_dev
);
871 config_read
= pci_default_read_config
;
873 config_write
= pci_default_write_config
;
874 pci_dev
->config_read
= config_read
;
875 pci_dev
->config_write
= config_write
;
876 bus
->devices
[devfn
] = pci_dev
;
877 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
878 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
882 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
884 qemu_free_irqs(pci_dev
->irq
);
885 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
886 pci_config_free(pci_dev
);
889 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
894 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
895 r
= &pci_dev
->io_regions
[i
];
896 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
898 memory_region_del_subregion(r
->address_space
, r
->memory
);
902 static int pci_unregister_device(DeviceState
*dev
)
904 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
905 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
909 ret
= pc
->exit(pci_dev
);
913 pci_unregister_io_regions(pci_dev
);
914 pci_del_option_rom(pci_dev
);
915 g_free(pci_dev
->romfile
);
916 do_pci_unregister_device(pci_dev
);
920 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
921 uint8_t type
, MemoryRegion
*memory
)
926 pcibus_t size
= memory_region_size(memory
);
928 assert(region_num
>= 0);
929 assert(region_num
< PCI_NUM_REGIONS
);
930 if (size
& (size
-1)) {
931 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
932 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
936 r
= &pci_dev
->io_regions
[region_num
];
937 r
->addr
= PCI_BAR_UNMAPPED
;
943 addr
= pci_bar(pci_dev
, region_num
);
944 if (region_num
== PCI_ROM_SLOT
) {
945 /* ROM enable bit is writable */
946 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
948 pci_set_long(pci_dev
->config
+ addr
, type
);
949 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
950 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
951 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
952 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
954 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
955 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
957 pci_dev
->io_regions
[region_num
].memory
= memory
;
958 pci_dev
->io_regions
[region_num
].address_space
959 = type
& PCI_BASE_ADDRESS_SPACE_IO
960 ? pci_dev
->bus
->address_space_io
961 : pci_dev
->bus
->address_space_mem
;
964 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
966 return pci_dev
->io_regions
[region_num
].addr
;
969 static pcibus_t
pci_bar_address(PCIDevice
*d
,
970 int reg
, uint8_t type
, pcibus_t size
)
972 pcibus_t new_addr
, last_addr
;
973 int bar
= pci_bar(d
, reg
);
974 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
976 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
977 if (!(cmd
& PCI_COMMAND_IO
)) {
978 return PCI_BAR_UNMAPPED
;
980 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
981 last_addr
= new_addr
+ size
- 1;
982 /* NOTE: we have only 64K ioports on PC */
983 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
984 return PCI_BAR_UNMAPPED
;
989 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
990 return PCI_BAR_UNMAPPED
;
992 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
993 new_addr
= pci_get_quad(d
->config
+ bar
);
995 new_addr
= pci_get_long(d
->config
+ bar
);
997 /* the ROM slot has a specific enable bit */
998 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
999 return PCI_BAR_UNMAPPED
;
1001 new_addr
&= ~(size
- 1);
1002 last_addr
= new_addr
+ size
- 1;
1003 /* NOTE: we do not support wrapping */
1004 /* XXX: as we cannot support really dynamic
1005 mappings, we handle specific values as invalid
1007 if (last_addr
<= new_addr
|| new_addr
== 0 ||
1008 last_addr
== PCI_BAR_UNMAPPED
) {
1009 return PCI_BAR_UNMAPPED
;
1012 /* Now pcibus_t is 64bit.
1013 * Check if 32 bit BAR wraps around explicitly.
1014 * Without this, PC ide doesn't work well.
1015 * TODO: remove this work around.
1017 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
1018 return PCI_BAR_UNMAPPED
;
1022 * OS is allowed to set BAR beyond its addressable
1023 * bits. For example, 32 bit OS can set 64bit bar
1024 * to >4G. Check it. TODO: we might need to support
1025 * it in the future for e.g. PAE.
1027 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
1028 return PCI_BAR_UNMAPPED
;
1034 static void pci_update_mappings(PCIDevice
*d
)
1040 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1041 r
= &d
->io_regions
[i
];
1043 /* this region isn't registered */
1047 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
1049 /* This bar isn't changed */
1050 if (new_addr
== r
->addr
)
1053 /* now do the real mapping */
1054 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1055 memory_region_del_subregion(r
->address_space
, r
->memory
);
1058 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
1059 memory_region_add_subregion_overlap(r
->address_space
,
1060 r
->addr
, r
->memory
, 1);
1065 static inline int pci_irq_disabled(PCIDevice
*d
)
1067 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
1070 /* Called after interrupt disabled field update in config space,
1071 * assert/deassert interrupts if necessary.
1072 * Gets original interrupt disable bit value (before update). */
1073 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1075 int i
, disabled
= pci_irq_disabled(d
);
1076 if (disabled
== was_irq_disabled
)
1078 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1079 int state
= pci_irq_state(d
, i
);
1080 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1084 uint32_t pci_default_read_config(PCIDevice
*d
,
1085 uint32_t address
, int len
)
1089 memcpy(&val
, d
->config
+ address
, len
);
1090 return le32_to_cpu(val
);
1093 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1095 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1097 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1098 uint8_t wmask
= d
->wmask
[addr
+ i
];
1099 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1100 assert(!(wmask
& w1cmask
));
1101 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1102 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1105 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
1106 if (kvm_enabled() && kvm_irqchip_in_kernel() &&
1107 addr
>= PIIX_CONFIG_IRQ_ROUTE
&&
1108 addr
< PIIX_CONFIG_IRQ_ROUTE
+ 4)
1109 assigned_dev_update_irqs();
1110 #endif /* CONFIG_KVM_DEVICE_ASSIGNMENT */
1112 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1113 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1114 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1115 range_covers_byte(addr
, l
, PCI_COMMAND
))
1116 pci_update_mappings(d
);
1118 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1119 pci_update_irq_disabled(d
, was_irq_disabled
);
1122 /***********************************************************/
1123 /* generic PCI irq support */
1125 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1126 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1128 PCIDevice
*pci_dev
= opaque
;
1131 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1135 pci_set_irq_state(pci_dev
, irq_num
, level
);
1136 pci_update_irq_status(pci_dev
);
1137 if (pci_irq_disabled(pci_dev
))
1139 pci_change_irq_level(pci_dev
, irq_num
, change
);
1142 int pci_map_irq(PCIDevice
*pci_dev
, int pin
)
1144 return pci_dev
->bus
->map_irq(pci_dev
, pin
);
1147 /***********************************************************/
1148 /* monitor info on PCI */
1153 const char *fw_name
;
1154 uint16_t fw_ign_bits
;
1157 static const pci_class_desc pci_class_descriptions
[] =
1159 { 0x0001, "VGA controller", "display"},
1160 { 0x0100, "SCSI controller", "scsi"},
1161 { 0x0101, "IDE controller", "ide"},
1162 { 0x0102, "Floppy controller", "fdc"},
1163 { 0x0103, "IPI controller", "ipi"},
1164 { 0x0104, "RAID controller", "raid"},
1165 { 0x0106, "SATA controller"},
1166 { 0x0107, "SAS controller"},
1167 { 0x0180, "Storage controller"},
1168 { 0x0200, "Ethernet controller", "ethernet"},
1169 { 0x0201, "Token Ring controller", "token-ring"},
1170 { 0x0202, "FDDI controller", "fddi"},
1171 { 0x0203, "ATM controller", "atm"},
1172 { 0x0280, "Network controller"},
1173 { 0x0300, "VGA controller", "display", 0x00ff},
1174 { 0x0301, "XGA controller"},
1175 { 0x0302, "3D controller"},
1176 { 0x0380, "Display controller"},
1177 { 0x0400, "Video controller", "video"},
1178 { 0x0401, "Audio controller", "sound"},
1180 { 0x0403, "Audio controller", "sound"},
1181 { 0x0480, "Multimedia controller"},
1182 { 0x0500, "RAM controller", "memory"},
1183 { 0x0501, "Flash controller", "flash"},
1184 { 0x0580, "Memory controller"},
1185 { 0x0600, "Host bridge", "host"},
1186 { 0x0601, "ISA bridge", "isa"},
1187 { 0x0602, "EISA bridge", "eisa"},
1188 { 0x0603, "MC bridge", "mca"},
1189 { 0x0604, "PCI bridge", "pci"},
1190 { 0x0605, "PCMCIA bridge", "pcmcia"},
1191 { 0x0606, "NUBUS bridge", "nubus"},
1192 { 0x0607, "CARDBUS bridge", "cardbus"},
1193 { 0x0608, "RACEWAY bridge"},
1194 { 0x0680, "Bridge"},
1195 { 0x0700, "Serial port", "serial"},
1196 { 0x0701, "Parallel port", "parallel"},
1197 { 0x0800, "Interrupt controller", "interrupt-controller"},
1198 { 0x0801, "DMA controller", "dma-controller"},
1199 { 0x0802, "Timer", "timer"},
1200 { 0x0803, "RTC", "rtc"},
1201 { 0x0900, "Keyboard", "keyboard"},
1202 { 0x0901, "Pen", "pen"},
1203 { 0x0902, "Mouse", "mouse"},
1204 { 0x0A00, "Dock station", "dock", 0x00ff},
1205 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1206 { 0x0c00, "Fireware contorller", "fireware"},
1207 { 0x0c01, "Access bus controller", "access-bus"},
1208 { 0x0c02, "SSA controller", "ssa"},
1209 { 0x0c03, "USB controller", "usb"},
1210 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1214 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1215 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1220 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1221 d
= bus
->devices
[devfn
];
1228 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1229 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1231 bus
= pci_find_bus(bus
, bus_num
);
1234 pci_for_each_device_under_bus(bus
, fn
);
1238 static const pci_class_desc
*get_class_desc(int class)
1240 const pci_class_desc
*desc
;
1242 desc
= pci_class_descriptions
;
1243 while (desc
->desc
&& class != desc
->class) {
1250 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1252 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1254 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1257 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1258 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1259 PciMemoryRegionList
*region
;
1265 region
= g_malloc0(sizeof(*region
));
1266 region
->value
= g_malloc0(sizeof(*region
->value
));
1268 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1269 region
->value
->type
= g_strdup("io");
1271 region
->value
->type
= g_strdup("memory");
1272 region
->value
->has_prefetch
= true;
1273 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1274 region
->value
->has_mem_type_64
= true;
1275 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1278 region
->value
->bar
= i
;
1279 region
->value
->address
= r
->addr
;
1280 region
->value
->size
= r
->size
;
1282 /* XXX: waiting for the qapi to support GSList */
1284 head
= cur_item
= region
;
1286 cur_item
->next
= region
;
1294 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1297 PciBridgeInfo
*info
;
1299 info
= g_malloc0(sizeof(*info
));
1301 info
->bus
.number
= dev
->config
[PCI_PRIMARY_BUS
];
1302 info
->bus
.secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1303 info
->bus
.subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1305 info
->bus
.io_range
= g_malloc0(sizeof(*info
->bus
.io_range
));
1306 info
->bus
.io_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1307 info
->bus
.io_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1309 info
->bus
.memory_range
= g_malloc0(sizeof(*info
->bus
.memory_range
));
1310 info
->bus
.memory_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1311 info
->bus
.memory_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1313 info
->bus
.prefetchable_range
= g_malloc0(sizeof(*info
->bus
.prefetchable_range
));
1314 info
->bus
.prefetchable_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1315 info
->bus
.prefetchable_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1317 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1318 PCIBus
*child_bus
= pci_find_bus(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1320 info
->has_devices
= true;
1321 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1328 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1331 const pci_class_desc
*desc
;
1332 PciDeviceInfo
*info
;
1336 info
= g_malloc0(sizeof(*info
));
1337 info
->bus
= bus_num
;
1338 info
->slot
= PCI_SLOT(dev
->devfn
);
1339 info
->function
= PCI_FUNC(dev
->devfn
);
1341 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1342 info
->class_info
.class = class;
1343 desc
= get_class_desc(class);
1345 info
->class_info
.has_desc
= true;
1346 info
->class_info
.desc
= g_strdup(desc
->desc
);
1349 info
->id
.vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1350 info
->id
.device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1351 info
->regions
= qmp_query_pci_regions(dev
);
1352 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1354 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1355 info
->has_irq
= true;
1356 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1359 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1360 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1361 info
->has_pci_bridge
= true;
1362 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1368 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1370 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1374 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1375 dev
= bus
->devices
[devfn
];
1377 info
= g_malloc0(sizeof(*info
));
1378 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1380 /* XXX: waiting for the qapi to support GSList */
1382 head
= cur_item
= info
;
1384 cur_item
->next
= info
;
1393 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1395 PciInfo
*info
= NULL
;
1397 bus
= pci_find_bus(bus
, bus_num
);
1399 info
= g_malloc0(sizeof(*info
));
1400 info
->bus
= bus_num
;
1401 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1407 PciInfoList
*qmp_query_pci(Error
**errp
)
1409 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1410 struct PCIHostBus
*host
;
1412 QLIST_FOREACH(host
, &host_buses
, next
) {
1413 info
= g_malloc0(sizeof(*info
));
1414 info
->value
= qmp_query_pci_bus(host
->bus
, 0);
1416 /* XXX: waiting for the qapi to support GSList */
1418 head
= cur_item
= info
;
1420 cur_item
->next
= info
;
1428 static const char * const pci_nic_models
[] = {
1440 static const char * const pci_nic_names
[] = {
1452 /* Initialize a PCI NIC. */
1453 /* FIXME callers should check for failure, but don't */
1454 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1455 const char *default_devaddr
)
1457 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1464 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1468 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1470 error_report("Invalid PCI device address %s for device %s",
1471 devaddr
, pci_nic_names
[i
]);
1475 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1476 dev
= &pci_dev
->qdev
;
1477 qdev_set_nic_properties(dev
, nd
);
1478 if (qdev_init(dev
) < 0)
1483 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1484 const char *default_devaddr
)
1488 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1491 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1497 /* Whether a given bus number is in range of the secondary
1498 * bus of the given bridge device. */
1499 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1501 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1502 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1503 dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1504 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1507 PCIBus
*pci_find_bus(PCIBus
*bus
, int bus_num
)
1515 if (pci_bus_num(bus
) == bus_num
) {
1519 /* Consider all bus numbers in range for the host pci bridge. */
1520 if (bus
->parent_dev
&&
1521 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1526 for (; bus
; bus
= sec
) {
1527 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1528 assert(sec
->parent_dev
);
1529 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1532 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1541 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1543 bus
= pci_find_bus(bus
, bus_num
);
1548 return bus
->devices
[devfn
];
1551 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
1553 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1554 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1557 bool is_default_rom
;
1559 /* initialize cap_present for pci_is_express() and pci_config_size() */
1560 if (pc
->is_express
) {
1561 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1564 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1565 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, pci_dev
->devfn
);
1566 if (pci_dev
== NULL
)
1568 if (qdev
->hotplugged
&& pc
->no_hotplug
) {
1569 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(pci_dev
)));
1570 do_pci_unregister_device(pci_dev
);
1574 rc
= pc
->init(pci_dev
);
1576 do_pci_unregister_device(pci_dev
);
1582 is_default_rom
= false;
1583 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
1584 pci_dev
->romfile
= g_strdup(pc
->romfile
);
1585 is_default_rom
= true;
1587 pci_add_option_rom(pci_dev
, is_default_rom
);
1590 /* Let buses differentiate between hotplug and when device is
1591 * enabled during qemu machine creation. */
1592 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
,
1593 qdev
->hotplugged
? PCI_HOTPLUG_ENABLED
:
1594 PCI_COLDPLUG_ENABLED
);
1596 int r
= pci_unregister_device(&pci_dev
->qdev
);
1604 static int pci_unplug_device(DeviceState
*qdev
)
1606 PCIDevice
*dev
= PCI_DEVICE(qdev
);
1607 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1609 if (pc
->no_hotplug
) {
1610 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(dev
)));
1613 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
,
1614 PCI_HOTPLUG_DISABLED
);
1617 void pci_qdev_register(DeviceInfo
*info
)
1619 info
->init
= pci_qdev_init
;
1620 if (!info
->unplug
) {
1621 info
->unplug
= pci_unplug_device
;
1623 info
->exit
= pci_unregister_device
;
1624 info
->bus_info
= &pci_bus_info
;
1625 qdev_register_subclass(info
, TYPE_PCI_DEVICE
);
1628 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1633 dev
= qdev_create(&bus
->qbus
, name
);
1634 qdev_prop_set_uint32(dev
, "addr", devfn
);
1635 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1636 return PCI_DEVICE(dev
);
1639 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1643 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1644 qdev_init_nofail(&dev
->qdev
);
1648 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1650 return pci_create_multifunction(bus
, devfn
, false, name
);
1653 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1655 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1658 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1660 int config_size
= pci_config_size(pdev
);
1661 int offset
= PCI_CONFIG_HEADER_SIZE
;
1663 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1666 else if (i
- offset
+ 1 == size
)
1671 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1676 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1679 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1680 prev
= next
+ PCI_CAP_LIST_NEXT
)
1681 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1689 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
1691 uint8_t next
, prev
, found
= 0;
1693 if (!(pdev
->used
[offset
])) {
1697 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
1699 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1700 prev
= next
+ PCI_CAP_LIST_NEXT
) {
1701 if (next
<= offset
&& next
> found
) {
1708 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1709 This is needed for an option rom which is used for more than one device. */
1710 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
1714 uint16_t rom_vendor_id
;
1715 uint16_t rom_device_id
;
1717 uint16_t pcir_offset
;
1720 /* Words in rom data are little endian (like in PCI configuration),
1721 so they can be read / written with pci_get_word / pci_set_word. */
1723 /* Only a valid rom will be patched. */
1724 rom_magic
= pci_get_word(ptr
);
1725 if (rom_magic
!= 0xaa55) {
1726 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
1729 pcir_offset
= pci_get_word(ptr
+ 0x18);
1730 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
1731 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
1735 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1736 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1737 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
1738 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
1740 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
1741 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
1745 if (vendor_id
!= rom_vendor_id
) {
1746 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1747 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
1748 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
1749 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1751 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
1754 if (device_id
!= rom_device_id
) {
1755 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1756 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
1757 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
1758 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1760 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
1764 /* Add an option rom for the device */
1765 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
)
1774 if (strlen(pdev
->romfile
) == 0)
1777 if (!pdev
->rom_bar
) {
1779 * Load rom via fw_cfg instead of creating a rom bar,
1780 * for 0.11 compatibility.
1782 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1783 if (class == 0x0300) {
1784 rom_add_vga(pdev
->romfile
);
1786 rom_add_option(pdev
->romfile
, -1);
1791 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1793 path
= g_strdup(pdev
->romfile
);
1796 size
= get_image_size(path
);
1798 error_report("%s: failed to find romfile \"%s\"",
1799 __FUNCTION__
, pdev
->romfile
);
1803 if (size
& (size
- 1)) {
1804 size
= 1 << qemu_fls(size
);
1807 if (qdev_get_info(&pdev
->qdev
)->vmsd
)
1808 snprintf(name
, sizeof(name
), "%s.rom", qdev_get_info(&pdev
->qdev
)->vmsd
->name
);
1810 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
1811 pdev
->has_rom
= true;
1812 memory_region_init_ram(&pdev
->rom
, name
, size
);
1813 vmstate_register_ram(&pdev
->rom
, &pdev
->qdev
);
1814 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
1815 load_image(path
, ptr
);
1818 if (is_default_rom
) {
1819 /* Only the default rom images will be patched (if needed). */
1820 pci_patch_ids(pdev
, ptr
, size
);
1823 qemu_put_ram_ptr(ptr
);
1825 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
1830 static void pci_del_option_rom(PCIDevice
*pdev
)
1835 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
1836 memory_region_destroy(&pdev
->rom
);
1837 pdev
->has_rom
= false;
1842 * Reserve space and add capability to the linked list in pci config space
1845 * Find and reserve space and add capability to the linked list
1846 * in pci config space */
1847 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
1848 uint8_t offset
, uint8_t size
)
1851 int i
, overlapping_cap
;
1854 offset
= pci_find_space(pdev
, size
);
1859 /* Verify that capabilities don't overlap. Note: device assignment
1860 * depends on this check to verify that the device is not broken.
1861 * Should never trigger for emulated devices, but it's helpful
1862 * for debugging these. */
1863 for (i
= offset
; i
< offset
+ size
; i
++) {
1864 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
1865 if (overlapping_cap
) {
1866 fprintf(stderr
, "ERROR: %04x:%02x:%02x.%x "
1867 "Attempt to add PCI capability %x at offset "
1868 "%x overlaps existing capability %x at offset %x\n",
1869 pci_find_domain(pdev
->bus
), pci_bus_num(pdev
->bus
),
1870 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
1871 cap_id
, offset
, overlapping_cap
, i
);
1877 config
= pdev
->config
+ offset
;
1878 config
[PCI_CAP_LIST_ID
] = cap_id
;
1879 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1880 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1881 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1882 memset(pdev
->used
+ offset
, 0xFF, size
);
1883 /* Make capability read-only by default */
1884 memset(pdev
->wmask
+ offset
, 0, size
);
1885 /* Check capability by default */
1886 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1890 /* Unlink capability from the pci config space. */
1891 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1893 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1896 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1897 /* Make capability writable again */
1898 memset(pdev
->wmask
+ offset
, 0xff, size
);
1899 memset(pdev
->w1cmask
+ offset
, 0, size
);
1900 /* Clear cmask as device-specific registers can't be checked */
1901 memset(pdev
->cmask
+ offset
, 0, size
);
1902 memset(pdev
->used
+ offset
, 0, size
);
1904 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1905 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1908 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1910 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1913 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1915 PCIDevice
*d
= (PCIDevice
*)dev
;
1916 const pci_class_desc
*desc
;
1921 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1922 desc
= pci_class_descriptions
;
1923 while (desc
->desc
&& class != desc
->class)
1926 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1928 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1931 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1932 "pci id %04x:%04x (sub %04x:%04x)\n",
1933 indent
, "", ctxt
, pci_bus_num(d
->bus
),
1934 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1935 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1936 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1937 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1938 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1939 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1940 r
= &d
->io_regions
[i
];
1943 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1944 " [0x%"FMT_PCIBUS
"]\n",
1946 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1947 r
->addr
, r
->addr
+ r
->size
- 1);
1951 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
1953 PCIDevice
*d
= (PCIDevice
*)dev
;
1954 const char *name
= NULL
;
1955 const pci_class_desc
*desc
= pci_class_descriptions
;
1956 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1958 while (desc
->desc
&&
1959 (class & ~desc
->fw_ign_bits
) !=
1960 (desc
->class & ~desc
->fw_ign_bits
)) {
1965 name
= desc
->fw_name
;
1969 pstrcpy(buf
, len
, name
);
1971 snprintf(buf
, len
, "pci%04x,%04x",
1972 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1973 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
1979 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
1981 PCIDevice
*d
= (PCIDevice
*)dev
;
1982 char path
[50], name
[33];
1985 off
= snprintf(path
, sizeof(path
), "%s@%x",
1986 pci_dev_fw_name(dev
, name
, sizeof name
),
1987 PCI_SLOT(d
->devfn
));
1988 if (PCI_FUNC(d
->devfn
))
1989 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
1990 return strdup(path
);
1993 static char *pcibus_get_dev_path(DeviceState
*dev
)
1995 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
1998 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
1999 * 00 is added here to make this format compatible with
2000 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2001 * Slot.Function list specifies the slot and function numbers for all
2002 * devices on the path from root to the specific device. */
2003 char domain
[] = "DDDD:00";
2004 char slot
[] = ":SS.F";
2005 int domain_len
= sizeof domain
- 1 /* For '\0' */;
2006 int slot_len
= sizeof slot
- 1 /* For '\0' */;
2011 /* Calculate # of slots on path between device and root. */;
2013 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2017 path_len
= domain_len
+ slot_len
* slot_depth
;
2019 /* Allocate memory, fill in the terminating null byte. */
2020 path
= g_malloc(path_len
+ 1 /* For '\0' */);
2021 path
[path_len
] = '\0';
2023 /* First field is the domain. */
2024 s
= snprintf(domain
, sizeof domain
, "%04x:00", pci_find_domain(d
->bus
));
2025 assert(s
== domain_len
);
2026 memcpy(path
, domain
, domain_len
);
2028 /* Fill in slot numbers. We walk up from device to root, so need to print
2029 * them in the reverse order, last to first. */
2030 p
= path
+ path_len
;
2031 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
2033 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
2034 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
2035 assert(s
== slot_len
);
2036 memcpy(p
, slot
, slot_len
);
2042 static int pci_qdev_find_recursive(PCIBus
*bus
,
2043 const char *id
, PCIDevice
**pdev
)
2045 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
2050 /* roughly check if given qdev is pci device */
2051 if (qdev_get_info(qdev
)->init
== &pci_qdev_init
&&
2052 qdev
->parent_bus
->info
== &pci_bus_info
) {
2053 *pdev
= PCI_DEVICE(qdev
);
2059 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
2061 struct PCIHostBus
*host
;
2064 QLIST_FOREACH(host
, &host_buses
, next
) {
2065 int tmp
= pci_qdev_find_recursive(host
->bus
, id
, pdev
);
2070 if (tmp
!= -ENODEV
) {
2078 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
2080 return dev
->bus
->address_space_mem
;
2083 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
2085 return dev
->bus
->address_space_io
;
2088 static TypeInfo pci_device_type_info
= {
2089 .name
= TYPE_PCI_DEVICE
,
2090 .parent
= TYPE_DEVICE
,
2091 .instance_size
= sizeof(PCIDevice
),
2093 .class_size
= sizeof(PCIDeviceClass
),
2096 static void pci_register_devices(void)
2098 type_register_static(&pci_device_type_info
);
2101 device_init(pci_register_devices
);