hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "vmware_vga.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "msi.h"
  40 #include "sysbus.h"
  41 #include "sysemu.h"
  42 #include "kvm.h"
  43 #include "blockdev.h"
  44 #include "ui/qemu-spice.h"
  45 #include "memory.h"
  46 #include "exec-memory.h"
  47
  48 /* output Bochs bios info messages */
  49 //#define DEBUG_BIOS
  50
  51 /* debug PC/ISA interrupts */
  52 //#define DEBUG_IRQ
  53
  54 #ifdef DEBUG_IRQ
  55 #define DPRINTF(fmt, ...)                                       \
  56     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  57 #else
  58 #define DPRINTF(fmt, ...)
  59 #endif
  60
  61 #define BIOS_FILENAME "bios.bin"
  62 #define VAPIC_FILENAME "vapic.bin"
  63
  64 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  65
  66 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  67 #define ACPI_DATA_SIZE       0x10000
  68 #define BIOS_CFG_IOPORT 0x510
  69 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  70 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  71 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  72 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  73 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  74
  75 #define MSI_ADDR_BASE 0xfee00000
  76
  77 #define E820_NR_ENTRIES         16
  78
  79 struct e820_entry {
  80     uint64_t address;
  81     uint64_t length;
  82     uint32_t type;
  83 } QEMU_PACKED __attribute((__aligned__(4)));
  84
  85 struct e820_table {
  86     uint32_t count;
  87     struct e820_entry entry[E820_NR_ENTRIES];
  88 } QEMU_PACKED __attribute((__aligned__(4)));
  89
  90 static struct e820_table e820_table;
  91 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  92
  93 void gsi_handler(void *opaque, int n, int level)
  94 {
  95     GSIState *s = opaque;
  96
  97     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  98     if (n < ISA_NUM_IRQS) {
  99         qemu_set_irq(s->i8259_irq[n], level);
 100     }
 101     qemu_set_irq(s->ioapic_irq[n], level);
 102 }
 103
 104 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 105 {
 106 }
 107
 108 /* MSDOS compatibility mode FPU exception support */
 109 static qemu_irq ferr_irq;
 110
 111 void pc_register_ferr_irq(qemu_irq irq)
 112 {
 113     ferr_irq = irq;
 114 }
 115
 116 /* XXX: add IGNNE support */
 117 void cpu_set_ferr(CPUX86State *s)
 118 {
 119     qemu_irq_raise(ferr_irq);
 120 }
 121
 122 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 123 {
 124     qemu_irq_lower(ferr_irq);
 125 }
 126
 127 /* TSC handling */
 128 uint64_t cpu_get_tsc(CPUX86State *env)
 129 {
 130     return cpu_get_ticks();
 131 }
 132
 133 /* SMM support */
 134
 135 static cpu_set_smm_t smm_set;
 136 static void *smm_arg;
 137
 138 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 139 {
 140     assert(smm_set == NULL);
 141     assert(smm_arg == NULL);
 142     smm_set = callback;
 143     smm_arg = arg;
 144 }
 145
 146 void cpu_smm_update(CPUState *env)
 147 {
 148     if (smm_set && smm_arg && env == first_cpu)
 149         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 150 }
 151
 152
 153 /* IRQ handling */
 154 int cpu_get_pic_interrupt(CPUState *env)
 155 {
 156     int intno;
 157
 158     intno = apic_get_interrupt(env->apic_state);
 159     if (intno >= 0) {
 160         return intno;
 161     }
 162     /* read the irq from the PIC */
 163     if (!apic_accept_pic_intr(env->apic_state)) {
 164         return -1;
 165     }
 166
 167     intno = pic_read_irq(isa_pic);
 168     return intno;
 169 }
 170
 171 static void pic_irq_request(void *opaque, int irq, int level)
 172 {
 173     CPUState *env = first_cpu;
 174
 175     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 176     if (env->apic_state) {
 177         while (env) {
 178             if (apic_accept_pic_intr(env->apic_state)) {
 179                 apic_deliver_pic_intr(env->apic_state, level);
 180             }
 181             env = env->next_cpu;
 182         }
 183     } else {
 184         if (level)
 185             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 186         else
 187             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 188     }
 189 }
 190
 191 /* PC cmos mappings */
 192
 193 #define REG_EQUIPMENT_BYTE          0x14
 194
 195 static int cmos_get_fd_drive_type(FDriveType fd0)
 196 {
 197     int val;
 198
 199     switch (fd0) {
 200     case FDRIVE_DRV_144:
 201         /* 1.44 Mb 3"5 drive */
 202         val = 4;
 203         break;
 204     case FDRIVE_DRV_288:
 205         /* 2.88 Mb 3"5 drive */
 206         val = 5;
 207         break;
 208     case FDRIVE_DRV_120:
 209         /* 1.2 Mb 5"5 drive */
 210         val = 2;
 211         break;
 212     case FDRIVE_DRV_NONE:
 213     default:
 214         val = 0;
 215         break;
 216     }
 217     return val;
 218 }
 219
 220 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
 221                          ISADevice *s)
 222 {
 223     int cylinders, heads, sectors;
 224     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 225     rtc_set_memory(s, type_ofs, 47);
 226     rtc_set_memory(s, info_ofs, cylinders);
 227     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 228     rtc_set_memory(s, info_ofs + 2, heads);
 229     rtc_set_memory(s, info_ofs + 3, 0xff);
 230     rtc_set_memory(s, info_ofs + 4, 0xff);
 231     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 232     rtc_set_memory(s, info_ofs + 6, cylinders);
 233     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 234     rtc_set_memory(s, info_ofs + 8, sectors);
 235 }
 236
 237 /* convert boot_device letter to something recognizable by the bios */
 238 static int boot_device2nibble(char boot_device)
 239 {
 240     switch(boot_device) {
 241     case 'a':
 242     case 'b':
 243         return 0x01; /* floppy boot */
 244     case 'c':
 245         return 0x02; /* hard drive boot */
 246     case 'd':
 247         return 0x03; /* CD-ROM boot */
 248     case 'n':
 249         return 0x04; /* Network boot */
 250     }
 251     return 0;
 252 }
 253
 254 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 255 {
 256 #define PC_MAX_BOOT_DEVICES 3
 257     int nbds, bds[3] = { 0, };
 258     int i;
 259
 260     nbds = strlen(boot_device);
 261     if (nbds > PC_MAX_BOOT_DEVICES) {
 262         error_report("Too many boot devices for PC");
 263         return(1);
 264     }
 265     for (i = 0; i < nbds; i++) {
 266         bds[i] = boot_device2nibble(boot_device[i]);
 267         if (bds[i] == 0) {
 268             error_report("Invalid boot device for PC: '%c'",
 269                          boot_device[i]);
 270             return(1);
 271         }
 272     }
 273     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 274     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 275     return(0);
 276 }
 277
 278 static int pc_boot_set(void *opaque, const char *boot_device)
 279 {
 280     return set_boot_dev(opaque, boot_device, 0);
 281 }
 282
 283 typedef struct pc_cmos_init_late_arg {
 284     ISADevice *rtc_state;
 285     BusState *idebus0, *idebus1;
 286 } pc_cmos_init_late_arg;
 287
 288 static void pc_cmos_init_late(void *opaque)
 289 {
 290     pc_cmos_init_late_arg *arg = opaque;
 291     ISADevice *s = arg->rtc_state;
 292     int val;
 293     BlockDriverState *hd_table[4];
 294     int i;
 295
 296     ide_get_bs(hd_table, arg->idebus0);
 297     ide_get_bs(hd_table + 2, arg->idebus1);
 298
 299     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 300     if (hd_table[0])
 301         cmos_init_hd(0x19, 0x1b, hd_table[0], s);
 302     if (hd_table[1])
 303         cmos_init_hd(0x1a, 0x24, hd_table[1], s);
 304
 305     val = 0;
 306     for (i = 0; i < 4; i++) {
 307         if (hd_table[i]) {
 308             int cylinders, heads, sectors, translation;
 309             /* NOTE: bdrv_get_geometry_hint() returns the physical
 310                 geometry.  It is always such that: 1 <= sects <= 63, 1
 311                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 312                 geometry can be different if a translation is done. */
 313             translation = bdrv_get_translation_hint(hd_table[i]);
 314             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 315                 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
 316                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 317                     /* No translation. */
 318                     translation = 0;
 319                 } else {
 320                     /* LBA translation. */
 321                     translation = 1;
 322                 }
 323             } else {
 324                 translation--;
 325             }
 326             val |= translation << (i * 2);
 327         }
 328     }
 329     rtc_set_memory(s, 0x39, val);
 330
 331     qemu_unregister_reset(pc_cmos_init_late, opaque);
 332 }
 333
 334 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 335                   const char *boot_device,
 336                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 337                   ISADevice *s)
 338 {
 339     int val, nb, nb_heads, max_track, last_sect, i;
 340     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 341     BlockDriverState *fd[MAX_FD];
 342     static pc_cmos_init_late_arg arg;
 343
 344     /* various important CMOS locations needed by PC/Bochs bios */
 345
 346     /* memory size */
 347     val = 640; /* base memory in K */
 348     rtc_set_memory(s, 0x15, val);
 349     rtc_set_memory(s, 0x16, val >> 8);
 350
 351     val = (ram_size / 1024) - 1024;
 352     if (val > 65535)
 353         val = 65535;
 354     rtc_set_memory(s, 0x17, val);
 355     rtc_set_memory(s, 0x18, val >> 8);
 356     rtc_set_memory(s, 0x30, val);
 357     rtc_set_memory(s, 0x31, val >> 8);
 358
 359     if (above_4g_mem_size) {
 360         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 361         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 362         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 363     }
 364
 365     if (ram_size > (16 * 1024 * 1024))
 366         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 367     else
 368         val = 0;
 369     if (val > 65535)
 370         val = 65535;
 371     rtc_set_memory(s, 0x34, val);
 372     rtc_set_memory(s, 0x35, val >> 8);
 373
 374     /* set the number of CPU */
 375     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 376
 377     /* set boot devices, and disable floppy signature check if requested */
 378     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 379         exit(1);
 380     }
 381
 382     /* floppy type */
 383     if (floppy) {
 384         fdc_get_bs(fd, floppy);
 385         for (i = 0; i < 2; i++) {
 386             if (fd[i] && bdrv_is_inserted(fd[i])) {
 387                 bdrv_get_floppy_geometry_hint(fd[i], &nb_heads, &max_track,
 388                                               &last_sect, FDRIVE_DRV_NONE,
 389                                               &fd_type[i]);
 390             }
 391         }
 392     }
 393     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 394         cmos_get_fd_drive_type(fd_type[1]);
 395     rtc_set_memory(s, 0x10, val);
 396
 397     val = 0;
 398     nb = 0;
 399     if (fd_type[0] < FDRIVE_DRV_NONE) {
 400         nb++;
 401     }
 402     if (fd_type[1] < FDRIVE_DRV_NONE) {
 403         nb++;
 404     }
 405     switch (nb) {
 406     case 0:
 407         break;
 408     case 1:
 409         val |= 0x01; /* 1 drive, ready for boot */
 410         break;
 411     case 2:
 412         val |= 0x41; /* 2 drives, ready for boot */
 413         break;
 414     }
 415     val |= 0x02; /* FPU is there */
 416     val |= 0x04; /* PS/2 mouse installed */
 417     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 418
 419     /* hard drives */
 420     arg.rtc_state = s;
 421     arg.idebus0 = idebus0;
 422     arg.idebus1 = idebus1;
 423     qemu_register_reset(pc_cmos_init_late, &arg);
 424 }
 425
 426 /* port 92 stuff: could be split off */
 427 typedef struct Port92State {
 428     ISADevice dev;
 429     MemoryRegion io;
 430     uint8_t outport;
 431     qemu_irq *a20_out;
 432 } Port92State;
 433
 434 static void port92_write(void *opaque, uint32_t addr, uint32_t val)
 435 {
 436     Port92State *s = opaque;
 437
 438     DPRINTF("port92: write 0x%02x\n", val);
 439     s->outport = val;
 440     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 441     if (val & 1) {
 442         qemu_system_reset_request();
 443     }
 444 }
 445
 446 static uint32_t port92_read(void *opaque, uint32_t addr)
 447 {
 448     Port92State *s = opaque;
 449     uint32_t ret;
 450
 451     ret = s->outport;
 452     DPRINTF("port92: read 0x%02x\n", ret);
 453     return ret;
 454 }
 455
 456 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 457 {
 458     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 459
 460     s->a20_out = a20_out;
 461 }
 462
 463 static const VMStateDescription vmstate_port92_isa = {
 464     .name = "port92",
 465     .version_id = 1,
 466     .minimum_version_id = 1,
 467     .minimum_version_id_old = 1,
 468     .fields      = (VMStateField []) {
 469         VMSTATE_UINT8(outport, Port92State),
 470         VMSTATE_END_OF_LIST()
 471     }
 472 };
 473
 474 static void port92_reset(DeviceState *d)
 475 {
 476     Port92State *s = container_of(d, Port92State, dev.qdev);
 477
 478     s->outport &= ~1;
 479 }
 480
 481 static const MemoryRegionPortio port92_portio[] = {
 482     { 0, 1, 1, .read = port92_read, .write = port92_write },
 483     PORTIO_END_OF_LIST(),
 484 };
 485
 486 static const MemoryRegionOps port92_ops = {
 487     .old_portio = port92_portio
 488 };
 489
 490 static int port92_initfn(ISADevice *dev)
 491 {
 492     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 493
 494     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 495     isa_register_ioport(dev, &s->io, 0x92);
 496
 497     s->outport = 0;
 498     return 0;
 499 }
 500
 501 static void port92_class_initfn(ObjectClass *klass, void *data)
 502 {
 503     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 504     ic->init = port92_initfn;
 505 }
 506
 507 static DeviceInfo port92_info = {
 508     .name     = "port92",
 509     .size     = sizeof(Port92State),
 510     .vmsd     = &vmstate_port92_isa,
 511     .no_user  = 1,
 512     .reset    = port92_reset,
 513     .class_init          = port92_class_initfn,
 514 };
 515
 516 static void port92_register(void)
 517 {
 518     isa_qdev_register(&port92_info);
 519 }
 520 device_init(port92_register)
 521
 522 static void handle_a20_line_change(void *opaque, int irq, int level)
 523 {
 524     CPUState *cpu = opaque;
 525
 526     /* XXX: send to all CPUs ? */
 527     /* XXX: add logic to handle multiple A20 line sources */
 528     cpu_x86_set_a20(cpu, level);
 529 }
 530
 531 /***********************************************************/
 532 /* Bochs BIOS debug ports */
 533
 534 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 535 {
 536     static const char shutdown_str[8] = "Shutdown";
 537     static int shutdown_index = 0;
 538
 539     switch(addr) {
 540         /* Bochs BIOS messages */
 541     case 0x400:
 542     case 0x401:
 543         /* used to be panic, now unused */
 544         break;
 545     case 0x402:
 546     case 0x403:
 547 #ifdef DEBUG_BIOS
 548         fprintf(stderr, "%c", val);
 549 #endif
 550         break;
 551     case 0x8900:
 552         /* same as Bochs power off */
 553         if (val == shutdown_str[shutdown_index]) {
 554             shutdown_index++;
 555             if (shutdown_index == 8) {
 556                 shutdown_index = 0;
 557                 qemu_system_shutdown_request();
 558             }
 559         } else {
 560             shutdown_index = 0;
 561         }
 562         break;
 563
 564         /* LGPL'ed VGA BIOS messages */
 565     case 0x501:
 566     case 0x502:
 567         exit((val << 1) | 1);
 568     case 0x500:
 569     case 0x503:
 570 #ifdef DEBUG_BIOS
 571         fprintf(stderr, "%c", val);
 572 #endif
 573         break;
 574     }
 575 }
 576
 577 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 578 {
 579     int index = le32_to_cpu(e820_table.count);
 580     struct e820_entry *entry;
 581
 582     if (index >= E820_NR_ENTRIES)
 583         return -EBUSY;
 584     entry = &e820_table.entry[index++];
 585
 586     entry->address = cpu_to_le64(address);
 587     entry->length = cpu_to_le64(length);
 588     entry->type = cpu_to_le32(type);
 589
 590     e820_table.count = cpu_to_le32(index);
 591     return index;
 592 }
 593
 594 static void *bochs_bios_init(void)
 595 {
 596     void *fw_cfg;
 597     uint8_t *smbios_table;
 598     size_t smbios_len;
 599     uint64_t *numa_fw_cfg;
 600     int i, j;
 601
 602     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 603     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 604     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 605     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 606     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 607
 608     register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
 609     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 610     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 611     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 612     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 613
 614     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 615
 616     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 617     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 618     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 619                      acpi_tables_len);
 620     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 621
 622     smbios_table = smbios_get_table(&smbios_len);
 623     if (smbios_table)
 624         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 625                          smbios_table, smbios_len);
 626     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 627                      sizeof(struct e820_table));
 628
 629     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 630                      sizeof(struct hpet_fw_config));
 631     /* allocate memory for the NUMA channel: one (64bit) word for the number
 632      * of nodes, one word for each VCPU->node and one word for each node to
 633      * hold the amount of memory.
 634      */
 635     numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
 636     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 637     for (i = 0; i < max_cpus; i++) {
 638         for (j = 0; j < nb_numa_nodes; j++) {
 639             if (node_cpumask[j] & (1 << i)) {
 640                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 641                 break;
 642             }
 643         }
 644     }
 645     for (i = 0; i < nb_numa_nodes; i++) {
 646         numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 647     }
 648     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 649                      (1 + max_cpus + nb_numa_nodes) * 8);
 650
 651     return fw_cfg;
 652 }
 653
 654 static long get_file_size(FILE *f)
 655 {
 656     long where, size;
 657
 658     /* XXX: on Unix systems, using fstat() probably makes more sense */
 659
 660     where = ftell(f);
 661     fseek(f, 0, SEEK_END);
 662     size = ftell(f);
 663     fseek(f, where, SEEK_SET);
 664
 665     return size;
 666 }
 667
 668 static void load_linux(void *fw_cfg,
 669                        const char *kernel_filename,
 670                        const char *initrd_filename,
 671                        const char *kernel_cmdline,
 672                        target_phys_addr_t max_ram_size)
 673 {
 674     uint16_t protocol;
 675     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 676     uint32_t initrd_max;
 677     uint8_t header[8192], *setup, *kernel, *initrd_data;
 678     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 679     FILE *f;
 680     char *vmode;
 681
 682     /* Align to 16 bytes as a paranoia measure */
 683     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 684
 685     /* load the kernel header */
 686     f = fopen(kernel_filename, "rb");
 687     if (!f || !(kernel_size = get_file_size(f)) ||
 688         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 689         MIN(ARRAY_SIZE(header), kernel_size)) {
 690         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 691                 kernel_filename, strerror(errno));
 692         exit(1);
 693     }
 694
 695     /* kernel protocol version */
 696 #if 0
 697     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 698 #endif
 699     if (ldl_p(header+0x202) == 0x53726448)
 700         protocol = lduw_p(header+0x206);
 701     else {
 702         /* This looks like a multiboot kernel. If it is, let's stop
 703            treating it like a Linux kernel. */
 704         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 705                            kernel_cmdline, kernel_size, header))
 706             return;
 707         protocol = 0;
 708     }
 709
 710     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 711         /* Low kernel */
 712         real_addr    = 0x90000;
 713         cmdline_addr = 0x9a000 - cmdline_size;
 714         prot_addr    = 0x10000;
 715     } else if (protocol < 0x202) {
 716         /* High but ancient kernel */
 717         real_addr    = 0x90000;
 718         cmdline_addr = 0x9a000 - cmdline_size;
 719         prot_addr    = 0x100000;
 720     } else {
 721         /* High and recent kernel */
 722         real_addr    = 0x10000;
 723         cmdline_addr = 0x20000;
 724         prot_addr    = 0x100000;
 725     }
 726
 727 #if 0
 728     fprintf(stderr,
 729             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 730             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 731             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 732             real_addr,
 733             cmdline_addr,
 734             prot_addr);
 735 #endif
 736
 737     /* highest address for loading the initrd */
 738     if (protocol >= 0x203)
 739         initrd_max = ldl_p(header+0x22c);
 740     else
 741         initrd_max = 0x37ffffff;
 742
 743     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 744         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 745
 746     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 747     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 748     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 749                      (uint8_t*)strdup(kernel_cmdline),
 750                      strlen(kernel_cmdline)+1);
 751
 752     if (protocol >= 0x202) {
 753         stl_p(header+0x228, cmdline_addr);
 754     } else {
 755         stw_p(header+0x20, 0xA33F);
 756         stw_p(header+0x22, cmdline_addr-real_addr);
 757     }
 758
 759     /* handle vga= parameter */
 760     vmode = strstr(kernel_cmdline, "vga=");
 761     if (vmode) {
 762         unsigned int video_mode;
 763         /* skip "vga=" */
 764         vmode += 4;
 765         if (!strncmp(vmode, "normal", 6)) {
 766             video_mode = 0xffff;
 767         } else if (!strncmp(vmode, "ext", 3)) {
 768             video_mode = 0xfffe;
 769         } else if (!strncmp(vmode, "ask", 3)) {
 770             video_mode = 0xfffd;
 771         } else {
 772             video_mode = strtol(vmode, NULL, 0);
 773         }
 774         stw_p(header+0x1fa, video_mode);
 775     }
 776
 777     /* loader type */
 778     /* High nybble = B reserved for Qemu; low nybble is revision number.
 779        If this code is substantially changed, you may want to consider
 780        incrementing the revision. */
 781     if (protocol >= 0x200)
 782         header[0x210] = 0xB0;
 783
 784     /* heap */
 785     if (protocol >= 0x201) {
 786         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 787         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 788     }
 789
 790     /* load initrd */
 791     if (initrd_filename) {
 792         if (protocol < 0x200) {
 793             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 794             exit(1);
 795         }
 796
 797         initrd_size = get_image_size(initrd_filename);
 798         if (initrd_size < 0) {
 799             fprintf(stderr, "qemu: error reading initrd %s\n",
 800                     initrd_filename);
 801             exit(1);
 802         }
 803
 804         initrd_addr = (initrd_max-initrd_size) & ~4095;
 805
 806         initrd_data = g_malloc(initrd_size);
 807         load_image(initrd_filename, initrd_data);
 808
 809         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 810         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 811         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 812
 813         stl_p(header+0x218, initrd_addr);
 814         stl_p(header+0x21c, initrd_size);
 815     }
 816
 817     /* load kernel and setup */
 818     setup_size = header[0x1f1];
 819     if (setup_size == 0)
 820         setup_size = 4;
 821     setup_size = (setup_size+1)*512;
 822     kernel_size -= setup_size;
 823
 824     setup  = g_malloc(setup_size);
 825     kernel = g_malloc(kernel_size);
 826     fseek(f, 0, SEEK_SET);
 827     if (fread(setup, 1, setup_size, f) != setup_size) {
 828         fprintf(stderr, "fread() failed\n");
 829         exit(1);
 830     }
 831     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 832         fprintf(stderr, "fread() failed\n");
 833         exit(1);
 834     }
 835     fclose(f);
 836     memcpy(setup, header, MIN(sizeof(header), setup_size));
 837
 838     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 839     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 840     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 841
 842     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 843     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 844     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 845
 846     option_rom[nb_option_roms].name = "linuxboot.bin";
 847     option_rom[nb_option_roms].bootindex = 0;
 848     nb_option_roms++;
 849 }
 850
 851 #define NE2000_NB_MAX 6
 852
 853 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 854                                               0x280, 0x380 };
 855 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 856
 857 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 858 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 859
 860 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 861 {
 862     static int nb_ne2k = 0;
 863
 864     if (nb_ne2k == NE2000_NB_MAX)
 865         return;
 866     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 867                     ne2000_irq[nb_ne2k], nd);
 868     nb_ne2k++;
 869 }
 870
 871 int cpu_is_bsp(CPUState *env)
 872 {
 873     /* We hard-wire the BSP to the first CPU. */
 874     return env->cpu_index == 0;
 875 }
 876
 877 DeviceState *cpu_get_current_apic(void)
 878 {
 879     if (cpu_single_env) {
 880         return cpu_single_env->apic_state;
 881     } else {
 882         return NULL;
 883     }
 884 }
 885
 886 static DeviceState *apic_init(void *env, uint8_t apic_id)
 887 {
 888     DeviceState *dev;
 889     static int apic_mapped;
 890
 891 #ifdef UNUSED_UPSTREAM_KVM
 892     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 893         dev = qdev_create(NULL, "kvm-apic");
 894     } else
 895 #endif
 896     {
 897         dev = qdev_create(NULL, "apic");
 898     }
 899     qdev_prop_set_uint8(dev, "id", apic_id);
 900     qdev_prop_set_ptr(dev, "cpu_env", env);
 901     qdev_init_nofail(dev);
 902
 903     /* XXX: mapping more APICs at the same memory location */
 904     if (apic_mapped == 0) {
 905         /* NOTE: the APIC is directly connected to the CPU - it is not
 906            on the global memory bus. */
 907         /* XXX: what if the base changes? */
 908         sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
 909         apic_mapped = 1;
 910     }
 911
 912 #ifdef UNUSED_UPSTREAM_KVM
 913     /* KVM does not support MSI yet. */
 914     if (!kvm_enabled() || !kvm_irqchip_in_kernel()) {
 915         msi_supported = true;
 916     }
 917 #else
 918      msi_supported = true;
 919 #endif
 920
 921     return dev;
 922 }
 923
 924 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 925    BIOS will read it and start S3 resume at POST Entry */
 926 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
 927 {
 928     ISADevice *s = opaque;
 929
 930     if (level) {
 931         rtc_set_memory(s, 0xF, 0xFE);
 932     }
 933 }
 934
 935 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 936 {
 937     CPUState *s = opaque;
 938
 939     if (level) {
 940         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 941     }
 942 }
 943
 944 static void pc_cpu_reset(void *opaque)
 945 {
 946     CPUState *env = opaque;
 947
 948     cpu_reset(env);
 949     env->halted = !cpu_is_bsp(env);
 950 }
 951
 952 CPUState *pc_new_cpu(const char *cpu_model)
 953 {
 954     CPUState *env;
 955
 956     if (cpu_model == NULL) {
 957 #ifdef TARGET_X86_64
 958         cpu_model = "qemu64";
 959 #else
 960         cpu_model = "qemu32";
 961 #endif
 962     }
 963
 964     env = cpu_init(cpu_model);
 965     if (!env) {
 966         fprintf(stderr, "Unable to find x86 CPU definition\n");
 967         exit(1);
 968     }
 969     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 970         env->apic_state = apic_init(env, env->cpuid_apic_id);
 971     }
 972     qemu_register_reset(pc_cpu_reset, env);
 973     pc_cpu_reset(env);
 974     return env;
 975 }
 976
 977 void pc_cpus_init(const char *cpu_model)
 978 {
 979     int i;
 980
 981     /* init CPUs */
 982     for(i = 0; i < smp_cpus; i++) {
 983         pc_new_cpu(cpu_model);
 984     }
 985 }
 986
 987 void pc_memory_init(MemoryRegion *system_memory,
 988                     const char *kernel_filename,
 989                     const char *kernel_cmdline,
 990                     const char *initrd_filename,
 991                     ram_addr_t below_4g_mem_size,
 992                     ram_addr_t above_4g_mem_size,
 993                     MemoryRegion *rom_memory,
 994                     MemoryRegion **ram_memory)
 995 {
 996     char *filename;
 997     int ret, linux_boot, i;
 998     MemoryRegion *ram, *bios, *isa_bios, *option_rom_mr;
 999     MemoryRegion *ram_below_4g, *ram_above_4g;
1000     int bios_size, isa_bios_size;
1001     void *fw_cfg;
1002
1003     linux_boot = (kernel_filename != NULL);
1004
1005     /* Allocate RAM.  We allocate it as a single memory region and use
1006      * aliases to address portions of it, mostly for backwards compatibility
1007      * with older qemus that used qemu_ram_alloc().
1008      */
1009     ram = g_malloc(sizeof(*ram));
1010     memory_region_init_ram(ram, "pc.ram",
1011                            below_4g_mem_size + above_4g_mem_size);
1012     vmstate_register_ram_global(ram);
1013     *ram_memory = ram;
1014     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1015     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
1016                              0, below_4g_mem_size);
1017     memory_region_add_subregion(system_memory, 0, ram_below_4g);
1018     if (above_4g_mem_size > 0) {
1019         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1020         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
1021                                  below_4g_mem_size, above_4g_mem_size);
1022         memory_region_add_subregion(system_memory, 0x100000000ULL,
1023                                     ram_above_4g);
1024     }
1025
1026     /* BIOS load */
1027     if (bios_name == NULL)
1028         bios_name = BIOS_FILENAME;
1029     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1030     if (filename) {
1031         bios_size = get_image_size(filename);
1032     } else {
1033         bios_size = -1;
1034     }
1035     if (bios_size <= 0 ||
1036         (bios_size % 65536) != 0) {
1037         goto bios_error;
1038     }
1039     bios = g_malloc(sizeof(*bios));
1040     memory_region_init_ram(bios, "pc.bios", bios_size);
1041     vmstate_register_ram_global(bios);
1042     memory_region_set_readonly(bios, true);
1043     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
1044     if (ret != 0) {
1045     bios_error:
1046         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1047         exit(1);
1048     }
1049     if (filename) {
1050         g_free(filename);
1051     }
1052     /* map the last 128KB of the BIOS in ISA space */
1053     isa_bios_size = bios_size;
1054     if (isa_bios_size > (128 * 1024))
1055         isa_bios_size = 128 * 1024;
1056     isa_bios = g_malloc(sizeof(*isa_bios));
1057     memory_region_init_alias(isa_bios, "isa-bios", bios,
1058                              bios_size - isa_bios_size, isa_bios_size);
1059     memory_region_add_subregion_overlap(rom_memory,
1060                                         0x100000 - isa_bios_size,
1061                                         isa_bios,
1062                                         1);
1063     memory_region_set_readonly(isa_bios, true);
1064
1065     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1066     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
1067     vmstate_register_ram_global(option_rom_mr);
1068     memory_region_add_subregion_overlap(rom_memory,
1069                                         PC_ROM_MIN_VGA,
1070                                         option_rom_mr,
1071                                         1);
1072
1073     /* map all the bios at the top of memory */
1074     memory_region_add_subregion(rom_memory,
1075                                 (uint32_t)(-bios_size),
1076                                 bios);
1077
1078     option_rom[nb_option_roms].name = g_strdup(VAPIC_FILENAME);
1079     option_rom[nb_option_roms].bootindex = -1;
1080     nb_option_roms++;
1081
1082     fw_cfg = bochs_bios_init();
1083     rom_set_fw(fw_cfg);
1084
1085     if (linux_boot) {
1086         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1087     }
1088
1089     for (i = 0; i < nb_option_roms; i++) {
1090         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1091     }
1092 }
1093
1094 qemu_irq *pc_allocate_cpu_irq(void)
1095 {
1096     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1097 }
1098
1099 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1100 {
1101     DeviceState *dev = NULL;
1102
1103     if (cirrus_vga_enabled) {
1104         if (pci_bus) {
1105             dev = pci_cirrus_vga_init(pci_bus);
1106         } else {
1107             dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev;
1108         }
1109     } else if (vmsvga_enabled) {
1110         if (pci_bus) {
1111             dev = pci_vmsvga_init(pci_bus);
1112         } else {
1113             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1114         }
1115 #ifdef CONFIG_SPICE
1116     } else if (qxl_enabled) {
1117         if (pci_bus) {
1118             dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
1119         } else {
1120             fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1121         }
1122 #endif
1123     } else if (std_vga_enabled) {
1124         if (pci_bus) {
1125             dev = pci_vga_init(pci_bus);
1126         } else {
1127             dev = isa_vga_init(isa_bus);
1128         }
1129     }
1130
1131     return dev;
1132 }
1133
1134 static void cpu_request_exit(void *opaque, int irq, int level)
1135 {
1136     CPUState *env = cpu_single_env;
1137
1138     if (env && level) {
1139         cpu_exit(env);
1140     }
1141 }
1142
1143 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1144                           ISADevice **rtc_state,
1145                           ISADevice **floppy,
1146                           bool no_vmport)
1147 {
1148     int i;
1149     DriveInfo *fd[MAX_FD];
1150     qemu_irq rtc_irq = NULL;
1151     qemu_irq *a20_line;
1152     ISADevice *i8042, *port92, *vmmouse, *pit;
1153     qemu_irq *cpu_exit_irq;
1154
1155     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1156
1157     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1158
1159     if (!no_hpet) {
1160         DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1161
1162         if (hpet) {
1163             for (i = 0; i < GSI_NUM_PINS; i++) {
1164                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1165             }
1166             rtc_irq = qdev_get_gpio_in(hpet, 0);
1167         }
1168     }
1169     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1170
1171     qemu_register_boot_set(pc_boot_set, *rtc_state);
1172
1173     pit = pit_init(isa_bus, 0x40, 0);
1174     pcspk_init(pit);
1175
1176     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1177         if (serial_hds[i]) {
1178             serial_isa_init(isa_bus, i, serial_hds[i]);
1179         }
1180     }
1181
1182     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1183         if (parallel_hds[i]) {
1184             parallel_init(isa_bus, i, parallel_hds[i]);
1185         }
1186     }
1187
1188     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1189     i8042 = isa_create_simple(isa_bus, "i8042");
1190     i8042_setup_a20_line(i8042, &a20_line[0]);
1191     if (!no_vmport) {
1192         vmport_init(isa_bus);
1193         vmmouse = isa_try_create(isa_bus, "vmmouse");
1194     } else {
1195         vmmouse = NULL;
1196     }
1197     if (vmmouse) {
1198         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1199         qdev_init_nofail(&vmmouse->qdev);
1200     }
1201     port92 = isa_create_simple(isa_bus, "port92");
1202     port92_init(port92, &a20_line[1]);
1203
1204     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1205     DMA_init(0, cpu_exit_irq);
1206
1207     for(i = 0; i < MAX_FD; i++) {
1208         fd[i] = drive_get(IF_FLOPPY, 0, i);
1209     }
1210     *floppy = fdctrl_init_isa(isa_bus, fd);
1211 }
1212
1213 void pc_pci_device_init(PCIBus *pci_bus)
1214 {
1215     int max_bus;
1216     int bus;
1217
1218     max_bus = drive_get_max_bus(IF_SCSI);
1219     for (bus = 0; bus <= max_bus; bus++) {
1220         pci_create_simple(pci_bus, -1, "lsi53c895a");
1221     }
1222 }