hw/musicpal.c

   1 /*
   2  * Marvell MV88W8618 / Freecom MusicPal emulation.
   3  *
   4  * Copyright (c) 2008 Jan Kiszka
   5  *
   6  * This code is licensed under the GNU GPL v2.
   7  *
   8  * Contributions after 2012-01-13 are licensed under the terms of the
   9  * GNU GPL, version 2 or (at your option) any later version.
  10  */
  11
  12 #include "sysbus.h"
  13 #include "arm-misc.h"
  14 #include "devices.h"
  15 #include "net.h"
  16 #include "sysemu.h"
  17 #include "boards.h"
  18 #include "pc.h"
  19 #include "qemu-timer.h"
  20 #include "ptimer.h"
  21 #include "block.h"
  22 #include "flash.h"
  23 #include "console.h"
  24 #include "i2c.h"
  25 #include "blockdev.h"
  26 #include "exec-memory.h"
  27
  28 #define MP_MISC_BASE            0x80002000
  29 #define MP_MISC_SIZE            0x00001000
  30
  31 #define MP_ETH_BASE             0x80008000
  32 #define MP_ETH_SIZE             0x00001000
  33
  34 #define MP_WLAN_BASE            0x8000C000
  35 #define MP_WLAN_SIZE            0x00000800
  36
  37 #define MP_UART1_BASE           0x8000C840
  38 #define MP_UART2_BASE           0x8000C940
  39
  40 #define MP_GPIO_BASE            0x8000D000
  41 #define MP_GPIO_SIZE            0x00001000
  42
  43 #define MP_FLASHCFG_BASE        0x90006000
  44 #define MP_FLASHCFG_SIZE        0x00001000
  45
  46 #define MP_AUDIO_BASE           0x90007000
  47
  48 #define MP_PIC_BASE             0x90008000
  49 #define MP_PIC_SIZE             0x00001000
  50
  51 #define MP_PIT_BASE             0x90009000
  52 #define MP_PIT_SIZE             0x00001000
  53
  54 #define MP_LCD_BASE             0x9000c000
  55 #define MP_LCD_SIZE             0x00001000
  56
  57 #define MP_SRAM_BASE            0xC0000000
  58 #define MP_SRAM_SIZE            0x00020000
  59
  60 #define MP_RAM_DEFAULT_SIZE     32*1024*1024
  61 #define MP_FLASH_SIZE_MAX       32*1024*1024
  62
  63 #define MP_TIMER1_IRQ           4
  64 #define MP_TIMER2_IRQ           5
  65 #define MP_TIMER3_IRQ           6
  66 #define MP_TIMER4_IRQ           7
  67 #define MP_EHCI_IRQ             8
  68 #define MP_ETH_IRQ              9
  69 #define MP_UART1_IRQ            11
  70 #define MP_UART2_IRQ            11
  71 #define MP_GPIO_IRQ             12
  72 #define MP_RTC_IRQ              28
  73 #define MP_AUDIO_IRQ            30
  74
  75 /* Wolfson 8750 I2C address */
  76 #define MP_WM_ADDR              0x1A
  77
  78 /* Ethernet register offsets */
  79 #define MP_ETH_SMIR             0x010
  80 #define MP_ETH_PCXR             0x408
  81 #define MP_ETH_SDCMR            0x448
  82 #define MP_ETH_ICR              0x450
  83 #define MP_ETH_IMR              0x458
  84 #define MP_ETH_FRDP0            0x480
  85 #define MP_ETH_FRDP1            0x484
  86 #define MP_ETH_FRDP2            0x488
  87 #define MP_ETH_FRDP3            0x48C
  88 #define MP_ETH_CRDP0            0x4A0
  89 #define MP_ETH_CRDP1            0x4A4
  90 #define MP_ETH_CRDP2            0x4A8
  91 #define MP_ETH_CRDP3            0x4AC
  92 #define MP_ETH_CTDP0            0x4E0
  93 #define MP_ETH_CTDP1            0x4E4
  94 #define MP_ETH_CTDP2            0x4E8
  95 #define MP_ETH_CTDP3            0x4EC
  96
  97 /* MII PHY access */
  98 #define MP_ETH_SMIR_DATA        0x0000FFFF
  99 #define MP_ETH_SMIR_ADDR        0x03FF0000
 100 #define MP_ETH_SMIR_OPCODE      (1 << 26) /* Read value */
 101 #define MP_ETH_SMIR_RDVALID     (1 << 27)
 102
 103 /* PHY registers */
 104 #define MP_ETH_PHY1_BMSR        0x00210000
 105 #define MP_ETH_PHY1_PHYSID1     0x00410000
 106 #define MP_ETH_PHY1_PHYSID2     0x00610000
 107
 108 #define MP_PHY_BMSR_LINK        0x0004
 109 #define MP_PHY_BMSR_AUTONEG     0x0008
 110
 111 #define MP_PHY_88E3015          0x01410E20
 112
 113 /* TX descriptor status */
 114 #define MP_ETH_TX_OWN           (1 << 31)
 115
 116 /* RX descriptor status */
 117 #define MP_ETH_RX_OWN           (1 << 31)
 118
 119 /* Interrupt cause/mask bits */
 120 #define MP_ETH_IRQ_RX_BIT       0
 121 #define MP_ETH_IRQ_RX           (1 << MP_ETH_IRQ_RX_BIT)
 122 #define MP_ETH_IRQ_TXHI_BIT     2
 123 #define MP_ETH_IRQ_TXLO_BIT     3
 124
 125 /* Port config bits */
 126 #define MP_ETH_PCXR_2BSM_BIT    28 /* 2-byte incoming suffix */
 127
 128 /* SDMA command bits */
 129 #define MP_ETH_CMD_TXHI         (1 << 23)
 130 #define MP_ETH_CMD_TXLO         (1 << 22)
 131
 132 typedef struct mv88w8618_tx_desc {
 133     uint32_t cmdstat;
 134     uint16_t res;
 135     uint16_t bytes;
 136     uint32_t buffer;
 137     uint32_t next;
 138 } mv88w8618_tx_desc;
 139
 140 typedef struct mv88w8618_rx_desc {
 141     uint32_t cmdstat;
 142     uint16_t bytes;
 143     uint16_t buffer_size;
 144     uint32_t buffer;
 145     uint32_t next;
 146 } mv88w8618_rx_desc;
 147
 148 typedef struct mv88w8618_eth_state {
 149     SysBusDevice busdev;
 150     MemoryRegion iomem;
 151     qemu_irq irq;
 152     uint32_t smir;
 153     uint32_t icr;
 154     uint32_t imr;
 155     int mmio_index;
 156     uint32_t vlan_header;
 157     uint32_t tx_queue[2];
 158     uint32_t rx_queue[4];
 159     uint32_t frx_queue[4];
 160     uint32_t cur_rx[4];
 161     NICState *nic;
 162     NICConf conf;
 163 } mv88w8618_eth_state;
 164
 165 static void eth_rx_desc_put(uint32_t addr, mv88w8618_rx_desc *desc)
 166 {
 167     cpu_to_le32s(&desc->cmdstat);
 168     cpu_to_le16s(&desc->bytes);
 169     cpu_to_le16s(&desc->buffer_size);
 170     cpu_to_le32s(&desc->buffer);
 171     cpu_to_le32s(&desc->next);
 172     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 173 }
 174
 175 static void eth_rx_desc_get(uint32_t addr, mv88w8618_rx_desc *desc)
 176 {
 177     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 178     le32_to_cpus(&desc->cmdstat);
 179     le16_to_cpus(&desc->bytes);
 180     le16_to_cpus(&desc->buffer_size);
 181     le32_to_cpus(&desc->buffer);
 182     le32_to_cpus(&desc->next);
 183 }
 184
 185 static int eth_can_receive(VLANClientState *nc)
 186 {
 187     return 1;
 188 }
 189
 190 static ssize_t eth_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
 191 {
 192     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 193     uint32_t desc_addr;
 194     mv88w8618_rx_desc desc;
 195     int i;
 196
 197     for (i = 0; i < 4; i++) {
 198         desc_addr = s->cur_rx[i];
 199         if (!desc_addr) {
 200             continue;
 201         }
 202         do {
 203             eth_rx_desc_get(desc_addr, &desc);
 204             if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >= size) {
 205                 cpu_physical_memory_write(desc.buffer + s->vlan_header,
 206                                           buf, size);
 207                 desc.bytes = size + s->vlan_header;
 208                 desc.cmdstat &= ~MP_ETH_RX_OWN;
 209                 s->cur_rx[i] = desc.next;
 210
 211                 s->icr |= MP_ETH_IRQ_RX;
 212                 if (s->icr & s->imr) {
 213                     qemu_irq_raise(s->irq);
 214                 }
 215                 eth_rx_desc_put(desc_addr, &desc);
 216                 return size;
 217             }
 218             desc_addr = desc.next;
 219         } while (desc_addr != s->rx_queue[i]);
 220     }
 221     return size;
 222 }
 223
 224 static void eth_tx_desc_put(uint32_t addr, mv88w8618_tx_desc *desc)
 225 {
 226     cpu_to_le32s(&desc->cmdstat);
 227     cpu_to_le16s(&desc->res);
 228     cpu_to_le16s(&desc->bytes);
 229     cpu_to_le32s(&desc->buffer);
 230     cpu_to_le32s(&desc->next);
 231     cpu_physical_memory_write(addr, (void *)desc, sizeof(*desc));
 232 }
 233
 234 static void eth_tx_desc_get(uint32_t addr, mv88w8618_tx_desc *desc)
 235 {
 236     cpu_physical_memory_read(addr, (void *)desc, sizeof(*desc));
 237     le32_to_cpus(&desc->cmdstat);
 238     le16_to_cpus(&desc->res);
 239     le16_to_cpus(&desc->bytes);
 240     le32_to_cpus(&desc->buffer);
 241     le32_to_cpus(&desc->next);
 242 }
 243
 244 static void eth_send(mv88w8618_eth_state *s, int queue_index)
 245 {
 246     uint32_t desc_addr = s->tx_queue[queue_index];
 247     mv88w8618_tx_desc desc;
 248     uint32_t next_desc;
 249     uint8_t buf[2048];
 250     int len;
 251
 252     do {
 253         eth_tx_desc_get(desc_addr, &desc);
 254         next_desc = desc.next;
 255         if (desc.cmdstat & MP_ETH_TX_OWN) {
 256             len = desc.bytes;
 257             if (len < 2048) {
 258                 cpu_physical_memory_read(desc.buffer, buf, len);
 259                 qemu_send_packet(&s->nic->nc, buf, len);
 260             }
 261             desc.cmdstat &= ~MP_ETH_TX_OWN;
 262             s->icr |= 1 << (MP_ETH_IRQ_TXLO_BIT - queue_index);
 263             eth_tx_desc_put(desc_addr, &desc);
 264         }
 265         desc_addr = next_desc;
 266     } while (desc_addr != s->tx_queue[queue_index]);
 267 }
 268
 269 static uint64_t mv88w8618_eth_read(void *opaque, target_phys_addr_t offset,
 270                                    unsigned size)
 271 {
 272     mv88w8618_eth_state *s = opaque;
 273
 274     switch (offset) {
 275     case MP_ETH_SMIR:
 276         if (s->smir & MP_ETH_SMIR_OPCODE) {
 277             switch (s->smir & MP_ETH_SMIR_ADDR) {
 278             case MP_ETH_PHY1_BMSR:
 279                 return MP_PHY_BMSR_LINK | MP_PHY_BMSR_AUTONEG |
 280                        MP_ETH_SMIR_RDVALID;
 281             case MP_ETH_PHY1_PHYSID1:
 282                 return (MP_PHY_88E3015 >> 16) | MP_ETH_SMIR_RDVALID;
 283             case MP_ETH_PHY1_PHYSID2:
 284                 return (MP_PHY_88E3015 & 0xFFFF) | MP_ETH_SMIR_RDVALID;
 285             default:
 286                 return MP_ETH_SMIR_RDVALID;
 287             }
 288         }
 289         return 0;
 290
 291     case MP_ETH_ICR:
 292         return s->icr;
 293
 294     case MP_ETH_IMR:
 295         return s->imr;
 296
 297     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 298         return s->frx_queue[(offset - MP_ETH_FRDP0)/4];
 299
 300     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 301         return s->rx_queue[(offset - MP_ETH_CRDP0)/4];
 302
 303     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 304         return s->tx_queue[(offset - MP_ETH_CTDP0)/4];
 305
 306     default:
 307         return 0;
 308     }
 309 }
 310
 311 static void mv88w8618_eth_write(void *opaque, target_phys_addr_t offset,
 312                                 uint64_t value, unsigned size)
 313 {
 314     mv88w8618_eth_state *s = opaque;
 315
 316     switch (offset) {
 317     case MP_ETH_SMIR:
 318         s->smir = value;
 319         break;
 320
 321     case MP_ETH_PCXR:
 322         s->vlan_header = ((value >> MP_ETH_PCXR_2BSM_BIT) & 1) * 2;
 323         break;
 324
 325     case MP_ETH_SDCMR:
 326         if (value & MP_ETH_CMD_TXHI) {
 327             eth_send(s, 1);
 328         }
 329         if (value & MP_ETH_CMD_TXLO) {
 330             eth_send(s, 0);
 331         }
 332         if (value & (MP_ETH_CMD_TXHI | MP_ETH_CMD_TXLO) && s->icr & s->imr) {
 333             qemu_irq_raise(s->irq);
 334         }
 335         break;
 336
 337     case MP_ETH_ICR:
 338         s->icr &= value;
 339         break;
 340
 341     case MP_ETH_IMR:
 342         s->imr = value;
 343         if (s->icr & s->imr) {
 344             qemu_irq_raise(s->irq);
 345         }
 346         break;
 347
 348     case MP_ETH_FRDP0 ... MP_ETH_FRDP3:
 349         s->frx_queue[(offset - MP_ETH_FRDP0)/4] = value;
 350         break;
 351
 352     case MP_ETH_CRDP0 ... MP_ETH_CRDP3:
 353         s->rx_queue[(offset - MP_ETH_CRDP0)/4] =
 354             s->cur_rx[(offset - MP_ETH_CRDP0)/4] = value;
 355         break;
 356
 357     case MP_ETH_CTDP0 ... MP_ETH_CTDP3:
 358         s->tx_queue[(offset - MP_ETH_CTDP0)/4] = value;
 359         break;
 360     }
 361 }
 362
 363 static const MemoryRegionOps mv88w8618_eth_ops = {
 364     .read = mv88w8618_eth_read,
 365     .write = mv88w8618_eth_write,
 366     .endianness = DEVICE_NATIVE_ENDIAN,
 367 };
 368
 369 static void eth_cleanup(VLANClientState *nc)
 370 {
 371     mv88w8618_eth_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 372
 373     s->nic = NULL;
 374 }
 375
 376 static NetClientInfo net_mv88w8618_info = {
 377     .type = NET_CLIENT_TYPE_NIC,
 378     .size = sizeof(NICState),
 379     .can_receive = eth_can_receive,
 380     .receive = eth_receive,
 381     .cleanup = eth_cleanup,
 382 };
 383
 384 static int mv88w8618_eth_init(SysBusDevice *dev)
 385 {
 386     mv88w8618_eth_state *s = FROM_SYSBUS(mv88w8618_eth_state, dev);
 387
 388     sysbus_init_irq(dev, &s->irq);
 389     s->nic = qemu_new_nic(&net_mv88w8618_info, &s->conf,
 390                           object_get_typename(OBJECT(dev)), dev->qdev.id, s);
 391     memory_region_init_io(&s->iomem, &mv88w8618_eth_ops, s, "mv88w8618-eth",
 392                           MP_ETH_SIZE);
 393     sysbus_init_mmio(dev, &s->iomem);
 394     return 0;
 395 }
 396
 397 static const VMStateDescription mv88w8618_eth_vmsd = {
 398     .name = "mv88w8618_eth",
 399     .version_id = 1,
 400     .minimum_version_id = 1,
 401     .minimum_version_id_old = 1,
 402     .fields = (VMStateField[]) {
 403         VMSTATE_UINT32(smir, mv88w8618_eth_state),
 404         VMSTATE_UINT32(icr, mv88w8618_eth_state),
 405         VMSTATE_UINT32(imr, mv88w8618_eth_state),
 406         VMSTATE_UINT32(vlan_header, mv88w8618_eth_state),
 407         VMSTATE_UINT32_ARRAY(tx_queue, mv88w8618_eth_state, 2),
 408         VMSTATE_UINT32_ARRAY(rx_queue, mv88w8618_eth_state, 4),
 409         VMSTATE_UINT32_ARRAY(frx_queue, mv88w8618_eth_state, 4),
 410         VMSTATE_UINT32_ARRAY(cur_rx, mv88w8618_eth_state, 4),
 411         VMSTATE_END_OF_LIST()
 412     }
 413 };
 414
 415 static Property mv88w8618_eth_properties[] = {
 416     DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf),
 417     DEFINE_PROP_END_OF_LIST(),
 418 };
 419
 420 static void mv88w8618_eth_class_init(ObjectClass *klass, void *data)
 421 {
 422     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 423
 424     k->init = mv88w8618_eth_init;
 425 }
 426
 427 static DeviceInfo mv88w8618_eth_info = {
 428     .name = "mv88w8618_eth",
 429     .size = sizeof(mv88w8618_eth_state),
 430     .vmsd = &mv88w8618_eth_vmsd,
 431     .props = mv88w8618_eth_properties,
 432     .class_init = mv88w8618_eth_class_init,
 433 };
 434
 435 /* LCD register offsets */
 436 #define MP_LCD_IRQCTRL          0x180
 437 #define MP_LCD_IRQSTAT          0x184
 438 #define MP_LCD_SPICTRL          0x1ac
 439 #define MP_LCD_INST             0x1bc
 440 #define MP_LCD_DATA             0x1c0
 441
 442 /* Mode magics */
 443 #define MP_LCD_SPI_DATA         0x00100011
 444 #define MP_LCD_SPI_CMD          0x00104011
 445 #define MP_LCD_SPI_INVALID      0x00000000
 446
 447 /* Commmands */
 448 #define MP_LCD_INST_SETPAGE0    0xB0
 449 /* ... */
 450 #define MP_LCD_INST_SETPAGE7    0xB7
 451
 452 #define MP_LCD_TEXTCOLOR        0xe0e0ff /* RRGGBB */
 453
 454 typedef struct musicpal_lcd_state {
 455     SysBusDevice busdev;
 456     MemoryRegion iomem;
 457     uint32_t brightness;
 458     uint32_t mode;
 459     uint32_t irqctrl;
 460     uint32_t page;
 461     uint32_t page_off;
 462     DisplayState *ds;
 463     uint8_t video_ram[128*64/8];
 464 } musicpal_lcd_state;
 465
 466 static uint8_t scale_lcd_color(musicpal_lcd_state *s, uint8_t col)
 467 {
 468     switch (s->brightness) {
 469     case 7:
 470         return col;
 471     case 0:
 472         return 0;
 473     default:
 474         return (col * s->brightness) / 7;
 475     }
 476 }
 477
 478 #define SET_LCD_PIXEL(depth, type) \
 479 static inline void glue(set_lcd_pixel, depth) \
 480         (musicpal_lcd_state *s, int x, int y, type col) \
 481 { \
 482     int dx, dy; \
 483     type *pixel = &((type *) ds_get_data(s->ds))[(y * 128 * 3 + x) * 3]; \
 484 \
 485     for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
 486         for (dx = 0; dx < 3; dx++, pixel++) \
 487             *pixel = col; \
 488 }
 489 SET_LCD_PIXEL(8, uint8_t)
 490 SET_LCD_PIXEL(16, uint16_t)
 491 SET_LCD_PIXEL(32, uint32_t)
 492
 493 #include "pixel_ops.h"
 494
 495 static void lcd_refresh(void *opaque)
 496 {
 497     musicpal_lcd_state *s = opaque;
 498     int x, y, col;
 499
 500     switch (ds_get_bits_per_pixel(s->ds)) {
 501     case 0:
 502         return;
 503 #define LCD_REFRESH(depth, func) \
 504     case depth: \
 505         col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
 506                    scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
 507                    scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
 508         for (x = 0; x < 128; x++) { \
 509             for (y = 0; y < 64; y++) { \
 510                 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
 511                     glue(set_lcd_pixel, depth)(s, x, y, col); \
 512                 } else { \
 513                     glue(set_lcd_pixel, depth)(s, x, y, 0); \
 514                 } \
 515             } \
 516         } \
 517         break;
 518     LCD_REFRESH(8, rgb_to_pixel8)
 519     LCD_REFRESH(16, rgb_to_pixel16)
 520     LCD_REFRESH(32, (is_surface_bgr(s->ds->surface) ?
 521                      rgb_to_pixel32bgr : rgb_to_pixel32))
 522     default:
 523         hw_error("unsupported colour depth %i\n",
 524                   ds_get_bits_per_pixel(s->ds));
 525     }
 526
 527     dpy_update(s->ds, 0, 0, 128*3, 64*3);
 528 }
 529
 530 static void lcd_invalidate(void *opaque)
 531 {
 532 }
 533
 534 static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
 535 {
 536     musicpal_lcd_state *s = opaque;
 537     s->brightness &= ~(1 << irq);
 538     s->brightness |= level << irq;
 539 }
 540
 541 static uint64_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset,
 542                                   unsigned size)
 543 {
 544     musicpal_lcd_state *s = opaque;
 545
 546     switch (offset) {
 547     case MP_LCD_IRQCTRL:
 548         return s->irqctrl;
 549
 550     default:
 551         return 0;
 552     }
 553 }
 554
 555 static void musicpal_lcd_write(void *opaque, target_phys_addr_t offset,
 556                                uint64_t value, unsigned size)
 557 {
 558     musicpal_lcd_state *s = opaque;
 559
 560     switch (offset) {
 561     case MP_LCD_IRQCTRL:
 562         s->irqctrl = value;
 563         break;
 564
 565     case MP_LCD_SPICTRL:
 566         if (value == MP_LCD_SPI_DATA || value == MP_LCD_SPI_CMD) {
 567             s->mode = value;
 568         } else {
 569             s->mode = MP_LCD_SPI_INVALID;
 570         }
 571         break;
 572
 573     case MP_LCD_INST:
 574         if (value >= MP_LCD_INST_SETPAGE0 && value <= MP_LCD_INST_SETPAGE7) {
 575             s->page = value - MP_LCD_INST_SETPAGE0;
 576             s->page_off = 0;
 577         }
 578         break;
 579
 580     case MP_LCD_DATA:
 581         if (s->mode == MP_LCD_SPI_CMD) {
 582             if (value >= MP_LCD_INST_SETPAGE0 &&
 583                 value <= MP_LCD_INST_SETPAGE7) {
 584                 s->page = value - MP_LCD_INST_SETPAGE0;
 585                 s->page_off = 0;
 586             }
 587         } else if (s->mode == MP_LCD_SPI_DATA) {
 588             s->video_ram[s->page*128 + s->page_off] = value;
 589             s->page_off = (s->page_off + 1) & 127;
 590         }
 591         break;
 592     }
 593 }
 594
 595 static const MemoryRegionOps musicpal_lcd_ops = {
 596     .read = musicpal_lcd_read,
 597     .write = musicpal_lcd_write,
 598     .endianness = DEVICE_NATIVE_ENDIAN,
 599 };
 600
 601 static int musicpal_lcd_init(SysBusDevice *dev)
 602 {
 603     musicpal_lcd_state *s = FROM_SYSBUS(musicpal_lcd_state, dev);
 604
 605     s->brightness = 7;
 606
 607     memory_region_init_io(&s->iomem, &musicpal_lcd_ops, s,
 608                           "musicpal-lcd", MP_LCD_SIZE);
 609     sysbus_init_mmio(dev, &s->iomem);
 610
 611     s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
 612                                  NULL, NULL, s);
 613     qemu_console_resize(s->ds, 128*3, 64*3);
 614
 615     qdev_init_gpio_in(&dev->qdev, musicpal_lcd_gpio_brigthness_in, 3);
 616
 617     return 0;
 618 }
 619
 620 static const VMStateDescription musicpal_lcd_vmsd = {
 621     .name = "musicpal_lcd",
 622     .version_id = 1,
 623     .minimum_version_id = 1,
 624     .minimum_version_id_old = 1,
 625     .fields = (VMStateField[]) {
 626         VMSTATE_UINT32(brightness, musicpal_lcd_state),
 627         VMSTATE_UINT32(mode, musicpal_lcd_state),
 628         VMSTATE_UINT32(irqctrl, musicpal_lcd_state),
 629         VMSTATE_UINT32(page, musicpal_lcd_state),
 630         VMSTATE_UINT32(page_off, musicpal_lcd_state),
 631         VMSTATE_BUFFER(video_ram, musicpal_lcd_state),
 632         VMSTATE_END_OF_LIST()
 633     }
 634 };
 635
 636 static void musicpal_lcd_class_init(ObjectClass *klass, void *data)
 637 {
 638     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 639
 640     k->init = musicpal_lcd_init;
 641 }
 642
 643 static DeviceInfo musicpal_lcd_info = {
 644     .name = "musicpal_lcd",
 645     .size = sizeof(musicpal_lcd_state),
 646     .vmsd = &musicpal_lcd_vmsd,
 647     .class_init = musicpal_lcd_class_init,
 648 };
 649
 650 /* PIC register offsets */
 651 #define MP_PIC_STATUS           0x00
 652 #define MP_PIC_ENABLE_SET       0x08
 653 #define MP_PIC_ENABLE_CLR       0x0C
 654
 655 typedef struct mv88w8618_pic_state
 656 {
 657     SysBusDevice busdev;
 658     MemoryRegion iomem;
 659     uint32_t level;
 660     uint32_t enabled;
 661     qemu_irq parent_irq;
 662 } mv88w8618_pic_state;
 663
 664 static void mv88w8618_pic_update(mv88w8618_pic_state *s)
 665 {
 666     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 667 }
 668
 669 static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
 670 {
 671     mv88w8618_pic_state *s = opaque;
 672
 673     if (level) {
 674         s->level |= 1 << irq;
 675     } else {
 676         s->level &= ~(1 << irq);
 677     }
 678     mv88w8618_pic_update(s);
 679 }
 680
 681 static uint64_t mv88w8618_pic_read(void *opaque, target_phys_addr_t offset,
 682                                    unsigned size)
 683 {
 684     mv88w8618_pic_state *s = opaque;
 685
 686     switch (offset) {
 687     case MP_PIC_STATUS:
 688         return s->level & s->enabled;
 689
 690     default:
 691         return 0;
 692     }
 693 }
 694
 695 static void mv88w8618_pic_write(void *opaque, target_phys_addr_t offset,
 696                                 uint64_t value, unsigned size)
 697 {
 698     mv88w8618_pic_state *s = opaque;
 699
 700     switch (offset) {
 701     case MP_PIC_ENABLE_SET:
 702         s->enabled |= value;
 703         break;
 704
 705     case MP_PIC_ENABLE_CLR:
 706         s->enabled &= ~value;
 707         s->level &= ~value;
 708         break;
 709     }
 710     mv88w8618_pic_update(s);
 711 }
 712
 713 static void mv88w8618_pic_reset(DeviceState *d)
 714 {
 715     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state,
 716                                          sysbus_from_qdev(d));
 717
 718     s->level = 0;
 719     s->enabled = 0;
 720 }
 721
 722 static const MemoryRegionOps mv88w8618_pic_ops = {
 723     .read = mv88w8618_pic_read,
 724     .write = mv88w8618_pic_write,
 725     .endianness = DEVICE_NATIVE_ENDIAN,
 726 };
 727
 728 static int mv88w8618_pic_init(SysBusDevice *dev)
 729 {
 730     mv88w8618_pic_state *s = FROM_SYSBUS(mv88w8618_pic_state, dev);
 731
 732     qdev_init_gpio_in(&dev->qdev, mv88w8618_pic_set_irq, 32);
 733     sysbus_init_irq(dev, &s->parent_irq);
 734     memory_region_init_io(&s->iomem, &mv88w8618_pic_ops, s,
 735                           "musicpal-pic", MP_PIC_SIZE);
 736     sysbus_init_mmio(dev, &s->iomem);
 737     return 0;
 738 }
 739
 740 static const VMStateDescription mv88w8618_pic_vmsd = {
 741     .name = "mv88w8618_pic",
 742     .version_id = 1,
 743     .minimum_version_id = 1,
 744     .minimum_version_id_old = 1,
 745     .fields = (VMStateField[]) {
 746         VMSTATE_UINT32(level, mv88w8618_pic_state),
 747         VMSTATE_UINT32(enabled, mv88w8618_pic_state),
 748         VMSTATE_END_OF_LIST()
 749     }
 750 };
 751
 752 static void mv88w8618_pic_class_init(ObjectClass *klass, void *data)
 753 {
 754     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 755
 756     k->init = mv88w8618_pic_init;
 757 }
 758
 759 static DeviceInfo mv88w8618_pic_info = {
 760     .name = "mv88w8618_pic",
 761     .size = sizeof(mv88w8618_pic_state),
 762     .reset = mv88w8618_pic_reset,
 763     .vmsd = &mv88w8618_pic_vmsd,
 764     .class_init = mv88w8618_pic_class_init,
 765 };
 766
 767 /* PIT register offsets */
 768 #define MP_PIT_TIMER1_LENGTH    0x00
 769 /* ... */
 770 #define MP_PIT_TIMER4_LENGTH    0x0C
 771 #define MP_PIT_CONTROL          0x10
 772 #define MP_PIT_TIMER1_VALUE     0x14
 773 /* ... */
 774 #define MP_PIT_TIMER4_VALUE     0x20
 775 #define MP_BOARD_RESET          0x34
 776
 777 /* Magic board reset value (probably some watchdog behind it) */
 778 #define MP_BOARD_RESET_MAGIC    0x10000
 779
 780 typedef struct mv88w8618_timer_state {
 781     ptimer_state *ptimer;
 782     uint32_t limit;
 783     int freq;
 784     qemu_irq irq;
 785 } mv88w8618_timer_state;
 786
 787 typedef struct mv88w8618_pit_state {
 788     SysBusDevice busdev;
 789     MemoryRegion iomem;
 790     mv88w8618_timer_state timer[4];
 791 } mv88w8618_pit_state;
 792
 793 static void mv88w8618_timer_tick(void *opaque)
 794 {
 795     mv88w8618_timer_state *s = opaque;
 796
 797     qemu_irq_raise(s->irq);
 798 }
 799
 800 static void mv88w8618_timer_init(SysBusDevice *dev, mv88w8618_timer_state *s,
 801                                  uint32_t freq)
 802 {
 803     QEMUBH *bh;
 804
 805     sysbus_init_irq(dev, &s->irq);
 806     s->freq = freq;
 807
 808     bh = qemu_bh_new(mv88w8618_timer_tick, s);
 809     s->ptimer = ptimer_init(bh);
 810 }
 811
 812 static uint64_t mv88w8618_pit_read(void *opaque, target_phys_addr_t offset,
 813                                    unsigned size)
 814 {
 815     mv88w8618_pit_state *s = opaque;
 816     mv88w8618_timer_state *t;
 817
 818     switch (offset) {
 819     case MP_PIT_TIMER1_VALUE ... MP_PIT_TIMER4_VALUE:
 820         t = &s->timer[(offset-MP_PIT_TIMER1_VALUE) >> 2];
 821         return ptimer_get_count(t->ptimer);
 822
 823     default:
 824         return 0;
 825     }
 826 }
 827
 828 static void mv88w8618_pit_write(void *opaque, target_phys_addr_t offset,
 829                                 uint64_t value, unsigned size)
 830 {
 831     mv88w8618_pit_state *s = opaque;
 832     mv88w8618_timer_state *t;
 833     int i;
 834
 835     switch (offset) {
 836     case MP_PIT_TIMER1_LENGTH ... MP_PIT_TIMER4_LENGTH:
 837         t = &s->timer[offset >> 2];
 838         t->limit = value;
 839         if (t->limit > 0) {
 840             ptimer_set_limit(t->ptimer, t->limit, 1);
 841         } else {
 842             ptimer_stop(t->ptimer);
 843         }
 844         break;
 845
 846     case MP_PIT_CONTROL:
 847         for (i = 0; i < 4; i++) {
 848             t = &s->timer[i];
 849             if (value & 0xf && t->limit > 0) {
 850                 ptimer_set_limit(t->ptimer, t->limit, 0);
 851                 ptimer_set_freq(t->ptimer, t->freq);
 852                 ptimer_run(t->ptimer, 0);
 853             } else {
 854                 ptimer_stop(t->ptimer);
 855             }
 856             value >>= 4;
 857         }
 858         break;
 859
 860     case MP_BOARD_RESET:
 861         if (value == MP_BOARD_RESET_MAGIC) {
 862             qemu_system_reset_request();
 863         }
 864         break;
 865     }
 866 }
 867
 868 static void mv88w8618_pit_reset(DeviceState *d)
 869 {
 870     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state,
 871                                          sysbus_from_qdev(d));
 872     int i;
 873
 874     for (i = 0; i < 4; i++) {
 875         ptimer_stop(s->timer[i].ptimer);
 876         s->timer[i].limit = 0;
 877     }
 878 }
 879
 880 static const MemoryRegionOps mv88w8618_pit_ops = {
 881     .read = mv88w8618_pit_read,
 882     .write = mv88w8618_pit_write,
 883     .endianness = DEVICE_NATIVE_ENDIAN,
 884 };
 885
 886 static int mv88w8618_pit_init(SysBusDevice *dev)
 887 {
 888     mv88w8618_pit_state *s = FROM_SYSBUS(mv88w8618_pit_state, dev);
 889     int i;
 890
 891     /* Letting them all run at 1 MHz is likely just a pragmatic
 892      * simplification. */
 893     for (i = 0; i < 4; i++) {
 894         mv88w8618_timer_init(dev, &s->timer[i], 1000000);
 895     }
 896
 897     memory_region_init_io(&s->iomem, &mv88w8618_pit_ops, s,
 898                           "musicpal-pit", MP_PIT_SIZE);
 899     sysbus_init_mmio(dev, &s->iomem);
 900     return 0;
 901 }
 902
 903 static const VMStateDescription mv88w8618_timer_vmsd = {
 904     .name = "timer",
 905     .version_id = 1,
 906     .minimum_version_id = 1,
 907     .minimum_version_id_old = 1,
 908     .fields = (VMStateField[]) {
 909         VMSTATE_PTIMER(ptimer, mv88w8618_timer_state),
 910         VMSTATE_UINT32(limit, mv88w8618_timer_state),
 911         VMSTATE_END_OF_LIST()
 912     }
 913 };
 914
 915 static const VMStateDescription mv88w8618_pit_vmsd = {
 916     .name = "mv88w8618_pit",
 917     .version_id = 1,
 918     .minimum_version_id = 1,
 919     .minimum_version_id_old = 1,
 920     .fields = (VMStateField[]) {
 921         VMSTATE_STRUCT_ARRAY(timer, mv88w8618_pit_state, 4, 1,
 922                              mv88w8618_timer_vmsd, mv88w8618_timer_state),
 923         VMSTATE_END_OF_LIST()
 924     }
 925 };
 926
 927 static void mv88w8618_pit_class_init(ObjectClass *klass, void *data)
 928 {
 929     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 930
 931     k->init = mv88w8618_pit_init;
 932 }
 933
 934 static DeviceInfo mv88w8618_pit_info = {
 935     .name = "mv88w8618_pit",
 936     .size = sizeof(mv88w8618_pit_state),
 937     .reset = mv88w8618_pit_reset,
 938     .vmsd = &mv88w8618_pit_vmsd,
 939     .class_init = mv88w8618_pit_class_init,
 940 };
 941
 942 /* Flash config register offsets */
 943 #define MP_FLASHCFG_CFGR0    0x04
 944
 945 typedef struct mv88w8618_flashcfg_state {
 946     SysBusDevice busdev;
 947     MemoryRegion iomem;
 948     uint32_t cfgr0;
 949 } mv88w8618_flashcfg_state;
 950
 951 static uint64_t mv88w8618_flashcfg_read(void *opaque,
 952                                         target_phys_addr_t offset,
 953                                         unsigned size)
 954 {
 955     mv88w8618_flashcfg_state *s = opaque;
 956
 957     switch (offset) {
 958     case MP_FLASHCFG_CFGR0:
 959         return s->cfgr0;
 960
 961     default:
 962         return 0;
 963     }
 964 }
 965
 966 static void mv88w8618_flashcfg_write(void *opaque, target_phys_addr_t offset,
 967                                      uint64_t value, unsigned size)
 968 {
 969     mv88w8618_flashcfg_state *s = opaque;
 970
 971     switch (offset) {
 972     case MP_FLASHCFG_CFGR0:
 973         s->cfgr0 = value;
 974         break;
 975     }
 976 }
 977
 978 static const MemoryRegionOps mv88w8618_flashcfg_ops = {
 979     .read = mv88w8618_flashcfg_read,
 980     .write = mv88w8618_flashcfg_write,
 981     .endianness = DEVICE_NATIVE_ENDIAN,
 982 };
 983
 984 static int mv88w8618_flashcfg_init(SysBusDevice *dev)
 985 {
 986     mv88w8618_flashcfg_state *s = FROM_SYSBUS(mv88w8618_flashcfg_state, dev);
 987
 988     s->cfgr0 = 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
 989     memory_region_init_io(&s->iomem, &mv88w8618_flashcfg_ops, s,
 990                           "musicpal-flashcfg", MP_FLASHCFG_SIZE);
 991     sysbus_init_mmio(dev, &s->iomem);
 992     return 0;
 993 }
 994
 995 static const VMStateDescription mv88w8618_flashcfg_vmsd = {
 996     .name = "mv88w8618_flashcfg",
 997     .version_id = 1,
 998     .minimum_version_id = 1,
 999     .minimum_version_id_old = 1,
1000     .fields = (VMStateField[]) {
1001         VMSTATE_UINT32(cfgr0, mv88w8618_flashcfg_state),
1002         VMSTATE_END_OF_LIST()
1003     }
1004 };
1005
1006 static void mv88w8618_flashcfg_class_init(ObjectClass *klass, void *data)
1007 {
1008     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1009
1010     k->init = mv88w8618_flashcfg_init;
1011 }
1012
1013 static DeviceInfo mv88w8618_flashcfg_info = {
1014     .name = "mv88w8618_flashcfg",
1015     .size = sizeof(mv88w8618_flashcfg_state),
1016     .vmsd = &mv88w8618_flashcfg_vmsd,
1017     .class_init = mv88w8618_flashcfg_class_init,
1018 };
1019
1020 /* Misc register offsets */
1021 #define MP_MISC_BOARD_REVISION  0x18
1022
1023 #define MP_BOARD_REVISION       0x31
1024
1025 static uint64_t musicpal_misc_read(void *opaque, target_phys_addr_t offset,
1026                                    unsigned size)
1027 {
1028     switch (offset) {
1029     case MP_MISC_BOARD_REVISION:
1030         return MP_BOARD_REVISION;
1031
1032     default:
1033         return 0;
1034     }
1035 }
1036
1037 static void musicpal_misc_write(void *opaque, target_phys_addr_t offset,
1038                                 uint64_t value, unsigned size)
1039 {
1040 }
1041
1042 static const MemoryRegionOps musicpal_misc_ops = {
1043     .read = musicpal_misc_read,
1044     .write = musicpal_misc_write,
1045     .endianness = DEVICE_NATIVE_ENDIAN,
1046 };
1047
1048 static void musicpal_misc_init(SysBusDevice *dev)
1049 {
1050     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1051
1052     memory_region_init_io(iomem, &musicpal_misc_ops, NULL,
1053                           "musicpal-misc", MP_MISC_SIZE);
1054     sysbus_add_memory(dev, MP_MISC_BASE, iomem);
1055 }
1056
1057 /* WLAN register offsets */
1058 #define MP_WLAN_MAGIC1          0x11c
1059 #define MP_WLAN_MAGIC2          0x124
1060
1061 static uint64_t mv88w8618_wlan_read(void *opaque, target_phys_addr_t offset,
1062                                     unsigned size)
1063 {
1064     switch (offset) {
1065     /* Workaround to allow loading the binary-only wlandrv.ko crap
1066      * from the original Freecom firmware. */
1067     case MP_WLAN_MAGIC1:
1068         return ~3;
1069     case MP_WLAN_MAGIC2:
1070         return -1;
1071
1072     default:
1073         return 0;
1074     }
1075 }
1076
1077 static void mv88w8618_wlan_write(void *opaque, target_phys_addr_t offset,
1078                                  uint64_t value, unsigned size)
1079 {
1080 }
1081
1082 static const MemoryRegionOps mv88w8618_wlan_ops = {
1083     .read = mv88w8618_wlan_read,
1084     .write =mv88w8618_wlan_write,
1085     .endianness = DEVICE_NATIVE_ENDIAN,
1086 };
1087
1088 static int mv88w8618_wlan_init(SysBusDevice *dev)
1089 {
1090     MemoryRegion *iomem = g_new(MemoryRegion, 1);
1091
1092     memory_region_init_io(iomem, &mv88w8618_wlan_ops, NULL,
1093                           "musicpal-wlan", MP_WLAN_SIZE);
1094     sysbus_init_mmio(dev, iomem);
1095     return 0;
1096 }
1097
1098 /* GPIO register offsets */
1099 #define MP_GPIO_OE_LO           0x008
1100 #define MP_GPIO_OUT_LO          0x00c
1101 #define MP_GPIO_IN_LO           0x010
1102 #define MP_GPIO_IER_LO          0x014
1103 #define MP_GPIO_IMR_LO          0x018
1104 #define MP_GPIO_ISR_LO          0x020
1105 #define MP_GPIO_OE_HI           0x508
1106 #define MP_GPIO_OUT_HI          0x50c
1107 #define MP_GPIO_IN_HI           0x510
1108 #define MP_GPIO_IER_HI          0x514
1109 #define MP_GPIO_IMR_HI          0x518
1110 #define MP_GPIO_ISR_HI          0x520
1111
1112 /* GPIO bits & masks */
1113 #define MP_GPIO_LCD_BRIGHTNESS  0x00070000
1114 #define MP_GPIO_I2C_DATA_BIT    29
1115 #define MP_GPIO_I2C_CLOCK_BIT   30
1116
1117 /* LCD brightness bits in GPIO_OE_HI */
1118 #define MP_OE_LCD_BRIGHTNESS    0x0007
1119
1120 typedef struct musicpal_gpio_state {
1121     SysBusDevice busdev;
1122     MemoryRegion iomem;
1123     uint32_t lcd_brightness;
1124     uint32_t out_state;
1125     uint32_t in_state;
1126     uint32_t ier;
1127     uint32_t imr;
1128     uint32_t isr;
1129     qemu_irq irq;
1130     qemu_irq out[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1131 } musicpal_gpio_state;
1132
1133 static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
1134     int i;
1135     uint32_t brightness;
1136
1137     /* compute brightness ratio */
1138     switch (s->lcd_brightness) {
1139     case 0x00000007:
1140         brightness = 0;
1141         break;
1142
1143     case 0x00020000:
1144         brightness = 1;
1145         break;
1146
1147     case 0x00020001:
1148         brightness = 2;
1149         break;
1150
1151     case 0x00040000:
1152         brightness = 3;
1153         break;
1154
1155     case 0x00010006:
1156         brightness = 4;
1157         break;
1158
1159     case 0x00020005:
1160         brightness = 5;
1161         break;
1162
1163     case 0x00040003:
1164         brightness = 6;
1165         break;
1166
1167     case 0x00030004:
1168     default:
1169         brightness = 7;
1170     }
1171
1172     /* set lcd brightness GPIOs  */
1173     for (i = 0; i <= 2; i++) {
1174         qemu_set_irq(s->out[i], (brightness >> i) & 1);
1175     }
1176 }
1177
1178 static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
1179 {
1180     musicpal_gpio_state *s = opaque;
1181     uint32_t mask = 1 << pin;
1182     uint32_t delta = level << pin;
1183     uint32_t old = s->in_state & mask;
1184
1185     s->in_state &= ~mask;
1186     s->in_state |= delta;
1187
1188     if ((old ^ delta) &&
1189         ((level && (s->imr & mask)) || (!level && (s->ier & mask)))) {
1190         s->isr = mask;
1191         qemu_irq_raise(s->irq);
1192     }
1193 }
1194
1195 static uint64_t musicpal_gpio_read(void *opaque, target_phys_addr_t offset,
1196                                    unsigned size)
1197 {
1198     musicpal_gpio_state *s = opaque;
1199
1200     switch (offset) {
1201     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1202         return s->lcd_brightness & MP_OE_LCD_BRIGHTNESS;
1203
1204     case MP_GPIO_OUT_LO:
1205         return s->out_state & 0xFFFF;
1206     case MP_GPIO_OUT_HI:
1207         return s->out_state >> 16;
1208
1209     case MP_GPIO_IN_LO:
1210         return s->in_state & 0xFFFF;
1211     case MP_GPIO_IN_HI:
1212         return s->in_state >> 16;
1213
1214     case MP_GPIO_IER_LO:
1215         return s->ier & 0xFFFF;
1216     case MP_GPIO_IER_HI:
1217         return s->ier >> 16;
1218
1219     case MP_GPIO_IMR_LO:
1220         return s->imr & 0xFFFF;
1221     case MP_GPIO_IMR_HI:
1222         return s->imr >> 16;
1223
1224     case MP_GPIO_ISR_LO:
1225         return s->isr & 0xFFFF;
1226     case MP_GPIO_ISR_HI:
1227         return s->isr >> 16;
1228
1229     default:
1230         return 0;
1231     }
1232 }
1233
1234 static void musicpal_gpio_write(void *opaque, target_phys_addr_t offset,
1235                                 uint64_t value, unsigned size)
1236 {
1237     musicpal_gpio_state *s = opaque;
1238     switch (offset) {
1239     case MP_GPIO_OE_HI: /* used for LCD brightness control */
1240         s->lcd_brightness = (s->lcd_brightness & MP_GPIO_LCD_BRIGHTNESS) |
1241                          (value & MP_OE_LCD_BRIGHTNESS);
1242         musicpal_gpio_brightness_update(s);
1243         break;
1244
1245     case MP_GPIO_OUT_LO:
1246         s->out_state = (s->out_state & 0xFFFF0000) | (value & 0xFFFF);
1247         break;
1248     case MP_GPIO_OUT_HI:
1249         s->out_state = (s->out_state & 0xFFFF) | (value << 16);
1250         s->lcd_brightness = (s->lcd_brightness & 0xFFFF) |
1251                             (s->out_state & MP_GPIO_LCD_BRIGHTNESS);
1252         musicpal_gpio_brightness_update(s);
1253         qemu_set_irq(s->out[3], (s->out_state >> MP_GPIO_I2C_DATA_BIT) & 1);
1254         qemu_set_irq(s->out[4], (s->out_state >> MP_GPIO_I2C_CLOCK_BIT) & 1);
1255         break;
1256
1257     case MP_GPIO_IER_LO:
1258         s->ier = (s->ier & 0xFFFF0000) | (value & 0xFFFF);
1259         break;
1260     case MP_GPIO_IER_HI:
1261         s->ier = (s->ier & 0xFFFF) | (value << 16);
1262         break;
1263
1264     case MP_GPIO_IMR_LO:
1265         s->imr = (s->imr & 0xFFFF0000) | (value & 0xFFFF);
1266         break;
1267     case MP_GPIO_IMR_HI:
1268         s->imr = (s->imr & 0xFFFF) | (value << 16);
1269         break;
1270     }
1271 }
1272
1273 static const MemoryRegionOps musicpal_gpio_ops = {
1274     .read = musicpal_gpio_read,
1275     .write = musicpal_gpio_write,
1276     .endianness = DEVICE_NATIVE_ENDIAN,
1277 };
1278
1279 static void musicpal_gpio_reset(DeviceState *d)
1280 {
1281     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state,
1282                                          sysbus_from_qdev(d));
1283
1284     s->lcd_brightness = 0;
1285     s->out_state = 0;
1286     s->in_state = 0xffffffff;
1287     s->ier = 0;
1288     s->imr = 0;
1289     s->isr = 0;
1290 }
1291
1292 static int musicpal_gpio_init(SysBusDevice *dev)
1293 {
1294     musicpal_gpio_state *s = FROM_SYSBUS(musicpal_gpio_state, dev);
1295
1296     sysbus_init_irq(dev, &s->irq);
1297
1298     memory_region_init_io(&s->iomem, &musicpal_gpio_ops, s,
1299                           "musicpal-gpio", MP_GPIO_SIZE);
1300     sysbus_init_mmio(dev, &s->iomem);
1301
1302     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1303
1304     qdev_init_gpio_in(&dev->qdev, musicpal_gpio_pin_event, 32);
1305
1306     return 0;
1307 }
1308
1309 static const VMStateDescription musicpal_gpio_vmsd = {
1310     .name = "musicpal_gpio",
1311     .version_id = 1,
1312     .minimum_version_id = 1,
1313     .minimum_version_id_old = 1,
1314     .fields = (VMStateField[]) {
1315         VMSTATE_UINT32(lcd_brightness, musicpal_gpio_state),
1316         VMSTATE_UINT32(out_state, musicpal_gpio_state),
1317         VMSTATE_UINT32(in_state, musicpal_gpio_state),
1318         VMSTATE_UINT32(ier, musicpal_gpio_state),
1319         VMSTATE_UINT32(imr, musicpal_gpio_state),
1320         VMSTATE_UINT32(isr, musicpal_gpio_state),
1321         VMSTATE_END_OF_LIST()
1322     }
1323 };
1324
1325 static void musicpal_gpio_class_init(ObjectClass *klass, void *data)
1326 {
1327     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1328
1329     k->init = musicpal_gpio_init;
1330 }
1331
1332 static DeviceInfo musicpal_gpio_info = {
1333     .name = "musicpal_gpio",
1334     .size = sizeof(musicpal_gpio_state),
1335     .reset = musicpal_gpio_reset,
1336     .vmsd = &musicpal_gpio_vmsd,
1337     .class_init = musicpal_gpio_class_init,
1338 };
1339
1340 /* Keyboard codes & masks */
1341 #define KEY_RELEASED            0x80
1342 #define KEY_CODE                0x7f
1343
1344 #define KEYCODE_TAB             0x0f
1345 #define KEYCODE_ENTER           0x1c
1346 #define KEYCODE_F               0x21
1347 #define KEYCODE_M               0x32
1348
1349 #define KEYCODE_EXTENDED        0xe0
1350 #define KEYCODE_UP              0x48
1351 #define KEYCODE_DOWN            0x50
1352 #define KEYCODE_LEFT            0x4b
1353 #define KEYCODE_RIGHT           0x4d
1354
1355 #define MP_KEY_WHEEL_VOL       (1 << 0)
1356 #define MP_KEY_WHEEL_VOL_INV   (1 << 1)
1357 #define MP_KEY_WHEEL_NAV       (1 << 2)
1358 #define MP_KEY_WHEEL_NAV_INV   (1 << 3)
1359 #define MP_KEY_BTN_FAVORITS    (1 << 4)
1360 #define MP_KEY_BTN_MENU        (1 << 5)
1361 #define MP_KEY_BTN_VOLUME      (1 << 6)
1362 #define MP_KEY_BTN_NAVIGATION  (1 << 7)
1363
1364 typedef struct musicpal_key_state {
1365     SysBusDevice busdev;
1366     MemoryRegion iomem;
1367     uint32_t kbd_extended;
1368     uint32_t pressed_keys;
1369     qemu_irq out[8];
1370 } musicpal_key_state;
1371
1372 static void musicpal_key_event(void *opaque, int keycode)
1373 {
1374     musicpal_key_state *s = opaque;
1375     uint32_t event = 0;
1376     int i;
1377
1378     if (keycode == KEYCODE_EXTENDED) {
1379         s->kbd_extended = 1;
1380         return;
1381     }
1382
1383     if (s->kbd_extended) {
1384         switch (keycode & KEY_CODE) {
1385         case KEYCODE_UP:
1386             event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
1387             break;
1388
1389         case KEYCODE_DOWN:
1390             event = MP_KEY_WHEEL_NAV;
1391             break;
1392
1393         case KEYCODE_LEFT:
1394             event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
1395             break;
1396
1397         case KEYCODE_RIGHT:
1398             event = MP_KEY_WHEEL_VOL;
1399             break;
1400         }
1401     } else {
1402         switch (keycode & KEY_CODE) {
1403         case KEYCODE_F:
1404             event = MP_KEY_BTN_FAVORITS;
1405             break;
1406
1407         case KEYCODE_TAB:
1408             event = MP_KEY_BTN_VOLUME;
1409             break;
1410
1411         case KEYCODE_ENTER:
1412             event = MP_KEY_BTN_NAVIGATION;
1413             break;
1414
1415         case KEYCODE_M:
1416             event = MP_KEY_BTN_MENU;
1417             break;
1418         }
1419         /* Do not repeat already pressed buttons */
1420         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1421             event = 0;
1422         }
1423     }
1424
1425     if (event) {
1426         /* Raise GPIO pin first if repeating a key */
1427         if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
1428             for (i = 0; i <= 7; i++) {
1429                 if (event & (1 << i)) {
1430                     qemu_set_irq(s->out[i], 1);
1431                 }
1432             }
1433         }
1434         for (i = 0; i <= 7; i++) {
1435             if (event & (1 << i)) {
1436                 qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
1437             }
1438         }
1439         if (keycode & KEY_RELEASED) {
1440             s->pressed_keys &= ~event;
1441         } else {
1442             s->pressed_keys |= event;
1443         }
1444     }
1445
1446     s->kbd_extended = 0;
1447 }
1448
1449 static int musicpal_key_init(SysBusDevice *dev)
1450 {
1451     musicpal_key_state *s = FROM_SYSBUS(musicpal_key_state, dev);
1452
1453     memory_region_init(&s->iomem, "dummy", 0);
1454     sysbus_init_mmio(dev, &s->iomem);
1455
1456     s->kbd_extended = 0;
1457     s->pressed_keys = 0;
1458
1459     qdev_init_gpio_out(&dev->qdev, s->out, ARRAY_SIZE(s->out));
1460
1461     qemu_add_kbd_event_handler(musicpal_key_event, s);
1462
1463     return 0;
1464 }
1465
1466 static const VMStateDescription musicpal_key_vmsd = {
1467     .name = "musicpal_key",
1468     .version_id = 1,
1469     .minimum_version_id = 1,
1470     .minimum_version_id_old = 1,
1471     .fields = (VMStateField[]) {
1472         VMSTATE_UINT32(kbd_extended, musicpal_key_state),
1473         VMSTATE_UINT32(pressed_keys, musicpal_key_state),
1474         VMSTATE_END_OF_LIST()
1475     }
1476 };
1477
1478 static void musicpal_key_class_init(ObjectClass *klass, void *data)
1479 {
1480     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1481
1482     k->init = musicpal_key_init;
1483 }
1484
1485 static DeviceInfo musicpal_key_info = {
1486     .name = "musicpal_key",
1487     .size = sizeof(musicpal_key_state),
1488     .vmsd = &musicpal_key_vmsd,
1489     .class_init = musicpal_key_class_init,
1490 };
1491
1492 static struct arm_boot_info musicpal_binfo = {
1493     .loader_start = 0x0,
1494     .board_id = 0x20e,
1495 };
1496
1497 static void musicpal_init(ram_addr_t ram_size,
1498                const char *boot_device,
1499                const char *kernel_filename, const char *kernel_cmdline,
1500                const char *initrd_filename, const char *cpu_model)
1501 {
1502     CPUState *env;
1503     qemu_irq *cpu_pic;
1504     qemu_irq pic[32];
1505     DeviceState *dev;
1506     DeviceState *i2c_dev;
1507     DeviceState *lcd_dev;
1508     DeviceState *key_dev;
1509     DeviceState *wm8750_dev;
1510     SysBusDevice *s;
1511     i2c_bus *i2c;
1512     int i;
1513     unsigned long flash_size;
1514     DriveInfo *dinfo;
1515     MemoryRegion *address_space_mem = get_system_memory();
1516     MemoryRegion *ram = g_new(MemoryRegion, 1);
1517     MemoryRegion *sram = g_new(MemoryRegion, 1);
1518
1519     if (!cpu_model) {
1520         cpu_model = "arm926";
1521     }
1522     env = cpu_init(cpu_model);
1523     if (!env) {
1524         fprintf(stderr, "Unable to find CPU definition\n");
1525         exit(1);
1526     }
1527     cpu_pic = arm_pic_init_cpu(env);
1528
1529     /* For now we use a fixed - the original - RAM size */
1530     memory_region_init_ram(ram, "musicpal.ram", MP_RAM_DEFAULT_SIZE);
1531     vmstate_register_ram_global(ram);
1532     memory_region_add_subregion(address_space_mem, 0, ram);
1533
1534     memory_region_init_ram(sram, "musicpal.sram", MP_SRAM_SIZE);
1535     vmstate_register_ram_global(sram);
1536     memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram);
1537
1538     dev = sysbus_create_simple("mv88w8618_pic", MP_PIC_BASE,
1539                                cpu_pic[ARM_PIC_CPU_IRQ]);
1540     for (i = 0; i < 32; i++) {
1541         pic[i] = qdev_get_gpio_in(dev, i);
1542     }
1543     sysbus_create_varargs("mv88w8618_pit", MP_PIT_BASE, pic[MP_TIMER1_IRQ],
1544                           pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ],
1545                           pic[MP_TIMER4_IRQ], NULL);
1546
1547     if (serial_hds[0]) {
1548         serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ],
1549                        1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN);
1550     }
1551     if (serial_hds[1]) {
1552         serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ],
1553                        1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN);
1554     }
1555
1556     /* Register flash */
1557     dinfo = drive_get(IF_PFLASH, 0, 0);
1558     if (dinfo) {
1559         flash_size = bdrv_getlength(dinfo->bdrv);
1560         if (flash_size != 8*1024*1024 && flash_size != 16*1024*1024 &&
1561             flash_size != 32*1024*1024) {
1562             fprintf(stderr, "Invalid flash image size\n");
1563             exit(1);
1564         }
1565
1566         /*
1567          * The original U-Boot accesses the flash at 0xFE000000 instead of
1568          * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1569          * image is smaller than 32 MB.
1570          */
1571 #ifdef TARGET_WORDS_BIGENDIAN
1572         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1573                               "musicpal.flash", flash_size,
1574                               dinfo->bdrv, 0x10000,
1575                               (flash_size + 0xffff) >> 16,
1576                               MP_FLASH_SIZE_MAX / flash_size,
1577                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1578                               0x5555, 0x2AAA, 1);
1579 #else
1580         pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
1581                               "musicpal.flash", flash_size,
1582                               dinfo->bdrv, 0x10000,
1583                               (flash_size + 0xffff) >> 16,
1584                               MP_FLASH_SIZE_MAX / flash_size,
1585                               2, 0x00BF, 0x236D, 0x0000, 0x0000,
1586                               0x5555, 0x2AAA, 0);
1587 #endif
1588
1589     }
1590     sysbus_create_simple("mv88w8618_flashcfg", MP_FLASHCFG_BASE, NULL);
1591
1592     qemu_check_nic_model(&nd_table[0], "mv88w8618");
1593     dev = qdev_create(NULL, "mv88w8618_eth");
1594     qdev_set_nic_properties(dev, &nd_table[0]);
1595     qdev_init_nofail(dev);
1596     sysbus_mmio_map(sysbus_from_qdev(dev), 0, MP_ETH_BASE);
1597     sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[MP_ETH_IRQ]);
1598
1599     sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE, NULL);
1600
1601     musicpal_misc_init(sysbus_from_qdev(dev));
1602
1603     dev = sysbus_create_simple("musicpal_gpio", MP_GPIO_BASE, pic[MP_GPIO_IRQ]);
1604     i2c_dev = sysbus_create_simple("gpio_i2c", -1, NULL);
1605     i2c = (i2c_bus *)qdev_get_child_bus(i2c_dev, "i2c");
1606
1607     lcd_dev = sysbus_create_simple("musicpal_lcd", MP_LCD_BASE, NULL);
1608     key_dev = sysbus_create_simple("musicpal_key", -1, NULL);
1609
1610     /* I2C read data */
1611     qdev_connect_gpio_out(i2c_dev, 0,
1612                           qdev_get_gpio_in(dev, MP_GPIO_I2C_DATA_BIT));
1613     /* I2C data */
1614     qdev_connect_gpio_out(dev, 3, qdev_get_gpio_in(i2c_dev, 0));
1615     /* I2C clock */
1616     qdev_connect_gpio_out(dev, 4, qdev_get_gpio_in(i2c_dev, 1));
1617
1618     for (i = 0; i < 3; i++) {
1619         qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(lcd_dev, i));
1620     }
1621     for (i = 0; i < 4; i++) {
1622         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 8));
1623     }
1624     for (i = 4; i < 8; i++) {
1625         qdev_connect_gpio_out(key_dev, i, qdev_get_gpio_in(dev, i + 15));
1626     }
1627
1628     wm8750_dev = i2c_create_slave(i2c, "wm8750", MP_WM_ADDR);
1629     dev = qdev_create(NULL, "mv88w8618_audio");
1630     s = sysbus_from_qdev(dev);
1631     qdev_prop_set_ptr(dev, "wm8750", wm8750_dev);
1632     qdev_init_nofail(dev);
1633     sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
1634     sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
1635
1636     musicpal_binfo.ram_size = MP_RAM_DEFAULT_SIZE;
1637     musicpal_binfo.kernel_filename = kernel_filename;
1638     musicpal_binfo.kernel_cmdline = kernel_cmdline;
1639     musicpal_binfo.initrd_filename = initrd_filename;
1640     arm_load_kernel(env, &musicpal_binfo);
1641 }
1642
1643 static QEMUMachine musicpal_machine = {
1644     .name = "musicpal",
1645     .desc = "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1646     .init = musicpal_init,
1647 };
1648
1649 static void musicpal_machine_init(void)
1650 {
1651     qemu_register_machine(&musicpal_machine);
1652 }
1653
1654 machine_init(musicpal_machine_init);
1655
1656 static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data)
1657 {
1658     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1659
1660     sdc->init = mv88w8618_wlan_init;
1661 }
1662
1663 static DeviceInfo mv88w8618_wlan_info = {
1664     .name = "mv88w8618_wlan",
1665     .size = sizeof(SysBusDevice),
1666     .class_init = mv88w8618_wlan_class_init,
1667 };
1668
1669 static void musicpal_register_devices(void)
1670 {
1671     sysbus_register_withprop(&mv88w8618_pic_info);
1672     sysbus_register_withprop(&mv88w8618_pit_info);
1673     sysbus_register_withprop(&mv88w8618_flashcfg_info);
1674     sysbus_register_withprop(&mv88w8618_eth_info);
1675     sysbus_qdev_register(&mv88w8618_wlan_info);
1676     sysbus_register_withprop(&musicpal_lcd_info);
1677     sysbus_register_withprop(&musicpal_gpio_info);
1678     sysbus_register_withprop(&musicpal_key_info);
1679 }
1680
1681 device_init(musicpal_register_devices)