hw/msix.c

   1 /*
   2  * MSI-X device support
   3  *
   4  * This module includes support for MSI-X in pci devices.
   5  *
   6  * Author: Michael S. Tsirkin <mst@redhat.com>
   7  *
   8  *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  *
  13  * Contributions after 2012-01-13 are licensed under the terms of the
  14  * GNU GPL, version 2 or (at your option) any later version.
  15  */
  16
  17 #include "hw.h"
  18 #include "msi.h"
  19 #include "msix.h"
  20 #include "pci.h"
  21 #include "range.h"
  22 #include "kvm.h"
  23
  24 #define MSIX_CAP_LENGTH 12
  25
  26 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
  27 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
  28 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
  29 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
  30
  31 /* How much space does an MSIX table need. */
  32 /* The spec requires giving the table structure
  33  * a 4K aligned region all by itself. */
  34 #define MSIX_PAGE_SIZE 0x1000
  35 /* Reserve second half of the page for pending bits */
  36 #define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
  37 #define MSIX_MAX_ENTRIES 32
  38
  39
  40 /* KVM specific MSIX helpers */
  41 static void kvm_msix_free(PCIDevice *dev)
  42 {
  43     int vector, changed = 0;
  44
  45     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
  46         if (dev->msix_entry_used[vector]) {
  47             kvm_msi_message_del(&dev->msix_irq_entries[vector]);
  48             changed = 1;
  49         }
  50     }
  51     if (changed) {
  52         kvm_commit_irq_routes();
  53     }
  54 }
  55
  56 static void kvm_msix_message_from_vector(PCIDevice *dev, unsigned vector,
  57                                          KVMMsiMessage *kmm)
  58 {
  59     uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
  60
  61     kmm->addr_lo = pci_get_long(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
  62     kmm->addr_hi = pci_get_long(table_entry + PCI_MSIX_ENTRY_UPPER_ADDR);
  63     kmm->data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
  64 }
  65
  66 static void kvm_msix_update(PCIDevice *dev, int vector,
  67                             int was_masked, int is_masked)
  68 {
  69     KVMMsiMessage new_entry, *entry;
  70     int mask_cleared = was_masked && !is_masked;
  71     int r;
  72
  73     /* It is only legal to change an entry when it is masked. Therefore, it is
  74      * enough to update the routing in kernel when mask is being cleared. */
  75     if (!mask_cleared) {
  76         return;
  77     }
  78     if (!dev->msix_entry_used[vector]) {
  79         return;
  80     }
  81
  82     entry = dev->msix_irq_entries + vector;
  83     kvm_msix_message_from_vector(dev, vector, &new_entry);
  84     r = kvm_msi_message_update(entry, &new_entry);
  85     if (r < 0) {
  86         fprintf(stderr, "%s: kvm_update_msix failed: %s\n", __func__,
  87                 strerror(-r));
  88         exit(1);
  89     }
  90     if (r > 0) {
  91         *entry = new_entry;
  92         r = kvm_commit_irq_routes();
  93         if (r) {
  94             fprintf(stderr, "%s: kvm_commit_irq_routes failed: %s\n", __func__,
  95                     strerror(-r));
  96             exit(1);
  97         }
  98     }
  99 }
 100
 101 static int kvm_msix_vector_add(PCIDevice *dev, unsigned vector)
 102 {
 103     KVMMsiMessage *kmm = dev->msix_irq_entries + vector;
 104     int r;
 105
 106     kvm_msix_message_from_vector(dev, vector, kmm);
 107     r = kvm_msi_message_add(kmm);
 108     if (r < 0) {
 109         fprintf(stderr, "%s: kvm_add_msix failed: %s\n", __func__, strerror(-r));
 110         return r;
 111     }
 112
 113     r = kvm_commit_irq_routes();
 114     if (r < 0) {
 115         fprintf(stderr, "%s: kvm_commit_irq_routes failed: %s\n", __func__, strerror(-r));
 116         return r;
 117     }
 118     return 0;
 119 }
 120
 121 static void kvm_msix_vector_del(PCIDevice *dev, unsigned vector)
 122 {
 123     kvm_msi_message_del(&dev->msix_irq_entries[vector]);
 124     kvm_commit_irq_routes();
 125 }
 126
 127 /* Add MSI-X capability to the config space for the device. */
 128 /* Given a bar and its size, add MSI-X table on top of it
 129  * and fill MSI-X capability in the config space.
 130  * Original bar size must be a power of 2 or 0.
 131  * New bar size is returned. */
 132 static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
 133                            unsigned bar_nr, unsigned bar_size)
 134 {
 135     int config_offset;
 136     uint8_t *config;
 137
 138     pdev->msix_bar_size = bar_size;
 139
 140     config_offset = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
 141
 142     if (!config_offset) {
 143         uint32_t new_size;
 144
 145         if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
 146             return -EINVAL;
 147         if (bar_size > 0x80000000)
 148             return -ENOSPC;
 149
 150         /* Add space for MSI-X structures */
 151         if (!bar_size) {
 152             new_size = MSIX_PAGE_SIZE;
 153         } else if (bar_size < MSIX_PAGE_SIZE) {
 154             bar_size = MSIX_PAGE_SIZE;
 155             new_size = MSIX_PAGE_SIZE * 2;
 156         } else {
 157             new_size = bar_size * 2;
 158         }
 159
 160         pdev->msix_bar_size = new_size;
 161         config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX,
 162                                            0, MSIX_CAP_LENGTH);
 163         if (config_offset < 0)
 164             return config_offset;
 165         config = pdev->config + config_offset;
 166
 167         pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
 168         /* Table on top of BAR */
 169         pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
 170         /* Pending bits on top of that */
 171         pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
 172                      bar_nr);
 173     }
 174     pdev->msix_cap = config_offset;
 175     /* Make flags bit writable. */
 176     pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
 177             MSIX_MASKALL_MASK;
 178     pdev->msix_function_masked = true;
 179     return 0;
 180 }
 181
 182 static uint64_t msix_mmio_read(void *opaque, target_phys_addr_t addr,
 183                                unsigned size)
 184 {
 185     PCIDevice *dev = opaque;
 186     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 187     void *page = dev->msix_table_page;
 188
 189     return pci_get_long(page + offset);
 190 }
 191
 192 static uint8_t msix_pending_mask(int vector)
 193 {
 194     return 1 << (vector % 8);
 195 }
 196
 197 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
 198 {
 199     return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
 200 }
 201
 202 static int msix_is_pending(PCIDevice *dev, int vector)
 203 {
 204     return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
 205 }
 206
 207 static void msix_set_pending(PCIDevice *dev, int vector)
 208 {
 209     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
 210 }
 211
 212 static void msix_clr_pending(PCIDevice *dev, int vector)
 213 {
 214     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
 215 }
 216
 217 static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
 218 {
 219     unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 220     return fmask || dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
 221 }
 222
 223 static bool msix_is_masked(PCIDevice *dev, int vector)
 224 {
 225     return msix_vector_masked(dev, vector, dev->msix_function_masked);
 226 }
 227
 228 static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
 229 {
 230     bool is_masked = msix_is_masked(dev, vector);
 231     if (is_masked == was_masked) {
 232         return;
 233     }
 234
 235     if (dev->msix_mask_notifier) {
 236         int ret;
 237         ret = dev->msix_mask_notifier(dev, vector, is_masked);
 238         assert(ret >= 0);
 239     }
 240
 241     if (!is_masked && msix_is_pending(dev, vector)) {
 242         msix_clr_pending(dev, vector);
 243         msix_notify(dev, vector);
 244     }
 245 }
 246
 247 static void msix_update_function_masked(PCIDevice *dev)
 248 {
 249     dev->msix_function_masked = !msix_enabled(dev) ||
 250         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
 251 }
 252
 253 /* Handle MSI-X capability config write. */
 254 void msix_write_config(PCIDevice *dev, uint32_t addr,
 255                        uint32_t val, int len)
 256 {
 257     unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
 258     int vector;
 259     bool was_masked;
 260
 261     if (!range_covers_byte(addr, len, enable_pos)) {
 262         return;
 263     }
 264
 265     was_masked = dev->msix_function_masked;
 266     msix_update_function_masked(dev);
 267
 268     if (!msix_enabled(dev)) {
 269         return;
 270     }
 271
 272     pci_device_deassert_intx(dev);
 273
 274     if (dev->msix_function_masked == was_masked) {
 275         return;
 276     }
 277
 278     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 279         msix_handle_mask_update(dev, vector,
 280                                 msix_vector_masked(dev, vector, was_masked));
 281     }
 282 }
 283
 284 static void msix_mmio_write(void *opaque, target_phys_addr_t addr,
 285                             uint64_t val, unsigned size)
 286 {
 287     PCIDevice *dev = opaque;
 288     unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;
 289     int vector = offset / PCI_MSIX_ENTRY_SIZE;
 290     bool was_masked;
 291
 292     /* MSI-X page includes a read-only PBA and a writeable Vector Control. */
 293     if (vector >= dev->msix_entries_nr) {
 294         return;
 295     }
 296
 297     was_masked = msix_is_masked(dev, vector);
 298     pci_set_long(dev->msix_table_page + offset, val);
 299     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 300         kvm_msix_update(dev, vector, was_masked, msix_is_masked(dev, vector));
 301     }
 302     msix_handle_mask_update(dev, vector, was_masked);
 303 }
 304
 305 static const MemoryRegionOps msix_mmio_ops = {
 306     .read = msix_mmio_read,
 307     .write = msix_mmio_write,
 308     .endianness = DEVICE_NATIVE_ENDIAN,
 309     .valid = {
 310         .min_access_size = 4,
 311         .max_access_size = 4,
 312     },
 313 };
 314
 315 static void msix_mmio_setup(PCIDevice *d, MemoryRegion *bar)
 316 {
 317     uint8_t *config = d->config + d->msix_cap;
 318     uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
 319     uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
 320     /* TODO: for assigned devices, we'll want to make it possible to map
 321      * pending bits separately in case they are in a separate bar. */
 322
 323     memory_region_add_subregion(bar, offset, &d->msix_mmio);
 324 }
 325
 326 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
 327 {
 328     int vector, r;
 329     for (vector = 0; vector < nentries; ++vector) {
 330         unsigned offset =
 331             vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 332         int was_masked = msix_is_masked(dev, vector);
 333         dev->msix_table_page[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 334         if (was_masked != msix_is_masked(dev, vector) &&
 335             dev->msix_mask_notifier) {
 336             r = dev->msix_mask_notifier(dev, vector,
 337                                         msix_is_masked(dev, vector));
 338             assert(r >= 0);
 339         }
 340     }
 341 }
 342
 343 /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
 344  * modified, it should be retrieved with msix_bar_size. */
 345 int msix_init(struct PCIDevice *dev, unsigned short nentries,
 346               MemoryRegion *bar,
 347               unsigned bar_nr, unsigned bar_size)
 348 {
 349     int ret;
 350
 351     /* Nothing to do if MSI is not supported by interrupt controller */
 352     if (!msi_supported ||
 353         (kvm_enabled() && kvm_irqchip_in_kernel() && !kvm_has_gsi_routing())) {
 354         return -ENOTSUP;
 355     }
 356     if (nentries > MSIX_MAX_ENTRIES)
 357         return -EINVAL;
 358
 359     dev->msix_mask_notifier = NULL;
 360     dev->msix_entry_used = g_malloc0(MSIX_MAX_ENTRIES *
 361                                         sizeof *dev->msix_entry_used);
 362
 363     dev->msix_table_page = g_malloc0(MSIX_PAGE_SIZE);
 364     msix_mask_all(dev, nentries);
 365
 366     memory_region_init_io(&dev->msix_mmio, &msix_mmio_ops, dev,
 367                           "msix", MSIX_PAGE_SIZE);
 368
 369     dev->msix_entries_nr = nentries;
 370     ret = msix_add_config(dev, nentries, bar_nr, bar_size);
 371     if (ret)
 372         goto err_config;
 373
 374     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 375         dev->msix_irq_entries = g_malloc(nentries *
 376                                          sizeof *dev->msix_irq_entries);
 377     }
 378
 379     dev->cap_present |= QEMU_PCI_CAP_MSIX;
 380     msix_mmio_setup(dev, bar);
 381     return 0;
 382
 383 err_config:
 384     dev->msix_entries_nr = 0;
 385     memory_region_destroy(&dev->msix_mmio);
 386     g_free(dev->msix_table_page);
 387     dev->msix_table_page = NULL;
 388     g_free(dev->msix_entry_used);
 389     dev->msix_entry_used = NULL;
 390     return ret;
 391 }
 392
 393 static void msix_free_irq_entries(PCIDevice *dev)
 394 {
 395     int vector;
 396
 397     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 398         kvm_msix_free(dev);
 399     }
 400
 401     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 402         dev->msix_entry_used[vector] = 0;
 403         msix_clr_pending(dev, vector);
 404     }
 405 }
 406
 407 /* Clean up resources for the device. */
 408 int msix_uninit(PCIDevice *dev, MemoryRegion *bar)
 409 {
 410     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 411         return 0;
 412     pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 413     dev->msix_cap = 0;
 414     msix_free_irq_entries(dev);
 415     dev->msix_entries_nr = 0;
 416     memory_region_del_subregion(bar, &dev->msix_mmio);
 417     memory_region_destroy(&dev->msix_mmio);
 418     g_free(dev->msix_table_page);
 419     dev->msix_table_page = NULL;
 420     g_free(dev->msix_entry_used);
 421     dev->msix_entry_used = NULL;
 422     g_free(dev->msix_irq_entries);
 423     dev->msix_irq_entries = NULL;
 424     dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
 425     return 0;
 426 }
 427
 428 void msix_save(PCIDevice *dev, QEMUFile *f)
 429 {
 430     unsigned n = dev->msix_entries_nr;
 431
 432     if (!msi_supported) {
 433         return;
 434     }
 435
 436     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 437         return;
 438     }
 439     qemu_put_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
 440     qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 441 }
 442
 443 /* Should be called after restoring the config space. */
 444 void msix_load(PCIDevice *dev, QEMUFile *f)
 445 {
 446     unsigned n = dev->msix_entries_nr;
 447
 448     if (!msi_supported)
 449         return;
 450
 451     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) {
 452         return;
 453     }
 454
 455     msix_free_irq_entries(dev);
 456     qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
 457     qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
 458     msix_update_function_masked(dev);
 459 }
 460
 461 /* Does device support MSI-X? */
 462 int msix_present(PCIDevice *dev)
 463 {
 464     return dev->cap_present & QEMU_PCI_CAP_MSIX;
 465 }
 466
 467 /* Is MSI-X enabled? */
 468 int msix_enabled(PCIDevice *dev)
 469 {
 470     return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
 471         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 472          MSIX_ENABLE_MASK);
 473 }
 474
 475 /* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
 476 uint32_t msix_bar_size(PCIDevice *dev)
 477 {
 478     return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
 479         dev->msix_bar_size : 0;
 480 }
 481
 482 /* Send an MSI-X message */
 483 void msix_notify(PCIDevice *dev, unsigned vector)
 484 {
 485     uint8_t *table_entry = dev->msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
 486     uint64_t address;
 487     uint32_t data;
 488
 489     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 490         return;
 491     if (msix_is_masked(dev, vector)) {
 492         msix_set_pending(dev, vector);
 493         return;
 494     }
 495
 496     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 497         kvm_set_irq(dev->msix_irq_entries[vector].gsi, 1, NULL);
 498         return;
 499     }
 500
 501     address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
 502     data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
 503     stl_le_phys(address, data);
 504 }
 505
 506 void msix_reset(PCIDevice *dev)
 507 {
 508     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 509         return;
 510     msix_free_irq_entries(dev);
 511     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
 512             ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
 513     memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
 514     msix_mask_all(dev, dev->msix_entries_nr);
 515 }
 516
 517 /* PCI spec suggests that devices make it possible for software to configure
 518  * less vectors than supported by the device, but does not specify a standard
 519  * mechanism for devices to do so.
 520  *
 521  * We support this by asking devices to declare vectors software is going to
 522  * actually use, and checking this on the notification path. Devices that
 523  * don't want to follow the spec suggestion can declare all vectors as used. */
 524
 525 /* Mark vector as used. */
 526 int msix_vector_use(PCIDevice *dev, unsigned vector)
 527 {
 528     int ret;
 529     if (vector >= dev->msix_entries_nr)
 530         return -EINVAL;
 531     if (kvm_enabled() && kvm_irqchip_in_kernel() &&
 532         !dev->msix_entry_used[vector]) {
 533         ret = kvm_msix_vector_add(dev, vector);
 534         if (ret) {
 535             return ret;
 536         }
 537     }
 538     ++dev->msix_entry_used[vector];
 539     return 0;
 540 }
 541
 542 /* Mark vector as unused. */
 543 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
 544 {
 545     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
 546         return;
 547     }
 548     if (--dev->msix_entry_used[vector]) {
 549         return;
 550     }
 551     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 552         kvm_msix_vector_del(dev, vector);
 553     }
 554     msix_clr_pending(dev, vector);
 555 }
 556
 557 void msix_unuse_all_vectors(PCIDevice *dev)
 558 {
 559     if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
 560         return;
 561     msix_free_irq_entries(dev);
 562 }
 563
 564 /* Invoke the notifier if vector entry is used and unmasked. */
 565 static int msix_notify_if_unmasked(PCIDevice *dev, unsigned vector, int masked)
 566 {
 567     assert(dev->msix_mask_notifier);
 568     if (!dev->msix_entry_used[vector] || msix_is_masked(dev, vector)) {
 569         return 0;
 570     }
 571     return dev->msix_mask_notifier(dev, vector, masked);
 572 }
 573
 574 static int msix_set_mask_notifier_for_vector(PCIDevice *dev, unsigned vector)
 575 {
 576         /* Notifier has been set. Invoke it on unmasked vectors. */
 577         return msix_notify_if_unmasked(dev, vector, 0);
 578 }
 579
 580 static int msix_unset_mask_notifier_for_vector(PCIDevice *dev, unsigned vector)
 581 {
 582         /* Notifier will be unset. Invoke it to mask unmasked entries. */
 583         return msix_notify_if_unmasked(dev, vector, 1);
 584 }
 585
 586 int msix_set_mask_notifier(PCIDevice *dev, msix_mask_notifier_func f)
 587 {
 588     int r, n;
 589     assert(!dev->msix_mask_notifier);
 590     dev->msix_mask_notifier = f;
 591     for (n = 0; n < dev->msix_entries_nr; ++n) {
 592         r = msix_set_mask_notifier_for_vector(dev, n);
 593         if (r < 0) {
 594             goto undo;
 595         }
 596     }
 597     return 0;
 598
 599 undo:
 600     while (--n >= 0) {
 601         msix_unset_mask_notifier_for_vector(dev, n);
 602     }
 603     dev->msix_mask_notifier = NULL;
 604     return r;
 605 }
 606
 607 int msix_unset_mask_notifier(PCIDevice *dev)
 608 {
 609     int r, n;
 610     assert(dev->msix_mask_notifier);
 611     for (n = 0; n < dev->msix_entries_nr; ++n) {
 612         r = msix_unset_mask_notifier_for_vector(dev, n);
 613         if (r < 0) {
 614             goto undo;
 615         }
 616     }
 617     dev->msix_mask_notifier = NULL;
 618     return 0;
 619
 620 undo:
 621     while (--n >= 0) {
 622         msix_set_mask_notifier_for_vector(dev, n);
 623     }
 624     return r;
 625 }