2 * ioapic.c IOAPIC emulation logic
4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * Split the ioapic logic from apic.c
7 * Xiantao Zhang <xiantao.zhang@intel.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "ioapic_internal.h"
31 //#define DEBUG_IOAPIC
34 #define DPRINTF(fmt, ...) \
35 do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...)
40 static IOAPICCommonState
*ioapics
[MAX_IOAPICS
];
42 static void ioapic_service(IOAPICCommonState
*s
)
47 uint8_t delivery_mode
;
53 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
56 entry
= s
->ioredtbl
[i
];
57 if (!(entry
& IOAPIC_LVT_MASKED
)) {
58 trig_mode
= ((entry
>> IOAPIC_LVT_TRIGGER_MODE_SHIFT
) & 1);
59 dest
= entry
>> IOAPIC_LVT_DEST_SHIFT
;
60 dest_mode
= (entry
>> IOAPIC_LVT_DEST_MODE_SHIFT
) & 1;
62 (entry
>> IOAPIC_LVT_DELIV_MODE_SHIFT
) & IOAPIC_DM_MASK
;
63 if (trig_mode
== IOAPIC_TRIGGER_EDGE
) {
66 s
->ioredtbl
[i
] |= IOAPIC_LVT_REMOTE_IRR
;
68 if (delivery_mode
== IOAPIC_DM_EXTINT
) {
69 vector
= pic_read_irq(isa_pic
);
71 vector
= entry
& IOAPIC_VECTOR_MASK
;
73 apic_deliver_irq(dest
, dest_mode
, delivery_mode
,
80 static void ioapic_set_irq(void *opaque
, int vector
, int level
)
82 IOAPICCommonState
*s
= opaque
;
84 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
85 * to GSI 2. GSI maps to ioapic 1-1. This is not
86 * the cleanest way of doing it but it should work. */
88 DPRINTF("%s: %s vec %x\n", __func__
, level
? "raise" : "lower", vector
);
92 if (vector
>= 0 && vector
< IOAPIC_NUM_PINS
) {
93 uint32_t mask
= 1 << vector
;
94 uint64_t entry
= s
->ioredtbl
[vector
];
96 if (entry
& (1 << IOAPIC_LVT_POLARITY_SHIFT
)) {
99 if (((entry
>> IOAPIC_LVT_TRIGGER_MODE_SHIFT
) & 1) ==
100 IOAPIC_TRIGGER_LEVEL
) {
101 /* level triggered */
109 /* According to the 82093AA manual, we must ignore edge requests
110 * if the input pin is masked. */
111 if (level
&& !(entry
& IOAPIC_LVT_MASKED
)) {
119 void ioapic_eoi_broadcast(int vector
)
121 IOAPICCommonState
*s
;
125 for (i
= 0; i
< MAX_IOAPICS
; i
++) {
130 for (n
= 0; n
< IOAPIC_NUM_PINS
; n
++) {
131 entry
= s
->ioredtbl
[n
];
132 if ((entry
& IOAPIC_LVT_REMOTE_IRR
)
133 && (entry
& IOAPIC_VECTOR_MASK
) == vector
) {
134 s
->ioredtbl
[n
] = entry
& ~IOAPIC_LVT_REMOTE_IRR
;
135 if (!(entry
& IOAPIC_LVT_MASKED
) && (s
->irr
& (1 << n
))) {
144 ioapic_mem_read(void *opaque
, target_phys_addr_t addr
, unsigned int size
)
146 IOAPICCommonState
*s
= opaque
;
150 switch (addr
& 0xff) {
151 case IOAPIC_IOREGSEL
:
158 switch (s
->ioregsel
) {
160 val
= s
->id
<< IOAPIC_ID_SHIFT
;
163 val
= IOAPIC_VERSION
|
164 ((IOAPIC_NUM_PINS
- 1) << IOAPIC_VER_ENTRIES_SHIFT
);
170 index
= (s
->ioregsel
- IOAPIC_REG_REDTBL_BASE
) >> 1;
171 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
172 if (s
->ioregsel
& 1) {
173 val
= s
->ioredtbl
[index
] >> 32;
175 val
= s
->ioredtbl
[index
] & 0xffffffff;
179 DPRINTF("read: %08x = %08x\n", s
->ioregsel
, val
);
186 ioapic_mem_write(void *opaque
, target_phys_addr_t addr
, uint64_t val
,
189 IOAPICCommonState
*s
= opaque
;
192 switch (addr
& 0xff) {
193 case IOAPIC_IOREGSEL
:
200 DPRINTF("write: %08x = %08x\n", s
->ioregsel
, val
);
201 switch (s
->ioregsel
) {
203 s
->id
= (val
>> IOAPIC_ID_SHIFT
) & IOAPIC_ID_MASK
;
209 index
= (s
->ioregsel
- IOAPIC_REG_REDTBL_BASE
) >> 1;
210 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
211 if (s
->ioregsel
& 1) {
212 s
->ioredtbl
[index
] &= 0xffffffff;
213 s
->ioredtbl
[index
] |= (uint64_t)val
<< 32;
215 s
->ioredtbl
[index
] &= ~0xffffffffULL
;
216 s
->ioredtbl
[index
] |= val
;
225 static void kvm_kernel_ioapic_save_to_user(IOAPICCommonState
*s
)
227 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
228 struct kvm_irqchip chip
;
229 struct kvm_ioapic_state
*kioapic
;
232 chip
.chip_id
= KVM_IRQCHIP_IOAPIC
;
233 kvm_get_irqchip(kvm_state
, &chip
);
234 kioapic
= &chip
.chip
.ioapic
;
237 s
->ioregsel
= kioapic
->ioregsel
;
238 s
->irr
= kioapic
->irr
;
239 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
240 s
->ioredtbl
[i
] = kioapic
->redirtbl
[i
].bits
;
245 static void kvm_kernel_ioapic_load_from_user(IOAPICCommonState
*s
)
247 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
248 struct kvm_irqchip chip
;
249 struct kvm_ioapic_state
*kioapic
;
252 chip
.chip_id
= KVM_IRQCHIP_IOAPIC
;
253 kioapic
= &chip
.chip
.ioapic
;
256 kioapic
->ioregsel
= s
->ioregsel
;
257 kioapic
->base_address
= s
->busdev
.mmio
[0].addr
;
258 kioapic
->irr
= s
->irr
;
259 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
260 kioapic
->redirtbl
[i
].bits
= s
->ioredtbl
[i
];
263 kvm_set_irqchip(kvm_state
, &chip
);
267 static void kvm_ioapic_pre_save(IOAPICCommonState
*s
)
270 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
271 kvm_kernel_ioapic_save_to_user(s
);
275 static void kvm_ioapic_post_load(IOAPICCommonState
*s
)
277 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
278 kvm_kernel_ioapic_load_from_user(s
);
282 static void ioapic_reset(DeviceState
*d
)
284 IOAPICCommonState
*s
= DO_UPCAST(IOAPICCommonState
, busdev
.qdev
, d
);
286 ioapic_reset_common(d
);
287 #ifdef KVM_CAP_IRQCHIP
288 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
289 kvm_kernel_ioapic_load_from_user(s
);
294 static const MemoryRegionOps ioapic_io_ops
= {
295 .read
= ioapic_mem_read
,
296 .write
= ioapic_mem_write
,
297 .endianness
= DEVICE_NATIVE_ENDIAN
,
300 static void ioapic_init(IOAPICCommonState
*s
, int instance_no
)
302 memory_region_init_io(&s
->io_memory
, &ioapic_io_ops
, s
, "ioapic", 0x1000);
304 qdev_init_gpio_in(&s
->busdev
.qdev
, ioapic_set_irq
, IOAPIC_NUM_PINS
);
306 ioapics
[instance_no
] = s
;
309 static void ioapic_class_init(ObjectClass
*klass
, void *data
)
311 IOAPICCommonClass
*k
= IOAPIC_COMMON_CLASS(klass
);
313 k
->init
= ioapic_init
;
314 k
->pre_save
= kvm_ioapic_pre_save
;
315 k
->post_load
= kvm_ioapic_post_load
;
318 static DeviceInfo ioapic_info
= {
320 .size
= sizeof(IOAPICCommonState
),
321 .reset
= ioapic_reset
,
322 .class_init
= ioapic_class_init
,
325 static void ioapic_register_devices(void)
327 ioapic_qdev_register(&ioapic_info
);
330 device_init(ioapic_register_devices
)