hw/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "sysbus.h"
  11 #include "primecell.h"
  12 #include "devices.h"
  13 #include "boards.h"
  14 #include "arm-misc.h"
  15 #include "net.h"
  16 #include "exec-memory.h"
  17 #include "sysemu.h"
  18
  19 typedef struct {
  20     SysBusDevice busdev;
  21     MemoryRegion iomem;
  22     uint32_t memsz;
  23     MemoryRegion flash;
  24     uint32_t cm_osc;
  25     uint32_t cm_ctrl;
  26     uint32_t cm_lock;
  27     uint32_t cm_auxosc;
  28     uint32_t cm_sdram;
  29     uint32_t cm_init;
  30     uint32_t cm_flags;
  31     uint32_t cm_nvflags;
  32     uint32_t int_level;
  33     uint32_t irq_enabled;
  34     uint32_t fiq_enabled;
  35 } integratorcm_state;
  36
  37 static uint8_t integrator_spd[128] = {
  38    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  39    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  40 };
  41
  42 static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset,
  43                                   unsigned size)
  44 {
  45     integratorcm_state *s = (integratorcm_state *)opaque;
  46     if (offset >= 0x100 && offset < 0x200) {
  47         /* CM_SPD */
  48         if (offset >= 0x180)
  49             return 0;
  50         return integrator_spd[offset >> 2];
  51     }
  52     switch (offset >> 2) {
  53     case 0: /* CM_ID */
  54         return 0x411a3001;
  55     case 1: /* CM_PROC */
  56         return 0;
  57     case 2: /* CM_OSC */
  58         return s->cm_osc;
  59     case 3: /* CM_CTRL */
  60         return s->cm_ctrl;
  61     case 4: /* CM_STAT */
  62         return 0x00100000;
  63     case 5: /* CM_LOCK */
  64         if (s->cm_lock == 0xa05f) {
  65             return 0x1a05f;
  66         } else {
  67             return s->cm_lock;
  68         }
  69     case 6: /* CM_LMBUSCNT */
  70         /* ??? High frequency timer.  */
  71         hw_error("integratorcm_read: CM_LMBUSCNT");
  72     case 7: /* CM_AUXOSC */
  73         return s->cm_auxosc;
  74     case 8: /* CM_SDRAM */
  75         return s->cm_sdram;
  76     case 9: /* CM_INIT */
  77         return s->cm_init;
  78     case 10: /* CM_REFCT */
  79         /* ??? High frequency timer.  */
  80         hw_error("integratorcm_read: CM_REFCT");
  81     case 12: /* CM_FLAGS */
  82         return s->cm_flags;
  83     case 14: /* CM_NVFLAGS */
  84         return s->cm_nvflags;
  85     case 16: /* CM_IRQ_STAT */
  86         return s->int_level & s->irq_enabled;
  87     case 17: /* CM_IRQ_RSTAT */
  88         return s->int_level;
  89     case 18: /* CM_IRQ_ENSET */
  90         return s->irq_enabled;
  91     case 20: /* CM_SOFT_INTSET */
  92         return s->int_level & 1;
  93     case 24: /* CM_FIQ_STAT */
  94         return s->int_level & s->fiq_enabled;
  95     case 25: /* CM_FIQ_RSTAT */
  96         return s->int_level;
  97     case 26: /* CM_FIQ_ENSET */
  98         return s->fiq_enabled;
  99     case 32: /* CM_VOLTAGE_CTL0 */
 100     case 33: /* CM_VOLTAGE_CTL1 */
 101     case 34: /* CM_VOLTAGE_CTL2 */
 102     case 35: /* CM_VOLTAGE_CTL3 */
 103         /* ??? Voltage control unimplemented.  */
 104         return 0;
 105     default:
 106         hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
 107                  (int)offset);
 108         return 0;
 109     }
 110 }
 111
 112 static void integratorcm_do_remap(integratorcm_state *s)
 113 {
 114     /* Sync memory region state with CM_CTRL REMAP bit:
 115      * bit 0 => flash at address 0; bit 1 => RAM
 116      */
 117     memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
 118 }
 119
 120 static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
 121 {
 122     if (value & 8) {
 123         qemu_system_reset_request();
 124     }
 125     if ((s->cm_ctrl ^ value) & 1) {
 126         /* (value & 1) != 0 means the green "MISC LED" is lit.
 127          * We don't have any nice place to display LEDs. printf is a bad
 128          * idea because Linux uses the LED as a heartbeat and the output
 129          * will swamp anything else on the terminal.
 130          */
 131     }
 132     /* Note that the RESET bit [3] always reads as zero */
 133     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
 134     integratorcm_do_remap(s);
 135 }
 136
 137 static void integratorcm_update(integratorcm_state *s)
 138 {
 139     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 140        are active.  */
 141     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 142         hw_error("Core module interrupt\n");
 143 }
 144
 145 static void integratorcm_write(void *opaque, target_phys_addr_t offset,
 146                                uint64_t value, unsigned size)
 147 {
 148     integratorcm_state *s = (integratorcm_state *)opaque;
 149     switch (offset >> 2) {
 150     case 2: /* CM_OSC */
 151         if (s->cm_lock == 0xa05f)
 152             s->cm_osc = value;
 153         break;
 154     case 3: /* CM_CTRL */
 155         integratorcm_set_ctrl(s, value);
 156         break;
 157     case 5: /* CM_LOCK */
 158         s->cm_lock = value & 0xffff;
 159         break;
 160     case 7: /* CM_AUXOSC */
 161         if (s->cm_lock == 0xa05f)
 162             s->cm_auxosc = value;
 163         break;
 164     case 8: /* CM_SDRAM */
 165         s->cm_sdram = value;
 166         break;
 167     case 9: /* CM_INIT */
 168         /* ??? This can change the memory bus frequency.  */
 169         s->cm_init = value;
 170         break;
 171     case 12: /* CM_FLAGSS */
 172         s->cm_flags |= value;
 173         break;
 174     case 13: /* CM_FLAGSC */
 175         s->cm_flags &= ~value;
 176         break;
 177     case 14: /* CM_NVFLAGSS */
 178         s->cm_nvflags |= value;
 179         break;
 180     case 15: /* CM_NVFLAGSS */
 181         s->cm_nvflags &= ~value;
 182         break;
 183     case 18: /* CM_IRQ_ENSET */
 184         s->irq_enabled |= value;
 185         integratorcm_update(s);
 186         break;
 187     case 19: /* CM_IRQ_ENCLR */
 188         s->irq_enabled &= ~value;
 189         integratorcm_update(s);
 190         break;
 191     case 20: /* CM_SOFT_INTSET */
 192         s->int_level |= (value & 1);
 193         integratorcm_update(s);
 194         break;
 195     case 21: /* CM_SOFT_INTCLR */
 196         s->int_level &= ~(value & 1);
 197         integratorcm_update(s);
 198         break;
 199     case 26: /* CM_FIQ_ENSET */
 200         s->fiq_enabled |= value;
 201         integratorcm_update(s);
 202         break;
 203     case 27: /* CM_FIQ_ENCLR */
 204         s->fiq_enabled &= ~value;
 205         integratorcm_update(s);
 206         break;
 207     case 32: /* CM_VOLTAGE_CTL0 */
 208     case 33: /* CM_VOLTAGE_CTL1 */
 209     case 34: /* CM_VOLTAGE_CTL2 */
 210     case 35: /* CM_VOLTAGE_CTL3 */
 211         /* ??? Voltage control unimplemented.  */
 212         break;
 213     default:
 214         hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
 215                  (int)offset);
 216         break;
 217     }
 218 }
 219
 220 /* Integrator/CM control registers.  */
 221
 222 static const MemoryRegionOps integratorcm_ops = {
 223     .read = integratorcm_read,
 224     .write = integratorcm_write,
 225     .endianness = DEVICE_NATIVE_ENDIAN,
 226 };
 227
 228 static int integratorcm_init(SysBusDevice *dev)
 229 {
 230     integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
 231
 232     s->cm_osc = 0x01000048;
 233     /* ??? What should the high bits of this value be?  */
 234     s->cm_auxosc = 0x0007feff;
 235     s->cm_sdram = 0x00011122;
 236     if (s->memsz >= 256) {
 237         integrator_spd[31] = 64;
 238         s->cm_sdram |= 0x10;
 239     } else if (s->memsz >= 128) {
 240         integrator_spd[31] = 32;
 241         s->cm_sdram |= 0x0c;
 242     } else if (s->memsz >= 64) {
 243         integrator_spd[31] = 16;
 244         s->cm_sdram |= 0x08;
 245     } else if (s->memsz >= 32) {
 246         integrator_spd[31] = 4;
 247         s->cm_sdram |= 0x04;
 248     } else {
 249         integrator_spd[31] = 2;
 250     }
 251     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 252     s->cm_init = 0x00000112;
 253     memory_region_init_ram(&s->flash, "integrator.flash", 0x100000);
 254     vmstate_register_ram_global(&s->flash);
 255
 256     memory_region_init_io(&s->iomem, &integratorcm_ops, s,
 257                           "integratorcm", 0x00800000);
 258     sysbus_init_mmio(dev, &s->iomem);
 259
 260     integratorcm_do_remap(s);
 261     /* ??? Save/restore.  */
 262     return 0;
 263 }
 264
 265 /* Integrator/CP hardware emulation.  */
 266 /* Primary interrupt controller.  */
 267
 268 typedef struct icp_pic_state
 269 {
 270   SysBusDevice busdev;
 271   MemoryRegion iomem;
 272   uint32_t level;
 273   uint32_t irq_enabled;
 274   uint32_t fiq_enabled;
 275   qemu_irq parent_irq;
 276   qemu_irq parent_fiq;
 277 } icp_pic_state;
 278
 279 static void icp_pic_update(icp_pic_state *s)
 280 {
 281     uint32_t flags;
 282
 283     flags = (s->level & s->irq_enabled);
 284     qemu_set_irq(s->parent_irq, flags != 0);
 285     flags = (s->level & s->fiq_enabled);
 286     qemu_set_irq(s->parent_fiq, flags != 0);
 287 }
 288
 289 static void icp_pic_set_irq(void *opaque, int irq, int level)
 290 {
 291     icp_pic_state *s = (icp_pic_state *)opaque;
 292     if (level)
 293         s->level |= 1 << irq;
 294     else
 295         s->level &= ~(1 << irq);
 296     icp_pic_update(s);
 297 }
 298
 299 static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
 300                              unsigned size)
 301 {
 302     icp_pic_state *s = (icp_pic_state *)opaque;
 303
 304     switch (offset >> 2) {
 305     case 0: /* IRQ_STATUS */
 306         return s->level & s->irq_enabled;
 307     case 1: /* IRQ_RAWSTAT */
 308         return s->level;
 309     case 2: /* IRQ_ENABLESET */
 310         return s->irq_enabled;
 311     case 4: /* INT_SOFTSET */
 312         return s->level & 1;
 313     case 8: /* FRQ_STATUS */
 314         return s->level & s->fiq_enabled;
 315     case 9: /* FRQ_RAWSTAT */
 316         return s->level;
 317     case 10: /* FRQ_ENABLESET */
 318         return s->fiq_enabled;
 319     case 3: /* IRQ_ENABLECLR */
 320     case 5: /* INT_SOFTCLR */
 321     case 11: /* FRQ_ENABLECLR */
 322     default:
 323         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
 324         return 0;
 325     }
 326 }
 327
 328 static void icp_pic_write(void *opaque, target_phys_addr_t offset,
 329                           uint64_t value, unsigned size)
 330 {
 331     icp_pic_state *s = (icp_pic_state *)opaque;
 332
 333     switch (offset >> 2) {
 334     case 2: /* IRQ_ENABLESET */
 335         s->irq_enabled |= value;
 336         break;
 337     case 3: /* IRQ_ENABLECLR */
 338         s->irq_enabled &= ~value;
 339         break;
 340     case 4: /* INT_SOFTSET */
 341         if (value & 1)
 342             icp_pic_set_irq(s, 0, 1);
 343         break;
 344     case 5: /* INT_SOFTCLR */
 345         if (value & 1)
 346             icp_pic_set_irq(s, 0, 0);
 347         break;
 348     case 10: /* FRQ_ENABLESET */
 349         s->fiq_enabled |= value;
 350         break;
 351     case 11: /* FRQ_ENABLECLR */
 352         s->fiq_enabled &= ~value;
 353         break;
 354     case 0: /* IRQ_STATUS */
 355     case 1: /* IRQ_RAWSTAT */
 356     case 8: /* FRQ_STATUS */
 357     case 9: /* FRQ_RAWSTAT */
 358     default:
 359         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
 360         return;
 361     }
 362     icp_pic_update(s);
 363 }
 364
 365 static const MemoryRegionOps icp_pic_ops = {
 366     .read = icp_pic_read,
 367     .write = icp_pic_write,
 368     .endianness = DEVICE_NATIVE_ENDIAN,
 369 };
 370
 371 static int icp_pic_init(SysBusDevice *dev)
 372 {
 373     icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
 374
 375     qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
 376     sysbus_init_irq(dev, &s->parent_irq);
 377     sysbus_init_irq(dev, &s->parent_fiq);
 378     memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000);
 379     sysbus_init_mmio(dev, &s->iomem);
 380     return 0;
 381 }
 382
 383 /* CP control registers.  */
 384
 385 static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
 386                                  unsigned size)
 387 {
 388     switch (offset >> 2) {
 389     case 0: /* CP_IDFIELD */
 390         return 0x41034003;
 391     case 1: /* CP_FLASHPROG */
 392         return 0;
 393     case 2: /* CP_INTREG */
 394         return 0;
 395     case 3: /* CP_DECODE */
 396         return 0x11;
 397     default:
 398         hw_error("icp_control_read: Bad offset %x\n", (int)offset);
 399         return 0;
 400     }
 401 }
 402
 403 static void icp_control_write(void *opaque, target_phys_addr_t offset,
 404                           uint64_t value, unsigned size)
 405 {
 406     switch (offset >> 2) {
 407     case 1: /* CP_FLASHPROG */
 408     case 2: /* CP_INTREG */
 409     case 3: /* CP_DECODE */
 410         /* Nothing interesting implemented yet.  */
 411         break;
 412     default:
 413         hw_error("icp_control_write: Bad offset %x\n", (int)offset);
 414     }
 415 }
 416
 417 static const MemoryRegionOps icp_control_ops = {
 418     .read = icp_control_read,
 419     .write = icp_control_write,
 420     .endianness = DEVICE_NATIVE_ENDIAN,
 421 };
 422
 423 static void icp_control_init(target_phys_addr_t base)
 424 {
 425     MemoryRegion *io;
 426
 427     io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion));
 428     memory_region_init_io(io, &icp_control_ops, NULL,
 429                           "control", 0x00800000);
 430     memory_region_add_subregion(get_system_memory(), base, io);
 431     /* ??? Save/restore.  */
 432 }
 433
 434
 435 /* Board init.  */
 436
 437 static struct arm_boot_info integrator_binfo = {
 438     .loader_start = 0x0,
 439     .board_id = 0x113,
 440 };
 441
 442 static void integratorcp_init(ram_addr_t ram_size,
 443                      const char *boot_device,
 444                      const char *kernel_filename, const char *kernel_cmdline,
 445                      const char *initrd_filename, const char *cpu_model)
 446 {
 447     CPUState *env;
 448     MemoryRegion *address_space_mem = get_system_memory();
 449     MemoryRegion *ram = g_new(MemoryRegion, 1);
 450     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 451     qemu_irq pic[32];
 452     qemu_irq *cpu_pic;
 453     DeviceState *dev;
 454     int i;
 455
 456     if (!cpu_model)
 457         cpu_model = "arm926";
 458     env = cpu_init(cpu_model);
 459     if (!env) {
 460         fprintf(stderr, "Unable to find CPU definition\n");
 461         exit(1);
 462     }
 463     memory_region_init_ram(ram, "integrator.ram", ram_size);
 464     vmstate_register_ram_global(ram);
 465     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 466     /* ??? RAM should repeat to fill physical memory space.  */
 467     /* SDRAM at address zero*/
 468     memory_region_add_subregion(address_space_mem, 0, ram);
 469     /* And again at address 0x80000000 */
 470     memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
 471     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
 472
 473     dev = qdev_create(NULL, "integrator_core");
 474     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 475     qdev_init_nofail(dev);
 476     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 477
 478     cpu_pic = arm_pic_init_cpu(env);
 479     dev = sysbus_create_varargs("integrator_pic", 0x14000000,
 480                                 cpu_pic[ARM_PIC_CPU_IRQ],
 481                                 cpu_pic[ARM_PIC_CPU_FIQ], NULL);
 482     for (i = 0; i < 32; i++) {
 483         pic[i] = qdev_get_gpio_in(dev, i);
 484     }
 485     sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
 486     sysbus_create_varargs("integrator_pit", 0x13000000,
 487                           pic[5], pic[6], pic[7], NULL);
 488     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 489     sysbus_create_simple("pl011", 0x16000000, pic[1]);
 490     sysbus_create_simple("pl011", 0x17000000, pic[2]);
 491     icp_control_init(0xcb000000);
 492     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 493     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 494     sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 495     if (nd_table[0].vlan)
 496         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 497
 498     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
 499
 500     integrator_binfo.ram_size = ram_size;
 501     integrator_binfo.kernel_filename = kernel_filename;
 502     integrator_binfo.kernel_cmdline = kernel_cmdline;
 503     integrator_binfo.initrd_filename = initrd_filename;
 504     arm_load_kernel(env, &integrator_binfo);
 505 }
 506
 507 static QEMUMachine integratorcp_machine = {
 508     .name = "integratorcp",
 509     .desc = "ARM Integrator/CP (ARM926EJ-S)",
 510     .init = integratorcp_init,
 511     .is_default = 1,
 512 };
 513
 514 static void integratorcp_machine_init(void)
 515 {
 516     qemu_register_machine(&integratorcp_machine);
 517 }
 518
 519 machine_init(integratorcp_machine_init);
 520
 521 static Property core_properties[] = {
 522     DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0),
 523     DEFINE_PROP_END_OF_LIST(),
 524 };
 525
 526 static void core_class_init(ObjectClass *klass, void *data)
 527 {
 528     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 529
 530     k->init = integratorcm_init;
 531 }
 532
 533 static DeviceInfo core_info = {
 534     .name = "integrator_core",
 535     .size = sizeof(integratorcm_state),
 536     .props = core_properties,
 537     .class_init = core_class_init,
 538 };
 539
 540 static void icp_pic_class_init(ObjectClass *klass, void *data)
 541 {
 542     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 543
 544     sdc->init = icp_pic_init;
 545 }
 546
 547 static DeviceInfo icp_pic_info = {
 548     .name = "integrator_pic",
 549     .size = sizeof(icp_pic_state),
 550     .class_init = icp_pic_class_init,
 551 };
 552
 553 static void integratorcp_register_devices(void)
 554 {
 555     sysbus_qdev_register(&icp_pic_info);
 556     sysbus_register_withprop(&core_info);
 557 }
 558
 559 device_init(integratorcp_register_devices)