hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "monitor.h"
  28 #include "qemu-timer.h"
  29 #include "i8259_internal.h"
  30
  31 #include "kvm.h"
  32 #include "apic_internal.h"
  33
  34 static void kvm_i8259_set_irq(void *opaque, int irq, int level);
  35
  36 /* debug PIC */
  37 //#define DEBUG_PIC
  38
  39 #ifdef DEBUG_PIC
  40 #define DPRINTF(fmt, ...)                                       \
  41     do { printf("pic: " fmt , ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...)
  44 #endif
  45
  46 //#define DEBUG_IRQ_LATENCY
  47 //#define DEBUG_IRQ_COUNT
  48
  49 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
  50 static int irq_level[16];
  51 #endif
  52 #ifdef DEBUG_IRQ_COUNT
  53 static uint64_t irq_count[16];
  54 #endif
  55 #ifdef DEBUG_IRQ_LATENCY
  56 static int64_t irq_time[16];
  57 #endif
  58 DeviceState *isa_pic;
  59 static PICCommonState *slave_pic;
  60
  61 /* return the highest priority found in mask (highest = smallest
  62    number). Return 8 if no irq */
  63 static int get_priority(PICCommonState *s, int mask)
  64 {
  65     int priority;
  66
  67     if (mask == 0) {
  68         return 8;
  69     }
  70     priority = 0;
  71     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) {
  72         priority++;
  73     }
  74     return priority;
  75 }
  76
  77 /* return the pic wanted interrupt. return -1 if none */
  78 static int pic_get_irq(PICCommonState *s)
  79 {
  80     int mask, cur_priority, priority;
  81
  82     mask = s->irr & ~s->imr;
  83     priority = get_priority(s, mask);
  84     if (priority == 8) {
  85         return -1;
  86     }
  87     /* compute current priority. If special fully nested mode on the
  88        master, the IRQ coming from the slave is not taken into account
  89        for the priority computation. */
  90     mask = s->isr;
  91     if (s->special_mask) {
  92         mask &= ~s->imr;
  93     }
  94     if (s->special_fully_nested_mode && s->master) {
  95         mask &= ~(1 << 2);
  96     }
  97     cur_priority = get_priority(s, mask);
  98     if (priority < cur_priority) {
  99         /* higher priority found: an irq should be generated */
 100         return (priority + s->priority_add) & 7;
 101     } else {
 102         return -1;
 103     }
 104 }
 105
 106 /* Update INT output. Must be called every time the output may have changed. */
 107 static void pic_update_irq(PICCommonState *s)
 108 {
 109     int irq;
 110
 111     irq = pic_get_irq(s);
 112     if (irq >= 0) {
 113         DPRINTF("pic%d: imr=%x irr=%x padd=%d\n",
 114                 s->master ? 0 : 1, s->imr, s->irr, s->priority_add);
 115         qemu_irq_raise(s->int_out[0]);
 116     } else {
 117         qemu_irq_lower(s->int_out[0]);
 118     }
 119 }
 120
 121 /* set irq level. If an edge is detected, then the IRR is set to 1 */
 122 static void pic_set_irq(void *opaque, int irq, int level)
 123 {
 124     PICCommonState *s = opaque;
 125     int mask = 1 << irq;
 126
 127 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT) || \
 128     defined(DEBUG_IRQ_LATENCY)
 129     int irq_index = s->master ? irq : irq + 8;
 130 #endif
 131 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 132     if (level != irq_level[irq_index]) {
 133         DPRINTF("pic_set_irq: irq=%d level=%d\n", irq_index, level);
 134         irq_level[irq_index] = level;
 135 #ifdef DEBUG_IRQ_COUNT
 136         if (level == 1) {
 137             irq_count[irq_index]++;
 138         }
 139 #endif
 140     }
 141 #endif
 142 #ifdef DEBUG_IRQ_LATENCY
 143     if (level) {
 144         irq_time[irq_index] = qemu_get_clock_ns(vm_clock);
 145     }
 146 #endif
 147
 148     if (s->elcr & mask) {
 149         /* level triggered */
 150         if (level) {
 151             s->irr |= mask;
 152             s->last_irr |= mask;
 153         } else {
 154             s->irr &= ~mask;
 155             s->last_irr &= ~mask;
 156         }
 157     } else {
 158         /* edge triggered */
 159         if (level) {
 160             if ((s->last_irr & mask) == 0) {
 161                 s->irr |= mask;
 162             }
 163             s->last_irr |= mask;
 164         } else {
 165             s->last_irr &= ~mask;
 166         }
 167     }
 168     pic_update_irq(s);
 169 }
 170
 171 /* acknowledge interrupt 'irq' */
 172 static void pic_intack(PICCommonState *s, int irq)
 173 {
 174     if (s->auto_eoi) {
 175         if (s->rotate_on_auto_eoi) {
 176             s->priority_add = (irq + 1) & 7;
 177         }
 178     } else {
 179         s->isr |= (1 << irq);
 180     }
 181     /* We don't clear a level sensitive interrupt here */
 182     if (!(s->elcr & (1 << irq))) {
 183         s->irr &= ~(1 << irq);
 184     }
 185     pic_update_irq(s);
 186 }
 187
 188 int pic_read_irq(DeviceState *d)
 189 {
 190     PICCommonState *s = DO_UPCAST(PICCommonState, dev.qdev, d);
 191     int irq, irq2, intno;
 192
 193     irq = pic_get_irq(s);
 194     if (irq >= 0) {
 195         if (irq == 2) {
 196             irq2 = pic_get_irq(slave_pic);
 197             if (irq2 >= 0) {
 198                 pic_intack(slave_pic, irq2);
 199             } else {
 200                 /* spurious IRQ on slave controller */
 201                 irq2 = 7;
 202             }
 203             intno = slave_pic->irq_base + irq2;
 204         } else {
 205             intno = s->irq_base + irq;
 206         }
 207         pic_intack(s, irq);
 208     } else {
 209         /* spurious IRQ on host controller */
 210         irq = 7;
 211         intno = s->irq_base + irq;
 212     }
 213
 214 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_LATENCY)
 215     if (irq == 2) {
 216         irq = irq2 + 8;
 217     }
 218 #endif
 219 #ifdef DEBUG_IRQ_LATENCY
 220     printf("IRQ%d latency=%0.3fus\n",
 221            irq,
 222            (double)(qemu_get_clock_ns(vm_clock) -
 223                     irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
 224 #endif
 225     DPRINTF("pic_interrupt: irq=%d\n", irq);
 226     return intno;
 227 }
 228
 229 static int kvm_kernel_pic_load_from_user(PICCommonState *s);
 230
 231 static void pic_init_reset(PICCommonState *s)
 232 {
 233     pic_reset_common(s);
 234
 235     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 236         kvm_kernel_pic_load_from_user(s);
 237         return;
 238     }
 239
 240     pic_update_irq(s);
 241 }
 242
 243 static void pic_reset(DeviceState *dev)
 244 {
 245     PICCommonState *s = DO_UPCAST(PICCommonState, dev.qdev, dev);
 246
 247     pic_init_reset(s);
 248     s->elcr = 0;
 249 }
 250
 251 static void pic_ioport_write(void *opaque, target_phys_addr_t addr64,
 252                              uint64_t val64, unsigned size)
 253 {
 254     PICCommonState *s = opaque;
 255     uint32_t addr = addr64;
 256     uint32_t val = val64;
 257     int priority, cmd, irq;
 258
 259     DPRINTF("write: addr=0x%02x val=0x%02x\n", addr, val);
 260     if (addr == 0) {
 261         if (val & 0x10) {
 262             pic_init_reset(s);
 263             s->init_state = 1;
 264             s->init4 = val & 1;
 265             s->single_mode = val & 2;
 266             if (val & 0x08) {
 267                 hw_error("level sensitive irq not supported");
 268             }
 269         } else if (val & 0x08) {
 270             if (val & 0x04) {
 271                 s->poll = 1;
 272             }
 273             if (val & 0x02) {
 274                 s->read_reg_select = val & 1;
 275             }
 276             if (val & 0x40) {
 277                 s->special_mask = (val >> 5) & 1;
 278             }
 279         } else {
 280             cmd = val >> 5;
 281             switch (cmd) {
 282             case 0:
 283             case 4:
 284                 s->rotate_on_auto_eoi = cmd >> 2;
 285                 break;
 286             case 1: /* end of interrupt */
 287             case 5:
 288                 priority = get_priority(s, s->isr);
 289                 if (priority != 8) {
 290                     irq = (priority + s->priority_add) & 7;
 291                     s->isr &= ~(1 << irq);
 292                     if (cmd == 5) {
 293                         s->priority_add = (irq + 1) & 7;
 294                     }
 295                     pic_update_irq(s);
 296                 }
 297                 break;
 298             case 3:
 299                 irq = val & 7;
 300                 s->isr &= ~(1 << irq);
 301                 pic_update_irq(s);
 302                 break;
 303             case 6:
 304                 s->priority_add = (val + 1) & 7;
 305                 pic_update_irq(s);
 306                 break;
 307             case 7:
 308                 irq = val & 7;
 309                 s->isr &= ~(1 << irq);
 310                 s->priority_add = (irq + 1) & 7;
 311                 pic_update_irq(s);
 312                 break;
 313             default:
 314                 /* no operation */
 315                 break;
 316             }
 317         }
 318     } else {
 319         switch (s->init_state) {
 320         case 0:
 321             /* normal mode */
 322             s->imr = val;
 323             pic_update_irq(s);
 324             break;
 325         case 1:
 326             s->irq_base = val & 0xf8;
 327             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 328             break;
 329         case 2:
 330             if (s->init4) {
 331                 s->init_state = 3;
 332             } else {
 333                 s->init_state = 0;
 334             }
 335             break;
 336         case 3:
 337             s->special_fully_nested_mode = (val >> 4) & 1;
 338             s->auto_eoi = (val >> 1) & 1;
 339             s->init_state = 0;
 340             break;
 341         }
 342     }
 343 }
 344
 345 static uint64_t pic_ioport_read(void *opaque, target_phys_addr_t addr,
 346                                 unsigned size)
 347 {
 348     PICCommonState *s = opaque;
 349     int ret;
 350
 351     if (s->poll) {
 352         ret = pic_get_irq(s);
 353         if (ret >= 0) {
 354             pic_intack(s, ret);
 355             ret |= 0x80;
 356         } else {
 357             ret = 0;
 358         }
 359         s->poll = 0;
 360     } else {
 361         if (addr == 0) {
 362             if (s->read_reg_select) {
 363                 ret = s->isr;
 364             } else {
 365                 ret = s->irr;
 366             }
 367         } else {
 368             ret = s->imr;
 369         }
 370     }
 371     DPRINTF("read: addr=0x%02x val=0x%02x\n", addr, ret);
 372     return ret;
 373 }
 374
 375 int pic_get_output(DeviceState *d)
 376 {
 377     PICCommonState *s = DO_UPCAST(PICCommonState, dev.qdev, d);
 378
 379     return (pic_get_irq(s) >= 0);
 380 }
 381
 382 static void elcr_ioport_write(void *opaque, target_phys_addr_t addr,
 383                               uint64_t val, unsigned size)
 384 {
 385     PICCommonState *s = opaque;
 386     s->elcr = val & s->elcr_mask;
 387 }
 388
 389 static uint64_t elcr_ioport_read(void *opaque, target_phys_addr_t addr,
 390                                  unsigned size)
 391 {
 392     PICCommonState *s = opaque;
 393     return s->elcr;
 394 }
 395
 396 static void kvm_kernel_pic_save_to_user(PICCommonState *s);
 397
 398 static void kvm_pic_pre_save(PICCommonState *s)
 399 {
 400     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 401         kvm_kernel_pic_save_to_user(s);
 402     }
 403 }
 404
 405 static void kvm_pic_post_load(PICCommonState *s)
 406 {
 407     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 408         kvm_kernel_pic_load_from_user(s);
 409     }
 410 }
 411
 412 static const MemoryRegionOps pic_base_ioport_ops = {
 413     .read = pic_ioport_read,
 414     .write = pic_ioport_write,
 415     .impl = {
 416         .min_access_size = 1,
 417         .max_access_size = 1,
 418     },
 419 };
 420
 421 static const MemoryRegionOps pic_elcr_ioport_ops = {
 422     .read = elcr_ioport_read,
 423     .write = elcr_ioport_write,
 424     .impl = {
 425         .min_access_size = 1,
 426         .max_access_size = 1,
 427     },
 428 };
 429
 430 static void pic_init(PICCommonState *s)
 431 {
 432     memory_region_init_io(&s->base_io, &pic_base_ioport_ops, s, "pic", 2);
 433     memory_region_init_io(&s->elcr_io, &pic_elcr_ioport_ops, s, "elcr", 1);
 434
 435     qdev_init_gpio_out(&s->dev.qdev, s->int_out, ARRAY_SIZE(s->int_out));
 436     qdev_init_gpio_in(&s->dev.qdev, pic_set_irq, 8);
 437 }
 438
 439 void pic_info(Monitor *mon)
 440 {
 441     int i;
 442     PICCommonState *s;
 443
 444     if (!isa_pic) {
 445         return;
 446     }
 447     for (i = 0; i < 2; i++) {
 448         s = i == 0 ? DO_UPCAST(PICCommonState, dev.qdev, isa_pic) : slave_pic;
 449         monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
 450                        "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 451                        i, s->irr, s->imr, s->isr, s->priority_add,
 452                        s->irq_base, s->read_reg_select, s->elcr,
 453                        s->special_fully_nested_mode);
 454     }
 455 }
 456
 457 void irq_info(Monitor *mon)
 458 {
 459 #ifndef DEBUG_IRQ_COUNT
 460     monitor_printf(mon, "irq statistic code not compiled.\n");
 461 #else
 462     int i;
 463     int64_t count;
 464
 465     monitor_printf(mon, "IRQ statistics:\n");
 466     for (i = 0; i < 16; i++) {
 467         count = irq_count[i];
 468         if (count > 0) {
 469             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 470         }
 471     }
 472 #endif
 473 }
 474
 475 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
 476 {
 477     qemu_irq *irq_set;
 478     ISADevice *dev;
 479     int i;
 480
 481     irq_set = g_malloc(ISA_NUM_IRQS * sizeof(qemu_irq));
 482
 483     dev = i8259_init_chip("isa-i8259", bus, true);
 484
 485     qdev_connect_gpio_out(&dev->qdev, 0, parent_irq);
 486     for (i = 0 ; i < 8; i++) {
 487         irq_set[i] = qdev_get_gpio_in(&dev->qdev, i);
 488     }
 489
 490     isa_pic = &dev->qdev;
 491
 492     dev = i8259_init_chip("isa-i8259", bus, false);
 493
 494     qdev_connect_gpio_out(&dev->qdev, 0, irq_set[2]);
 495     for (i = 0 ; i < 8; i++) {
 496         irq_set[i + 8] = qdev_get_gpio_in(&dev->qdev, i);
 497     }
 498
 499     slave_pic = DO_UPCAST(PICCommonState, dev, dev);
 500
 501     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 502         irq_set = qemu_allocate_irqs(kvm_i8259_set_irq, NULL, 24);
 503     }
 504
 505     return irq_set;
 506 }
 507
 508 static void i8259_class_init(ObjectClass *klass, void *data)
 509 {
 510     PICCommonClass *k = PIC_COMMON_CLASS(klass);
 511
 512     k->init = pic_init;
 513     k->pre_save  = kvm_pic_pre_save;
 514     k->post_load = kvm_pic_post_load;
 515 }
 516
 517 static DeviceInfo i8259_info = {
 518     .name  = "isa-i8259",
 519     .reset = pic_reset,
 520     .class_init = i8259_class_init,
 521 };
 522
 523 static void pic_register(void)
 524 {
 525     pic_qdev_register(&i8259_info);
 526 }
 527
 528 static void kvm_kernel_pic_save_to_user(PICCommonState *s)
 529 {
 530 #ifdef KVM_CAP_IRQCHIP
 531     struct kvm_irqchip chip;
 532     struct kvm_pic_state *kpic;
 533
 534     chip.chip_id = s->master ?
 535                    KVM_IRQCHIP_PIC_MASTER :
 536                    KVM_IRQCHIP_PIC_SLAVE;
 537     kvm_get_irqchip(kvm_state, &chip);
 538     kpic = &chip.chip.pic;
 539
 540     s->last_irr = kpic->last_irr;
 541     s->irr = kpic->irr;
 542     s->imr = kpic->imr;
 543     s->isr = kpic->isr;
 544     s->priority_add = kpic->priority_add;
 545     s->irq_base = kpic->irq_base;
 546     s->read_reg_select = kpic->read_reg_select;
 547     s->poll = kpic->poll;
 548     s->special_mask = kpic->special_mask;
 549     s->init_state = kpic->init_state;
 550     s->auto_eoi = kpic->auto_eoi;
 551     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 552     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 553     s->init4 = kpic->init4;
 554     s->elcr = kpic->elcr;
 555     s->elcr_mask = kpic->elcr_mask;
 556 #endif
 557 }
 558
 559 static int kvm_kernel_pic_load_from_user(PICCommonState *s)
 560 {
 561 #ifdef KVM_CAP_IRQCHIP
 562     struct kvm_irqchip chip;
 563     struct kvm_pic_state *kpic;
 564
 565     chip.chip_id = s->master ?
 566                    KVM_IRQCHIP_PIC_MASTER :
 567                    KVM_IRQCHIP_PIC_SLAVE;
 568     kpic = &chip.chip.pic;
 569
 570     kpic->last_irr = s->last_irr;
 571     kpic->irr = s->irr;
 572     kpic->imr = s->imr;
 573     kpic->isr = s->isr;
 574     kpic->priority_add = s->priority_add;
 575     kpic->irq_base = s->irq_base;
 576     kpic->read_reg_select = s->read_reg_select;
 577     kpic->poll = s->poll;
 578     kpic->special_mask = s->special_mask;
 579     kpic->init_state = s->init_state;
 580     kpic->auto_eoi = s->auto_eoi;
 581     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 582     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 583     kpic->init4 = s->init4;
 584     kpic->elcr = s->elcr;
 585     kpic->elcr_mask = s->elcr_mask;
 586
 587     kvm_set_irqchip(kvm_state, &chip);
 588 #endif
 589     return 0;
 590 }
 591
 592 static void kvm_i8259_set_irq(void *opaque, int irq, int level)
 593 {
 594     int pic_ret;
 595     if (kvm_set_irq(irq, level, &pic_ret)) {
 596         apic_report_irq_delivered(pic_ret);
 597         return;
 598     }
 599 }
 600
 601 device_init(pic_register)