hw/i82378.c

   1 /*
   2  * QEMU Intel i82378 emulation (PCI to ISA bridge)
   3  *
   4  * Copyright (c) 2010-2011 Hervé Poussineau
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "pci.h"
  21 #include "pc.h"
  22
  23 //#define DEBUG_I82378
  24
  25 #ifdef DEBUG_I82378
  26 #define DPRINTF(fmt, ...) \
  27 do { fprintf(stderr, "i82378: " fmt , ## __VA_ARGS__); } while (0)
  28 #else
  29 #define DPRINTF(fmt, ...) \
  30 do {} while (0)
  31 #endif
  32
  33 #define BADF(fmt, ...) \
  34 do { fprintf(stderr, "i82378 ERROR: " fmt , ## __VA_ARGS__); } while (0)
  35
  36 typedef struct I82378State {
  37     qemu_irq out[2];
  38     qemu_irq *i8259;
  39     MemoryRegion io;
  40     MemoryRegion mem;
  41 } I82378State;
  42
  43 typedef struct PCIi82378State {
  44     PCIDevice pci_dev;
  45     uint32_t isa_io_base;
  46     uint32_t isa_mem_base;
  47     I82378State state;
  48 } PCIi82378State;
  49
  50 static const VMStateDescription vmstate_pci_i82378 = {
  51     .name = "pci-i82378",
  52     .version_id = 0,
  53     .minimum_version_id = 0,
  54     .fields = (VMStateField[]) {
  55         VMSTATE_PCI_DEVICE(pci_dev, PCIi82378State),
  56         VMSTATE_END_OF_LIST()
  57     },
  58 };
  59
  60 static void i82378_io_write(void *opaque, target_phys_addr_t addr,
  61                             uint64_t value, unsigned int size)
  62 {
  63     switch (size) {
  64     case 1:
  65         DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
  66                 addr, value);
  67         cpu_outb(addr, value);
  68         break;
  69     case 2:
  70         DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
  71                 addr, value);
  72         cpu_outw(addr, value);
  73         break;
  74     case 4:
  75         DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
  76                 addr, value);
  77         cpu_outl(addr, value);
  78         break;
  79     default:
  80         abort();
  81     }
  82 }
  83
  84 static uint64_t i82378_io_read(void *opaque, target_phys_addr_t addr,
  85                                unsigned int size)
  86 {
  87     DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
  88     switch (size) {
  89     case 1:
  90         return cpu_inb(addr);
  91     case 2:
  92         return cpu_inw(addr);
  93     case 4:
  94         return cpu_inl(addr);
  95     default:
  96         abort();
  97     }
  98 }
  99
 100 static const MemoryRegionOps i82378_io_ops = {
 101     .read = i82378_io_read,
 102     .write = i82378_io_write,
 103     .endianness = DEVICE_LITTLE_ENDIAN,
 104 };
 105
 106 static void i82378_mem_write(void *opaque, target_phys_addr_t addr,
 107                              uint64_t value, unsigned int size)
 108 {
 109     switch (size) {
 110     case 1:
 111         DPRINTF("%s: " TARGET_FMT_plx "=%02" PRIx64 "\n", __func__,
 112                 addr, value);
 113         cpu_outb(addr, value);
 114         break;
 115     case 2:
 116         DPRINTF("%s: " TARGET_FMT_plx "=%04" PRIx64 "\n", __func__,
 117                 addr, value);
 118         cpu_outw(addr, value);
 119         break;
 120     case 4:
 121         DPRINTF("%s: " TARGET_FMT_plx "=%08" PRIx64 "\n", __func__,
 122                 addr, value);
 123         cpu_outl(addr, value);
 124         break;
 125     default:
 126         abort();
 127     }
 128 }
 129
 130 static uint64_t i82378_mem_read(void *opaque, target_phys_addr_t addr,
 131                                 unsigned int size)
 132 {
 133     DPRINTF("%s: " TARGET_FMT_plx "\n", __func__, addr);
 134     switch (size) {
 135     case 1:
 136         return cpu_inb(addr);
 137     case 2:
 138         return cpu_inw(addr);
 139     case 4:
 140         return cpu_inl(addr);
 141     default:
 142         abort();
 143     }
 144 }
 145
 146 static const MemoryRegionOps i82378_mem_ops = {
 147     .read = i82378_mem_read,
 148     .write = i82378_mem_write,
 149     .endianness = DEVICE_LITTLE_ENDIAN,
 150 };
 151
 152 static void i82378_request_out0_irq(void *opaque, int irq, int level)
 153 {
 154     I82378State *s = opaque;
 155     qemu_set_irq(s->out[0], level);
 156 }
 157
 158 static void i82378_request_pic_irq(void *opaque, int irq, int level)
 159 {
 160     DeviceState *dev = opaque;
 161     PCIDevice *pci = DO_UPCAST(PCIDevice, qdev, dev);
 162     PCIi82378State *s = DO_UPCAST(PCIi82378State, pci_dev, pci);
 163
 164     qemu_set_irq(s->state.i8259[irq], level);
 165 }
 166
 167 static void i82378_init(DeviceState *dev, I82378State *s)
 168 {
 169     ISABus *isabus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(dev, "isa.0"));
 170     ISADevice *pit;
 171     qemu_irq *out0_irq;
 172
 173     /* This device has:
 174        2 82C59 (irq)
 175        1 82C54 (pit)
 176        2 82C37 (dma)
 177        NMI
 178        Utility Bus Support Registers
 179
 180        All devices accept byte access only, except timer
 181      */
 182
 183     qdev_init_gpio_out(dev, s->out, 2);
 184     qdev_init_gpio_in(dev, i82378_request_pic_irq, 16);
 185
 186     /* Workaround the fact that i8259 is not qdev'ified... */
 187     out0_irq = qemu_allocate_irqs(i82378_request_out0_irq, s, 1);
 188
 189     /* 2 82C59 (irq) */
 190     s->i8259 = i8259_init(isabus, *out0_irq);
 191     isa_bus_irqs(isabus, s->i8259);
 192
 193     /* 1 82C54 (pit) */
 194     pit = pit_init(isabus, 0x40, 0);
 195
 196     /* speaker */
 197     pcspk_init(pit);
 198
 199     /* 2 82C37 (dma) */
 200     DMA_init(1, &s->out[1]);
 201     isa_create_simple(isabus, "i82374");
 202
 203     /* timer */
 204     isa_create_simple(isabus, "mc146818rtc");
 205 }
 206
 207 static int pci_i82378_init(PCIDevice *dev)
 208 {
 209     PCIi82378State *pci = DO_UPCAST(PCIi82378State, pci_dev, dev);
 210     I82378State *s = &pci->state;
 211     uint8_t *pci_conf;
 212
 213     pci_conf = dev->config;
 214     pci_set_word(pci_conf + PCI_COMMAND,
 215                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 216     pci_set_word(pci_conf + PCI_STATUS,
 217                  PCI_STATUS_DEVSEL_MEDIUM);
 218
 219     pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
 220
 221     memory_region_init_io(&s->io, &i82378_io_ops, s, "i82378-io", 0x00010000);
 222     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io);
 223
 224     memory_region_init_io(&s->mem, &i82378_mem_ops, s, "i82378-mem", 0x01000000);
 225     memory_region_set_coalescing(&s->mem);
 226     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
 227
 228     /* Make I/O address read only */
 229     pci_set_word(dev->wmask + PCI_COMMAND, PCI_COMMAND_SPECIAL);
 230     pci_set_long(dev->wmask + PCI_BASE_ADDRESS_0, 0);
 231     pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, pci->isa_io_base);
 232
 233     isa_mem_base = pci->isa_mem_base;
 234     isa_bus_new(&dev->qdev, pci_address_space_io(dev));
 235
 236     i82378_init(&dev->qdev, s);
 237
 238     return 0;
 239 }
 240
 241 static void pci_i82378_class_init(ObjectClass *klass, void *data)
 242 {
 243     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 244
 245     k->init = pci_i82378_init;
 246     k->vendor_id = PCI_VENDOR_ID_INTEL;
 247     k->device_id = PCI_DEVICE_ID_INTEL_82378;
 248     k->revision = 0x03;
 249     k->class_id = PCI_CLASS_BRIDGE_ISA;
 250     k->subsystem_vendor_id = 0x0;
 251     k->subsystem_id = 0x0;
 252 }
 253
 254 static DeviceInfo pci_i82378_info = {
 255     .name = "i82378",
 256     .size = sizeof(PCIi82378State),
 257     .vmsd = &vmstate_pci_i82378,
 258     .class_init = pci_i82378_class_init,
 259     .props = (Property[]) {
 260         DEFINE_PROP_HEX32("iobase", PCIi82378State, isa_io_base, 0x80000000),
 261         DEFINE_PROP_HEX32("membase", PCIi82378State, isa_mem_base, 0xc0000000),
 262         DEFINE_PROP_END_OF_LIST()
 263     },
 264 };
 265
 266 static void i82378_register_devices(void)
 267 {
 268     pci_qdev_register(&pci_i82378_info);
 269 }
 270
 271 device_init(i82378_register_devices)