hw/hpet.c

   1 /*
   2  *  High Precisition Event Timer emulation
   3  *
   4  *  Copyright (c) 2007 Alexander Graf
   5  *  Copyright (c) 2008 IBM Corporation
   6  *
   7  *  Authors: Beth Kon <bkon@us.ibm.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  *
  22  * *****************************************************************
  23  *
  24  * This driver attempts to emulate an HPET device in software.
  25  */
  26
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30 #include "qemu-timer.h"
  31 #include "hpet_emul.h"
  32 #include "sysbus.h"
  33 #include "mc146818rtc.h"
  34
  35 //#define HPET_DEBUG
  36 #ifdef HPET_DEBUG
  37 #define DPRINTF printf
  38 #else
  39 #define DPRINTF(...)
  40 #endif
  41
  42 #define HPET_MSI_SUPPORT        0
  43
  44 struct HPETState;
  45 typedef struct HPETTimer {  /* timers */
  46     uint8_t tn;             /*timer number*/
  47     QEMUTimer *qemu_timer;
  48     struct HPETState *state;
  49     /* Memory-mapped, software visible timer registers */
  50     uint64_t config;        /* configuration/cap */
  51     uint64_t cmp;           /* comparator */
  52     uint64_t fsb;           /* FSB route */
  53     /* Hidden register state */
  54     uint64_t period;        /* Last value written to comparator */
  55     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
  56                              * mode. Next pop will be actual timer expiration.
  57                              */
  58 } HPETTimer;
  59
  60 typedef struct HPETState {
  61     SysBusDevice busdev;
  62     MemoryRegion iomem;
  63     uint64_t hpet_offset;
  64     qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
  65     uint32_t flags;
  66     uint8_t rtc_irq_level;
  67     uint8_t num_timers;
  68     HPETTimer timer[HPET_MAX_TIMERS];
  69
  70     /* Memory-mapped, software visible registers */
  71     uint64_t capability;        /* capabilities */
  72     uint64_t config;            /* configuration */
  73     uint64_t isr;               /* interrupt status reg */
  74     uint64_t hpet_counter;      /* main counter */
  75     uint8_t  hpet_id;           /* instance id */
  76 } HPETState;
  77
  78 static uint32_t hpet_in_legacy_mode(HPETState *s)
  79 {
  80     return s->config & HPET_CFG_LEGACY;
  81 }
  82
  83 static uint32_t timer_int_route(struct HPETTimer *timer)
  84 {
  85     return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  86 }
  87
  88 static uint32_t timer_fsb_route(HPETTimer *t)
  89 {
  90     return t->config & HPET_TN_FSB_ENABLE;
  91 }
  92
  93 static uint32_t hpet_enabled(HPETState *s)
  94 {
  95     return s->config & HPET_CFG_ENABLE;
  96 }
  97
  98 static uint32_t timer_is_periodic(HPETTimer *t)
  99 {
 100     return t->config & HPET_TN_PERIODIC;
 101 }
 102
 103 static uint32_t timer_enabled(HPETTimer *t)
 104 {
 105     return t->config & HPET_TN_ENABLE;
 106 }
 107
 108 static uint32_t hpet_time_after(uint64_t a, uint64_t b)
 109 {
 110     return ((int32_t)(b) - (int32_t)(a) < 0);
 111 }
 112
 113 static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
 114 {
 115     return ((int64_t)(b) - (int64_t)(a) < 0);
 116 }
 117
 118 static uint64_t ticks_to_ns(uint64_t value)
 119 {
 120     return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
 121 }
 122
 123 static uint64_t ns_to_ticks(uint64_t value)
 124 {
 125     return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
 126 }
 127
 128 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
 129 {
 130     new &= mask;
 131     new |= old & ~mask;
 132     return new;
 133 }
 134
 135 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
 136 {
 137     return (!(old & mask) && (new & mask));
 138 }
 139
 140 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
 141 {
 142     return ((old & mask) && !(new & mask));
 143 }
 144
 145 static uint64_t hpet_get_ticks(HPETState *s)
 146 {
 147     return ns_to_ticks(qemu_get_clock_ns(vm_clock) + s->hpet_offset);
 148 }
 149
 150 /*
 151  * calculate diff between comparator value and current ticks
 152  */
 153 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
 154 {
 155
 156     if (t->config & HPET_TN_32BIT) {
 157         uint32_t diff, cmp;
 158
 159         cmp = (uint32_t)t->cmp;
 160         diff = cmp - (uint32_t)current;
 161         diff = (int32_t)diff > 0 ? diff : (uint32_t)1;
 162         return (uint64_t)diff;
 163     } else {
 164         uint64_t diff, cmp;
 165
 166         cmp = t->cmp;
 167         diff = cmp - current;
 168         diff = (int64_t)diff > 0 ? diff : (uint64_t)1;
 169         return diff;
 170     }
 171 }
 172
 173 static void update_irq(struct HPETTimer *timer, int set)
 174 {
 175     uint64_t mask;
 176     HPETState *s;
 177     int route;
 178
 179     if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
 180         /* if LegacyReplacementRoute bit is set, HPET specification requires
 181          * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
 182          * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
 183          */
 184         route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
 185     } else {
 186         route = timer_int_route(timer);
 187     }
 188     s = timer->state;
 189     mask = 1 << timer->tn;
 190     if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
 191         s->isr &= ~mask;
 192         if (!timer_fsb_route(timer)) {
 193             qemu_irq_lower(s->irqs[route]);
 194         }
 195     } else if (timer_fsb_route(timer)) {
 196         stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
 197     } else if (timer->config & HPET_TN_TYPE_LEVEL) {
 198         s->isr |= mask;
 199         qemu_irq_raise(s->irqs[route]);
 200     } else {
 201         s->isr &= ~mask;
 202         qemu_irq_pulse(s->irqs[route]);
 203     }
 204 }
 205
 206 static void hpet_pre_save(void *opaque)
 207 {
 208     HPETState *s = opaque;
 209
 210     /* save current counter value */
 211     s->hpet_counter = hpet_get_ticks(s);
 212 }
 213
 214 static int hpet_pre_load(void *opaque)
 215 {
 216     HPETState *s = opaque;
 217
 218     /* version 1 only supports 3, later versions will load the actual value */
 219     s->num_timers = HPET_MIN_TIMERS;
 220     return 0;
 221 }
 222
 223 static int hpet_post_load(void *opaque, int version_id)
 224 {
 225     HPETState *s = opaque;
 226
 227     /* Recalculate the offset between the main counter and guest time */
 228     s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
 229
 230     /* Push number of timers into capability returned via HPET_ID */
 231     s->capability &= ~HPET_ID_NUM_TIM_MASK;
 232     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 233     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 234
 235     /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
 236     s->flags &= ~(1 << HPET_MSI_SUPPORT);
 237     if (s->timer[0].config & HPET_TN_FSB_CAP) {
 238         s->flags |= 1 << HPET_MSI_SUPPORT;
 239     }
 240
 241     if (hpet_in_legacy_mode(s)) {
 242         hpet_pit_disable();
 243     }
 244
 245     return 0;
 246 }
 247
 248 static const VMStateDescription vmstate_hpet_timer = {
 249     .name = "hpet_timer",
 250     .version_id = 1,
 251     .minimum_version_id = 1,
 252     .minimum_version_id_old = 1,
 253     .fields      = (VMStateField []) {
 254         VMSTATE_UINT8(tn, HPETTimer),
 255         VMSTATE_UINT64(config, HPETTimer),
 256         VMSTATE_UINT64(cmp, HPETTimer),
 257         VMSTATE_UINT64(fsb, HPETTimer),
 258         VMSTATE_UINT64(period, HPETTimer),
 259         VMSTATE_UINT8(wrap_flag, HPETTimer),
 260         VMSTATE_TIMER(qemu_timer, HPETTimer),
 261         VMSTATE_END_OF_LIST()
 262     }
 263 };
 264
 265 static const VMStateDescription vmstate_hpet = {
 266     .name = "hpet",
 267     .version_id = 2,
 268     .minimum_version_id = 1,
 269     .minimum_version_id_old = 1,
 270     .pre_save = hpet_pre_save,
 271     .pre_load = hpet_pre_load,
 272     .post_load = hpet_post_load,
 273     .fields      = (VMStateField []) {
 274         VMSTATE_UINT64(config, HPETState),
 275         VMSTATE_UINT64(isr, HPETState),
 276         VMSTATE_UINT64(hpet_counter, HPETState),
 277         VMSTATE_UINT8_V(num_timers, HPETState, 2),
 278         VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
 279                                     vmstate_hpet_timer, HPETTimer),
 280         VMSTATE_END_OF_LIST()
 281     }
 282 };
 283
 284 /*
 285  * timer expiration callback
 286  */
 287 static void hpet_timer(void *opaque)
 288 {
 289     HPETTimer *t = opaque;
 290     uint64_t diff;
 291
 292     uint64_t period = t->period;
 293     uint64_t cur_tick = hpet_get_ticks(t->state);
 294
 295     if (timer_is_periodic(t) && period != 0) {
 296         if (t->config & HPET_TN_32BIT) {
 297             while (hpet_time_after(cur_tick, t->cmp)) {
 298                 t->cmp = (uint32_t)(t->cmp + t->period);
 299             }
 300         } else {
 301             while (hpet_time_after64(cur_tick, t->cmp)) {
 302                 t->cmp += period;
 303             }
 304         }
 305         diff = hpet_calculate_diff(t, cur_tick);
 306         qemu_mod_timer(t->qemu_timer,
 307                        qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
 308     } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 309         if (t->wrap_flag) {
 310             diff = hpet_calculate_diff(t, cur_tick);
 311             qemu_mod_timer(t->qemu_timer, qemu_get_clock_ns(vm_clock) +
 312                            (int64_t)ticks_to_ns(diff));
 313             t->wrap_flag = 0;
 314         }
 315     }
 316     update_irq(t, 1);
 317 }
 318
 319 static void hpet_set_timer(HPETTimer *t)
 320 {
 321     uint64_t diff;
 322     uint32_t wrap_diff;  /* how many ticks until we wrap? */
 323     uint64_t cur_tick = hpet_get_ticks(t->state);
 324
 325     /* whenever new timer is being set up, make sure wrap_flag is 0 */
 326     t->wrap_flag = 0;
 327     diff = hpet_calculate_diff(t, cur_tick);
 328
 329     /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
 330      * counter wraps in addition to an interrupt with comparator match.
 331      */
 332     if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
 333         wrap_diff = 0xffffffff - (uint32_t)cur_tick;
 334         if (wrap_diff < (uint32_t)diff) {
 335             diff = wrap_diff;
 336             t->wrap_flag = 1;
 337         }
 338     }
 339     qemu_mod_timer(t->qemu_timer,
 340                    qemu_get_clock_ns(vm_clock) + (int64_t)ticks_to_ns(diff));
 341 }
 342
 343 static void hpet_del_timer(HPETTimer *t)
 344 {
 345     qemu_del_timer(t->qemu_timer);
 346     update_irq(t, 0);
 347 }
 348
 349 #ifdef HPET_DEBUG
 350 static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
 351 {
 352     printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
 353     return 0;
 354 }
 355
 356 static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
 357 {
 358     printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
 359     return 0;
 360 }
 361 #endif
 362
 363 static uint64_t hpet_ram_read(void *opaque, target_phys_addr_t addr,
 364                               unsigned size)
 365 {
 366     HPETState *s = opaque;
 367     uint64_t cur_tick, index;
 368
 369     DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
 370     index = addr;
 371     /*address range of all TN regs*/
 372     if (index >= 0x100 && index <= 0x3ff) {
 373         uint8_t timer_id = (addr - 0x100) / 0x20;
 374         HPETTimer *timer = &s->timer[timer_id];
 375
 376         if (timer_id > s->num_timers) {
 377             DPRINTF("qemu: timer id out of range\n");
 378             return 0;
 379         }
 380
 381         switch ((addr - 0x100) % 0x20) {
 382         case HPET_TN_CFG:
 383             return timer->config;
 384         case HPET_TN_CFG + 4: // Interrupt capabilities
 385             return timer->config >> 32;
 386         case HPET_TN_CMP: // comparator register
 387             return timer->cmp;
 388         case HPET_TN_CMP + 4:
 389             return timer->cmp >> 32;
 390         case HPET_TN_ROUTE:
 391             return timer->fsb;
 392         case HPET_TN_ROUTE + 4:
 393             return timer->fsb >> 32;
 394         default:
 395             DPRINTF("qemu: invalid hpet_ram_readl\n");
 396             break;
 397         }
 398     } else {
 399         switch (index) {
 400         case HPET_ID:
 401             return s->capability;
 402         case HPET_PERIOD:
 403             return s->capability >> 32;
 404         case HPET_CFG:
 405             return s->config;
 406         case HPET_CFG + 4:
 407             DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
 408             return 0;
 409         case HPET_COUNTER:
 410             if (hpet_enabled(s)) {
 411                 cur_tick = hpet_get_ticks(s);
 412             } else {
 413                 cur_tick = s->hpet_counter;
 414             }
 415             DPRINTF("qemu: reading counter  = %" PRIx64 "\n", cur_tick);
 416             return cur_tick;
 417         case HPET_COUNTER + 4:
 418             if (hpet_enabled(s)) {
 419                 cur_tick = hpet_get_ticks(s);
 420             } else {
 421                 cur_tick = s->hpet_counter;
 422             }
 423             DPRINTF("qemu: reading counter + 4  = %" PRIx64 "\n", cur_tick);
 424             return cur_tick >> 32;
 425         case HPET_STATUS:
 426             return s->isr;
 427         default:
 428             DPRINTF("qemu: invalid hpet_ram_readl\n");
 429             break;
 430         }
 431     }
 432     return 0;
 433 }
 434
 435 static void hpet_ram_write(void *opaque, target_phys_addr_t addr,
 436                            uint64_t value, unsigned size)
 437 {
 438     int i;
 439     HPETState *s = opaque;
 440     uint64_t old_val, new_val, val, index;
 441
 442     DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
 443     index = addr;
 444     old_val = hpet_ram_read(opaque, addr, 4);
 445     new_val = value;
 446
 447     /*address range of all TN regs*/
 448     if (index >= 0x100 && index <= 0x3ff) {
 449         uint8_t timer_id = (addr - 0x100) / 0x20;
 450         HPETTimer *timer = &s->timer[timer_id];
 451
 452         DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
 453         if (timer_id > s->num_timers) {
 454             DPRINTF("qemu: timer id out of range\n");
 455             return;
 456         }
 457         switch ((addr - 0x100) % 0x20) {
 458         case HPET_TN_CFG:
 459             DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
 460             if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
 461                 update_irq(timer, 0);
 462             }
 463             val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
 464             timer->config = (timer->config & 0xffffffff00000000ULL) | val;
 465             if (new_val & HPET_TN_32BIT) {
 466                 timer->cmp = (uint32_t)timer->cmp;
 467                 timer->period = (uint32_t)timer->period;
 468             }
 469             if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 470                 hpet_set_timer(timer);
 471             } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
 472                 hpet_del_timer(timer);
 473             }
 474             break;
 475         case HPET_TN_CFG + 4: // Interrupt capabilities
 476             DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
 477             break;
 478         case HPET_TN_CMP: // comparator register
 479             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
 480             if (timer->config & HPET_TN_32BIT) {
 481                 new_val = (uint32_t)new_val;
 482             }
 483             if (!timer_is_periodic(timer)
 484                 || (timer->config & HPET_TN_SETVAL)) {
 485                 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
 486             }
 487             if (timer_is_periodic(timer)) {
 488                 /*
 489                  * FIXME: Clamp period to reasonable min value?
 490                  * Clamp period to reasonable max value
 491                  */
 492                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 493                 timer->period =
 494                     (timer->period & 0xffffffff00000000ULL) | new_val;
 495             }
 496             timer->config &= ~HPET_TN_SETVAL;
 497             if (hpet_enabled(s)) {
 498                 hpet_set_timer(timer);
 499             }
 500             break;
 501         case HPET_TN_CMP + 4: // comparator register high order
 502             DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
 503             if (!timer_is_periodic(timer)
 504                 || (timer->config & HPET_TN_SETVAL)) {
 505                 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
 506             } else {
 507                 /*
 508                  * FIXME: Clamp period to reasonable min value?
 509                  * Clamp period to reasonable max value
 510                  */
 511                 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
 512                 timer->period =
 513                     (timer->period & 0xffffffffULL) | new_val << 32;
 514                 }
 515                 timer->config &= ~HPET_TN_SETVAL;
 516                 if (hpet_enabled(s)) {
 517                     hpet_set_timer(timer);
 518                 }
 519                 break;
 520         case HPET_TN_ROUTE:
 521             timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
 522             break;
 523         case HPET_TN_ROUTE + 4:
 524             timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
 525             break;
 526         default:
 527             DPRINTF("qemu: invalid hpet_ram_writel\n");
 528             break;
 529         }
 530         return;
 531     } else {
 532         switch (index) {
 533         case HPET_ID:
 534             return;
 535         case HPET_CFG:
 536             val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
 537             s->config = (s->config & 0xffffffff00000000ULL) | val;
 538             if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 539                 /* Enable main counter and interrupt generation. */
 540                 s->hpet_offset =
 541                     ticks_to_ns(s->hpet_counter) - qemu_get_clock_ns(vm_clock);
 542                 for (i = 0; i < s->num_timers; i++) {
 543                     if ((&s->timer[i])->cmp != ~0ULL) {
 544                         hpet_set_timer(&s->timer[i]);
 545                     }
 546                 }
 547             } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
 548                 /* Halt main counter and disable interrupt generation. */
 549                 s->hpet_counter = hpet_get_ticks(s);
 550                 for (i = 0; i < s->num_timers; i++) {
 551                     hpet_del_timer(&s->timer[i]);
 552                 }
 553             }
 554             /* i8254 and RTC are disabled when HPET is in legacy mode */
 555             if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 556                 hpet_pit_disable();
 557                 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
 558             } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
 559                 hpet_pit_enable();
 560                 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
 561             }
 562             break;
 563         case HPET_CFG + 4:
 564             DPRINTF("qemu: invalid HPET_CFG+4 write\n");
 565             break;
 566         case HPET_STATUS:
 567             val = new_val & s->isr;
 568             for (i = 0; i < s->num_timers; i++) {
 569                 if (val & (1 << i)) {
 570                     update_irq(&s->timer[i], 0);
 571                 }
 572             }
 573             break;
 574         case HPET_COUNTER:
 575             if (hpet_enabled(s)) {
 576                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 577             }
 578             s->hpet_counter =
 579                 (s->hpet_counter & 0xffffffff00000000ULL) | value;
 580             DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
 581                     value, s->hpet_counter);
 582             break;
 583         case HPET_COUNTER + 4:
 584             if (hpet_enabled(s)) {
 585                 DPRINTF("qemu: Writing counter while HPET enabled!\n");
 586             }
 587             s->hpet_counter =
 588                 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
 589             DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
 590                     value, s->hpet_counter);
 591             break;
 592         default:
 593             DPRINTF("qemu: invalid hpet_ram_writel\n");
 594             break;
 595         }
 596     }
 597 }
 598
 599 static const MemoryRegionOps hpet_ram_ops = {
 600     .read = hpet_ram_read,
 601     .write = hpet_ram_write,
 602     .valid = {
 603         .min_access_size = 4,
 604         .max_access_size = 4,
 605     },
 606     .endianness = DEVICE_NATIVE_ENDIAN,
 607 };
 608
 609 static void hpet_reset(DeviceState *d)
 610 {
 611     HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d));
 612     int i;
 613     static int count = 0;
 614
 615     for (i = 0; i < s->num_timers; i++) {
 616         HPETTimer *timer = &s->timer[i];
 617
 618         hpet_del_timer(timer);
 619         timer->cmp = ~0ULL;
 620         timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
 621         if (s->flags & (1 << HPET_MSI_SUPPORT)) {
 622             timer->config |= HPET_TN_FSB_CAP;
 623         }
 624         /* advertise availability of ioapic inti2 */
 625         timer->config |=  0x00000004ULL << 32;
 626         timer->period = 0ULL;
 627         timer->wrap_flag = 0;
 628     }
 629
 630     s->hpet_counter = 0ULL;
 631     s->hpet_offset = 0ULL;
 632     s->config = 0ULL;
 633     if (count > 0) {
 634         /* we don't enable pit when hpet_reset is first called (by hpet_init)
 635          * because hpet is taking over for pit here. On subsequent invocations,
 636          * hpet_reset is called due to system reset. At this point control must
 637          * be returned to pit until SW reenables hpet.
 638          */
 639         hpet_pit_enable();
 640     }
 641     hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
 642     hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr;
 643     count = 1;
 644 }
 645
 646 static void hpet_handle_rtc_irq(void *opaque, int n, int level)
 647 {
 648     HPETState *s = FROM_SYSBUS(HPETState, opaque);
 649
 650     s->rtc_irq_level = level;
 651     if (!hpet_in_legacy_mode(s)) {
 652         qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
 653     }
 654 }
 655
 656 static int hpet_init(SysBusDevice *dev)
 657 {
 658     HPETState *s = FROM_SYSBUS(HPETState, dev);
 659     int i;
 660     HPETTimer *timer;
 661
 662     if (hpet_cfg.count == UINT8_MAX) {
 663         /* first instance */
 664         hpet_cfg.count = 0;
 665     }
 666
 667     if (hpet_cfg.count == 8) {
 668         fprintf(stderr, "Only 8 instances of HPET is allowed\n");
 669         return -1;
 670     }
 671
 672     s->hpet_id = hpet_cfg.count++;
 673
 674     for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
 675         sysbus_init_irq(dev, &s->irqs[i]);
 676     }
 677
 678     if (s->num_timers < HPET_MIN_TIMERS) {
 679         s->num_timers = HPET_MIN_TIMERS;
 680     } else if (s->num_timers > HPET_MAX_TIMERS) {
 681         s->num_timers = HPET_MAX_TIMERS;
 682     }
 683     for (i = 0; i < HPET_MAX_TIMERS; i++) {
 684         timer = &s->timer[i];
 685         timer->qemu_timer = qemu_new_timer_ns(vm_clock, hpet_timer, timer);
 686         timer->tn = i;
 687         timer->state = s;
 688     }
 689
 690     /* 64-bit main counter; LegacyReplacementRoute. */
 691     s->capability = 0x8086a001ULL;
 692     s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
 693     s->capability |= ((HPET_CLK_PERIOD) << 32);
 694
 695     qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1);
 696
 697     /* HPET Area */
 698     memory_region_init_io(&s->iomem, &hpet_ram_ops, s, "hpet", 0x400);
 699     sysbus_init_mmio(dev, &s->iomem);
 700     return 0;
 701 }
 702
 703 static Property hpet_device_properties[] = {
 704     DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
 705     DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
 706     DEFINE_PROP_END_OF_LIST(),
 707 };
 708
 709 static void hpet_device_class_init(ObjectClass *klass, void *data)
 710 {
 711     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 712
 713     k->init = hpet_init;
 714 }
 715
 716 static DeviceInfo hpet_device_info = {
 717     .name = "hpet",
 718     .size = sizeof(HPETState),
 719     .no_user = 1,
 720     .vmsd = &vmstate_hpet,
 721     .reset = hpet_reset,
 722     .props = hpet_device_properties,
 723     .class_init = hpet_device_class_init,
 724 };
 725
 726 static void hpet_register_device(void)
 727 {
 728     sysbus_register_withprop(&hpet_device_info);
 729 }
 730
 731 device_init(hpet_register_device)