hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "apic_internal.h"
  20 #include "apic.h"
  21 #include "ioapic.h"
  22 #include "host-utils.h"
  23 #include "trace.h"
  24 #include "pc.h"
  25 #include "kvm.h"
  26
  27 #define MAX_APIC_WORDS 8
  28
  29 /* Intel APIC constants: from include/asm/msidef.h */
  30 #define MSI_DATA_VECTOR_SHIFT           0
  31 #define MSI_DATA_VECTOR_MASK            0x000000ff
  32 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  33 #define MSI_DATA_TRIGGER_SHIFT          15
  34 #define MSI_DATA_LEVEL_SHIFT            14
  35 #define MSI_ADDR_DEST_MODE_SHIFT        2
  36 #define MSI_ADDR_DEST_ID_SHIFT          12
  37 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  38
  39 static APICCommonState *local_apics[MAX_APICS + 1];
  40
  41 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
  42 static void apic_update_irq(APICCommonState *s);
  43 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
  44                                       uint8_t dest, uint8_t dest_mode);
  45
  46 /* Find first bit starting from msb */
  47 static int fls_bit(uint32_t value)
  48 {
  49     return 31 - clz32(value);
  50 }
  51
  52 /* Find first bit starting from lsb */
  53 static int ffs_bit(uint32_t value)
  54 {
  55     return ctz32(value);
  56 }
  57
  58 static inline void set_bit(uint32_t *tab, int index)
  59 {
  60     int i, mask;
  61     i = index >> 5;
  62     mask = 1 << (index & 0x1f);
  63     tab[i] |= mask;
  64 }
  65
  66 static inline void reset_bit(uint32_t *tab, int index)
  67 {
  68     int i, mask;
  69     i = index >> 5;
  70     mask = 1 << (index & 0x1f);
  71     tab[i] &= ~mask;
  72 }
  73
  74 static inline int get_bit(uint32_t *tab, int index)
  75 {
  76     int i, mask;
  77     i = index >> 5;
  78     mask = 1 << (index & 0x1f);
  79     return !!(tab[i] & mask);
  80 }
  81
  82 static void apic_local_deliver(APICCommonState *s, int vector)
  83 {
  84     uint32_t lvt = s->lvt[vector];
  85     int trigger_mode;
  86
  87     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
  88
  89     if (lvt & APIC_LVT_MASKED)
  90         return;
  91
  92     switch ((lvt >> 8) & 7) {
  93     case APIC_DM_SMI:
  94         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
  95         break;
  96
  97     case APIC_DM_NMI:
  98         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
  99         break;
 100
 101     case APIC_DM_EXTINT:
 102         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 103         break;
 104
 105     case APIC_DM_FIXED:
 106         trigger_mode = APIC_TRIGGER_EDGE;
 107         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 108             (lvt & APIC_LVT_LEVEL_TRIGGER))
 109             trigger_mode = APIC_TRIGGER_LEVEL;
 110         apic_set_irq(s, lvt & 0xff, trigger_mode);
 111     }
 112 }
 113
 114 void apic_deliver_pic_intr(DeviceState *d, int level)
 115 {
 116     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 117
 118     if (level) {
 119         apic_local_deliver(s, APIC_LVT_LINT0);
 120     } else {
 121         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 122
 123         switch ((lvt >> 8) & 7) {
 124         case APIC_DM_FIXED:
 125             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 126                 break;
 127             reset_bit(s->irr, lvt & 0xff);
 128             /* fall through */
 129         case APIC_DM_EXTINT:
 130             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 131             break;
 132         }
 133     }
 134 }
 135
 136 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id);
 137
 138 static void kvm_irqchip_deliver_nmi(void *p)
 139 {
 140     APICCommonState *s = p;
 141     struct kvm_lapic_state klapic;
 142     uint32_t lvt;
 143
 144     kvm_get_lapic(s->cpu_env, &klapic);
 145     lvt = kapic_reg(&klapic, 0x32 + APIC_LVT_LINT1);
 146
 147     if (lvt & APIC_LVT_MASKED) {
 148         return;
 149     }
 150
 151     if (((lvt >> 8) & 7) != APIC_DM_NMI) {
 152         return;
 153     }
 154
 155     kvm_vcpu_ioctl(s->cpu_env, KVM_NMI);
 156 }
 157
 158 static void apic_external_nmi(APICCommonState *s)
 159 {
 160     if (kvm_irqchip_in_kernel()) {
 161         run_on_cpu(s->cpu_env, kvm_irqchip_deliver_nmi, s);
 162     } else {
 163         apic_local_deliver(s, APIC_LVT_LINT1);
 164     }
 165 }
 166
 167 #define foreach_apic(apic, deliver_bitmask, code) \
 168 {\
 169     int __i, __j, __mask;\
 170     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 171         __mask = deliver_bitmask[__i];\
 172         if (__mask) {\
 173             for(__j = 0; __j < 32; __j++) {\
 174                 if (__mask & (1 << __j)) {\
 175                     apic = local_apics[__i * 32 + __j];\
 176                     if (apic) {\
 177                         code;\
 178                     }\
 179                 }\
 180             }\
 181         }\
 182     }\
 183 }
 184
 185 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 186                              uint8_t delivery_mode, uint8_t vector_num,
 187                              uint8_t trigger_mode)
 188 {
 189     APICCommonState *apic_iter;
 190
 191     switch (delivery_mode) {
 192         case APIC_DM_LOWPRI:
 193             /* XXX: search for focus processor, arbitration */
 194             {
 195                 int i, d;
 196                 d = -1;
 197                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 198                     if (deliver_bitmask[i]) {
 199                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 200                         break;
 201                     }
 202                 }
 203                 if (d >= 0) {
 204                     apic_iter = local_apics[d];
 205                     if (apic_iter) {
 206                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 207                     }
 208                 }
 209             }
 210             return;
 211
 212         case APIC_DM_FIXED:
 213             break;
 214
 215         case APIC_DM_SMI:
 216             foreach_apic(apic_iter, deliver_bitmask,
 217                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 218             return;
 219
 220         case APIC_DM_NMI:
 221             foreach_apic(apic_iter, deliver_bitmask,
 222                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 223             return;
 224
 225         case APIC_DM_INIT:
 226             /* normal INIT IPI sent to processors */
 227             foreach_apic(apic_iter, deliver_bitmask,
 228                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 229             return;
 230
 231         case APIC_DM_EXTINT:
 232             /* handled in I/O APIC code */
 233             break;
 234
 235         default:
 236             return;
 237     }
 238
 239     foreach_apic(apic_iter, deliver_bitmask,
 240                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 241 }
 242
 243 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
 244                       uint8_t vector_num, uint8_t trigger_mode)
 245 {
 246     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 247
 248     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 249                            trigger_mode);
 250
 251     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 252     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 253 }
 254
 255 static void apic_set_base(APICCommonState *s, uint64_t val)
 256 {
 257     if (kvm_enabled() && kvm_irqchip_in_kernel())
 258         s->apicbase = val;
 259     else
 260         s->apicbase = (val & 0xfffff000) |
 261             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 262     /* if disabled, cannot be enabled again */
 263     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 264         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 265         cpu_clear_apic_feature(s->cpu_env);
 266         s->spurious_vec &= ~APIC_SV_ENABLE;
 267     }
 268 }
 269
 270 static void apic_set_tpr(APICCommonState *s, uint8_t val)
 271 {
 272     s->tpr = (val & 0x0f) << 4;
 273     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 274         return;
 275     }
 276     apic_update_irq(s);
 277 }
 278
 279 /* return -1 if no bit is set */
 280 static int get_highest_priority_int(uint32_t *tab)
 281 {
 282     int i;
 283     for(i = 7; i >= 0; i--) {
 284         if (tab[i] != 0) {
 285             return i * 32 + fls_bit(tab[i]);
 286         }
 287     }
 288     return -1;
 289 }
 290
 291 static int apic_get_ppr(APICCommonState *s)
 292 {
 293     int tpr, isrv, ppr;
 294
 295     tpr = (s->tpr >> 4);
 296     isrv = get_highest_priority_int(s->isr);
 297     if (isrv < 0)
 298         isrv = 0;
 299     isrv >>= 4;
 300     if (tpr >= isrv)
 301         ppr = s->tpr;
 302     else
 303         ppr = isrv << 4;
 304     return ppr;
 305 }
 306
 307 static int apic_get_arb_pri(APICCommonState *s)
 308 {
 309     /* XXX: arbitration */
 310     return 0;
 311 }
 312
 313
 314 /*
 315  * <0 - low prio interrupt,
 316  * 0  - no interrupt,
 317  * >0 - interrupt number
 318  */
 319 static int apic_irq_pending(APICCommonState *s)
 320 {
 321     int irrv, ppr;
 322     irrv = get_highest_priority_int(s->irr);
 323     if (irrv < 0) {
 324         return 0;
 325     }
 326     ppr = apic_get_ppr(s);
 327     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
 328         return -1;
 329     }
 330
 331     return irrv;
 332 }
 333
 334 /* signal the CPU if an irq is pending */
 335 static void apic_update_irq(APICCommonState *s)
 336 {
 337     if (!(s->spurious_vec & APIC_SV_ENABLE)) {
 338         return;
 339     }
 340     if (apic_irq_pending(s) > 0) {
 341         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 342     } else if (apic_accept_pic_intr(&s->busdev.qdev) &&
 343                pic_get_output(isa_pic)) {
 344         apic_deliver_pic_intr(&s->busdev.qdev, 1);
 345     }
 346 }
 347
 348 static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
 349 {
 350     apic_report_irq_delivered(!get_bit(s->irr, vector_num));
 351
 352     set_bit(s->irr, vector_num);
 353     if (trigger_mode)
 354         set_bit(s->tmr, vector_num);
 355     else
 356         reset_bit(s->tmr, vector_num);
 357     apic_update_irq(s);
 358 }
 359
 360 static void apic_eoi(APICCommonState *s)
 361 {
 362     int isrv;
 363     isrv = get_highest_priority_int(s->isr);
 364     if (isrv < 0)
 365         return;
 366     reset_bit(s->isr, isrv);
 367     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
 368         ioapic_eoi_broadcast(isrv);
 369     }
 370     apic_update_irq(s);
 371 }
 372
 373 static int apic_find_dest(uint8_t dest)
 374 {
 375     APICCommonState *apic = local_apics[dest];
 376     int i;
 377
 378     if (apic && apic->id == dest)
 379         return dest;  /* shortcut in case apic->id == apic->idx */
 380
 381     for (i = 0; i < MAX_APICS; i++) {
 382         apic = local_apics[i];
 383         if (apic && apic->id == dest)
 384             return i;
 385         if (!apic)
 386             break;
 387     }
 388
 389     return -1;
 390 }
 391
 392 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 393                                       uint8_t dest, uint8_t dest_mode)
 394 {
 395     APICCommonState *apic_iter;
 396     int i;
 397
 398     if (dest_mode == 0) {
 399         if (dest == 0xff) {
 400             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 401         } else {
 402             int idx = apic_find_dest(dest);
 403             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 404             if (idx >= 0)
 405                 set_bit(deliver_bitmask, idx);
 406         }
 407     } else {
 408         /* XXX: cluster mode */
 409         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 410         for(i = 0; i < MAX_APICS; i++) {
 411             apic_iter = local_apics[i];
 412             if (apic_iter) {
 413                 if (apic_iter->dest_mode == 0xf) {
 414                     if (dest & apic_iter->log_dest)
 415                         set_bit(deliver_bitmask, i);
 416                 } else if (apic_iter->dest_mode == 0x0) {
 417                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 418                         (dest & apic_iter->log_dest & 0x0f)) {
 419                         set_bit(deliver_bitmask, i);
 420                     }
 421                 }
 422             } else {
 423                 break;
 424             }
 425         }
 426     }
 427 }
 428
 429 static void apic_startup(APICCommonState *s, int vector_num)
 430 {
 431     s->sipi_vector = vector_num;
 432     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 433 }
 434
 435 void apic_sipi(DeviceState *d)
 436 {
 437     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 438
 439     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 440
 441     if (!s->wait_for_sipi)
 442         return;
 443     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 444     s->wait_for_sipi = 0;
 445 }
 446
 447 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
 448                          uint8_t delivery_mode, uint8_t vector_num,
 449                          uint8_t trigger_mode)
 450 {
 451     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 452     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 453     int dest_shorthand = (s->icr[0] >> 18) & 3;
 454     APICCommonState *apic_iter;
 455
 456     switch (dest_shorthand) {
 457     case 0:
 458         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 459         break;
 460     case 1:
 461         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 462         set_bit(deliver_bitmask, s->idx);
 463         break;
 464     case 2:
 465         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 466         break;
 467     case 3:
 468         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 469         reset_bit(deliver_bitmask, s->idx);
 470         break;
 471     }
 472
 473     switch (delivery_mode) {
 474         case APIC_DM_INIT:
 475             {
 476                 int trig_mode = (s->icr[0] >> 15) & 1;
 477                 int level = (s->icr[0] >> 14) & 1;
 478                 if (level == 0 && trig_mode == 1) {
 479                     foreach_apic(apic_iter, deliver_bitmask,
 480                                  apic_iter->arb_id = apic_iter->id );
 481                     return;
 482                 }
 483             }
 484             break;
 485
 486         case APIC_DM_SIPI:
 487             foreach_apic(apic_iter, deliver_bitmask,
 488                          apic_startup(apic_iter, vector_num) );
 489             return;
 490     }
 491
 492     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
 493 }
 494
 495 int apic_get_interrupt(DeviceState *d)
 496 {
 497     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 498     int intno;
 499
 500     /* if the APIC is installed or enabled, we let the 8259 handle the
 501        IRQs */
 502     if (!s)
 503         return -1;
 504     if (!(s->spurious_vec & APIC_SV_ENABLE))
 505         return -1;
 506
 507     intno = apic_irq_pending(s);
 508
 509     if (intno == 0) {
 510         return -1;
 511     } else if (intno < 0) {
 512         return s->spurious_vec & 0xff;
 513     }
 514     reset_bit(s->irr, intno);
 515     set_bit(s->isr, intno);
 516     apic_update_irq(s);
 517     return intno;
 518 }
 519
 520 int apic_accept_pic_intr(DeviceState *d)
 521 {
 522     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 523     uint32_t lvt0;
 524
 525     if (!s)
 526         return -1;
 527
 528     lvt0 = s->lvt[APIC_LVT_LINT0];
 529
 530     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 531         (lvt0 & APIC_LVT_MASKED) == 0)
 532         return 1;
 533
 534     return 0;
 535 }
 536
 537 static uint32_t apic_get_current_count(APICCommonState *s)
 538 {
 539     int64_t d;
 540     uint32_t val;
 541     d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >>
 542         s->count_shift;
 543     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 544         /* periodic */
 545         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 546     } else {
 547         if (d >= s->initial_count)
 548             val = 0;
 549         else
 550             val = s->initial_count - d;
 551     }
 552     return val;
 553 }
 554
 555 static void apic_timer_update(APICCommonState *s, int64_t current_time)
 556 {
 557     if (apic_next_timer(s, current_time)) {
 558         qemu_mod_timer(s->timer, s->next_time);
 559     } else {
 560         qemu_del_timer(s->timer);
 561     }
 562 }
 563
 564 static void apic_timer(void *opaque)
 565 {
 566     APICCommonState *s = opaque;
 567
 568     apic_local_deliver(s, APIC_LVT_TIMER);
 569     apic_timer_update(s, s->next_time);
 570 }
 571
 572 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 573 {
 574     return 0;
 575 }
 576
 577 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 578 {
 579     return 0;
 580 }
 581
 582 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 583 {
 584 }
 585
 586 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 587 {
 588 }
 589
 590 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 591 {
 592     DeviceState *d;
 593     APICCommonState *s;
 594     uint32_t val;
 595     int index;
 596
 597     d = cpu_get_current_apic();
 598     if (!d) {
 599         return 0;
 600     }
 601     s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 602
 603     index = (addr >> 4) & 0xff;
 604     switch(index) {
 605     case 0x02: /* id */
 606         val = s->id << 24;
 607         break;
 608     case 0x03: /* version */
 609         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 610         break;
 611     case 0x08:
 612         val = s->tpr;
 613         break;
 614     case 0x09:
 615         val = apic_get_arb_pri(s);
 616         break;
 617     case 0x0a:
 618         /* ppr */
 619         val = apic_get_ppr(s);
 620         break;
 621     case 0x0b:
 622         val = 0;
 623         break;
 624     case 0x0d:
 625         val = s->log_dest << 24;
 626         break;
 627     case 0x0e:
 628         val = s->dest_mode << 28;
 629         break;
 630     case 0x0f:
 631         val = s->spurious_vec;
 632         break;
 633     case 0x10 ... 0x17:
 634         val = s->isr[index & 7];
 635         break;
 636     case 0x18 ... 0x1f:
 637         val = s->tmr[index & 7];
 638         break;
 639     case 0x20 ... 0x27:
 640         val = s->irr[index & 7];
 641         break;
 642     case 0x28:
 643         val = s->esr;
 644         break;
 645     case 0x30:
 646     case 0x31:
 647         val = s->icr[index & 1];
 648         break;
 649     case 0x32 ... 0x37:
 650         val = s->lvt[index - 0x32];
 651         break;
 652     case 0x38:
 653         val = s->initial_count;
 654         break;
 655     case 0x39:
 656         val = apic_get_current_count(s);
 657         break;
 658     case 0x3e:
 659         val = s->divide_conf;
 660         break;
 661     default:
 662         s->esr |= ESR_ILLEGAL_ADDRESS;
 663         val = 0;
 664         break;
 665     }
 666     trace_apic_mem_readl(addr, val);
 667     return val;
 668 }
 669
 670 static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
 671 {
 672     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 673     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 674     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 675     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 676     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 677     /* XXX: Ignore redirection hint. */
 678     apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
 679 }
 680
 681 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 682 {
 683     DeviceState *d;
 684     APICCommonState *s;
 685     int index = (addr >> 4) & 0xff;
 686     if (addr > 0xfff || !index) {
 687         /* MSI and MMIO APIC are at the same memory location,
 688          * but actually not on the global bus: MSI is on PCI bus
 689          * APIC is connected directly to the CPU.
 690          * Mapping them on the global bus happens to work because
 691          * MSI registers are reserved in APIC MMIO and vice versa. */
 692         apic_send_msi(addr, val);
 693         return;
 694     }
 695
 696     d = cpu_get_current_apic();
 697     if (!d) {
 698         return;
 699     }
 700     s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 701
 702     trace_apic_mem_writel(addr, val);
 703
 704     switch(index) {
 705     case 0x02:
 706         s->id = (val >> 24);
 707         break;
 708     case 0x03:
 709         break;
 710     case 0x08:
 711         s->tpr = val;
 712         apic_update_irq(s);
 713         break;
 714     case 0x09:
 715     case 0x0a:
 716         break;
 717     case 0x0b: /* EOI */
 718         apic_eoi(s);
 719         break;
 720     case 0x0d:
 721         s->log_dest = val >> 24;
 722         break;
 723     case 0x0e:
 724         s->dest_mode = val >> 28;
 725         break;
 726     case 0x0f:
 727         s->spurious_vec = val & 0x1ff;
 728         apic_update_irq(s);
 729         break;
 730     case 0x10 ... 0x17:
 731     case 0x18 ... 0x1f:
 732     case 0x20 ... 0x27:
 733     case 0x28:
 734         break;
 735     case 0x30:
 736         s->icr[0] = val;
 737         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 738                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 739                      (s->icr[0] >> 15) & 1);
 740         break;
 741     case 0x31:
 742         s->icr[1] = val;
 743         break;
 744     case 0x32 ... 0x37:
 745         {
 746             int n = index - 0x32;
 747             s->lvt[n] = val;
 748             if (n == APIC_LVT_TIMER)
 749                 apic_timer_update(s, qemu_get_clock_ns(vm_clock));
 750         }
 751         break;
 752     case 0x38:
 753         s->initial_count = val;
 754         s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
 755         apic_timer_update(s, s->initial_count_load_time);
 756         break;
 757     case 0x39:
 758         break;
 759     case 0x3e:
 760         {
 761             int v;
 762             s->divide_conf = val & 0xb;
 763             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 764             s->count_shift = (v + 1) & 7;
 765         }
 766         break;
 767     default:
 768         s->esr |= ESR_ILLEGAL_ADDRESS;
 769         break;
 770     }
 771 }
 772
 773 #ifdef KVM_CAP_IRQCHIP
 774
 775 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 776 {
 777     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 778 }
 779
 780 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 781                                  int reg_id, uint32_t val)
 782 {
 783     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 784 }
 785
 786 static void kvm_kernel_lapic_save_to_user(APICCommonState *s)
 787 {
 788     struct kvm_lapic_state apic;
 789     struct kvm_lapic_state *kapic = &apic;
 790     int i, v;
 791
 792     kvm_get_lapic(s->cpu_env, kapic);
 793
 794     s->id = kapic_reg(kapic, 0x2) >> 24;
 795     s->tpr = kapic_reg(kapic, 0x8);
 796     s->arb_id = kapic_reg(kapic, 0x9);
 797     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 798     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 799     s->spurious_vec = kapic_reg(kapic, 0xf);
 800     for (i = 0; i < 8; i++) {
 801         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 802         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 803         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 804     }
 805     s->esr = kapic_reg(kapic, 0x28);
 806     s->icr[0] = kapic_reg(kapic, 0x30);
 807     s->icr[1] = kapic_reg(kapic, 0x31);
 808     for (i = 0; i < APIC_LVT_NB; i++)
 809         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 810     s->initial_count = kapic_reg(kapic, 0x38);
 811     s->divide_conf = kapic_reg(kapic, 0x3e);
 812
 813     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 814     s->count_shift = (v + 1) & 7;
 815
 816     s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
 817     apic_next_timer(s, s->initial_count_load_time);
 818 }
 819
 820 static void kvm_kernel_lapic_load_from_user(APICCommonState *s)
 821 {
 822     struct kvm_lapic_state apic;
 823     struct kvm_lapic_state *klapic = &apic;
 824     int i;
 825
 826     memset(klapic, 0, sizeof apic);
 827     kapic_set_reg(klapic, 0x2, s->id << 24);
 828     kapic_set_reg(klapic, 0x8, s->tpr);
 829     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 830     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 831     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 832     for (i = 0; i < 8; i++) {
 833         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 834         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 835         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 836     }
 837     kapic_set_reg(klapic, 0x28, s->esr);
 838     kapic_set_reg(klapic, 0x30, s->icr[0]);
 839     kapic_set_reg(klapic, 0x31, s->icr[1]);
 840     for (i = 0; i < APIC_LVT_NB; i++)
 841         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 842     kapic_set_reg(klapic, 0x38, s->initial_count);
 843     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 844
 845     kvm_set_lapic(s->cpu_env, klapic);
 846 }
 847
 848 #endif
 849
 850 void kvm_load_lapic(CPUState *env)
 851 {
 852 #ifdef KVM_CAP_IRQCHIP
 853     APICCommonState *s =
 854         DO_UPCAST(APICCommonState, busdev.qdev, env->apic_state);
 855
 856     if (!s) {
 857         return;
 858     }
 859
 860     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 861         kvm_kernel_lapic_load_from_user(s);
 862     }
 863 #endif
 864 }
 865
 866 void kvm_save_lapic(CPUState *env)
 867 {
 868 #ifdef KVM_CAP_IRQCHIP
 869     APICCommonState *s =
 870         DO_UPCAST(APICCommonState, busdev.qdev, env->apic_state);
 871
 872     if (!s) {
 873         return;
 874     }
 875
 876     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 877         kvm_kernel_lapic_save_to_user(s);
 878     }
 879 #endif
 880 }
 881
 882 static void apic_post_load(APICCommonState *s)
 883 {
 884     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 885         return;
 886     }
 887     if (s->timer_expiry != -1) {
 888         qemu_mod_timer(s->timer, s->timer_expiry);
 889     } else {
 890         qemu_del_timer(s->timer);
 891     }
 892 }
 893
 894 static const MemoryRegionOps apic_io_ops = {
 895     .old_mmio = {
 896         .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, },
 897         .write = { apic_mem_writeb, apic_mem_writew, apic_mem_writel, },
 898     },
 899     .endianness = DEVICE_NATIVE_ENDIAN,
 900 };
 901
 902 static void apic_init(APICCommonState *s)
 903 {
 904     memory_region_init_io(&s->io_memory, &apic_io_ops, s, "apic-msi",
 905                           MSI_SPACE_SIZE);
 906
 907     s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
 908     local_apics[s->idx] = s;
 909 }
 910
 911 static void apic_class_init(ObjectClass *klass, void *data)
 912 {
 913     APICCommonClass *k = APIC_COMMON_CLASS(klass);
 914
 915     k->init = apic_init;
 916     k->set_base = apic_set_base;
 917     k->set_tpr = apic_set_tpr;
 918     k->external_nmi = apic_external_nmi;
 919     k->post_load = apic_post_load;
 920 }
 921
 922 static DeviceInfo apic_info = {
 923     .name = "apic",
 924     .class_init = apic_class_init,
 925 };
 926
 927 static void apic_register_devices(void)
 928 {
 929     apic_qdev_register(&apic_info);
 930 }
 931
 932 device_init(apic_register_devices)