hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw.h"
  22 #include "pc.h"
  23 #include "apm.h"
  24 #include "pm_smbus.h"
  25 #include "pci.h"
  26 #include "acpi.h"
  27 #include "sysemu.h"
  28 #include "range.h"
  29 #include "ioport.h"
  30
  31 //#define DEBUG
  32
  33 #ifdef DEBUG
  34 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  35 #else
  36 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  37 #endif
  38
  39 #define ACPI_DBG_IO_ADDR  0xb044
  40
  41 #define GPE_BASE 0xafe0
  42 #define PROC_BASE 0xaf00
  43 #define GPE_LEN 4
  44 #define PCI_BASE 0xae00
  45 #define PCI_EJ_BASE 0xae08
  46 #define PCI_RMV_BASE 0xae0c
  47
  48 #define PIIX4_CPU_HOTPLUG_STATUS 4
  49 #define PIIX4_PCI_HOTPLUG_STATUS 2
  50
  51 struct gpe_regs {
  52     uint8_t cpus_sts[32];
  53 };
  54
  55 struct pci_status {
  56     uint32_t up;
  57     uint32_t down;
  58 };
  59
  60 typedef struct PIIX4PMState {
  61     PCIDevice dev;
  62     IORange ioport;
  63     ACPIPM1EVT pm1a;
  64     ACPIPM1CNT pm1_cnt;
  65
  66     APMState apm;
  67
  68     ACPIPMTimer tmr;
  69
  70     PMSMBus smb;
  71     uint32_t smb_io_base;
  72
  73     qemu_irq irq;
  74     qemu_irq smi_irq;
  75     int kvm_enabled;
  76     Notifier machine_ready;
  77
  78     /* for pci hotplug */
  79     ACPIGPE gpe;
  80     struct gpe_regs gpe_cpu;
  81     struct pci_status pci0_status;
  82     uint32_t pci0_hotplug_enable;
  83 } PIIX4PMState;
  84
  85 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  86
  87 #define ACPI_ENABLE 0xf1
  88 #define ACPI_DISABLE 0xf0
  89
  90 static void pm_update_sci(PIIX4PMState *s)
  91 {
  92     int sci_level, pmsts;
  93
  94     pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
  95     sci_level = (((pmsts & s->pm1a.en) &
  96                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  97                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  98                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  99                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
 100         (((s->gpe.sts[0] & s->gpe.en[0]) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
 101
 102     qemu_set_irq(s->irq, sci_level);
 103     /* schedule a timer interruption if needed */
 104     acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
 105                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 106 }
 107
 108 static void pm_tmr_timer(ACPIPMTimer *tmr)
 109 {
 110     PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr);
 111     pm_update_sci(s);
 112 }
 113
 114 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 115                             uint64_t val)
 116 {
 117     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 118
 119     if (width != 2) {
 120         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 121                       (unsigned)addr, width, (unsigned)val);
 122     }
 123
 124     switch(addr) {
 125     case 0x00:
 126         acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
 127         pm_update_sci(s);
 128         break;
 129     case 0x02:
 130         s->pm1a.en = val;
 131         pm_update_sci(s);
 132         break;
 133     case 0x04:
 134         acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
 135         break;
 136     default:
 137         break;
 138     }
 139     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
 140                   (unsigned int)val);
 141 }
 142
 143 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 144                             uint64_t *data)
 145 {
 146     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 147     uint32_t val;
 148
 149     switch(addr) {
 150     case 0x00:
 151         val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
 152         break;
 153     case 0x02:
 154         val = s->pm1a.en;
 155         break;
 156     case 0x04:
 157         val = s->pm1_cnt.cnt;
 158         break;
 159     case 0x08:
 160         val = acpi_pm_tmr_get(&s->tmr);
 161         break;
 162     default:
 163         val = 0;
 164         break;
 165     }
 166     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
 167     *data = val;
 168 }
 169
 170 static const IORangeOps pm_iorange_ops = {
 171     .read = pm_ioport_read,
 172     .write = pm_ioport_write,
 173 };
 174
 175 static void apm_ctrl_changed(uint32_t val, void *arg)
 176 {
 177     PIIX4PMState *s = arg;
 178
 179     /* ACPI specs 3.0, 4.7.2.5 */
 180     acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
 181
 182     if (s->dev.config[0x5b] & (1 << 1)) {
 183         if (s->smi_irq) {
 184             qemu_irq_raise(s->smi_irq);
 185         }
 186     }
 187 }
 188
 189 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 190 {
 191     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 192 }
 193
 194 static void pm_io_space_update(PIIX4PMState *s)
 195 {
 196     uint32_t pm_io_base;
 197
 198     if (s->dev.config[0x80] & 1) {
 199         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 200         pm_io_base &= 0xffc0;
 201
 202         /* XXX: need to improve memory and ioport allocation */
 203         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 204         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 205         ioport_register(&s->ioport);
 206     }
 207 }
 208
 209 static void pm_write_config(PCIDevice *d,
 210                             uint32_t address, uint32_t val, int len)
 211 {
 212     pci_default_write_config(d, address, val, len);
 213     if (range_covers_byte(address, len, 0x80))
 214         pm_io_space_update((PIIX4PMState *)d);
 215 }
 216
 217 static int vmstate_acpi_post_load(void *opaque, int version_id)
 218 {
 219     PIIX4PMState *s = opaque;
 220
 221     pm_io_space_update(s);
 222     return 0;
 223 }
 224
 225 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 226  {                                                                   \
 227      .name       = (stringify(_field)),                              \
 228      .version_id = 0,                                                \
 229      .info       = &vmstate_info_uint16,                             \
 230      .size       = sizeof(uint16_t),                                 \
 231      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 232      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 233  }
 234
 235 static const VMStateDescription vmstate_gpe = {
 236     .name = "gpe",
 237     .version_id = 1,
 238     .minimum_version_id = 1,
 239     .minimum_version_id_old = 1,
 240     .fields      = (VMStateField []) {
 241         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 242         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 243         VMSTATE_END_OF_LIST()
 244     }
 245 };
 246
 247 static const VMStateDescription vmstate_pci_status = {
 248     .name = "pci_status",
 249     .version_id = 1,
 250     .minimum_version_id = 1,
 251     .minimum_version_id_old = 1,
 252     .fields      = (VMStateField []) {
 253         VMSTATE_UINT32(up, struct pci_status),
 254         VMSTATE_UINT32(down, struct pci_status),
 255         VMSTATE_END_OF_LIST()
 256     }
 257 };
 258
 259 static const VMStateDescription vmstate_acpi = {
 260     .name = "piix4_pm",
 261     .version_id = 2,
 262     .minimum_version_id = 1,
 263     .minimum_version_id_old = 1,
 264     .post_load = vmstate_acpi_post_load,
 265     .fields      = (VMStateField []) {
 266         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 267         VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
 268         VMSTATE_UINT16(pm1a.en, PIIX4PMState),
 269         VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
 270         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 271         VMSTATE_TIMER(tmr.timer, PIIX4PMState),
 272         VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
 273         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 274         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 275                        struct pci_status),
 276         VMSTATE_END_OF_LIST()
 277     }
 278 };
 279
 280 static void piix4_update_hotplug(PIIX4PMState *s)
 281 {
 282     PCIDevice *dev = &s->dev;
 283     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 284     DeviceState *qdev, *next;
 285
 286     s->pci0_hotplug_enable = ~0;
 287
 288     QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 289         PCIDevice *pdev = PCI_DEVICE(qdev);
 290         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
 291         int slot = PCI_SLOT(pdev->devfn);
 292
 293         if (pc->no_hotplug) {
 294             s->pci0_hotplug_enable &= ~(1 << slot);
 295         }
 296     }
 297 }
 298
 299 static void piix4_reset(void *opaque)
 300 {
 301     PIIX4PMState *s = opaque;
 302     uint8_t *pci_conf = s->dev.config;
 303
 304     pci_conf[0x58] = 0;
 305     pci_conf[0x59] = 0;
 306     pci_conf[0x5a] = 0;
 307     pci_conf[0x5b] = 0;
 308
 309     if (s->kvm_enabled) {
 310         /* Mark SMM as already inited (until KVM supports SMM). */
 311         pci_conf[0x5B] = 0x02;
 312     }
 313     piix4_update_hotplug(s);
 314 }
 315
 316 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 317 {
 318     PIIX4PMState *s = opaque;
 319     ACPIPM1EVT *pm1a = s? &s->pm1a: NULL;
 320     ACPIPMTimer *tmr = s? &s->tmr: NULL;
 321
 322     acpi_pm1_evt_power_down(pm1a, tmr);
 323 }
 324
 325 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 326 {
 327     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 328     uint8_t *pci_conf;
 329
 330     pci_conf = s->dev.config;
 331     pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
 332     pci_conf[0x63] = 0x60;
 333     pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
 334         (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
 335
 336 }
 337
 338 static PIIX4PMState *global_piix4_pm_state; /* cpu hotadd */
 339
 340 static int piix4_pm_initfn(PCIDevice *dev)
 341 {
 342     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 343     uint8_t *pci_conf;
 344
 345     /* for cpu hotadd */
 346     global_piix4_pm_state = s;
 347
 348     pci_conf = s->dev.config;
 349     pci_conf[0x06] = 0x80;
 350     pci_conf[0x07] = 0x02;
 351     pci_conf[0x09] = 0x00;
 352     pci_conf[0x3d] = 0x01; // interrupt pin 1
 353
 354     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 355
 356     /* APM */
 357     apm_init(&s->apm, apm_ctrl_changed, s);
 358
 359     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 360
 361     if (s->kvm_enabled) {
 362         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 363          * support SMM mode. */
 364         pci_conf[0x5B] = 0x02;
 365     }
 366
 367     /* XXX: which specification is used ? The i82731AB has different
 368        mappings */
 369     pci_conf[0x90] = s->smb_io_base | 1;
 370     pci_conf[0x91] = s->smb_io_base >> 8;
 371     pci_conf[0xd2] = 0x09;
 372     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 373     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 374
 375     acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
 376     acpi_gpe_init(&s->gpe, GPE_LEN);
 377
 378     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 379
 380     pm_smbus_init(&s->dev.qdev, &s->smb);
 381     s->machine_ready.notify = piix4_pm_machine_ready;
 382     qemu_add_machine_init_done_notifier(&s->machine_ready);
 383     qemu_register_reset(piix4_reset, s);
 384     piix4_acpi_system_hot_add_init(dev->bus, s);
 385
 386     return 0;
 387 }
 388
 389 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 390                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 391                        int kvm_enabled)
 392 {
 393     PCIDevice *dev;
 394     PIIX4PMState *s;
 395
 396     dev = pci_create(bus, devfn, "PIIX4_PM");
 397     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 398
 399     s = DO_UPCAST(PIIX4PMState, dev, dev);
 400     s->irq = sci_irq;
 401     acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
 402     s->smi_irq = smi_irq;
 403     s->kvm_enabled = kvm_enabled;
 404
 405     qdev_init_nofail(&dev->qdev);
 406
 407     return s->smb.smbus;
 408 }
 409
 410 static Property piix4_pm_properties[] = {
 411     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 412     DEFINE_PROP_END_OF_LIST(),
 413 };
 414
 415 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 416 {
 417     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 418
 419     k->no_hotplug = 1;
 420     k->init = piix4_pm_initfn;
 421     k->config_write = pm_write_config;
 422     k->vendor_id = PCI_VENDOR_ID_INTEL;
 423     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 424     k->revision = 0x03;
 425     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 426 }
 427
 428 static DeviceInfo piix4_pm_info = {
 429     .name = "PIIX4_PM",
 430     .desc = "PM",
 431     .size = sizeof(PIIX4PMState),
 432     .vmsd = &vmstate_acpi,
 433     .no_user = 1,
 434     .props = piix4_pm_properties,
 435     .class_init = piix4_pm_class_init,
 436 };
 437
 438 static void piix4_pm_register(void)
 439 {
 440     pci_qdev_register(&piix4_pm_info);
 441 }
 442
 443 device_init(piix4_pm_register);
 444
 445 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 446 {
 447     PIIX4PMState *s = opaque;
 448     uint32_t val = 0;
 449     struct gpe_regs *g = &s->gpe_cpu;
 450
 451     switch (addr) {
 452         case PROC_BASE ... PROC_BASE+31:
 453             val = g->cpus_sts[addr - PROC_BASE];
 454             break;
 455         default:
 456             val = acpi_gpe_ioport_readb(&s->gpe, addr);
 457     }
 458
 459     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 460     return val;
 461 }
 462
 463 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 464 {
 465     PIIX4PMState *s = opaque;
 466
 467     acpi_gpe_ioport_writeb(&s->gpe, addr, val);
 468     pm_update_sci(s);
 469
 470     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 471 }
 472
 473 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 474 {
 475     uint32_t val = 0;
 476     struct pci_status *g = opaque;
 477     switch (addr) {
 478         case PCI_BASE:
 479             val = g->up;
 480             break;
 481         case PCI_BASE + 4:
 482             val = g->down;
 483             break;
 484         default:
 485             break;
 486     }
 487
 488     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 489     return val;
 490 }
 491
 492 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 493 {
 494     struct pci_status *g = opaque;
 495     switch (addr) {
 496         case PCI_BASE:
 497             g->up = val;
 498             break;
 499         case PCI_BASE + 4:
 500             g->down = val;
 501             break;
 502    }
 503
 504     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 505 }
 506
 507 static uint32_t pciej_read(void *opaque, uint32_t addr)
 508 {
 509     PIIX4_DPRINTF("pciej read %x\n", addr);
 510     return 0;
 511 }
 512
 513 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 514 {
 515     BusState *bus = opaque;
 516     DeviceState *qdev, *next;
 517     int slot = ffs(val) - 1;
 518
 519     QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 520         PCIDevice *dev = PCI_DEVICE(qdev);
 521         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 522         if (PCI_SLOT(dev->devfn) == slot && !pc->no_hotplug) {
 523             qdev_free(qdev);
 524         }
 525     }
 526
 527
 528     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 529 }
 530
 531 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 532 {
 533     PIIX4PMState *s = opaque;
 534
 535     return s->pci0_hotplug_enable;
 536 }
 537
 538 static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
 539 {
 540     return;
 541 }
 542
 543 extern const char *global_cpu_model;
 544
 545 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 546                                 PCIHotplugState state);
 547
 548 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 549 {
 550     struct pci_status *pci0_status = &s->pci0_status;
 551     int i = 0, cpus = smp_cpus;
 552
 553     while (cpus > 0) {
 554         s->gpe_cpu.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 555         cpus -= 8;
 556     }
 557
 558     register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
 559     register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
 560     acpi_gpe_blk(&s->gpe, GPE_BASE);
 561
 562     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s);
 563     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, s);
 564
 565     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 566     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 567
 568     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 569     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 570
 571     register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
 572     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 573
 574     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 575 }
 576
 577 #if defined(TARGET_I386)
 578 static void enable_processor(PIIX4PMState *s, int cpu)
 579 {
 580     struct gpe_regs *g = &s->gpe_cpu;
 581     ACPIGPE *gpe = &s->gpe;
 582
 583     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 584     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 585 }
 586
 587 static void disable_processor(PIIX4PMState *s, int cpu)
 588 {
 589     struct gpe_regs *g = &s->gpe_cpu;
 590     ACPIGPE *gpe = &s->gpe;
 591
 592     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 593     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 594 }
 595
 596 void qemu_system_cpu_hot_add(int cpu, int state)
 597 {
 598     CPUState *env;
 599     PIIX4PMState *s = global_piix4_pm_state;
 600
 601     if (state && !qemu_get_cpu(cpu)) {
 602         env = pc_new_cpu(global_cpu_model);
 603         if (!env) {
 604             fprintf(stderr, "cpu %d creation failed\n", cpu);
 605             return;
 606         }
 607         env->cpuid_apic_id = cpu;
 608     }
 609
 610     if (state)
 611         enable_processor(s, cpu);
 612     else
 613         disable_processor(s, cpu);
 614
 615     pm_update_sci(s);
 616 }
 617 #endif
 618
 619 static void enable_device(PIIX4PMState *s, int slot)
 620 {
 621     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 622     s->pci0_status.up |= (1 << slot);
 623 }
 624
 625 static void disable_device(PIIX4PMState *s, int slot)
 626 {
 627     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 628     s->pci0_status.down |= (1 << slot);
 629 }
 630
 631 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 632                                 PCIHotplugState state)
 633 {
 634     int slot = PCI_SLOT(dev->devfn);
 635     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 636                                 PCI_DEVICE(qdev));
 637
 638     /* Don't send event when device is enabled during qemu machine creation:
 639      * it is present on boot, no hotplug event is necessary. We do send an
 640      * event when the device is disabled later. */
 641     if (state == PCI_COLDPLUG_ENABLED) {
 642         return 0;
 643     }
 644
 645     s->pci0_status.up = 0;
 646     s->pci0_status.down = 0;
 647     if (state == PCI_HOTPLUG_ENABLED) {
 648         enable_device(s, slot);
 649     } else {
 650         disable_device(s, slot);
 651     }
 652
 653     pm_update_sci(s);
 654
 655     return 0;
 656 }