hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw.h"
  22 #include "pc.h"
  23 #include "apm.h"
  24 #include "pm_smbus.h"
  25 #include "pci.h"
  26 #include "acpi.h"
  27 #include "sysemu.h"
  28 #include "range.h"
  29 #include "ioport.h"
  30 #include "fw_cfg.h"
  31
  32 //#define DEBUG
  33
  34 #ifdef DEBUG
  35 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  36 #else
  37 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  38 #endif
  39
  40 #define ACPI_DBG_IO_ADDR  0xb044
  41
  42 #define GPE_BASE 0xafe0
  43 #define PROC_BASE 0xaf00
  44 #define GPE_LEN 4
  45 #define PCI_UP_BASE 0xae00
  46 #define PCI_DOWN_BASE 0xae04
  47 #define PCI_EJ_BASE 0xae08
  48 #define PCI_RMV_BASE 0xae0c
  49
  50 #define PIIX4_CPU_HOTPLUG_STATUS 4
  51 #define PIIX4_PCI_HOTPLUG_STATUS 2
  52
  53 struct gpe_regs {
  54     uint8_t cpus_sts[32];
  55 };
  56
  57 struct pci_status {
  58     uint32_t up; /* deprecated, maintained for migration compatibility */
  59     uint32_t down;
  60 };
  61
  62 typedef struct PIIX4PMState {
  63     PCIDevice dev;
  64     IORange ioport;
  65     ACPIREGS ar;
  66
  67     APMState apm;
  68
  69     PMSMBus smb;
  70     uint32_t smb_io_base;
  71
  72     qemu_irq irq;
  73     qemu_irq smi_irq;
  74     int kvm_enabled;
  75     Notifier machine_ready;
  76     Notifier powerdown_notifier;
  77
  78     /* for pci hotplug */
  79     struct gpe_regs gpe_cpu;
  80     struct pci_status pci0_status;
  81     uint32_t pci0_hotplug_enable;
  82     uint32_t pci0_slot_device_present;
  83
  84     uint8_t disable_s3;
  85     uint8_t disable_s4;
  86     uint8_t s4_val;
  87 } PIIX4PMState;
  88
  89 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  90
  91 #define ACPI_ENABLE 0xf1
  92 #define ACPI_DISABLE 0xf0
  93
  94 static void pm_update_sci(PIIX4PMState *s)
  95 {
  96     int sci_level, pmsts;
  97
  98     pmsts = acpi_pm1_evt_get_sts(&s->ar);
  99     sci_level = (((pmsts & s->ar.pm1.evt.en) &
 100                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
 101                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
 102                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
 103                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
 104         (((s->ar.gpe.sts[0] & s->ar.gpe.en[0])
 105           & PIIX4_PCI_HOTPLUG_STATUS) != 0);
 106
 107     qemu_set_irq(s->irq, sci_level);
 108     /* schedule a timer interruption if needed */
 109     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
 110                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 111 }
 112
 113 static void pm_tmr_timer(ACPIREGS *ar)
 114 {
 115     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 116     pm_update_sci(s);
 117 }
 118
 119 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 120                             uint64_t val)
 121 {
 122     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 123
 124     if (width != 2) {
 125         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 126                       (unsigned)addr, width, (unsigned)val);
 127     }
 128
 129     switch(addr) {
 130     case 0x00:
 131         acpi_pm1_evt_write_sts(&s->ar, val);
 132         pm_update_sci(s);
 133         break;
 134     case 0x02:
 135         acpi_pm1_evt_write_en(&s->ar, val);
 136         pm_update_sci(s);
 137         break;
 138     case 0x04:
 139         acpi_pm1_cnt_write(&s->ar, val, s->s4_val);
 140         break;
 141     default:
 142         break;
 143     }
 144     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
 145                   (unsigned int)val);
 146 }
 147
 148 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 149                             uint64_t *data)
 150 {
 151     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 152     uint32_t val;
 153
 154     switch(addr) {
 155     case 0x00:
 156         val = acpi_pm1_evt_get_sts(&s->ar);
 157         break;
 158     case 0x02:
 159         val = s->ar.pm1.evt.en;
 160         break;
 161     case 0x04:
 162         val = s->ar.pm1.cnt.cnt;
 163         break;
 164     case 0x08:
 165         val = acpi_pm_tmr_get(&s->ar);
 166         break;
 167     default:
 168         val = 0;
 169         break;
 170     }
 171     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
 172     *data = val;
 173 }
 174
 175 static const IORangeOps pm_iorange_ops = {
 176     .read = pm_ioport_read,
 177     .write = pm_ioport_write,
 178 };
 179
 180 static void apm_ctrl_changed(uint32_t val, void *arg)
 181 {
 182     PIIX4PMState *s = arg;
 183
 184     /* ACPI specs 3.0, 4.7.2.5 */
 185     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 186
 187     if (s->dev.config[0x5b] & (1 << 1)) {
 188         if (s->smi_irq) {
 189             qemu_irq_raise(s->smi_irq);
 190         }
 191     }
 192 }
 193
 194 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 195 {
 196     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 197 }
 198
 199 static void pm_io_space_update(PIIX4PMState *s)
 200 {
 201     uint32_t pm_io_base;
 202
 203     if (s->dev.config[0x80] & 1) {
 204         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 205         pm_io_base &= 0xffc0;
 206
 207         /* XXX: need to improve memory and ioport allocation */
 208         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 209         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 210         ioport_register(&s->ioport);
 211     }
 212 }
 213
 214 static void pm_write_config(PCIDevice *d,
 215                             uint32_t address, uint32_t val, int len)
 216 {
 217     pci_default_write_config(d, address, val, len);
 218     if (range_covers_byte(address, len, 0x80))
 219         pm_io_space_update((PIIX4PMState *)d);
 220 }
 221
 222 static void vmstate_pci_status_pre_save(void *opaque)
 223 {
 224     struct pci_status *pci0_status = opaque;
 225     PIIX4PMState *s = container_of(pci0_status, PIIX4PMState, pci0_status);
 226
 227     /* We no longer track up, so build a safe value for migrating
 228      * to a version that still does... of course these might get lost
 229      * by an old buggy implementation, but we try. */
 230     pci0_status->up = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 231 }
 232
 233 static int vmstate_acpi_post_load(void *opaque, int version_id)
 234 {
 235     PIIX4PMState *s = opaque;
 236
 237     pm_io_space_update(s);
 238     return 0;
 239 }
 240
 241 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 242  {                                                                   \
 243      .name       = (stringify(_field)),                              \
 244      .version_id = 0,                                                \
 245      .info       = &vmstate_info_uint16,                             \
 246      .size       = sizeof(uint16_t),                                 \
 247      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 248      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 249  }
 250
 251 static const VMStateDescription vmstate_gpe = {
 252     .name = "gpe",
 253     .version_id = 1,
 254     .minimum_version_id = 1,
 255     .minimum_version_id_old = 1,
 256     .fields      = (VMStateField []) {
 257         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 258         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 259         VMSTATE_END_OF_LIST()
 260     }
 261 };
 262
 263 static const VMStateDescription vmstate_pci_status = {
 264     .name = "pci_status",
 265     .version_id = 1,
 266     .minimum_version_id = 1,
 267     .minimum_version_id_old = 1,
 268     .pre_save = vmstate_pci_status_pre_save,
 269     .fields      = (VMStateField []) {
 270         VMSTATE_UINT32(up, struct pci_status),
 271         VMSTATE_UINT32(down, struct pci_status),
 272         VMSTATE_END_OF_LIST()
 273     }
 274 };
 275
 276 static const VMStateDescription vmstate_acpi = {
 277     .name = "piix4_pm",
 278     .version_id = 2,
 279     .minimum_version_id = 1,
 280     .minimum_version_id_old = 1,
 281     .post_load = vmstate_acpi_post_load,
 282     .fields      = (VMStateField []) {
 283         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 284         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 285         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 286         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 287         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 288         VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
 289         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 290         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 291         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 292                        struct pci_status),
 293         VMSTATE_END_OF_LIST()
 294     }
 295 };
 296
 297 static void acpi_piix_eject_slot(PIIX4PMState *s, unsigned slots)
 298 {
 299     BusChild *kid, *next;
 300     BusState *bus = qdev_get_parent_bus(&s->dev.qdev);
 301     int slot = ffs(slots) - 1;
 302     bool slot_free = true;
 303
 304     /* Mark request as complete */
 305     s->pci0_status.down &= ~(1U << slot);
 306
 307     QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
 308         DeviceState *qdev = kid->child;
 309         PCIDevice *dev = PCI_DEVICE(qdev);
 310         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 311         if (PCI_SLOT(dev->devfn) == slot) {
 312             if (pc->no_hotplug) {
 313                 slot_free = false;
 314             } else {
 315                 qdev_free(qdev);
 316             }
 317         }
 318     }
 319     if (slot_free) {
 320         s->pci0_slot_device_present &= ~(1U << slot);
 321     }
 322 }
 323
 324 static void piix4_update_hotplug(PIIX4PMState *s)
 325 {
 326     PCIDevice *dev = &s->dev;
 327     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 328     BusChild *kid, *next;
 329
 330     /* Execute any pending removes during reset */
 331     while (s->pci0_status.down) {
 332         acpi_piix_eject_slot(s, s->pci0_status.down);
 333     }
 334
 335     s->pci0_hotplug_enable = ~0;
 336     s->pci0_slot_device_present = 0;
 337
 338     QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
 339         DeviceState *qdev = kid->child;
 340         PCIDevice *pdev = PCI_DEVICE(qdev);
 341         PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
 342         int slot = PCI_SLOT(pdev->devfn);
 343
 344         if (pc->no_hotplug) {
 345             s->pci0_hotplug_enable &= ~(1U << slot);
 346         }
 347
 348         s->pci0_slot_device_present |= (1U << slot);
 349     }
 350 }
 351
 352 static void piix4_reset(void *opaque)
 353 {
 354     PIIX4PMState *s = opaque;
 355     uint8_t *pci_conf = s->dev.config;
 356
 357     pci_conf[0x58] = 0;
 358     pci_conf[0x59] = 0;
 359     pci_conf[0x5a] = 0;
 360     pci_conf[0x5b] = 0;
 361
 362     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 363     pci_conf[0x80] = 0;
 364
 365     if (s->kvm_enabled) {
 366         /* Mark SMM as already inited (until KVM supports SMM). */
 367         pci_conf[0x5B] = 0x02;
 368     }
 369     piix4_update_hotplug(s);
 370 }
 371
 372 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 373 {
 374     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 375
 376     assert(s != NULL);
 377     acpi_pm1_evt_power_down(&s->ar);
 378 }
 379
 380 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 381 {
 382     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 383     uint8_t *pci_conf;
 384
 385     pci_conf = s->dev.config;
 386     pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
 387     pci_conf[0x63] = 0x60;
 388     pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
 389         (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
 390
 391 }
 392
 393 static PIIX4PMState *global_piix4_pm_state; /* cpu hotadd */
 394
 395 static int piix4_pm_initfn(PCIDevice *dev)
 396 {
 397     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 398     uint8_t *pci_conf;
 399
 400     /* for cpu hotadd */
 401     global_piix4_pm_state = s;
 402
 403     pci_conf = s->dev.config;
 404     pci_conf[0x06] = 0x80;
 405     pci_conf[0x07] = 0x02;
 406     pci_conf[0x09] = 0x00;
 407     pci_conf[0x3d] = 0x01; // interrupt pin 1
 408
 409     /* APM */
 410     apm_init(&s->apm, apm_ctrl_changed, s);
 411
 412     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 413
 414     if (s->kvm_enabled) {
 415         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 416          * support SMM mode. */
 417         pci_conf[0x5B] = 0x02;
 418     }
 419
 420     /* XXX: which specification is used ? The i82731AB has different
 421        mappings */
 422     pci_conf[0x90] = s->smb_io_base | 1;
 423     pci_conf[0x91] = s->smb_io_base >> 8;
 424     pci_conf[0xd2] = 0x09;
 425     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 426     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 427
 428     acpi_pm_tmr_init(&s->ar, pm_tmr_timer);
 429     acpi_gpe_init(&s->ar, GPE_LEN);
 430
 431     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 432     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 433
 434     pm_smbus_init(&s->dev.qdev, &s->smb);
 435     s->machine_ready.notify = piix4_pm_machine_ready;
 436     qemu_add_machine_init_done_notifier(&s->machine_ready);
 437     qemu_register_reset(piix4_reset, s);
 438     piix4_acpi_system_hot_add_init(dev->bus, s);
 439
 440     return 0;
 441 }
 442
 443 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 444                        qemu_irq sci_irq, qemu_irq smi_irq,
 445                        int kvm_enabled, void *fw_cfg)
 446 {
 447     PCIDevice *dev;
 448     PIIX4PMState *s;
 449
 450     dev = pci_create(bus, devfn, "PIIX4_PM");
 451     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 452
 453     s = DO_UPCAST(PIIX4PMState, dev, dev);
 454     s->irq = sci_irq;
 455     acpi_pm1_cnt_init(&s->ar);
 456     s->smi_irq = smi_irq;
 457     s->kvm_enabled = kvm_enabled;
 458
 459     qdev_init_nofail(&dev->qdev);
 460
 461     if (fw_cfg) {
 462         uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
 463         suspend[3] = 1 | ((!s->disable_s3) << 7);
 464         suspend[4] = s->s4_val | ((!s->disable_s4) << 7);
 465
 466         fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
 467     }
 468
 469     return s->smb.smbus;
 470 }
 471
 472 static Property piix4_pm_properties[] = {
 473     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 474     DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0),
 475     DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0),
 476     DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2),
 477     DEFINE_PROP_END_OF_LIST(),
 478 };
 479
 480 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 481 {
 482     DeviceClass *dc = DEVICE_CLASS(klass);
 483     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 484
 485     k->no_hotplug = 1;
 486     k->init = piix4_pm_initfn;
 487     k->config_write = pm_write_config;
 488     k->vendor_id = PCI_VENDOR_ID_INTEL;
 489     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 490     k->revision = 0x03;
 491     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 492     dc->desc = "PM";
 493     dc->no_user = 1;
 494     dc->vmsd = &vmstate_acpi;
 495     dc->props = piix4_pm_properties;
 496 }
 497
 498 static TypeInfo piix4_pm_info = {
 499     .name          = "PIIX4_PM",
 500     .parent        = TYPE_PCI_DEVICE,
 501     .instance_size = sizeof(PIIX4PMState),
 502     .class_init    = piix4_pm_class_init,
 503 };
 504
 505 static void piix4_pm_register_types(void)
 506 {
 507     type_register_static(&piix4_pm_info);
 508 }
 509
 510 type_init(piix4_pm_register_types)
 511
 512 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 513 {
 514     PIIX4PMState *s = opaque;
 515     uint32_t val = 0;
 516     struct gpe_regs *g = &s->gpe_cpu;
 517
 518     switch (addr) {
 519         case PROC_BASE ... PROC_BASE+31:
 520             val = g->cpus_sts[addr - PROC_BASE];
 521             break;
 522         default:
 523             val = acpi_gpe_ioport_readb(&s->ar, addr);
 524     }
 525
 526     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 527     return val;
 528 }
 529
 530 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 531 {
 532     PIIX4PMState *s = opaque;
 533
 534     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 535     pm_update_sci(s);
 536
 537     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 538 }
 539
 540 static uint32_t pci_up_read(void *opaque, uint32_t addr)
 541 {
 542     PIIX4PMState *s = opaque;
 543     uint32_t val;
 544
 545     /* Manufacture an "up" value to cause a device check on any hotplug
 546      * slot with a device.  Extra device checks are harmless. */
 547     val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
 548
 549     PIIX4_DPRINTF("pci_up_read %x\n", val);
 550     return val;
 551 }
 552
 553 static uint32_t pci_down_read(void *opaque, uint32_t addr)
 554 {
 555     PIIX4PMState *s = opaque;
 556     uint32_t val = s->pci0_status.down;
 557
 558     PIIX4_DPRINTF("pci_down_read %x\n", val);
 559     return val;
 560 }
 561
 562 static uint32_t pci_features_read(void *opaque, uint32_t addr)
 563 {
 564     /* No feature defined yet */
 565     PIIX4_DPRINTF("pci_features_read %x\n", 0);
 566     return 0;
 567 }
 568
 569 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 570 {
 571     acpi_piix_eject_slot(opaque, val);
 572
 573     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 574 }
 575
 576 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 577 {
 578     PIIX4PMState *s = opaque;
 579
 580     return s->pci0_hotplug_enable;
 581 }
 582
 583 extern const char *global_cpu_model;
 584
 585 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 586                                 PCIHotplugState state);
 587
 588 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 589 {
 590     int i = 0, cpus = smp_cpus;
 591
 592     while (cpus > 0) {
 593         s->gpe_cpu.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 594         cpus -= 8;
 595     }
 596
 597     register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
 598     register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
 599     acpi_gpe_blk(&s->ar, GPE_BASE);
 600
 601     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s);
 602     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, s);
 603
 604     register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
 605     register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
 606
 607     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
 608     register_ioport_read(PCI_EJ_BASE, 4, 4,  pci_features_read, s);
 609
 610     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 611
 612     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 613 }
 614
 615 #if defined(TARGET_I386)
 616 static void enable_processor(PIIX4PMState *s, int cpu)
 617 {
 618     struct gpe_regs *g = &s->gpe_cpu;
 619     ACPIGPE *gpe = &s->ar.gpe;
 620
 621     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 622     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 623 }
 624
 625 static void disable_processor(PIIX4PMState *s, int cpu)
 626 {
 627     struct gpe_regs *g = &s->gpe_cpu;
 628     ACPIGPE *gpe = &s->ar.gpe;
 629
 630     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 631     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 632 }
 633
 634 void qemu_system_cpu_hot_add(int cpu, int state)
 635 {
 636     X86CPU *env;
 637     PIIX4PMState *s = global_piix4_pm_state;
 638
 639     if (state && !qemu_get_cpu(cpu)) {
 640         env = pc_new_cpu(global_cpu_model);
 641         if (!env) {
 642             fprintf(stderr, "cpu %d creation failed\n", cpu);
 643             return;
 644         }
 645         env->env.cpuid_apic_id = cpu;
 646     }
 647
 648     if (state)
 649         enable_processor(s, cpu);
 650     else
 651         disable_processor(s, cpu);
 652
 653     pm_update_sci(s);
 654 }
 655 #endif
 656
 657 static void enable_device(PIIX4PMState *s, int slot)
 658 {
 659     s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 660     s->pci0_slot_device_present |= (1U << slot);
 661 }
 662
 663 static void disable_device(PIIX4PMState *s, int slot)
 664 {
 665     s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 666     s->pci0_status.down |= (1U << slot);
 667 }
 668
 669 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 670                                 PCIHotplugState state)
 671 {
 672     int slot = PCI_SLOT(dev->devfn);
 673     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 674                                 PCI_DEVICE(qdev));
 675
 676     /* Don't send event when device is enabled during qemu machine creation:
 677      * it is present on boot, no hotplug event is necessary. We do send an
 678      * event when the device is disabled later. */
 679     if (state == PCI_COLDPLUG_ENABLED) {
 680         s->pci0_slot_device_present |= (1U << slot);
 681         return 0;
 682     }
 683
 684     if (state == PCI_HOTPLUG_ENABLED) {
 685         enable_device(s, slot);
 686     } else {
 687         disable_device(s, slot);
 688     }
 689
 690     pm_update_sci(s);
 691
 692     return 0;
 693 }