target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  34                                                         uint32_t exception,
  35                                                         int error_code,
  36                                                         uintptr_t pc)
  37 {
  38     CPUState *cs = CPU(mips_env_get_cpu(env));
  39
  40     if (exception < EXCP_SC) {
  41         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  42     }
  43     cs->exception_index = exception;
  44     env->error_code = error_code;
  45
  46     if (pc) {
  47         /* now we have a real cpu fault */
  48         cpu_restore_state(cs, pc);
  49     }
  50
  51     cpu_loop_exit(cs);
  52 }
  53
  54 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  55                                                     uint32_t exception,
  56                                                     uintptr_t pc)
  57 {
  58     do_raise_exception_err(env, exception, 0, pc);
  59 }
  60
  61 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  62                                 int error_code)
  63 {
  64     do_raise_exception_err(env, exception, error_code, 0);
  65 }
  66
  67 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  68 {
  69     do_raise_exception(env, exception, 0);
  70 }
  71
  72 #if defined(CONFIG_USER_ONLY)
  73 #define HELPER_LD(name, insn, type)                                     \
  74 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  75                              int mem_idx)                               \
  76 {                                                                       \
  77     return (type) insn##_raw(addr);                                     \
  78 }
  79 #else
  80 #define HELPER_LD(name, insn, type)                                     \
  81 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  82                              int mem_idx)                               \
  83 {                                                                       \
  84     switch (mem_idx)                                                    \
  85     {                                                                   \
  86     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  87     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  88     default:                                                            \
  89     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  90     }                                                                   \
  91 }
  92 #endif
  93 HELPER_LD(lbu, ldub, uint8_t)
  94 HELPER_LD(lhu, lduw, uint16_t)
  95 HELPER_LD(lw, ldl, int32_t)
  96 HELPER_LD(ld, ldq, int64_t)
  97 #undef HELPER_LD
  98
  99 #if defined(CONFIG_USER_ONLY)
 100 #define HELPER_ST(name, insn, type)                                     \
 101 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 102                              type val, int mem_idx)                     \
 103 {                                                                       \
 104     insn##_raw(addr, val);                                              \
 105 }
 106 #else
 107 #define HELPER_ST(name, insn, type)                                     \
 108 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 109                              type val, int mem_idx)                     \
 110 {                                                                       \
 111     switch (mem_idx)                                                    \
 112     {                                                                   \
 113     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 114     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 115     default:                                                            \
 116     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 117     }                                                                   \
 118 }
 119 #endif
 120 HELPER_ST(sb, stb, uint8_t)
 121 HELPER_ST(sh, stw, uint16_t)
 122 HELPER_ST(sw, stl, uint32_t)
 123 HELPER_ST(sd, stq, uint64_t)
 124 #undef HELPER_ST
 125
 126 target_ulong helper_clo (target_ulong arg1)
 127 {
 128     return clo32(arg1);
 129 }
 130
 131 target_ulong helper_clz (target_ulong arg1)
 132 {
 133     return clz32(arg1);
 134 }
 135
 136 #if defined(TARGET_MIPS64)
 137 target_ulong helper_dclo (target_ulong arg1)
 138 {
 139     return clo64(arg1);
 140 }
 141
 142 target_ulong helper_dclz (target_ulong arg1)
 143 {
 144     return clz64(arg1);
 145 }
 146 #endif /* TARGET_MIPS64 */
 147
 148 /* 64 bits arithmetic for 32 bits hosts */
 149 static inline uint64_t get_HILO(CPUMIPSState *env)
 150 {
 151     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 152 }
 153
 154 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 155 {
 156     target_ulong tmp;
 157     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 158     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 159     return tmp;
 160 }
 161
 162 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 163 {
 164     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 165     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 166     return tmp;
 167 }
 168
 169 /* Multiplication variants of the vr54xx. */
 170 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 171                          target_ulong arg2)
 172 {
 173     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 174                                  (int64_t)(int32_t)arg2));
 175 }
 176
 177 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 178                           target_ulong arg2)
 179 {
 180     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 181                        (uint64_t)(uint32_t)arg2);
 182 }
 183
 184 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 185                          target_ulong arg2)
 186 {
 187     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 188                        (int64_t)(int32_t)arg2);
 189 }
 190
 191 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 192                            target_ulong arg2)
 193 {
 194     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 195                        (int64_t)(int32_t)arg2);
 196 }
 197
 198 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 199                           target_ulong arg2)
 200 {
 201     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 202                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 203 }
 204
 205 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 206                             target_ulong arg2)
 207 {
 208     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 209                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 210 }
 211
 212 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 213                          target_ulong arg2)
 214 {
 215     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 216                        (int64_t)(int32_t)arg2);
 217 }
 218
 219 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 220                            target_ulong arg2)
 221 {
 222     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 223                        (int64_t)(int32_t)arg2);
 224 }
 225
 226 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 227                           target_ulong arg2)
 228 {
 229     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 230                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 231 }
 232
 233 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 234                             target_ulong arg2)
 235 {
 236     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 237                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 238 }
 239
 240 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 241                           target_ulong arg2)
 242 {
 243     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 244 }
 245
 246 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 247                            target_ulong arg2)
 248 {
 249     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 250                        (uint64_t)(uint32_t)arg2);
 251 }
 252
 253 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 254                            target_ulong arg2)
 255 {
 256     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 257                        (int64_t)(int32_t)arg2);
 258 }
 259
 260 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 261                             target_ulong arg2)
 262 {
 263     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 264                        (uint64_t)(uint32_t)arg2);
 265 }
 266
 267 static inline target_ulong bitswap(target_ulong v)
 268 {
 269     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 270               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 271     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 272               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 273     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 274               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 275     return v;
 276 }
 277
 278 #ifdef TARGET_MIPS64
 279 target_ulong helper_dbitswap(target_ulong rt)
 280 {
 281     return bitswap(rt);
 282 }
 283 #endif
 284
 285 target_ulong helper_bitswap(target_ulong rt)
 286 {
 287     return (int32_t)bitswap(rt);
 288 }
 289
 290 #ifndef CONFIG_USER_ONLY
 291
 292 static inline hwaddr do_translate_address(CPUMIPSState *env,
 293                                                       target_ulong address,
 294                                                       int rw)
 295 {
 296     hwaddr lladdr;
 297
 298     lladdr = cpu_mips_translate_address(env, address, rw);
 299
 300     if (lladdr == -1LL) {
 301         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 302     } else {
 303         return lladdr;
 304     }
 305 }
 306
 307 #define HELPER_LD_ATOMIC(name, insn)                                          \
 308 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 309 {                                                                             \
 310     env->lladdr = do_translate_address(env, arg, 0);                          \
 311     env->llval = do_##insn(env, arg, mem_idx);                                \
 312     return env->llval;                                                        \
 313 }
 314 HELPER_LD_ATOMIC(ll, lw)
 315 #ifdef TARGET_MIPS64
 316 HELPER_LD_ATOMIC(lld, ld)
 317 #endif
 318 #undef HELPER_LD_ATOMIC
 319
 320 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 321 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 322                            target_ulong arg2, int mem_idx)                    \
 323 {                                                                             \
 324     target_long tmp;                                                          \
 325                                                                               \
 326     if (arg2 & almask) {                                                      \
 327         env->CP0_BadVAddr = arg2;                                             \
 328         helper_raise_exception(env, EXCP_AdES);                               \
 329     }                                                                         \
 330     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 331         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 332         if (tmp == env->llval) {                                              \
 333             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 334             return 1;                                                         \
 335         }                                                                     \
 336     }                                                                         \
 337     return 0;                                                                 \
 338 }
 339 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 340 #ifdef TARGET_MIPS64
 341 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 342 #endif
 343 #undef HELPER_ST_ATOMIC
 344 #endif
 345
 346 #ifdef TARGET_WORDS_BIGENDIAN
 347 #define GET_LMASK(v) ((v) & 3)
 348 #define GET_OFFSET(addr, offset) (addr + (offset))
 349 #else
 350 #define GET_LMASK(v) (((v) & 3) ^ 3)
 351 #define GET_OFFSET(addr, offset) (addr - (offset))
 352 #endif
 353
 354 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 355                 int mem_idx)
 356 {
 357     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 358
 359     if (GET_LMASK(arg2) <= 2)
 360         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 361
 362     if (GET_LMASK(arg2) <= 1)
 363         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 364
 365     if (GET_LMASK(arg2) == 0)
 366         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 367 }
 368
 369 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 370                 int mem_idx)
 371 {
 372     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 373
 374     if (GET_LMASK(arg2) >= 1)
 375         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 376
 377     if (GET_LMASK(arg2) >= 2)
 378         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 379
 380     if (GET_LMASK(arg2) == 3)
 381         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 382 }
 383
 384 #if defined(TARGET_MIPS64)
 385 /* "half" load and stores.  We must do the memory access inline,
 386    or fault handling won't work.  */
 387
 388 #ifdef TARGET_WORDS_BIGENDIAN
 389 #define GET_LMASK64(v) ((v) & 7)
 390 #else
 391 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 392 #endif
 393
 394 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 395                 int mem_idx)
 396 {
 397     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 398
 399     if (GET_LMASK64(arg2) <= 6)
 400         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 401
 402     if (GET_LMASK64(arg2) <= 5)
 403         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 404
 405     if (GET_LMASK64(arg2) <= 4)
 406         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 407
 408     if (GET_LMASK64(arg2) <= 3)
 409         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 410
 411     if (GET_LMASK64(arg2) <= 2)
 412         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 413
 414     if (GET_LMASK64(arg2) <= 1)
 415         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 416
 417     if (GET_LMASK64(arg2) <= 0)
 418         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 419 }
 420
 421 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 422                 int mem_idx)
 423 {
 424     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 425
 426     if (GET_LMASK64(arg2) >= 1)
 427         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 428
 429     if (GET_LMASK64(arg2) >= 2)
 430         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 431
 432     if (GET_LMASK64(arg2) >= 3)
 433         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 434
 435     if (GET_LMASK64(arg2) >= 4)
 436         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 437
 438     if (GET_LMASK64(arg2) >= 5)
 439         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 440
 441     if (GET_LMASK64(arg2) >= 6)
 442         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 443
 444     if (GET_LMASK64(arg2) == 7)
 445         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 446 }
 447 #endif /* TARGET_MIPS64 */
 448
 449 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 450
 451 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 452                 uint32_t mem_idx)
 453 {
 454     target_ulong base_reglist = reglist & 0xf;
 455     target_ulong do_r31 = reglist & 0x10;
 456
 457     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 458         target_ulong i;
 459
 460         for (i = 0; i < base_reglist; i++) {
 461             env->active_tc.gpr[multiple_regs[i]] =
 462                 (target_long)do_lw(env, addr, mem_idx);
 463             addr += 4;
 464         }
 465     }
 466
 467     if (do_r31) {
 468         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 469     }
 470 }
 471
 472 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 473                 uint32_t mem_idx)
 474 {
 475     target_ulong base_reglist = reglist & 0xf;
 476     target_ulong do_r31 = reglist & 0x10;
 477
 478     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 479         target_ulong i;
 480
 481         for (i = 0; i < base_reglist; i++) {
 482             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 483             addr += 4;
 484         }
 485     }
 486
 487     if (do_r31) {
 488         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 489     }
 490 }
 491
 492 #if defined(TARGET_MIPS64)
 493 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 494                 uint32_t mem_idx)
 495 {
 496     target_ulong base_reglist = reglist & 0xf;
 497     target_ulong do_r31 = reglist & 0x10;
 498
 499     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 500         target_ulong i;
 501
 502         for (i = 0; i < base_reglist; i++) {
 503             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 504             addr += 8;
 505         }
 506     }
 507
 508     if (do_r31) {
 509         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 510     }
 511 }
 512
 513 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 514                 uint32_t mem_idx)
 515 {
 516     target_ulong base_reglist = reglist & 0xf;
 517     target_ulong do_r31 = reglist & 0x10;
 518
 519     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 520         target_ulong i;
 521
 522         for (i = 0; i < base_reglist; i++) {
 523             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 524             addr += 8;
 525         }
 526     }
 527
 528     if (do_r31) {
 529         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 530     }
 531 }
 532 #endif
 533
 534 #ifndef CONFIG_USER_ONLY
 535 /* SMP helpers.  */
 536 static bool mips_vpe_is_wfi(MIPSCPU *c)
 537 {
 538     CPUState *cpu = CPU(c);
 539     CPUMIPSState *env = &c->env;
 540
 541     /* If the VPE is halted but otherwise active, it means it's waiting for
 542        an interrupt.  */
 543     return cpu->halted && mips_vpe_active(env);
 544 }
 545
 546 static inline void mips_vpe_wake(MIPSCPU *c)
 547 {
 548     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 549        because there might be other conditions that state that c should
 550        be sleeping.  */
 551     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 552 }
 553
 554 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 555 {
 556     CPUState *cs = CPU(cpu);
 557
 558     /* The VPE was shut off, really go to bed.
 559        Reset any old _WAKE requests.  */
 560     cs->halted = 1;
 561     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 562 }
 563
 564 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 565 {
 566     CPUMIPSState *c = &cpu->env;
 567
 568     /* FIXME: TC reschedule.  */
 569     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 570         mips_vpe_wake(cpu);
 571     }
 572 }
 573
 574 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 575 {
 576     CPUMIPSState *c = &cpu->env;
 577
 578     /* FIXME: TC reschedule.  */
 579     if (!mips_vpe_active(c)) {
 580         mips_vpe_sleep(cpu);
 581     }
 582 }
 583
 584 /**
 585  * mips_cpu_map_tc:
 586  * @env: CPU from which mapping is performed.
 587  * @tc: Should point to an int with the value of the global TC index.
 588  *
 589  * This function will transform @tc into a local index within the
 590  * returned #CPUMIPSState.
 591  */
 592 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 593           which depends on runtime setup. Can probably be fixed by
 594           walking the list of CPUMIPSStates.  */
 595 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 596 {
 597     MIPSCPU *cpu;
 598     CPUState *cs;
 599     CPUState *other_cs;
 600     int vpe_idx;
 601     int tc_idx = *tc;
 602
 603     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 604         /* Not allowed to address other CPUs.  */
 605         *tc = env->current_tc;
 606         return env;
 607     }
 608
 609     cs = CPU(mips_env_get_cpu(env));
 610     vpe_idx = tc_idx / cs->nr_threads;
 611     *tc = tc_idx % cs->nr_threads;
 612     other_cs = qemu_get_cpu(vpe_idx);
 613     if (other_cs == NULL) {
 614         return env;
 615     }
 616     cpu = MIPS_CPU(other_cs);
 617     return &cpu->env;
 618 }
 619
 620 /* The per VPE CP0_Status register shares some fields with the per TC
 621    CP0_TCStatus registers. These fields are wired to the same registers,
 622    so changes to either of them should be reflected on both registers.
 623
 624    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 625
 626    These helper call synchronizes the regs for a given cpu.  */
 627
 628 /* Called for updates to CP0_Status.  */
 629 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 630 {
 631     int32_t tcstatus, *tcst;
 632     uint32_t v = cpu->CP0_Status;
 633     uint32_t cu, mx, asid, ksu;
 634     uint32_t mask = ((1 << CP0TCSt_TCU3)
 635                        | (1 << CP0TCSt_TCU2)
 636                        | (1 << CP0TCSt_TCU1)
 637                        | (1 << CP0TCSt_TCU0)
 638                        | (1 << CP0TCSt_TMX)
 639                        | (3 << CP0TCSt_TKSU)
 640                        | (0xff << CP0TCSt_TASID));
 641
 642     cu = (v >> CP0St_CU0) & 0xf;
 643     mx = (v >> CP0St_MX) & 0x1;
 644     ksu = (v >> CP0St_KSU) & 0x3;
 645     asid = env->CP0_EntryHi & 0xff;
 646
 647     tcstatus = cu << CP0TCSt_TCU0;
 648     tcstatus |= mx << CP0TCSt_TMX;
 649     tcstatus |= ksu << CP0TCSt_TKSU;
 650     tcstatus |= asid;
 651
 652     if (tc == cpu->current_tc) {
 653         tcst = &cpu->active_tc.CP0_TCStatus;
 654     } else {
 655         tcst = &cpu->tcs[tc].CP0_TCStatus;
 656     }
 657
 658     *tcst &= ~mask;
 659     *tcst |= tcstatus;
 660     compute_hflags(cpu);
 661 }
 662
 663 /* Called for updates to CP0_TCStatus.  */
 664 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 665                              target_ulong v)
 666 {
 667     uint32_t status;
 668     uint32_t tcu, tmx, tasid, tksu;
 669     uint32_t mask = ((1U << CP0St_CU3)
 670                        | (1 << CP0St_CU2)
 671                        | (1 << CP0St_CU1)
 672                        | (1 << CP0St_CU0)
 673                        | (1 << CP0St_MX)
 674                        | (3 << CP0St_KSU));
 675
 676     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 677     tmx = (v >> CP0TCSt_TMX) & 0x1;
 678     tasid = v & 0xff;
 679     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 680
 681     status = tcu << CP0St_CU0;
 682     status |= tmx << CP0St_MX;
 683     status |= tksu << CP0St_KSU;
 684
 685     cpu->CP0_Status &= ~mask;
 686     cpu->CP0_Status |= status;
 687
 688     /* Sync the TASID with EntryHi.  */
 689     cpu->CP0_EntryHi &= ~0xff;
 690     cpu->CP0_EntryHi = tasid;
 691
 692     compute_hflags(cpu);
 693 }
 694
 695 /* Called for updates to CP0_EntryHi.  */
 696 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 697 {
 698     int32_t *tcst;
 699     uint32_t asid, v = cpu->CP0_EntryHi;
 700
 701     asid = v & 0xff;
 702
 703     if (tc == cpu->current_tc) {
 704         tcst = &cpu->active_tc.CP0_TCStatus;
 705     } else {
 706         tcst = &cpu->tcs[tc].CP0_TCStatus;
 707     }
 708
 709     *tcst &= ~0xff;
 710     *tcst |= asid;
 711 }
 712
 713 /* CP0 helpers */
 714 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 715 {
 716     return env->mvp->CP0_MVPControl;
 717 }
 718
 719 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 720 {
 721     return env->mvp->CP0_MVPConf0;
 722 }
 723
 724 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 725 {
 726     return env->mvp->CP0_MVPConf1;
 727 }
 728
 729 target_ulong helper_mfc0_random(CPUMIPSState *env)
 730 {
 731     return (int32_t)cpu_mips_get_random(env);
 732 }
 733
 734 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 735 {
 736     return env->active_tc.CP0_TCStatus;
 737 }
 738
 739 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 740 {
 741     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 742     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 743
 744     if (other_tc == other->current_tc)
 745         return other->active_tc.CP0_TCStatus;
 746     else
 747         return other->tcs[other_tc].CP0_TCStatus;
 748 }
 749
 750 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 751 {
 752     return env->active_tc.CP0_TCBind;
 753 }
 754
 755 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 756 {
 757     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 758     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 759
 760     if (other_tc == other->current_tc)
 761         return other->active_tc.CP0_TCBind;
 762     else
 763         return other->tcs[other_tc].CP0_TCBind;
 764 }
 765
 766 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 767 {
 768     return env->active_tc.PC;
 769 }
 770
 771 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 772 {
 773     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 774     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 775
 776     if (other_tc == other->current_tc)
 777         return other->active_tc.PC;
 778     else
 779         return other->tcs[other_tc].PC;
 780 }
 781
 782 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 783 {
 784     return env->active_tc.CP0_TCHalt;
 785 }
 786
 787 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 788 {
 789     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 790     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 791
 792     if (other_tc == other->current_tc)
 793         return other->active_tc.CP0_TCHalt;
 794     else
 795         return other->tcs[other_tc].CP0_TCHalt;
 796 }
 797
 798 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 799 {
 800     return env->active_tc.CP0_TCContext;
 801 }
 802
 803 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 804 {
 805     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 806     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 807
 808     if (other_tc == other->current_tc)
 809         return other->active_tc.CP0_TCContext;
 810     else
 811         return other->tcs[other_tc].CP0_TCContext;
 812 }
 813
 814 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 815 {
 816     return env->active_tc.CP0_TCSchedule;
 817 }
 818
 819 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 820 {
 821     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 822     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 823
 824     if (other_tc == other->current_tc)
 825         return other->active_tc.CP0_TCSchedule;
 826     else
 827         return other->tcs[other_tc].CP0_TCSchedule;
 828 }
 829
 830 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 831 {
 832     return env->active_tc.CP0_TCScheFBack;
 833 }
 834
 835 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 836 {
 837     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 838     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 839
 840     if (other_tc == other->current_tc)
 841         return other->active_tc.CP0_TCScheFBack;
 842     else
 843         return other->tcs[other_tc].CP0_TCScheFBack;
 844 }
 845
 846 target_ulong helper_mfc0_count(CPUMIPSState *env)
 847 {
 848     return (int32_t)cpu_mips_get_count(env);
 849 }
 850
 851 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 852 {
 853     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 854     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 855
 856     return other->CP0_EntryHi;
 857 }
 858
 859 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 860 {
 861     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 862     int32_t tccause;
 863     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 864
 865     if (other_tc == other->current_tc) {
 866         tccause = other->CP0_Cause;
 867     } else {
 868         tccause = other->CP0_Cause;
 869     }
 870
 871     return tccause;
 872 }
 873
 874 target_ulong helper_mftc0_status(CPUMIPSState *env)
 875 {
 876     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 877     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 878
 879     return other->CP0_Status;
 880 }
 881
 882 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 883 {
 884     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 885 }
 886
 887 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 888 {
 889     return (int32_t)env->CP0_WatchLo[sel];
 890 }
 891
 892 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 893 {
 894     return env->CP0_WatchHi[sel];
 895 }
 896
 897 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 898 {
 899     target_ulong t0 = env->CP0_Debug;
 900     if (env->hflags & MIPS_HFLAG_DM)
 901         t0 |= 1 << CP0DB_DM;
 902
 903     return t0;
 904 }
 905
 906 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 907 {
 908     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 909     int32_t tcstatus;
 910     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 911
 912     if (other_tc == other->current_tc)
 913         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 914     else
 915         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 916
 917     /* XXX: Might be wrong, check with EJTAG spec. */
 918     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 919             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 920 }
 921
 922 #if defined(TARGET_MIPS64)
 923 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 924 {
 925     return env->active_tc.PC;
 926 }
 927
 928 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 929 {
 930     return env->active_tc.CP0_TCHalt;
 931 }
 932
 933 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 934 {
 935     return env->active_tc.CP0_TCContext;
 936 }
 937
 938 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 939 {
 940     return env->active_tc.CP0_TCSchedule;
 941 }
 942
 943 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 944 {
 945     return env->active_tc.CP0_TCScheFBack;
 946 }
 947
 948 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 949 {
 950     return env->lladdr >> env->CP0_LLAddr_shift;
 951 }
 952
 953 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 954 {
 955     return env->CP0_WatchLo[sel];
 956 }
 957 #endif /* TARGET_MIPS64 */
 958
 959 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 960 {
 961     uint32_t index_p = env->CP0_Index & 0x80000000;
 962     uint32_t tlb_index = arg1 & 0x7fffffff;
 963     if (tlb_index < env->tlb->nb_tlb) {
 964         if (env->insn_flags & ISA_MIPS32R6) {
 965             index_p |= arg1 & 0x80000000;
 966         }
 967         env->CP0_Index = index_p | tlb_index;
 968     }
 969 }
 970
 971 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 972 {
 973     uint32_t mask = 0;
 974     uint32_t newval;
 975
 976     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 977         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 978                 (1 << CP0MVPCo_EVP);
 979     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 980         mask |= (1 << CP0MVPCo_STLB);
 981     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 982
 983     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 984
 985     env->mvp->CP0_MVPControl = newval;
 986 }
 987
 988 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 989 {
 990     uint32_t mask;
 991     uint32_t newval;
 992
 993     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 994            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 995     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 996
 997     /* Yield scheduler intercept not implemented. */
 998     /* Gating storage scheduler intercept not implemented. */
 999
1000     // TODO: Enable/disable TCs.
1001
1002     env->CP0_VPEControl = newval;
1003 }
1004
1005 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1006 {
1007     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1008     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1009     uint32_t mask;
1010     uint32_t newval;
1011
1012     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1013            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1014     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1015
1016     /* TODO: Enable/disable TCs.  */
1017
1018     other->CP0_VPEControl = newval;
1019 }
1020
1021 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1022 {
1023     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1024     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1025     /* FIXME: Mask away return zero on read bits.  */
1026     return other->CP0_VPEControl;
1027 }
1028
1029 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1030 {
1031     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1032     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1033
1034     return other->CP0_VPEConf0;
1035 }
1036
1037 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1038 {
1039     uint32_t mask = 0;
1040     uint32_t newval;
1041
1042     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1043         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1044             mask |= (0xff << CP0VPEC0_XTC);
1045         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1046     }
1047     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1048
1049     // TODO: TC exclusive handling due to ERL/EXL.
1050
1051     env->CP0_VPEConf0 = newval;
1052 }
1053
1054 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1055 {
1056     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1057     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1058     uint32_t mask = 0;
1059     uint32_t newval;
1060
1061     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1062     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1063
1064     /* TODO: TC exclusive handling due to ERL/EXL.  */
1065     other->CP0_VPEConf0 = newval;
1066 }
1067
1068 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1069 {
1070     uint32_t mask = 0;
1071     uint32_t newval;
1072
1073     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1074         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1075                 (0xff << CP0VPEC1_NCP1);
1076     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1077
1078     /* UDI not implemented. */
1079     /* CP2 not implemented. */
1080
1081     // TODO: Handle FPU (CP1) binding.
1082
1083     env->CP0_VPEConf1 = newval;
1084 }
1085
1086 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1087 {
1088     /* Yield qualifier inputs not implemented. */
1089     env->CP0_YQMask = 0x00000000;
1090 }
1091
1092 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1093 {
1094     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1095 }
1096
1097 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1098 {
1099     /* Large physaddr (PABITS) not implemented */
1100     /* 1k pages not implemented */
1101     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1102     env->CP0_EntryLo0 = (arg1 & 0x3FFFFFFF) | (rxi << (CP0EnLo_XI - 30));
1103 }
1104
1105 #if defined(TARGET_MIPS64)
1106 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1107 {
1108     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1109     env->CP0_EntryLo0 = (arg1 & 0x3FFFFFFF) | rxi;
1110 }
1111 #endif
1112
1113 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1114 {
1115     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1116     uint32_t newval;
1117
1118     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1119
1120     env->active_tc.CP0_TCStatus = newval;
1121     sync_c0_tcstatus(env, env->current_tc, newval);
1122 }
1123
1124 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1125 {
1126     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1127     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1128
1129     if (other_tc == other->current_tc)
1130         other->active_tc.CP0_TCStatus = arg1;
1131     else
1132         other->tcs[other_tc].CP0_TCStatus = arg1;
1133     sync_c0_tcstatus(other, other_tc, arg1);
1134 }
1135
1136 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1137 {
1138     uint32_t mask = (1 << CP0TCBd_TBE);
1139     uint32_t newval;
1140
1141     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1142         mask |= (1 << CP0TCBd_CurVPE);
1143     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1144     env->active_tc.CP0_TCBind = newval;
1145 }
1146
1147 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1148 {
1149     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1150     uint32_t mask = (1 << CP0TCBd_TBE);
1151     uint32_t newval;
1152     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1153
1154     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1155         mask |= (1 << CP0TCBd_CurVPE);
1156     if (other_tc == other->current_tc) {
1157         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1158         other->active_tc.CP0_TCBind = newval;
1159     } else {
1160         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1161         other->tcs[other_tc].CP0_TCBind = newval;
1162     }
1163 }
1164
1165 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1166 {
1167     env->active_tc.PC = arg1;
1168     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1169     env->lladdr = 0ULL;
1170     /* MIPS16 not implemented. */
1171 }
1172
1173 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1174 {
1175     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1176     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1177
1178     if (other_tc == other->current_tc) {
1179         other->active_tc.PC = arg1;
1180         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1181         other->lladdr = 0ULL;
1182         /* MIPS16 not implemented. */
1183     } else {
1184         other->tcs[other_tc].PC = arg1;
1185         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1186         other->lladdr = 0ULL;
1187         /* MIPS16 not implemented. */
1188     }
1189 }
1190
1191 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1192 {
1193     MIPSCPU *cpu = mips_env_get_cpu(env);
1194
1195     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1196
1197     // TODO: Halt TC / Restart (if allocated+active) TC.
1198     if (env->active_tc.CP0_TCHalt & 1) {
1199         mips_tc_sleep(cpu, env->current_tc);
1200     } else {
1201         mips_tc_wake(cpu, env->current_tc);
1202     }
1203 }
1204
1205 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1206 {
1207     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1208     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1209     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1210
1211     // TODO: Halt TC / Restart (if allocated+active) TC.
1212
1213     if (other_tc == other->current_tc)
1214         other->active_tc.CP0_TCHalt = arg1;
1215     else
1216         other->tcs[other_tc].CP0_TCHalt = arg1;
1217
1218     if (arg1 & 1) {
1219         mips_tc_sleep(other_cpu, other_tc);
1220     } else {
1221         mips_tc_wake(other_cpu, other_tc);
1222     }
1223 }
1224
1225 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1226 {
1227     env->active_tc.CP0_TCContext = arg1;
1228 }
1229
1230 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1231 {
1232     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1233     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1234
1235     if (other_tc == other->current_tc)
1236         other->active_tc.CP0_TCContext = arg1;
1237     else
1238         other->tcs[other_tc].CP0_TCContext = arg1;
1239 }
1240
1241 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1242 {
1243     env->active_tc.CP0_TCSchedule = arg1;
1244 }
1245
1246 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1247 {
1248     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1249     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1250
1251     if (other_tc == other->current_tc)
1252         other->active_tc.CP0_TCSchedule = arg1;
1253     else
1254         other->tcs[other_tc].CP0_TCSchedule = arg1;
1255 }
1256
1257 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1258 {
1259     env->active_tc.CP0_TCScheFBack = arg1;
1260 }
1261
1262 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1263 {
1264     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1265     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1266
1267     if (other_tc == other->current_tc)
1268         other->active_tc.CP0_TCScheFBack = arg1;
1269     else
1270         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1271 }
1272
1273 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1274 {
1275     /* Large physaddr (PABITS) not implemented */
1276     /* 1k pages not implemented */
1277     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1278     env->CP0_EntryLo1 = (arg1 & 0x3FFFFFFF) | (rxi << (CP0EnLo_XI - 30));
1279 }
1280
1281 #if defined(TARGET_MIPS64)
1282 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1283 {
1284     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1285     env->CP0_EntryLo1 = (arg1 & 0x3FFFFFFF) | rxi;
1286 }
1287 #endif
1288
1289 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1290 {
1291     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1292 }
1293
1294 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1295 {
1296     uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1297     if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1298         (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1299          mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1300          mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1301         env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1302     }
1303 }
1304
1305 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1306 {
1307     /* SmartMIPS not implemented */
1308     /* Large physaddr (PABITS) not implemented */
1309     /* 1k pages not implemented */
1310     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1311                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1312 }
1313
1314 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1315 {
1316     if (env->insn_flags & ISA_MIPS32R6) {
1317         if (arg1 < env->tlb->nb_tlb) {
1318             env->CP0_Wired = arg1;
1319         }
1320     } else {
1321         env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1322     }
1323 }
1324
1325 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1326 {
1327     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1328 }
1329
1330 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1331 {
1332     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1333 }
1334
1335 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1336 {
1337     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1338 }
1339
1340 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1341 {
1342     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1343 }
1344
1345 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1346 {
1347     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1348 }
1349
1350 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1351 {
1352     uint32_t mask = 0x0000000F;
1353
1354     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1355         mask |= (1 << 29);
1356
1357         if (arg1 & (1 << 29)) {
1358             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1359         } else {
1360             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1361         }
1362     }
1363
1364     env->CP0_HWREna = arg1 & mask;
1365 }
1366
1367 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1368 {
1369     cpu_mips_store_count(env, arg1);
1370 }
1371
1372 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1373 {
1374     target_ulong old, val, mask;
1375     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1376     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1377         mask |= 1 << CP0EnHi_EHINV;
1378     }
1379
1380     /* 1k pages not implemented */
1381 #if defined(TARGET_MIPS64)
1382     if (env->insn_flags & ISA_MIPS32R6) {
1383         int entryhi_r = extract64(arg1, 62, 2);
1384         int config0_at = extract32(env->CP0_Config0, 13, 2);
1385         bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1386         if ((entryhi_r == 2) ||
1387             (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1388             /* skip EntryHi.R field if new value is reserved */
1389             mask &= ~(0x3ull << 62);
1390         }
1391     }
1392     mask &= env->SEGMask;
1393 #endif
1394     old = env->CP0_EntryHi;
1395     val = (arg1 & mask) | (old & ~mask);
1396     env->CP0_EntryHi = val;
1397     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1398         sync_c0_entryhi(env, env->current_tc);
1399     }
1400     /* If the ASID changes, flush qemu's TLB.  */
1401     if ((old & 0xFF) != (val & 0xFF))
1402         cpu_mips_tlb_flush(env, 1);
1403 }
1404
1405 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1406 {
1407     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1408     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1409
1410     other->CP0_EntryHi = arg1;
1411     sync_c0_entryhi(other, other_tc);
1412 }
1413
1414 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1415 {
1416     cpu_mips_store_compare(env, arg1);
1417 }
1418
1419 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1420 {
1421     MIPSCPU *cpu = mips_env_get_cpu(env);
1422     uint32_t val, old;
1423     uint32_t mask = env->CP0_Status_rw_bitmask;
1424
1425     if (env->insn_flags & ISA_MIPS32R6) {
1426         if (extract32(env->CP0_Status, CP0St_KSU, 2) == 0x3) {
1427             mask &= ~(3 << CP0St_KSU);
1428         }
1429         mask &= ~(0x00180000 & arg1);
1430     }
1431
1432     val = arg1 & mask;
1433     old = env->CP0_Status;
1434     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1435     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1436         sync_c0_status(env, env, env->current_tc);
1437     } else {
1438         compute_hflags(env);
1439     }
1440
1441     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1442         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1443                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1444                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1445                 env->CP0_Cause);
1446         switch (env->hflags & MIPS_HFLAG_KSU) {
1447         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1448         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1449         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1450         default:
1451             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1452             break;
1453         }
1454     }
1455 }
1456
1457 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1458 {
1459     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1460     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1461
1462     other->CP0_Status = arg1 & ~0xf1000018;
1463     sync_c0_status(env, other, other_tc);
1464 }
1465
1466 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1467 {
1468     /* vectored interrupts not implemented, no performance counters. */
1469     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1470 }
1471
1472 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1473 {
1474     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1475     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1476 }
1477
1478 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1479 {
1480     uint32_t mask = 0x00C00300;
1481     uint32_t old = cpu->CP0_Cause;
1482     int i;
1483
1484     if (cpu->insn_flags & ISA_MIPS32R2) {
1485         mask |= 1 << CP0Ca_DC;
1486     }
1487     if (cpu->insn_flags & ISA_MIPS32R6) {
1488         mask &= ~((1 << CP0Ca_WP) & arg1);
1489     }
1490
1491     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1492
1493     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1494         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1495             cpu_mips_stop_count(cpu);
1496         } else {
1497             cpu_mips_start_count(cpu);
1498         }
1499     }
1500
1501     /* Set/reset software interrupts */
1502     for (i = 0 ; i < 2 ; i++) {
1503         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1504             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1505         }
1506     }
1507 }
1508
1509 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1510 {
1511     mtc0_cause(env, arg1);
1512 }
1513
1514 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1515 {
1516     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1517     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1518
1519     mtc0_cause(other, arg1);
1520 }
1521
1522 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1523 {
1524     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1525     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1526
1527     return other->CP0_EPC;
1528 }
1529
1530 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1531 {
1532     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1533     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1534
1535     return other->CP0_EBase;
1536 }
1537
1538 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1539 {
1540     /* vectored interrupts not implemented */
1541     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1542 }
1543
1544 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1545 {
1546     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1547     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1548     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1549 }
1550
1551 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1552 {
1553     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1554     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1555
1556     switch (idx) {
1557     case 0: return other->CP0_Config0;
1558     case 1: return other->CP0_Config1;
1559     case 2: return other->CP0_Config2;
1560     case 3: return other->CP0_Config3;
1561     /* 4 and 5 are reserved.  */
1562     case 6: return other->CP0_Config6;
1563     case 7: return other->CP0_Config7;
1564     default:
1565         break;
1566     }
1567     return 0;
1568 }
1569
1570 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1571 {
1572     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1573 }
1574
1575 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1576 {
1577     /* tertiary/secondary caches not implemented */
1578     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1579 }
1580
1581 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1582 {
1583     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1584                        (arg1 & env->CP0_Config4_rw_bitmask);
1585 }
1586
1587 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1588 {
1589     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1590                        (arg1 & env->CP0_Config5_rw_bitmask);
1591     compute_hflags(env);
1592 }
1593
1594 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1595 {
1596     target_long mask = env->CP0_LLAddr_rw_bitmask;
1597     arg1 = arg1 << env->CP0_LLAddr_shift;
1598     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1599 }
1600
1601 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1602 {
1603     /* Watch exceptions for instructions, data loads, data stores
1604        not implemented. */
1605     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1606 }
1607
1608 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1609 {
1610     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1611     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1612 }
1613
1614 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1615 {
1616     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1617     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1618 }
1619
1620 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1621 {
1622     env->CP0_Framemask = arg1; /* XXX */
1623 }
1624
1625 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1626 {
1627     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1628     if (arg1 & (1 << CP0DB_DM))
1629         env->hflags |= MIPS_HFLAG_DM;
1630     else
1631         env->hflags &= ~MIPS_HFLAG_DM;
1632 }
1633
1634 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1635 {
1636     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1637     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1638     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1639
1640     /* XXX: Might be wrong, check with EJTAG spec. */
1641     if (other_tc == other->current_tc)
1642         other->active_tc.CP0_Debug_tcstatus = val;
1643     else
1644         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1645     other->CP0_Debug = (other->CP0_Debug &
1646                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1647                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1648 }
1649
1650 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1651 {
1652     env->CP0_Performance0 = arg1 & 0x000007ff;
1653 }
1654
1655 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1656 {
1657     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1658 }
1659
1660 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1661 {
1662     env->CP0_DataLo = arg1; /* XXX */
1663 }
1664
1665 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1666 {
1667     env->CP0_TagHi = arg1; /* XXX */
1668 }
1669
1670 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1671 {
1672     env->CP0_DataHi = arg1; /* XXX */
1673 }
1674
1675 /* MIPS MT functions */
1676 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1677 {
1678     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1679     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1680
1681     if (other_tc == other->current_tc)
1682         return other->active_tc.gpr[sel];
1683     else
1684         return other->tcs[other_tc].gpr[sel];
1685 }
1686
1687 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1688 {
1689     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1690     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1691
1692     if (other_tc == other->current_tc)
1693         return other->active_tc.LO[sel];
1694     else
1695         return other->tcs[other_tc].LO[sel];
1696 }
1697
1698 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1699 {
1700     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1701     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1702
1703     if (other_tc == other->current_tc)
1704         return other->active_tc.HI[sel];
1705     else
1706         return other->tcs[other_tc].HI[sel];
1707 }
1708
1709 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1710 {
1711     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1712     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1713
1714     if (other_tc == other->current_tc)
1715         return other->active_tc.ACX[sel];
1716     else
1717         return other->tcs[other_tc].ACX[sel];
1718 }
1719
1720 target_ulong helper_mftdsp(CPUMIPSState *env)
1721 {
1722     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1723     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1724
1725     if (other_tc == other->current_tc)
1726         return other->active_tc.DSPControl;
1727     else
1728         return other->tcs[other_tc].DSPControl;
1729 }
1730
1731 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1732 {
1733     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1734     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1735
1736     if (other_tc == other->current_tc)
1737         other->active_tc.gpr[sel] = arg1;
1738     else
1739         other->tcs[other_tc].gpr[sel] = arg1;
1740 }
1741
1742 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1743 {
1744     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1745     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1746
1747     if (other_tc == other->current_tc)
1748         other->active_tc.LO[sel] = arg1;
1749     else
1750         other->tcs[other_tc].LO[sel] = arg1;
1751 }
1752
1753 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1754 {
1755     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1756     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1757
1758     if (other_tc == other->current_tc)
1759         other->active_tc.HI[sel] = arg1;
1760     else
1761         other->tcs[other_tc].HI[sel] = arg1;
1762 }
1763
1764 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1765 {
1766     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1767     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1768
1769     if (other_tc == other->current_tc)
1770         other->active_tc.ACX[sel] = arg1;
1771     else
1772         other->tcs[other_tc].ACX[sel] = arg1;
1773 }
1774
1775 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1776 {
1777     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1778     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1779
1780     if (other_tc == other->current_tc)
1781         other->active_tc.DSPControl = arg1;
1782     else
1783         other->tcs[other_tc].DSPControl = arg1;
1784 }
1785
1786 /* MIPS MT functions */
1787 target_ulong helper_dmt(void)
1788 {
1789     // TODO
1790      return 0;
1791 }
1792
1793 target_ulong helper_emt(void)
1794 {
1795     // TODO
1796     return 0;
1797 }
1798
1799 target_ulong helper_dvpe(CPUMIPSState *env)
1800 {
1801     CPUState *other_cs = first_cpu;
1802     target_ulong prev = env->mvp->CP0_MVPControl;
1803
1804     CPU_FOREACH(other_cs) {
1805         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1806         /* Turn off all VPEs except the one executing the dvpe.  */
1807         if (&other_cpu->env != env) {
1808             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1809             mips_vpe_sleep(other_cpu);
1810         }
1811     }
1812     return prev;
1813 }
1814
1815 target_ulong helper_evpe(CPUMIPSState *env)
1816 {
1817     CPUState *other_cs = first_cpu;
1818     target_ulong prev = env->mvp->CP0_MVPControl;
1819
1820     CPU_FOREACH(other_cs) {
1821         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1822
1823         if (&other_cpu->env != env
1824             /* If the VPE is WFI, don't disturb its sleep.  */
1825             && !mips_vpe_is_wfi(other_cpu)) {
1826             /* Enable the VPE.  */
1827             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1828             mips_vpe_wake(other_cpu); /* And wake it up.  */
1829         }
1830     }
1831     return prev;
1832 }
1833 #endif /* !CONFIG_USER_ONLY */
1834
1835 void helper_fork(target_ulong arg1, target_ulong arg2)
1836 {
1837     // arg1 = rt, arg2 = rs
1838     // TODO: store to TC register
1839 }
1840
1841 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1842 {
1843     target_long arg1 = arg;
1844
1845     if (arg1 < 0) {
1846         /* No scheduling policy implemented. */
1847         if (arg1 != -2) {
1848             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1849                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1850                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1851                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1852                 helper_raise_exception(env, EXCP_THREAD);
1853             }
1854         }
1855     } else if (arg1 == 0) {
1856         if (0 /* TODO: TC underflow */) {
1857             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1858             helper_raise_exception(env, EXCP_THREAD);
1859         } else {
1860             // TODO: Deallocate TC
1861         }
1862     } else if (arg1 > 0) {
1863         /* Yield qualifier inputs not implemented. */
1864         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1865         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1866         helper_raise_exception(env, EXCP_THREAD);
1867     }
1868     return env->CP0_YQMask;
1869 }
1870
1871 #ifndef CONFIG_USER_ONLY
1872 /* TLB management */
1873 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1874 {
1875     MIPSCPU *cpu = mips_env_get_cpu(env);
1876
1877     /* Flush qemu's TLB and discard all shadowed entries.  */
1878     tlb_flush(CPU(cpu), flush_global);
1879     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1880 }
1881
1882 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1883 {
1884     /* Discard entries from env->tlb[first] onwards.  */
1885     while (env->tlb->tlb_in_use > first) {
1886         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1887     }
1888 }
1889
1890 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1891 {
1892     r4k_tlb_t *tlb;
1893
1894     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1895     tlb = &env->tlb->mmu.r4k.tlb[idx];
1896     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1897         tlb->EHINV = 1;
1898         return;
1899     }
1900     tlb->EHINV = 0;
1901     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1902 #if defined(TARGET_MIPS64)
1903     tlb->VPN &= env->SEGMask;
1904 #endif
1905     tlb->ASID = env->CP0_EntryHi & 0xFF;
1906     tlb->PageMask = env->CP0_PageMask;
1907     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1908     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1909     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1910     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1911     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1912     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1913     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1914     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1915     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1916     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1917     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1918     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1919     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1920 }
1921
1922 void r4k_helper_tlbinv(CPUMIPSState *env)
1923 {
1924     int idx;
1925     r4k_tlb_t *tlb;
1926     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1927
1928     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1929         tlb = &env->tlb->mmu.r4k.tlb[idx];
1930         if (!tlb->G && tlb->ASID == ASID) {
1931             tlb->EHINV = 1;
1932         }
1933     }
1934     cpu_mips_tlb_flush(env, 1);
1935 }
1936
1937 void r4k_helper_tlbinvf(CPUMIPSState *env)
1938 {
1939     int idx;
1940
1941     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1942         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1943     }
1944     cpu_mips_tlb_flush(env, 1);
1945 }
1946
1947 void r4k_helper_tlbwi(CPUMIPSState *env)
1948 {
1949     r4k_tlb_t *tlb;
1950     int idx;
1951     target_ulong VPN;
1952     uint8_t ASID;
1953     bool G, V0, D0, V1, D1;
1954
1955     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1956     tlb = &env->tlb->mmu.r4k.tlb[idx];
1957     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1958 #if defined(TARGET_MIPS64)
1959     VPN &= env->SEGMask;
1960 #endif
1961     ASID = env->CP0_EntryHi & 0xff;
1962     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1963     V0 = (env->CP0_EntryLo0 & 2) != 0;
1964     D0 = (env->CP0_EntryLo0 & 4) != 0;
1965     V1 = (env->CP0_EntryLo1 & 2) != 0;
1966     D1 = (env->CP0_EntryLo1 & 4) != 0;
1967
1968     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1969        permissions on the current entry. */
1970     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1971         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1972         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1973         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1974     }
1975
1976     r4k_invalidate_tlb(env, idx, 0);
1977     r4k_fill_tlb(env, idx);
1978 }
1979
1980 void r4k_helper_tlbwr(CPUMIPSState *env)
1981 {
1982     int r = cpu_mips_get_random(env);
1983
1984     r4k_invalidate_tlb(env, r, 1);
1985     r4k_fill_tlb(env, r);
1986 }
1987
1988 void r4k_helper_tlbp(CPUMIPSState *env)
1989 {
1990     r4k_tlb_t *tlb;
1991     target_ulong mask;
1992     target_ulong tag;
1993     target_ulong VPN;
1994     uint8_t ASID;
1995     int i;
1996
1997     ASID = env->CP0_EntryHi & 0xFF;
1998     for (i = 0; i < env->tlb->nb_tlb; i++) {
1999         tlb = &env->tlb->mmu.r4k.tlb[i];
2000         /* 1k pages are not supported. */
2001         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2002         tag = env->CP0_EntryHi & ~mask;
2003         VPN = tlb->VPN & ~mask;
2004 #if defined(TARGET_MIPS64)
2005         tag &= env->SEGMask;
2006 #endif
2007         /* Check ASID, virtual page number & size */
2008         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2009             /* TLB match */
2010             env->CP0_Index = i;
2011             break;
2012         }
2013     }
2014     if (i == env->tlb->nb_tlb) {
2015         /* No match.  Discard any shadow entries, if any of them match.  */
2016         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2017             tlb = &env->tlb->mmu.r4k.tlb[i];
2018             /* 1k pages are not supported. */
2019             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2020             tag = env->CP0_EntryHi & ~mask;
2021             VPN = tlb->VPN & ~mask;
2022 #if defined(TARGET_MIPS64)
2023             tag &= env->SEGMask;
2024 #endif
2025             /* Check ASID, virtual page number & size */
2026             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2027                 r4k_mips_tlb_flush_extra (env, i);
2028                 break;
2029             }
2030         }
2031
2032         env->CP0_Index |= 0x80000000;
2033     }
2034 }
2035
2036 void r4k_helper_tlbr(CPUMIPSState *env)
2037 {
2038     r4k_tlb_t *tlb;
2039     uint8_t ASID;
2040     int idx;
2041
2042     ASID = env->CP0_EntryHi & 0xFF;
2043     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2044     tlb = &env->tlb->mmu.r4k.tlb[idx];
2045
2046     /* If this will change the current ASID, flush qemu's TLB.  */
2047     if (ASID != tlb->ASID)
2048         cpu_mips_tlb_flush (env, 1);
2049
2050     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2051
2052     if (tlb->EHINV) {
2053         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2054         env->CP0_PageMask = 0;
2055         env->CP0_EntryLo0 = 0;
2056         env->CP0_EntryLo1 = 0;
2057     } else {
2058         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2059         env->CP0_PageMask = tlb->PageMask;
2060         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2061                         ((target_ulong)tlb->RI0 << CP0EnLo_RI) |
2062                         ((target_ulong)tlb->XI0 << CP0EnLo_XI) |
2063                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
2064         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2065                         ((target_ulong)tlb->RI1 << CP0EnLo_RI) |
2066                         ((target_ulong)tlb->XI1 << CP0EnLo_XI) |
2067                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
2068     }
2069 }
2070
2071 void helper_tlbwi(CPUMIPSState *env)
2072 {
2073     env->tlb->helper_tlbwi(env);
2074 }
2075
2076 void helper_tlbwr(CPUMIPSState *env)
2077 {
2078     env->tlb->helper_tlbwr(env);
2079 }
2080
2081 void helper_tlbp(CPUMIPSState *env)
2082 {
2083     env->tlb->helper_tlbp(env);
2084 }
2085
2086 void helper_tlbr(CPUMIPSState *env)
2087 {
2088     env->tlb->helper_tlbr(env);
2089 }
2090
2091 void helper_tlbinv(CPUMIPSState *env)
2092 {
2093     env->tlb->helper_tlbinv(env);
2094 }
2095
2096 void helper_tlbinvf(CPUMIPSState *env)
2097 {
2098     env->tlb->helper_tlbinvf(env);
2099 }
2100
2101 /* Specials */
2102 target_ulong helper_di(CPUMIPSState *env)
2103 {
2104     target_ulong t0 = env->CP0_Status;
2105
2106     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2107     return t0;
2108 }
2109
2110 target_ulong helper_ei(CPUMIPSState *env)
2111 {
2112     target_ulong t0 = env->CP0_Status;
2113
2114     env->CP0_Status = t0 | (1 << CP0St_IE);
2115     return t0;
2116 }
2117
2118 static void debug_pre_eret(CPUMIPSState *env)
2119 {
2120     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2121         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2122                 env->active_tc.PC, env->CP0_EPC);
2123         if (env->CP0_Status & (1 << CP0St_ERL))
2124             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2125         if (env->hflags & MIPS_HFLAG_DM)
2126             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2127         qemu_log("\n");
2128     }
2129 }
2130
2131 static void debug_post_eret(CPUMIPSState *env)
2132 {
2133     MIPSCPU *cpu = mips_env_get_cpu(env);
2134
2135     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2136         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2137                 env->active_tc.PC, env->CP0_EPC);
2138         if (env->CP0_Status & (1 << CP0St_ERL))
2139             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2140         if (env->hflags & MIPS_HFLAG_DM)
2141             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2142         switch (env->hflags & MIPS_HFLAG_KSU) {
2143         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2144         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2145         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2146         default:
2147             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2148             break;
2149         }
2150     }
2151 }
2152
2153 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2154 {
2155     env->active_tc.PC = error_pc & ~(target_ulong)1;
2156     if (error_pc & 1) {
2157         env->hflags |= MIPS_HFLAG_M16;
2158     } else {
2159         env->hflags &= ~(MIPS_HFLAG_M16);
2160     }
2161 }
2162
2163 void helper_eret(CPUMIPSState *env)
2164 {
2165     debug_pre_eret(env);
2166     if (env->CP0_Status & (1 << CP0St_ERL)) {
2167         set_pc(env, env->CP0_ErrorEPC);
2168         env->CP0_Status &= ~(1 << CP0St_ERL);
2169     } else {
2170         set_pc(env, env->CP0_EPC);
2171         env->CP0_Status &= ~(1 << CP0St_EXL);
2172     }
2173     compute_hflags(env);
2174     debug_post_eret(env);
2175     env->lladdr = 1;
2176 }
2177
2178 void helper_deret(CPUMIPSState *env)
2179 {
2180     debug_pre_eret(env);
2181     set_pc(env, env->CP0_DEPC);
2182
2183     env->hflags &= MIPS_HFLAG_DM;
2184     compute_hflags(env);
2185     debug_post_eret(env);
2186     env->lladdr = 1;
2187 }
2188 #endif /* !CONFIG_USER_ONLY */
2189
2190 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2191 {
2192     if ((env->hflags & MIPS_HFLAG_CP0) ||
2193         (env->CP0_HWREna & (1 << 0)))
2194         return env->CP0_EBase & 0x3ff;
2195     else
2196         helper_raise_exception(env, EXCP_RI);
2197
2198     return 0;
2199 }
2200
2201 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2202 {
2203     if ((env->hflags & MIPS_HFLAG_CP0) ||
2204         (env->CP0_HWREna & (1 << 1)))
2205         return env->SYNCI_Step;
2206     else
2207         helper_raise_exception(env, EXCP_RI);
2208
2209     return 0;
2210 }
2211
2212 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2213 {
2214     if ((env->hflags & MIPS_HFLAG_CP0) ||
2215         (env->CP0_HWREna & (1 << 2)))
2216         return env->CP0_Count;
2217     else
2218         helper_raise_exception(env, EXCP_RI);
2219
2220     return 0;
2221 }
2222
2223 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2224 {
2225     if ((env->hflags & MIPS_HFLAG_CP0) ||
2226         (env->CP0_HWREna & (1 << 3)))
2227         return env->CCRes;
2228     else
2229         helper_raise_exception(env, EXCP_RI);
2230
2231     return 0;
2232 }
2233
2234 void helper_pmon(CPUMIPSState *env, int function)
2235 {
2236     function /= 2;
2237     switch (function) {
2238     case 2: /* TODO: char inbyte(int waitflag); */
2239         if (env->active_tc.gpr[4] == 0)
2240             env->active_tc.gpr[2] = -1;
2241         /* Fall through */
2242     case 11: /* TODO: char inbyte (void); */
2243         env->active_tc.gpr[2] = -1;
2244         break;
2245     case 3:
2246     case 12:
2247         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2248         break;
2249     case 17:
2250         break;
2251     case 158:
2252         {
2253             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2254             printf("%s", fmt);
2255         }
2256         break;
2257     }
2258 }
2259
2260 void helper_wait(CPUMIPSState *env)
2261 {
2262     CPUState *cs = CPU(mips_env_get_cpu(env));
2263
2264     cs->halted = 1;
2265     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2266     helper_raise_exception(env, EXCP_HLT);
2267 }
2268
2269 #if !defined(CONFIG_USER_ONLY)
2270
2271 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2272                                   int access_type, int is_user,
2273                                   uintptr_t retaddr)
2274 {
2275     MIPSCPU *cpu = MIPS_CPU(cs);
2276     CPUMIPSState *env = &cpu->env;
2277     int error_code = 0;
2278     int excp;
2279
2280     env->CP0_BadVAddr = addr;
2281
2282     if (access_type == MMU_DATA_STORE) {
2283         excp = EXCP_AdES;
2284     } else {
2285         excp = EXCP_AdEL;
2286         if (access_type == MMU_INST_FETCH) {
2287             error_code |= EXCP_INST_NOTAVAIL;
2288         }
2289     }
2290
2291     do_raise_exception_err(env, excp, error_code, retaddr);
2292 }
2293
2294 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2295               uintptr_t retaddr)
2296 {
2297     int ret;
2298
2299     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2300     if (ret) {
2301         MIPSCPU *cpu = MIPS_CPU(cs);
2302         CPUMIPSState *env = &cpu->env;
2303
2304         do_raise_exception_err(env, cs->exception_index,
2305                                env->error_code, retaddr);
2306     }
2307 }
2308
2309 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2310                                 bool is_write, bool is_exec, int unused,
2311                                 unsigned size)
2312 {
2313     MIPSCPU *cpu = MIPS_CPU(cs);
2314     CPUMIPSState *env = &cpu->env;
2315
2316     /*
2317      * Raising an exception with KVM enabled will crash because it won't be from
2318      * the main execution loop so the longjmp won't have a matching setjmp.
2319      * Until we can trigger a bus error exception through KVM lets just ignore
2320      * the access.
2321      */
2322     if (kvm_enabled()) {
2323         return;
2324     }
2325
2326     if (is_exec) {
2327         helper_raise_exception(env, EXCP_IBE);
2328     } else {
2329         helper_raise_exception(env, EXCP_DBE);
2330     }
2331 }
2332 #endif /* !CONFIG_USER_ONLY */
2333
2334 /* Complex FPU operations which may need stack space. */
2335
2336 #define FLOAT_TWO32 make_float32(1 << 30)
2337 #define FLOAT_TWO64 make_float64(1ULL << 62)
2338 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2339 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2340
2341 /* convert MIPS rounding mode in FCR31 to IEEE library */
2342 unsigned int ieee_rm[] = {
2343     float_round_nearest_even,
2344     float_round_to_zero,
2345     float_round_up,
2346     float_round_down
2347 };
2348
2349 static inline void restore_rounding_mode(CPUMIPSState *env)
2350 {
2351     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2352                             &env->active_fpu.fp_status);
2353 }
2354
2355 static inline void restore_flush_mode(CPUMIPSState *env)
2356 {
2357     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2358                       &env->active_fpu.fp_status);
2359 }
2360
2361 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2362 {
2363     target_ulong arg1 = 0;
2364
2365     switch (reg) {
2366     case 0:
2367         arg1 = (int32_t)env->active_fpu.fcr0;
2368         break;
2369     case 1:
2370         /* UFR Support - Read Status FR */
2371         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2372             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2373                 arg1 = (int32_t)
2374                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2375             } else {
2376                 helper_raise_exception(env, EXCP_RI);
2377             }
2378         }
2379         break;
2380     case 25:
2381         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2382         break;
2383     case 26:
2384         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2385         break;
2386     case 28:
2387         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2388         break;
2389     default:
2390         arg1 = (int32_t)env->active_fpu.fcr31;
2391         break;
2392     }
2393
2394     return arg1;
2395 }
2396
2397 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2398 {
2399     switch (fs) {
2400     case 1:
2401         /* UFR Alias - Reset Status FR */
2402         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2403             return;
2404         }
2405         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2406             env->CP0_Status &= ~(1 << CP0St_FR);
2407             compute_hflags(env);
2408         } else {
2409             helper_raise_exception(env, EXCP_RI);
2410         }
2411         break;
2412     case 4:
2413         /* UNFR Alias - Set Status FR */
2414         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2415             return;
2416         }
2417         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2418             env->CP0_Status |= (1 << CP0St_FR);
2419             compute_hflags(env);
2420         } else {
2421             helper_raise_exception(env, EXCP_RI);
2422         }
2423         break;
2424     case 25:
2425         if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2426             return;
2427         }
2428         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2429                      ((arg1 & 0x1) << 23);
2430         break;
2431     case 26:
2432         if (arg1 & 0x007c0000)
2433             return;
2434         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2435         break;
2436     case 28:
2437         if (arg1 & 0x007c0000)
2438             return;
2439         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2440                      ((arg1 & 0x4) << 22);
2441         break;
2442     case 31:
2443         if (env->insn_flags & ISA_MIPS32R6) {
2444             uint32_t mask = 0xfefc0000;
2445             env->active_fpu.fcr31 = (arg1 & ~mask) |
2446                 (env->active_fpu.fcr31 & mask);
2447         } else if (!(arg1 & 0x007c0000)) {
2448             env->active_fpu.fcr31 = arg1;
2449         }
2450         break;
2451     default:
2452         return;
2453     }
2454     /* set rounding mode */
2455     restore_rounding_mode(env);
2456     /* set flush-to-zero mode */
2457     restore_flush_mode(env);
2458     set_float_exception_flags(0, &env->active_fpu.fp_status);
2459     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2460         do_raise_exception(env, EXCP_FPE, GETPC());
2461 }
2462
2463 int ieee_ex_to_mips(int xcpt)
2464 {
2465     int ret = 0;
2466     if (xcpt) {
2467         if (xcpt & float_flag_invalid) {
2468             ret |= FP_INVALID;
2469         }
2470         if (xcpt & float_flag_overflow) {
2471             ret |= FP_OVERFLOW;
2472         }
2473         if (xcpt & float_flag_underflow) {
2474             ret |= FP_UNDERFLOW;
2475         }
2476         if (xcpt & float_flag_divbyzero) {
2477             ret |= FP_DIV0;
2478         }
2479         if (xcpt & float_flag_inexact) {
2480             ret |= FP_INEXACT;
2481         }
2482     }
2483     return ret;
2484 }
2485
2486 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2487 {
2488     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2489
2490     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2491
2492     if (tmp) {
2493         set_float_exception_flags(0, &env->active_fpu.fp_status);
2494
2495         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2496             do_raise_exception(env, EXCP_FPE, pc);
2497         } else {
2498             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2499         }
2500     }
2501 }
2502
2503 /* Float support.
2504    Single precition routines have a "s" suffix, double precision a
2505    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2506    paired single lower "pl", paired single upper "pu".  */
2507
2508 /* unary operations, modifying fp status  */
2509 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2510 {
2511     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2512     update_fcr31(env, GETPC());
2513     return fdt0;
2514 }
2515
2516 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2517 {
2518     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2519     update_fcr31(env, GETPC());
2520     return fst0;
2521 }
2522
2523 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2524 {
2525     uint64_t fdt2;
2526
2527     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2528     update_fcr31(env, GETPC());
2529     return fdt2;
2530 }
2531
2532 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2533 {
2534     uint64_t fdt2;
2535
2536     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2537     update_fcr31(env, GETPC());
2538     return fdt2;
2539 }
2540
2541 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2542 {
2543     uint64_t fdt2;
2544
2545     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2546     update_fcr31(env, GETPC());
2547     return fdt2;
2548 }
2549
2550 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2551 {
2552     uint64_t dt2;
2553
2554     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2555     if (get_float_exception_flags(&env->active_fpu.fp_status)
2556         & (float_flag_invalid | float_flag_overflow)) {
2557         dt2 = FP_TO_INT64_OVERFLOW;
2558     }
2559     update_fcr31(env, GETPC());
2560     return dt2;
2561 }
2562
2563 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2564 {
2565     uint64_t dt2;
2566
2567     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2568     if (get_float_exception_flags(&env->active_fpu.fp_status)
2569         & (float_flag_invalid | float_flag_overflow)) {
2570         dt2 = FP_TO_INT64_OVERFLOW;
2571     }
2572     update_fcr31(env, GETPC());
2573     return dt2;
2574 }
2575
2576 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2577 {
2578     uint32_t fst2;
2579     uint32_t fsth2;
2580
2581     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2582     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2583     update_fcr31(env, GETPC());
2584     return ((uint64_t)fsth2 << 32) | fst2;
2585 }
2586
2587 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2588 {
2589     uint32_t wt2;
2590     uint32_t wth2;
2591     int excp, excph;
2592
2593     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2594     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2595     if (excp & (float_flag_overflow | float_flag_invalid)) {
2596         wt2 = FP_TO_INT32_OVERFLOW;
2597     }
2598
2599     set_float_exception_flags(0, &env->active_fpu.fp_status);
2600     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2601     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2602     if (excph & (float_flag_overflow | float_flag_invalid)) {
2603         wth2 = FP_TO_INT32_OVERFLOW;
2604     }
2605
2606     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2607     update_fcr31(env, GETPC());
2608
2609     return ((uint64_t)wth2 << 32) | wt2;
2610 }
2611
2612 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2613 {
2614     uint32_t fst2;
2615
2616     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2617     update_fcr31(env, GETPC());
2618     return fst2;
2619 }
2620
2621 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2622 {
2623     uint32_t fst2;
2624
2625     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2626     update_fcr31(env, GETPC());
2627     return fst2;
2628 }
2629
2630 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2631 {
2632     uint32_t fst2;
2633
2634     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2635     update_fcr31(env, GETPC());
2636     return fst2;
2637 }
2638
2639 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2640 {
2641     uint32_t wt2;
2642
2643     wt2 = wt0;
2644     update_fcr31(env, GETPC());
2645     return wt2;
2646 }
2647
2648 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2649 {
2650     uint32_t wt2;
2651
2652     wt2 = wth0;
2653     update_fcr31(env, GETPC());
2654     return wt2;
2655 }
2656
2657 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2658 {
2659     uint32_t wt2;
2660
2661     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2662     update_fcr31(env, GETPC());
2663     if (get_float_exception_flags(&env->active_fpu.fp_status)
2664         & (float_flag_invalid | float_flag_overflow)) {
2665         wt2 = FP_TO_INT32_OVERFLOW;
2666     }
2667     return wt2;
2668 }
2669
2670 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2671 {
2672     uint32_t wt2;
2673
2674     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2675     if (get_float_exception_flags(&env->active_fpu.fp_status)
2676         & (float_flag_invalid | float_flag_overflow)) {
2677         wt2 = FP_TO_INT32_OVERFLOW;
2678     }
2679     update_fcr31(env, GETPC());
2680     return wt2;
2681 }
2682
2683 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2684 {
2685     uint64_t dt2;
2686
2687     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2688     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2689     restore_rounding_mode(env);
2690     if (get_float_exception_flags(&env->active_fpu.fp_status)
2691         & (float_flag_invalid | float_flag_overflow)) {
2692         dt2 = FP_TO_INT64_OVERFLOW;
2693     }
2694     update_fcr31(env, GETPC());
2695     return dt2;
2696 }
2697
2698 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2699 {
2700     uint64_t dt2;
2701
2702     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2703     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2704     restore_rounding_mode(env);
2705     if (get_float_exception_flags(&env->active_fpu.fp_status)
2706         & (float_flag_invalid | float_flag_overflow)) {
2707         dt2 = FP_TO_INT64_OVERFLOW;
2708     }
2709     update_fcr31(env, GETPC());
2710     return dt2;
2711 }
2712
2713 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2714 {
2715     uint32_t wt2;
2716
2717     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2718     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2719     restore_rounding_mode(env);
2720     if (get_float_exception_flags(&env->active_fpu.fp_status)
2721         & (float_flag_invalid | float_flag_overflow)) {
2722         wt2 = FP_TO_INT32_OVERFLOW;
2723     }
2724     update_fcr31(env, GETPC());
2725     return wt2;
2726 }
2727
2728 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2729 {
2730     uint32_t wt2;
2731
2732     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2733     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2734     restore_rounding_mode(env);
2735     if (get_float_exception_flags(&env->active_fpu.fp_status)
2736         & (float_flag_invalid | float_flag_overflow)) {
2737         wt2 = FP_TO_INT32_OVERFLOW;
2738     }
2739     update_fcr31(env, GETPC());
2740     return wt2;
2741 }
2742
2743 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2744 {
2745     uint64_t dt2;
2746
2747     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2748     if (get_float_exception_flags(&env->active_fpu.fp_status)
2749         & (float_flag_invalid | float_flag_overflow)) {
2750         dt2 = FP_TO_INT64_OVERFLOW;
2751     }
2752     update_fcr31(env, GETPC());
2753     return dt2;
2754 }
2755
2756 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2757 {
2758     uint64_t dt2;
2759
2760     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2761     if (get_float_exception_flags(&env->active_fpu.fp_status)
2762         & (float_flag_invalid | float_flag_overflow)) {
2763         dt2 = FP_TO_INT64_OVERFLOW;
2764     }
2765     update_fcr31(env, GETPC());
2766     return dt2;
2767 }
2768
2769 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2770 {
2771     uint32_t wt2;
2772
2773     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2774     if (get_float_exception_flags(&env->active_fpu.fp_status)
2775         & (float_flag_invalid | float_flag_overflow)) {
2776         wt2 = FP_TO_INT32_OVERFLOW;
2777     }
2778     update_fcr31(env, GETPC());
2779     return wt2;
2780 }
2781
2782 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2783 {
2784     uint32_t wt2;
2785
2786     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2787     if (get_float_exception_flags(&env->active_fpu.fp_status)
2788         & (float_flag_invalid | float_flag_overflow)) {
2789         wt2 = FP_TO_INT32_OVERFLOW;
2790     }
2791     update_fcr31(env, GETPC());
2792     return wt2;
2793 }
2794
2795 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2796 {
2797     uint64_t dt2;
2798
2799     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2800     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2801     restore_rounding_mode(env);
2802     if (get_float_exception_flags(&env->active_fpu.fp_status)
2803         & (float_flag_invalid | float_flag_overflow)) {
2804         dt2 = FP_TO_INT64_OVERFLOW;
2805     }
2806     update_fcr31(env, GETPC());
2807     return dt2;
2808 }
2809
2810 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2811 {
2812     uint64_t dt2;
2813
2814     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2815     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2816     restore_rounding_mode(env);
2817     if (get_float_exception_flags(&env->active_fpu.fp_status)
2818         & (float_flag_invalid | float_flag_overflow)) {
2819         dt2 = FP_TO_INT64_OVERFLOW;
2820     }
2821     update_fcr31(env, GETPC());
2822     return dt2;
2823 }
2824
2825 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2826 {
2827     uint32_t wt2;
2828
2829     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2830     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2831     restore_rounding_mode(env);
2832     if (get_float_exception_flags(&env->active_fpu.fp_status)
2833         & (float_flag_invalid | float_flag_overflow)) {
2834         wt2 = FP_TO_INT32_OVERFLOW;
2835     }
2836     update_fcr31(env, GETPC());
2837     return wt2;
2838 }
2839
2840 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2841 {
2842     uint32_t wt2;
2843
2844     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2845     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2846     restore_rounding_mode(env);
2847     if (get_float_exception_flags(&env->active_fpu.fp_status)
2848         & (float_flag_invalid | float_flag_overflow)) {
2849         wt2 = FP_TO_INT32_OVERFLOW;
2850     }
2851     update_fcr31(env, GETPC());
2852     return wt2;
2853 }
2854
2855 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2856 {
2857     uint64_t dt2;
2858
2859     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2860     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2861     restore_rounding_mode(env);
2862     if (get_float_exception_flags(&env->active_fpu.fp_status)
2863         & (float_flag_invalid | float_flag_overflow)) {
2864         dt2 = FP_TO_INT64_OVERFLOW;
2865     }
2866     update_fcr31(env, GETPC());
2867     return dt2;
2868 }
2869
2870 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2871 {
2872     uint64_t dt2;
2873
2874     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2875     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2876     restore_rounding_mode(env);
2877     if (get_float_exception_flags(&env->active_fpu.fp_status)
2878         & (float_flag_invalid | float_flag_overflow)) {
2879         dt2 = FP_TO_INT64_OVERFLOW;
2880     }
2881     update_fcr31(env, GETPC());
2882     return dt2;
2883 }
2884
2885 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2886 {
2887     uint32_t wt2;
2888
2889     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2890     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2891     restore_rounding_mode(env);
2892     if (get_float_exception_flags(&env->active_fpu.fp_status)
2893         & (float_flag_invalid | float_flag_overflow)) {
2894         wt2 = FP_TO_INT32_OVERFLOW;
2895     }
2896     update_fcr31(env, GETPC());
2897     return wt2;
2898 }
2899
2900 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2901 {
2902     uint32_t wt2;
2903
2904     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2905     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2906     restore_rounding_mode(env);
2907     if (get_float_exception_flags(&env->active_fpu.fp_status)
2908         & (float_flag_invalid | float_flag_overflow)) {
2909         wt2 = FP_TO_INT32_OVERFLOW;
2910     }
2911     update_fcr31(env, GETPC());
2912     return wt2;
2913 }
2914
2915 /* unary operations, not modifying fp status  */
2916 #define FLOAT_UNOP(name)                                       \
2917 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2918 {                                                              \
2919     return float64_ ## name(fdt0);                             \
2920 }                                                              \
2921 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2922 {                                                              \
2923     return float32_ ## name(fst0);                             \
2924 }                                                              \
2925 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2926 {                                                              \
2927     uint32_t wt0;                                              \
2928     uint32_t wth0;                                             \
2929                                                                \
2930     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2931     wth0 = float32_ ## name(fdt0 >> 32);                       \
2932     return ((uint64_t)wth0 << 32) | wt0;                       \
2933 }
2934 FLOAT_UNOP(abs)
2935 FLOAT_UNOP(chs)
2936 #undef FLOAT_UNOP
2937
2938 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
2939 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
2940                                           uint ## bits ## _t fs,        \
2941                                           uint ## bits ## _t ft,        \
2942                                           uint ## bits ## _t fd)        \
2943 {                                                                       \
2944     uint ## bits ## _t fdret;                                           \
2945                                                                         \
2946     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
2947                                      &env->active_fpu.fp_status);       \
2948     update_fcr31(env, GETPC());                                         \
2949     return fdret;                                                       \
2950 }
2951
2952 FLOAT_FMADDSUB(maddf_s, 32, 0)
2953 FLOAT_FMADDSUB(maddf_d, 64, 0)
2954 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
2955 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
2956 #undef FLOAT_FMADDSUB
2957
2958 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
2959 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
2960                                           uint ## bits ## _t fs,        \
2961                                           uint ## bits ## _t ft)        \
2962 {                                                                       \
2963     uint ## bits ## _t fdret;                                           \
2964                                                                         \
2965     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
2966                                            &env->active_fpu.fp_status); \
2967     update_fcr31(env, GETPC());                                         \
2968     return fdret;                                                       \
2969 }
2970
2971 FLOAT_MINMAX(max_s, 32, maxnum)
2972 FLOAT_MINMAX(max_d, 64, maxnum)
2973 FLOAT_MINMAX(maxa_s, 32, maxnummag)
2974 FLOAT_MINMAX(maxa_d, 64, maxnummag)
2975
2976 FLOAT_MINMAX(min_s, 32, minnum)
2977 FLOAT_MINMAX(min_d, 64, minnum)
2978 FLOAT_MINMAX(mina_s, 32, minnummag)
2979 FLOAT_MINMAX(mina_d, 64, minnummag)
2980 #undef FLOAT_MINMAX
2981
2982 #define FLOAT_RINT(name, bits)                                              \
2983 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
2984                                           uint ## bits ## _t fs)            \
2985 {                                                                           \
2986     uint ## bits ## _t fdret;                                               \
2987                                                                             \
2988     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
2989     update_fcr31(env, GETPC());                                             \
2990     return fdret;                                                           \
2991 }
2992
2993 FLOAT_RINT(rint_s, 32)
2994 FLOAT_RINT(rint_d, 64)
2995 #undef FLOAT_RINT
2996
2997 #define FLOAT_CLASS_SIGNALING_NAN      0x001
2998 #define FLOAT_CLASS_QUIET_NAN          0x002
2999 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
3000 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
3001 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3002 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
3003 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
3004 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
3005 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3006 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
3007
3008 #define FLOAT_CLASS(name, bits)                                      \
3009 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
3010 {                                                                    \
3011     if (float ## bits ## _is_signaling_nan(arg)) {                   \
3012         return FLOAT_CLASS_SIGNALING_NAN;                            \
3013     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
3014         return FLOAT_CLASS_QUIET_NAN;                                \
3015     } else if (float ## bits ## _is_neg(arg)) {                      \
3016         if (float ## bits ## _is_infinity(arg)) {                    \
3017             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
3018         } else if (float ## bits ## _is_zero(arg)) {                 \
3019             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
3020         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3021             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
3022         } else {                                                     \
3023             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
3024         }                                                            \
3025     } else {                                                         \
3026         if (float ## bits ## _is_infinity(arg)) {                    \
3027             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
3028         } else if (float ## bits ## _is_zero(arg)) {                 \
3029             return FLOAT_CLASS_POSITIVE_ZERO;                        \
3030         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
3031             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
3032         } else {                                                     \
3033             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
3034         }                                                            \
3035     }                                                                \
3036 }
3037
3038 FLOAT_CLASS(class_s, 32)
3039 FLOAT_CLASS(class_d, 64)
3040 #undef FLOAT_CLASS
3041
3042 /* MIPS specific unary operations */
3043 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3044 {
3045     uint64_t fdt2;
3046
3047     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3048     update_fcr31(env, GETPC());
3049     return fdt2;
3050 }
3051
3052 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3053 {
3054     uint32_t fst2;
3055
3056     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3057     update_fcr31(env, GETPC());
3058     return fst2;
3059 }
3060
3061 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3062 {
3063     uint64_t fdt2;
3064
3065     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3066     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3067     update_fcr31(env, GETPC());
3068     return fdt2;
3069 }
3070
3071 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3072 {
3073     uint32_t fst2;
3074
3075     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3076     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3077     update_fcr31(env, GETPC());
3078     return fst2;
3079 }
3080
3081 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3082 {
3083     uint64_t fdt2;
3084
3085     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3086     update_fcr31(env, GETPC());
3087     return fdt2;
3088 }
3089
3090 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3091 {
3092     uint32_t fst2;
3093
3094     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3095     update_fcr31(env, GETPC());
3096     return fst2;
3097 }
3098
3099 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3100 {
3101     uint32_t fst2;
3102     uint32_t fsth2;
3103
3104     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3105     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3106     update_fcr31(env, GETPC());
3107     return ((uint64_t)fsth2 << 32) | fst2;
3108 }
3109
3110 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3111 {
3112     uint64_t fdt2;
3113
3114     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3115     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3116     update_fcr31(env, GETPC());
3117     return fdt2;
3118 }
3119
3120 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3121 {
3122     uint32_t fst2;
3123
3124     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3125     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3126     update_fcr31(env, GETPC());
3127     return fst2;
3128 }
3129
3130 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3131 {
3132     uint32_t fst2;
3133     uint32_t fsth2;
3134
3135     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3136     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3137     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3138     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3139     update_fcr31(env, GETPC());
3140     return ((uint64_t)fsth2 << 32) | fst2;
3141 }
3142
3143 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
3144
3145 /* binary operations */
3146 #define FLOAT_BINOP(name)                                          \
3147 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3148                                      uint64_t fdt0, uint64_t fdt1) \
3149 {                                                                  \
3150     uint64_t dt2;                                                  \
3151                                                                    \
3152     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3153     update_fcr31(env, GETPC());                                    \
3154     return dt2;                                                    \
3155 }                                                                  \
3156                                                                    \
3157 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3158                                      uint32_t fst0, uint32_t fst1) \
3159 {                                                                  \
3160     uint32_t wt2;                                                  \
3161                                                                    \
3162     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3163     update_fcr31(env, GETPC());                                    \
3164     return wt2;                                                    \
3165 }                                                                  \
3166                                                                    \
3167 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3168                                       uint64_t fdt0,               \
3169                                       uint64_t fdt1)               \
3170 {                                                                  \
3171     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3172     uint32_t fsth0 = fdt0 >> 32;                                   \
3173     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3174     uint32_t fsth1 = fdt1 >> 32;                                   \
3175     uint32_t wt2;                                                  \
3176     uint32_t wth2;                                                 \
3177                                                                    \
3178     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3179     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3180     update_fcr31(env, GETPC());                                    \
3181     return ((uint64_t)wth2 << 32) | wt2;                           \
3182 }
3183
3184 FLOAT_BINOP(add)
3185 FLOAT_BINOP(sub)
3186 FLOAT_BINOP(mul)
3187 FLOAT_BINOP(div)
3188 #undef FLOAT_BINOP
3189
3190 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3191 {                                                                    \
3192     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3193     if ((flags) & float_muladd_negate_c) {                           \
3194         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3195     } else {                                                         \
3196         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3197     }                                                                \
3198     if ((flags) & float_muladd_negate_result) {                      \
3199         a = prefix##_chs(a);                                         \
3200     }                                                                \
3201 }
3202
3203 /* FMA based operations */
3204 #define FLOAT_FMA(name, type)                                        \
3205 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3206                                      uint64_t fdt0, uint64_t fdt1,   \
3207                                      uint64_t fdt2)                  \
3208 {                                                                    \
3209     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3210     update_fcr31(env, GETPC());                                      \
3211     return fdt0;                                                     \
3212 }                                                                    \
3213                                                                      \
3214 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3215                                      uint32_t fst0, uint32_t fst1,   \
3216                                      uint32_t fst2)                  \
3217 {                                                                    \
3218     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3219     update_fcr31(env, GETPC());                                      \
3220     return fst0;                                                     \
3221 }                                                                    \
3222                                                                      \
3223 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3224                                       uint64_t fdt0, uint64_t fdt1,  \
3225                                       uint64_t fdt2)                 \
3226 {                                                                    \
3227     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3228     uint32_t fsth0 = fdt0 >> 32;                                     \
3229     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3230     uint32_t fsth1 = fdt1 >> 32;                                     \
3231     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3232     uint32_t fsth2 = fdt2 >> 32;                                     \
3233                                                                      \
3234     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3235     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3236     update_fcr31(env, GETPC());                                      \
3237     return ((uint64_t)fsth0 << 32) | fst0;                           \
3238 }
3239 FLOAT_FMA(madd, 0)
3240 FLOAT_FMA(msub, float_muladd_negate_c)
3241 FLOAT_FMA(nmadd, float_muladd_negate_result)
3242 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3243 #undef FLOAT_FMA
3244
3245 /* MIPS specific binary operations */
3246 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3247 {
3248     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3249     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3250     update_fcr31(env, GETPC());
3251     return fdt2;
3252 }
3253
3254 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3255 {
3256     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3257     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3258     update_fcr31(env, GETPC());
3259     return fst2;
3260 }
3261
3262 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3263 {
3264     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3265     uint32_t fsth0 = fdt0 >> 32;
3266     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3267     uint32_t fsth2 = fdt2 >> 32;
3268
3269     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3270     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3271     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3272     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3273     update_fcr31(env, GETPC());
3274     return ((uint64_t)fsth2 << 32) | fst2;
3275 }
3276
3277 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3278 {
3279     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3280     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3281     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3282     update_fcr31(env, GETPC());
3283     return fdt2;
3284 }
3285
3286 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3287 {
3288     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3289     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3290     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3291     update_fcr31(env, GETPC());
3292     return fst2;
3293 }
3294
3295 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3296 {
3297     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3298     uint32_t fsth0 = fdt0 >> 32;
3299     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3300     uint32_t fsth2 = fdt2 >> 32;
3301
3302     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3303     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3304     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3305     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3306     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3307     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3308     update_fcr31(env, GETPC());
3309     return ((uint64_t)fsth2 << 32) | fst2;
3310 }
3311
3312 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3313 {
3314     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3315     uint32_t fsth0 = fdt0 >> 32;
3316     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3317     uint32_t fsth1 = fdt1 >> 32;
3318     uint32_t fst2;
3319     uint32_t fsth2;
3320
3321     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3322     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3323     update_fcr31(env, GETPC());
3324     return ((uint64_t)fsth2 << 32) | fst2;
3325 }
3326
3327 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3328 {
3329     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3330     uint32_t fsth0 = fdt0 >> 32;
3331     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3332     uint32_t fsth1 = fdt1 >> 32;
3333     uint32_t fst2;
3334     uint32_t fsth2;
3335
3336     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3337     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3338     update_fcr31(env, GETPC());
3339     return ((uint64_t)fsth2 << 32) | fst2;
3340 }
3341
3342 /* compare operations */
3343 #define FOP_COND_D(op, cond)                                   \
3344 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3345                          uint64_t fdt1, int cc)                \
3346 {                                                              \
3347     int c;                                                     \
3348     c = cond;                                                  \
3349     update_fcr31(env, GETPC());                                \
3350     if (c)                                                     \
3351         SET_FP_COND(cc, env->active_fpu);                      \
3352     else                                                       \
3353         CLEAR_FP_COND(cc, env->active_fpu);                    \
3354 }                                                              \
3355 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3356                             uint64_t fdt1, int cc)             \
3357 {                                                              \
3358     int c;                                                     \
3359     fdt0 = float64_abs(fdt0);                                  \
3360     fdt1 = float64_abs(fdt1);                                  \
3361     c = cond;                                                  \
3362     update_fcr31(env, GETPC());                                \
3363     if (c)                                                     \
3364         SET_FP_COND(cc, env->active_fpu);                      \
3365     else                                                       \
3366         CLEAR_FP_COND(cc, env->active_fpu);                    \
3367 }
3368
3369 /* NOTE: the comma operator will make "cond" to eval to false,
3370  * but float64_unordered_quiet() is still called. */
3371 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3372 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3373 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3374 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3375 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3376 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3377 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3378 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3379 /* NOTE: the comma operator will make "cond" to eval to false,
3380  * but float64_unordered() is still called. */
3381 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3382 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3383 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3384 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3385 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3386 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3387 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3388 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3389
3390 #define FOP_COND_S(op, cond)                                   \
3391 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3392                          uint32_t fst1, int cc)                \
3393 {                                                              \
3394     int c;                                                     \
3395     c = cond;                                                  \
3396     update_fcr31(env, GETPC());                                \
3397     if (c)                                                     \
3398         SET_FP_COND(cc, env->active_fpu);                      \
3399     else                                                       \
3400         CLEAR_FP_COND(cc, env->active_fpu);                    \
3401 }                                                              \
3402 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3403                             uint32_t fst1, int cc)             \
3404 {                                                              \
3405     int c;                                                     \
3406     fst0 = float32_abs(fst0);                                  \
3407     fst1 = float32_abs(fst1);                                  \
3408     c = cond;                                                  \
3409     update_fcr31(env, GETPC());                                \
3410     if (c)                                                     \
3411         SET_FP_COND(cc, env->active_fpu);                      \
3412     else                                                       \
3413         CLEAR_FP_COND(cc, env->active_fpu);                    \
3414 }
3415
3416 /* NOTE: the comma operator will make "cond" to eval to false,
3417  * but float32_unordered_quiet() is still called. */
3418 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3419 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3420 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3421 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3422 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3423 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3424 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3425 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3426 /* NOTE: the comma operator will make "cond" to eval to false,
3427  * but float32_unordered() is still called. */
3428 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3429 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3430 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3431 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3432 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3433 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3434 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3435 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3436
3437 #define FOP_COND_PS(op, condl, condh)                           \
3438 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3439                           uint64_t fdt1, int cc)                \
3440 {                                                               \
3441     uint32_t fst0, fsth0, fst1, fsth1;                          \
3442     int ch, cl;                                                 \
3443     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3444     fsth0 = fdt0 >> 32;                                         \
3445     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3446     fsth1 = fdt1 >> 32;                                         \
3447     cl = condl;                                                 \
3448     ch = condh;                                                 \
3449     update_fcr31(env, GETPC());                                 \
3450     if (cl)                                                     \
3451         SET_FP_COND(cc, env->active_fpu);                       \
3452     else                                                        \
3453         CLEAR_FP_COND(cc, env->active_fpu);                     \
3454     if (ch)                                                     \
3455         SET_FP_COND(cc + 1, env->active_fpu);                   \
3456     else                                                        \
3457         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3458 }                                                               \
3459 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3460                              uint64_t fdt1, int cc)             \
3461 {                                                               \
3462     uint32_t fst0, fsth0, fst1, fsth1;                          \
3463     int ch, cl;                                                 \
3464     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3465     fsth0 = float32_abs(fdt0 >> 32);                            \
3466     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3467     fsth1 = float32_abs(fdt1 >> 32);                            \
3468     cl = condl;                                                 \
3469     ch = condh;                                                 \
3470     update_fcr31(env, GETPC());                                 \
3471     if (cl)                                                     \
3472         SET_FP_COND(cc, env->active_fpu);                       \
3473     else                                                        \
3474         CLEAR_FP_COND(cc, env->active_fpu);                     \
3475     if (ch)                                                     \
3476         SET_FP_COND(cc + 1, env->active_fpu);                   \
3477     else                                                        \
3478         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3479 }
3480
3481 /* NOTE: the comma operator will make "cond" to eval to false,
3482  * but float32_unordered_quiet() is still called. */
3483 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3484                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3485 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3486                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3487 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3488                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3489 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3490                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3491 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3492                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3493 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3494                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3495 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3496                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3497 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3498                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3499 /* NOTE: the comma operator will make "cond" to eval to false,
3500  * but float32_unordered() is still called. */
3501 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3502                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3503 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3504                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3505 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3506                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3507 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3508                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3509 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3510                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3511 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3512                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3513 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3514                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3515 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3516                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3517
3518 /* R6 compare operations */
3519 #define FOP_CONDN_D(op, cond)                                       \
3520 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3521                          uint64_t fdt1)                             \
3522 {                                                                   \
3523     uint64_t c;                                                     \
3524     c = cond;                                                       \
3525     update_fcr31(env, GETPC());                                     \
3526     if (c) {                                                        \
3527         return -1;                                                  \
3528     } else {                                                        \
3529         return 0;                                                   \
3530     }                                                               \
3531 }
3532
3533 /* NOTE: the comma operator will make "cond" to eval to false,
3534  * but float64_unordered_quiet() is still called. */
3535 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3536 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3537 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3538 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3539                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3540 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3541 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3542                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3543 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3544 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3545                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3546 /* NOTE: the comma operator will make "cond" to eval to false,
3547  * but float64_unordered() is still called. */
3548 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3549 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3550 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3551 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3552                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3553 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3554 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3555                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3556 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3557 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3558                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3559 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3560                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3561 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3562                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3563                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3564 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3565                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3566 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3567                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3568 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3569                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3570                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3571 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3572                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3573
3574 #define FOP_CONDN_S(op, cond)                                       \
3575 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3576                          uint32_t fst1)                             \
3577 {                                                                   \
3578     uint64_t c;                                                     \
3579     c = cond;                                                       \
3580     update_fcr31(env, GETPC());                                     \
3581     if (c) {                                                        \
3582         return -1;                                                  \
3583     } else {                                                        \
3584         return 0;                                                   \
3585     }                                                               \
3586 }
3587
3588 /* NOTE: the comma operator will make "cond" to eval to false,
3589  * but float32_unordered_quiet() is still called. */
3590 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3591 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3592 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3593 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3594                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3595 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3596 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3597                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3598 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3599 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3600                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3601 /* NOTE: the comma operator will make "cond" to eval to false,
3602  * but float32_unordered() is still called. */
3603 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3604 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3605 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3606 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3607                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3608 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3609 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3610                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3611 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3612 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3613                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3614 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3615                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3616 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3617                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3618                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3619 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3620                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3621 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3622                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3623 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3624                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3625                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3626 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3627                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3628
3629 /* MSA */
3630 /* Data format min and max values */
3631 #define DF_BITS(df) (1 << ((df) + 3))
3632
3633 /* Element-by-element access macros */
3634 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3635
3636 void helper_msa_ld_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs,
3637                      int32_t s10)
3638 {
3639     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3640     target_ulong addr = env->active_tc.gpr[rs] + (s10 << df);
3641     int i;
3642
3643     switch (df) {
3644     case DF_BYTE:
3645         for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
3646             pwd->b[i] = do_lbu(env, addr + (i << DF_BYTE),
3647                                 env->hflags & MIPS_HFLAG_KSU);
3648         }
3649         break;
3650     case DF_HALF:
3651         for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
3652             pwd->h[i] = do_lhu(env, addr + (i << DF_HALF),
3653                                 env->hflags & MIPS_HFLAG_KSU);
3654         }
3655         break;
3656     case DF_WORD:
3657         for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3658             pwd->w[i] = do_lw(env, addr + (i << DF_WORD),
3659                                 env->hflags & MIPS_HFLAG_KSU);
3660         }
3661         break;
3662     case DF_DOUBLE:
3663         for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3664             pwd->d[i] = do_ld(env, addr + (i << DF_DOUBLE),
3665                                 env->hflags & MIPS_HFLAG_KSU);
3666         }
3667         break;
3668     }
3669 }
3670
3671 void helper_msa_st_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs,
3672                      int32_t s10)
3673 {
3674     wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
3675     target_ulong addr = env->active_tc.gpr[rs] + (s10 << df);
3676     int i;
3677
3678     switch (df) {
3679     case DF_BYTE:
3680         for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
3681             do_sb(env, addr + (i << DF_BYTE), pwd->b[i],
3682                     env->hflags & MIPS_HFLAG_KSU);
3683         }
3684         break;
3685     case DF_HALF:
3686         for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
3687             do_sh(env, addr + (i << DF_HALF), pwd->h[i],
3688                     env->hflags & MIPS_HFLAG_KSU);
3689         }
3690         break;
3691     case DF_WORD:
3692         for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
3693             do_sw(env, addr + (i << DF_WORD), pwd->w[i],
3694                     env->hflags & MIPS_HFLAG_KSU);
3695         }
3696         break;
3697     case DF_DOUBLE:
3698         for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
3699             do_sd(env, addr + (i << DF_DOUBLE), pwd->d[i],
3700                     env->hflags & MIPS_HFLAG_KSU);
3701         }
3702         break;
3703     }
3704 }