target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "host-utils.h"
  22
  23 #include "helper.h"
  24
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "softmmu_exec.h"
  27 #endif /* !defined(CONFIG_USER_ONLY) */
  28
  29 #ifndef CONFIG_USER_ONLY
  30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  31 #endif
  32
  33 /*****************************************************************************/
  34 /* Exceptions processing helpers */
  35
  36 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  37                                 int error_code)
  38 {
  39 #if 1
  40     if (exception < 0x100)
  41         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  42 #endif
  43     env->exception_index = exception;
  44     env->error_code = error_code;
  45     cpu_loop_exit(env);
  46 }
  47
  48 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  49 {
  50     helper_raise_exception_err(env, exception, 0);
  51 }
  52
  53 #if !defined(CONFIG_USER_ONLY)
  54 static void do_restore_state(CPUMIPSState *env, uintptr_t pc)
  55 {
  56     TranslationBlock *tb;
  57
  58     tb = tb_find_pc (pc);
  59     if (tb) {
  60         cpu_restore_state(tb, env, pc);
  61     }
  62 }
  63 #endif
  64
  65 #if defined(CONFIG_USER_ONLY)
  66 #define HELPER_LD(name, insn, type)                                     \
  67 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  68                              int mem_idx)                               \
  69 {                                                                       \
  70     return (type) insn##_raw(addr);                                     \
  71 }
  72 #else
  73 #define HELPER_LD(name, insn, type)                                     \
  74 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  75                              int mem_idx)                               \
  76 {                                                                       \
  77     switch (mem_idx)                                                    \
  78     {                                                                   \
  79     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  80     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  81     default:                                                            \
  82     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  83     }                                                                   \
  84 }
  85 #endif
  86 HELPER_LD(lbu, ldub, uint8_t)
  87 HELPER_LD(lw, ldl, int32_t)
  88 #ifdef TARGET_MIPS64
  89 HELPER_LD(ld, ldq, int64_t)
  90 #endif
  91 #undef HELPER_LD
  92
  93 #if defined(CONFIG_USER_ONLY)
  94 #define HELPER_ST(name, insn, type)                                     \
  95 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
  96                              type val, int mem_idx)                     \
  97 {                                                                       \
  98     insn##_raw(addr, val);                                              \
  99 }
 100 #else
 101 #define HELPER_ST(name, insn, type)                                     \
 102 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 103                              type val, int mem_idx)                     \
 104 {                                                                       \
 105     switch (mem_idx)                                                    \
 106     {                                                                   \
 107     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 108     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 109     default:                                                            \
 110     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 111     }                                                                   \
 112 }
 113 #endif
 114 HELPER_ST(sb, stb, uint8_t)
 115 HELPER_ST(sw, stl, uint32_t)
 116 #ifdef TARGET_MIPS64
 117 HELPER_ST(sd, stq, uint64_t)
 118 #endif
 119 #undef HELPER_ST
 120
 121 target_ulong helper_clo (target_ulong arg1)
 122 {
 123     return clo32(arg1);
 124 }
 125
 126 target_ulong helper_clz (target_ulong arg1)
 127 {
 128     return clz32(arg1);
 129 }
 130
 131 #if defined(TARGET_MIPS64)
 132 target_ulong helper_dclo (target_ulong arg1)
 133 {
 134     return clo64(arg1);
 135 }
 136
 137 target_ulong helper_dclz (target_ulong arg1)
 138 {
 139     return clz64(arg1);
 140 }
 141 #endif /* TARGET_MIPS64 */
 142
 143 /* 64 bits arithmetic for 32 bits hosts */
 144 static inline uint64_t get_HILO(CPUMIPSState *env)
 145 {
 146     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 147 }
 148
 149 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 150 {
 151     target_ulong tmp;
 152     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 153     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 154     return tmp;
 155 }
 156
 157 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 158 {
 159     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 160     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 161     return tmp;
 162 }
 163
 164 /* Multiplication variants of the vr54xx. */
 165 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 166                          target_ulong arg2)
 167 {
 168     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 169                                  (int64_t)(int32_t)arg2));
 170 }
 171
 172 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 173                           target_ulong arg2)
 174 {
 175     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 176                        (uint64_t)(uint32_t)arg2);
 177 }
 178
 179 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 180                          target_ulong arg2)
 181 {
 182     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 183                        (int64_t)(int32_t)arg2);
 184 }
 185
 186 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 187                            target_ulong arg2)
 188 {
 189     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 190                        (int64_t)(int32_t)arg2);
 191 }
 192
 193 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 194                           target_ulong arg2)
 195 {
 196     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 197                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 198 }
 199
 200 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 201                             target_ulong arg2)
 202 {
 203     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 204                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 205 }
 206
 207 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 208                          target_ulong arg2)
 209 {
 210     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 211                        (int64_t)(int32_t)arg2);
 212 }
 213
 214 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 215                            target_ulong arg2)
 216 {
 217     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 218                        (int64_t)(int32_t)arg2);
 219 }
 220
 221 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 222                           target_ulong arg2)
 223 {
 224     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 225                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 226 }
 227
 228 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 229                             target_ulong arg2)
 230 {
 231     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 232                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 233 }
 234
 235 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 236                           target_ulong arg2)
 237 {
 238     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 239 }
 240
 241 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 242                            target_ulong arg2)
 243 {
 244     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 245                        (uint64_t)(uint32_t)arg2);
 246 }
 247
 248 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 249                            target_ulong arg2)
 250 {
 251     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 252                        (int64_t)(int32_t)arg2);
 253 }
 254
 255 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 256                             target_ulong arg2)
 257 {
 258     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 259                        (uint64_t)(uint32_t)arg2);
 260 }
 261
 262 #ifdef TARGET_MIPS64
 263 void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 264 {
 265     muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 266 }
 267
 268 void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 269 {
 270     mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 271 }
 272 #endif
 273
 274 #ifndef CONFIG_USER_ONLY
 275
 276 static inline target_phys_addr_t do_translate_address(CPUMIPSState *env,
 277                                                       target_ulong address,
 278                                                       int rw)
 279 {
 280     target_phys_addr_t lladdr;
 281
 282     lladdr = cpu_mips_translate_address(env, address, rw);
 283
 284     if (lladdr == -1LL) {
 285         cpu_loop_exit(env);
 286     } else {
 287         return lladdr;
 288     }
 289 }
 290
 291 #define HELPER_LD_ATOMIC(name, insn)                                          \
 292 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 293 {                                                                             \
 294     env->lladdr = do_translate_address(env, arg, 0);                          \
 295     env->llval = do_##insn(env, arg, mem_idx);                                \
 296     return env->llval;                                                        \
 297 }
 298 HELPER_LD_ATOMIC(ll, lw)
 299 #ifdef TARGET_MIPS64
 300 HELPER_LD_ATOMIC(lld, ld)
 301 #endif
 302 #undef HELPER_LD_ATOMIC
 303
 304 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 305 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 306                            target_ulong arg2, int mem_idx)                    \
 307 {                                                                             \
 308     target_long tmp;                                                          \
 309                                                                               \
 310     if (arg2 & almask) {                                                      \
 311         env->CP0_BadVAddr = arg2;                                             \
 312         helper_raise_exception(env, EXCP_AdES);                               \
 313     }                                                                         \
 314     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 315         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 316         if (tmp == env->llval) {                                              \
 317             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 318             return 1;                                                         \
 319         }                                                                     \
 320     }                                                                         \
 321     return 0;                                                                 \
 322 }
 323 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 324 #ifdef TARGET_MIPS64
 325 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 326 #endif
 327 #undef HELPER_ST_ATOMIC
 328 #endif
 329
 330 #ifdef TARGET_WORDS_BIGENDIAN
 331 #define GET_LMASK(v) ((v) & 3)
 332 #define GET_OFFSET(addr, offset) (addr + (offset))
 333 #else
 334 #define GET_LMASK(v) (((v) & 3) ^ 3)
 335 #define GET_OFFSET(addr, offset) (addr - (offset))
 336 #endif
 337
 338 target_ulong helper_lwl(CPUMIPSState *env, target_ulong arg1,
 339                         target_ulong arg2, int mem_idx)
 340 {
 341     target_ulong tmp;
 342
 343     tmp = do_lbu(env, arg2, mem_idx);
 344     arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
 345
 346     if (GET_LMASK(arg2) <= 2) {
 347         tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
 348         arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
 349     }
 350
 351     if (GET_LMASK(arg2) <= 1) {
 352         tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
 353         arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
 354     }
 355
 356     if (GET_LMASK(arg2) == 0) {
 357         tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
 358         arg1 = (arg1 & 0xFFFFFF00) | tmp;
 359     }
 360     return (int32_t)arg1;
 361 }
 362
 363 target_ulong helper_lwr(CPUMIPSState *env, target_ulong arg1,
 364                         target_ulong arg2, int mem_idx)
 365 {
 366     target_ulong tmp;
 367
 368     tmp = do_lbu(env, arg2, mem_idx);
 369     arg1 = (arg1 & 0xFFFFFF00) | tmp;
 370
 371     if (GET_LMASK(arg2) >= 1) {
 372         tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
 373         arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
 374     }
 375
 376     if (GET_LMASK(arg2) >= 2) {
 377         tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
 378         arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
 379     }
 380
 381     if (GET_LMASK(arg2) == 3) {
 382         tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
 383         arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
 384     }
 385     return (int32_t)arg1;
 386 }
 387
 388 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 389                 int mem_idx)
 390 {
 391     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 392
 393     if (GET_LMASK(arg2) <= 2)
 394         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 395
 396     if (GET_LMASK(arg2) <= 1)
 397         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 398
 399     if (GET_LMASK(arg2) == 0)
 400         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 401 }
 402
 403 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 404                 int mem_idx)
 405 {
 406     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 407
 408     if (GET_LMASK(arg2) >= 1)
 409         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 410
 411     if (GET_LMASK(arg2) >= 2)
 412         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 413
 414     if (GET_LMASK(arg2) == 3)
 415         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 416 }
 417
 418 #if defined(TARGET_MIPS64)
 419 /* "half" load and stores.  We must do the memory access inline,
 420    or fault handling won't work.  */
 421
 422 #ifdef TARGET_WORDS_BIGENDIAN
 423 #define GET_LMASK64(v) ((v) & 7)
 424 #else
 425 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 426 #endif
 427
 428 target_ulong helper_ldl(CPUMIPSState *env, target_ulong arg1,
 429                         target_ulong arg2, int mem_idx)
 430 {
 431     uint64_t tmp;
 432
 433     tmp = do_lbu(env, arg2, mem_idx);
 434     arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 435
 436     if (GET_LMASK64(arg2) <= 6) {
 437         tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx);
 438         arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
 439     }
 440
 441     if (GET_LMASK64(arg2) <= 5) {
 442         tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx);
 443         arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
 444     }
 445
 446     if (GET_LMASK64(arg2) <= 4) {
 447         tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx);
 448         arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
 449     }
 450
 451     if (GET_LMASK64(arg2) <= 3) {
 452         tmp = do_lbu(env, GET_OFFSET(arg2, 4), mem_idx);
 453         arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
 454     }
 455
 456     if (GET_LMASK64(arg2) <= 2) {
 457         tmp = do_lbu(env, GET_OFFSET(arg2, 5), mem_idx);
 458         arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
 459     }
 460
 461     if (GET_LMASK64(arg2) <= 1) {
 462         tmp = do_lbu(env, GET_OFFSET(arg2, 6), mem_idx);
 463         arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
 464     }
 465
 466     if (GET_LMASK64(arg2) == 0) {
 467         tmp = do_lbu(env, GET_OFFSET(arg2, 7), mem_idx);
 468         arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 469     }
 470
 471     return arg1;
 472 }
 473
 474 target_ulong helper_ldr(CPUMIPSState *env, target_ulong arg1,
 475                         target_ulong arg2, int mem_idx)
 476 {
 477     uint64_t tmp;
 478
 479     tmp = do_lbu(env, arg2, mem_idx);
 480     arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 481
 482     if (GET_LMASK64(arg2) >= 1) {
 483         tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx);
 484         arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
 485     }
 486
 487     if (GET_LMASK64(arg2) >= 2) {
 488         tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx);
 489         arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
 490     }
 491
 492     if (GET_LMASK64(arg2) >= 3) {
 493         tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx);
 494         arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
 495     }
 496
 497     if (GET_LMASK64(arg2) >= 4) {
 498         tmp = do_lbu(env, GET_OFFSET(arg2, -4), mem_idx);
 499         arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
 500     }
 501
 502     if (GET_LMASK64(arg2) >= 5) {
 503         tmp = do_lbu(env, GET_OFFSET(arg2, -5), mem_idx);
 504         arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
 505     }
 506
 507     if (GET_LMASK64(arg2) >= 6) {
 508         tmp = do_lbu(env, GET_OFFSET(arg2, -6), mem_idx);
 509         arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
 510     }
 511
 512     if (GET_LMASK64(arg2) == 7) {
 513         tmp = do_lbu(env, GET_OFFSET(arg2, -7), mem_idx);
 514         arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 515     }
 516
 517     return arg1;
 518 }
 519
 520 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 521                 int mem_idx)
 522 {
 523     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 524
 525     if (GET_LMASK64(arg2) <= 6)
 526         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 527
 528     if (GET_LMASK64(arg2) <= 5)
 529         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 530
 531     if (GET_LMASK64(arg2) <= 4)
 532         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 533
 534     if (GET_LMASK64(arg2) <= 3)
 535         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 536
 537     if (GET_LMASK64(arg2) <= 2)
 538         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 539
 540     if (GET_LMASK64(arg2) <= 1)
 541         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 542
 543     if (GET_LMASK64(arg2) <= 0)
 544         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 545 }
 546
 547 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 548                 int mem_idx)
 549 {
 550     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 551
 552     if (GET_LMASK64(arg2) >= 1)
 553         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 554
 555     if (GET_LMASK64(arg2) >= 2)
 556         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 557
 558     if (GET_LMASK64(arg2) >= 3)
 559         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 560
 561     if (GET_LMASK64(arg2) >= 4)
 562         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 563
 564     if (GET_LMASK64(arg2) >= 5)
 565         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 566
 567     if (GET_LMASK64(arg2) >= 6)
 568         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 569
 570     if (GET_LMASK64(arg2) == 7)
 571         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 572 }
 573 #endif /* TARGET_MIPS64 */
 574
 575 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 576
 577 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 578                 uint32_t mem_idx)
 579 {
 580     target_ulong base_reglist = reglist & 0xf;
 581     target_ulong do_r31 = reglist & 0x10;
 582 #ifdef CONFIG_USER_ONLY
 583 #undef ldfun
 584 #define ldfun(env, addr) ldl_raw(addr)
 585 #else
 586     uint32_t (*ldfun)(CPUMIPSState *env, target_ulong);
 587
 588     switch (mem_idx)
 589     {
 590     case 0: ldfun = cpu_ldl_kernel; break;
 591     case 1: ldfun = cpu_ldl_super; break;
 592     default:
 593     case 2: ldfun = cpu_ldl_user; break;
 594     }
 595 #endif
 596
 597     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 598         target_ulong i;
 599
 600         for (i = 0; i < base_reglist; i++) {
 601             env->active_tc.gpr[multiple_regs[i]] = (target_long)ldfun(env, addr);
 602             addr += 4;
 603         }
 604     }
 605
 606     if (do_r31) {
 607         env->active_tc.gpr[31] = (target_long)ldfun(env, addr);
 608     }
 609 }
 610
 611 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 612                 uint32_t mem_idx)
 613 {
 614     target_ulong base_reglist = reglist & 0xf;
 615     target_ulong do_r31 = reglist & 0x10;
 616 #ifdef CONFIG_USER_ONLY
 617 #undef stfun
 618 #define stfun(env, addr, val) stl_raw(addr, val)
 619 #else
 620     void (*stfun)(CPUMIPSState *env, target_ulong, uint32_t);
 621
 622     switch (mem_idx)
 623     {
 624     case 0: stfun = cpu_stl_kernel; break;
 625     case 1: stfun = cpu_stl_super; break;
 626      default:
 627     case 2: stfun = cpu_stl_user; break;
 628     }
 629 #endif
 630
 631     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 632         target_ulong i;
 633
 634         for (i = 0; i < base_reglist; i++) {
 635             stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]);
 636             addr += 4;
 637         }
 638     }
 639
 640     if (do_r31) {
 641         stfun(env, addr, env->active_tc.gpr[31]);
 642     }
 643 }
 644
 645 #if defined(TARGET_MIPS64)
 646 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 647                 uint32_t mem_idx)
 648 {
 649     target_ulong base_reglist = reglist & 0xf;
 650     target_ulong do_r31 = reglist & 0x10;
 651 #ifdef CONFIG_USER_ONLY
 652 #undef ldfun
 653 #define ldfun(env, addr) ldq_raw(addr)
 654 #else
 655     uint64_t (*ldfun)(CPUMIPSState *env, target_ulong);
 656
 657     switch (mem_idx)
 658     {
 659     case 0: ldfun = cpu_ldq_kernel; break;
 660     case 1: ldfun = cpu_ldq_super; break;
 661     default:
 662     case 2: ldfun = cpu_ldq_user; break;
 663     }
 664 #endif
 665
 666     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 667         target_ulong i;
 668
 669         for (i = 0; i < base_reglist; i++) {
 670             env->active_tc.gpr[multiple_regs[i]] = ldfun(env, addr);
 671             addr += 8;
 672         }
 673     }
 674
 675     if (do_r31) {
 676         env->active_tc.gpr[31] = ldfun(env, addr);
 677     }
 678 }
 679
 680 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 681                 uint32_t mem_idx)
 682 {
 683     target_ulong base_reglist = reglist & 0xf;
 684     target_ulong do_r31 = reglist & 0x10;
 685 #ifdef CONFIG_USER_ONLY
 686 #undef stfun
 687 #define stfun(env, addr, val) stq_raw(addr, val)
 688 #else
 689     void (*stfun)(CPUMIPSState *env, target_ulong, uint64_t);
 690
 691     switch (mem_idx)
 692     {
 693     case 0: stfun = cpu_stq_kernel; break;
 694     case 1: stfun = cpu_stq_super; break;
 695      default:
 696     case 2: stfun = cpu_stq_user; break;
 697     }
 698 #endif
 699
 700     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 701         target_ulong i;
 702
 703         for (i = 0; i < base_reglist; i++) {
 704             stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]);
 705             addr += 8;
 706         }
 707     }
 708
 709     if (do_r31) {
 710         stfun(env, addr, env->active_tc.gpr[31]);
 711     }
 712 }
 713 #endif
 714
 715 #ifndef CONFIG_USER_ONLY
 716 /* SMP helpers.  */
 717 static int mips_vpe_is_wfi(CPUMIPSState *c)
 718 {
 719     /* If the VPE is halted but otherwise active, it means it's waiting for
 720        an interrupt.  */
 721     return c->halted && mips_vpe_active(c);
 722 }
 723
 724 static inline void mips_vpe_wake(CPUMIPSState *c)
 725 {
 726     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 727        because there might be other conditions that state that c should
 728        be sleeping.  */
 729     cpu_interrupt(c, CPU_INTERRUPT_WAKE);
 730 }
 731
 732 static inline void mips_vpe_sleep(CPUMIPSState *c)
 733 {
 734     /* The VPE was shut off, really go to bed.
 735        Reset any old _WAKE requests.  */
 736     c->halted = 1;
 737     cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
 738 }
 739
 740 static inline void mips_tc_wake(CPUMIPSState *c, int tc)
 741 {
 742     /* FIXME: TC reschedule.  */
 743     if (mips_vpe_active(c) && !mips_vpe_is_wfi(c)) {
 744         mips_vpe_wake(c);
 745     }
 746 }
 747
 748 static inline void mips_tc_sleep(CPUMIPSState *c, int tc)
 749 {
 750     /* FIXME: TC reschedule.  */
 751     if (!mips_vpe_active(c)) {
 752         mips_vpe_sleep(c);
 753     }
 754 }
 755
 756 /* tc should point to an int with the value of the global TC index.
 757    This function will transform it into a local index within the
 758    returned CPUMIPSState.
 759
 760    FIXME: This code assumes that all VPEs have the same number of TCs,
 761           which depends on runtime setup. Can probably be fixed by
 762           walking the list of CPUMIPSStates.  */
 763 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 764 {
 765     CPUMIPSState *other;
 766     int vpe_idx, nr_threads = env->nr_threads;
 767     int tc_idx = *tc;
 768
 769     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 770         /* Not allowed to address other CPUs.  */
 771         *tc = env->current_tc;
 772         return env;
 773     }
 774
 775     vpe_idx = tc_idx / nr_threads;
 776     *tc = tc_idx % nr_threads;
 777     other = qemu_get_cpu(vpe_idx);
 778     return other ? other : env;
 779 }
 780
 781 /* The per VPE CP0_Status register shares some fields with the per TC
 782    CP0_TCStatus registers. These fields are wired to the same registers,
 783    so changes to either of them should be reflected on both registers.
 784
 785    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 786
 787    These helper call synchronizes the regs for a given cpu.  */
 788
 789 /* Called for updates to CP0_Status.  */
 790 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 791 {
 792     int32_t tcstatus, *tcst;
 793     uint32_t v = cpu->CP0_Status;
 794     uint32_t cu, mx, asid, ksu;
 795     uint32_t mask = ((1 << CP0TCSt_TCU3)
 796                        | (1 << CP0TCSt_TCU2)
 797                        | (1 << CP0TCSt_TCU1)
 798                        | (1 << CP0TCSt_TCU0)
 799                        | (1 << CP0TCSt_TMX)
 800                        | (3 << CP0TCSt_TKSU)
 801                        | (0xff << CP0TCSt_TASID));
 802
 803     cu = (v >> CP0St_CU0) & 0xf;
 804     mx = (v >> CP0St_MX) & 0x1;
 805     ksu = (v >> CP0St_KSU) & 0x3;
 806     asid = env->CP0_EntryHi & 0xff;
 807
 808     tcstatus = cu << CP0TCSt_TCU0;
 809     tcstatus |= mx << CP0TCSt_TMX;
 810     tcstatus |= ksu << CP0TCSt_TKSU;
 811     tcstatus |= asid;
 812
 813     if (tc == cpu->current_tc) {
 814         tcst = &cpu->active_tc.CP0_TCStatus;
 815     } else {
 816         tcst = &cpu->tcs[tc].CP0_TCStatus;
 817     }
 818
 819     *tcst &= ~mask;
 820     *tcst |= tcstatus;
 821     compute_hflags(cpu);
 822 }
 823
 824 /* Called for updates to CP0_TCStatus.  */
 825 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 826                              target_ulong v)
 827 {
 828     uint32_t status;
 829     uint32_t tcu, tmx, tasid, tksu;
 830     uint32_t mask = ((1 << CP0St_CU3)
 831                        | (1 << CP0St_CU2)
 832                        | (1 << CP0St_CU1)
 833                        | (1 << CP0St_CU0)
 834                        | (1 << CP0St_MX)
 835                        | (3 << CP0St_KSU));
 836
 837     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 838     tmx = (v >> CP0TCSt_TMX) & 0x1;
 839     tasid = v & 0xff;
 840     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 841
 842     status = tcu << CP0St_CU0;
 843     status |= tmx << CP0St_MX;
 844     status |= tksu << CP0St_KSU;
 845
 846     cpu->CP0_Status &= ~mask;
 847     cpu->CP0_Status |= status;
 848
 849     /* Sync the TASID with EntryHi.  */
 850     cpu->CP0_EntryHi &= ~0xff;
 851     cpu->CP0_EntryHi = tasid;
 852
 853     compute_hflags(cpu);
 854 }
 855
 856 /* Called for updates to CP0_EntryHi.  */
 857 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 858 {
 859     int32_t *tcst;
 860     uint32_t asid, v = cpu->CP0_EntryHi;
 861
 862     asid = v & 0xff;
 863
 864     if (tc == cpu->current_tc) {
 865         tcst = &cpu->active_tc.CP0_TCStatus;
 866     } else {
 867         tcst = &cpu->tcs[tc].CP0_TCStatus;
 868     }
 869
 870     *tcst &= ~0xff;
 871     *tcst |= asid;
 872 }
 873
 874 /* CP0 helpers */
 875 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 876 {
 877     return env->mvp->CP0_MVPControl;
 878 }
 879
 880 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 881 {
 882     return env->mvp->CP0_MVPConf0;
 883 }
 884
 885 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 886 {
 887     return env->mvp->CP0_MVPConf1;
 888 }
 889
 890 target_ulong helper_mfc0_random(CPUMIPSState *env)
 891 {
 892     return (int32_t)cpu_mips_get_random(env);
 893 }
 894
 895 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 896 {
 897     return env->active_tc.CP0_TCStatus;
 898 }
 899
 900 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 901 {
 902     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 903     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 904
 905     if (other_tc == other->current_tc)
 906         return other->active_tc.CP0_TCStatus;
 907     else
 908         return other->tcs[other_tc].CP0_TCStatus;
 909 }
 910
 911 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 912 {
 913     return env->active_tc.CP0_TCBind;
 914 }
 915
 916 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 917 {
 918     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 919     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 920
 921     if (other_tc == other->current_tc)
 922         return other->active_tc.CP0_TCBind;
 923     else
 924         return other->tcs[other_tc].CP0_TCBind;
 925 }
 926
 927 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 928 {
 929     return env->active_tc.PC;
 930 }
 931
 932 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 933 {
 934     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 935     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 936
 937     if (other_tc == other->current_tc)
 938         return other->active_tc.PC;
 939     else
 940         return other->tcs[other_tc].PC;
 941 }
 942
 943 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 944 {
 945     return env->active_tc.CP0_TCHalt;
 946 }
 947
 948 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 949 {
 950     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 951     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 952
 953     if (other_tc == other->current_tc)
 954         return other->active_tc.CP0_TCHalt;
 955     else
 956         return other->tcs[other_tc].CP0_TCHalt;
 957 }
 958
 959 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 960 {
 961     return env->active_tc.CP0_TCContext;
 962 }
 963
 964 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 965 {
 966     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 967     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 968
 969     if (other_tc == other->current_tc)
 970         return other->active_tc.CP0_TCContext;
 971     else
 972         return other->tcs[other_tc].CP0_TCContext;
 973 }
 974
 975 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 976 {
 977     return env->active_tc.CP0_TCSchedule;
 978 }
 979
 980 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 981 {
 982     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 983     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 984
 985     if (other_tc == other->current_tc)
 986         return other->active_tc.CP0_TCSchedule;
 987     else
 988         return other->tcs[other_tc].CP0_TCSchedule;
 989 }
 990
 991 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 992 {
 993     return env->active_tc.CP0_TCScheFBack;
 994 }
 995
 996 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 997 {
 998     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 999     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1000
1001     if (other_tc == other->current_tc)
1002         return other->active_tc.CP0_TCScheFBack;
1003     else
1004         return other->tcs[other_tc].CP0_TCScheFBack;
1005 }
1006
1007 target_ulong helper_mfc0_count(CPUMIPSState *env)
1008 {
1009     return (int32_t)cpu_mips_get_count(env);
1010 }
1011
1012 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
1013 {
1014     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1015     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1016
1017     return other->CP0_EntryHi;
1018 }
1019
1020 target_ulong helper_mftc0_cause(CPUMIPSState *env)
1021 {
1022     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1023     int32_t tccause;
1024     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1025
1026     if (other_tc == other->current_tc) {
1027         tccause = other->CP0_Cause;
1028     } else {
1029         tccause = other->CP0_Cause;
1030     }
1031
1032     return tccause;
1033 }
1034
1035 target_ulong helper_mftc0_status(CPUMIPSState *env)
1036 {
1037     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1038     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1039
1040     return other->CP0_Status;
1041 }
1042
1043 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
1044 {
1045     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
1046 }
1047
1048 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1049 {
1050     return (int32_t)env->CP0_WatchLo[sel];
1051 }
1052
1053 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
1054 {
1055     return env->CP0_WatchHi[sel];
1056 }
1057
1058 target_ulong helper_mfc0_debug(CPUMIPSState *env)
1059 {
1060     target_ulong t0 = env->CP0_Debug;
1061     if (env->hflags & MIPS_HFLAG_DM)
1062         t0 |= 1 << CP0DB_DM;
1063
1064     return t0;
1065 }
1066
1067 target_ulong helper_mftc0_debug(CPUMIPSState *env)
1068 {
1069     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1070     int32_t tcstatus;
1071     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1072
1073     if (other_tc == other->current_tc)
1074         tcstatus = other->active_tc.CP0_Debug_tcstatus;
1075     else
1076         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
1077
1078     /* XXX: Might be wrong, check with EJTAG spec. */
1079     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1080             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1081 }
1082
1083 #if defined(TARGET_MIPS64)
1084 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
1085 {
1086     return env->active_tc.PC;
1087 }
1088
1089 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
1090 {
1091     return env->active_tc.CP0_TCHalt;
1092 }
1093
1094 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
1095 {
1096     return env->active_tc.CP0_TCContext;
1097 }
1098
1099 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
1100 {
1101     return env->active_tc.CP0_TCSchedule;
1102 }
1103
1104 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
1105 {
1106     return env->active_tc.CP0_TCScheFBack;
1107 }
1108
1109 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
1110 {
1111     return env->lladdr >> env->CP0_LLAddr_shift;
1112 }
1113
1114 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1115 {
1116     return env->CP0_WatchLo[sel];
1117 }
1118 #endif /* TARGET_MIPS64 */
1119
1120 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1121 {
1122     int num = 1;
1123     unsigned int tmp = env->tlb->nb_tlb;
1124
1125     do {
1126         tmp >>= 1;
1127         num <<= 1;
1128     } while (tmp);
1129     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
1130 }
1131
1132 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1133 {
1134     uint32_t mask = 0;
1135     uint32_t newval;
1136
1137     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1138         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1139                 (1 << CP0MVPCo_EVP);
1140     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1141         mask |= (1 << CP0MVPCo_STLB);
1142     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1143
1144     // TODO: Enable/disable shared TLB, enable/disable VPEs.
1145
1146     env->mvp->CP0_MVPControl = newval;
1147 }
1148
1149 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1150 {
1151     uint32_t mask;
1152     uint32_t newval;
1153
1154     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1155            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1156     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1157
1158     /* Yield scheduler intercept not implemented. */
1159     /* Gating storage scheduler intercept not implemented. */
1160
1161     // TODO: Enable/disable TCs.
1162
1163     env->CP0_VPEControl = newval;
1164 }
1165
1166 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1167 {
1168     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1169     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1170     uint32_t mask;
1171     uint32_t newval;
1172
1173     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1174            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1175     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1176
1177     /* TODO: Enable/disable TCs.  */
1178
1179     other->CP0_VPEControl = newval;
1180 }
1181
1182 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1183 {
1184     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1185     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1186     /* FIXME: Mask away return zero on read bits.  */
1187     return other->CP0_VPEControl;
1188 }
1189
1190 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1191 {
1192     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1193     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1194
1195     return other->CP0_VPEConf0;
1196 }
1197
1198 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1199 {
1200     uint32_t mask = 0;
1201     uint32_t newval;
1202
1203     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1204         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1205             mask |= (0xff << CP0VPEC0_XTC);
1206         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1207     }
1208     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1209
1210     // TODO: TC exclusive handling due to ERL/EXL.
1211
1212     env->CP0_VPEConf0 = newval;
1213 }
1214
1215 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1216 {
1217     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1218     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1219     uint32_t mask = 0;
1220     uint32_t newval;
1221
1222     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1223     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1224
1225     /* TODO: TC exclusive handling due to ERL/EXL.  */
1226     other->CP0_VPEConf0 = newval;
1227 }
1228
1229 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1230 {
1231     uint32_t mask = 0;
1232     uint32_t newval;
1233
1234     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1235         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1236                 (0xff << CP0VPEC1_NCP1);
1237     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1238
1239     /* UDI not implemented. */
1240     /* CP2 not implemented. */
1241
1242     // TODO: Handle FPU (CP1) binding.
1243
1244     env->CP0_VPEConf1 = newval;
1245 }
1246
1247 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1248 {
1249     /* Yield qualifier inputs not implemented. */
1250     env->CP0_YQMask = 0x00000000;
1251 }
1252
1253 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1254 {
1255     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1256 }
1257
1258 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1259 {
1260     /* Large physaddr (PABITS) not implemented */
1261     /* 1k pages not implemented */
1262     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1263 }
1264
1265 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1266 {
1267     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1268     uint32_t newval;
1269
1270     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1271
1272     env->active_tc.CP0_TCStatus = newval;
1273     sync_c0_tcstatus(env, env->current_tc, newval);
1274 }
1275
1276 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1277 {
1278     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1279     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1280
1281     if (other_tc == other->current_tc)
1282         other->active_tc.CP0_TCStatus = arg1;
1283     else
1284         other->tcs[other_tc].CP0_TCStatus = arg1;
1285     sync_c0_tcstatus(other, other_tc, arg1);
1286 }
1287
1288 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1289 {
1290     uint32_t mask = (1 << CP0TCBd_TBE);
1291     uint32_t newval;
1292
1293     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1294         mask |= (1 << CP0TCBd_CurVPE);
1295     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1296     env->active_tc.CP0_TCBind = newval;
1297 }
1298
1299 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1300 {
1301     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1302     uint32_t mask = (1 << CP0TCBd_TBE);
1303     uint32_t newval;
1304     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1305
1306     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1307         mask |= (1 << CP0TCBd_CurVPE);
1308     if (other_tc == other->current_tc) {
1309         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1310         other->active_tc.CP0_TCBind = newval;
1311     } else {
1312         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1313         other->tcs[other_tc].CP0_TCBind = newval;
1314     }
1315 }
1316
1317 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1318 {
1319     env->active_tc.PC = arg1;
1320     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1321     env->lladdr = 0ULL;
1322     /* MIPS16 not implemented. */
1323 }
1324
1325 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1326 {
1327     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1328     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1329
1330     if (other_tc == other->current_tc) {
1331         other->active_tc.PC = arg1;
1332         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1333         other->lladdr = 0ULL;
1334         /* MIPS16 not implemented. */
1335     } else {
1336         other->tcs[other_tc].PC = arg1;
1337         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1338         other->lladdr = 0ULL;
1339         /* MIPS16 not implemented. */
1340     }
1341 }
1342
1343 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1344 {
1345     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1346
1347     // TODO: Halt TC / Restart (if allocated+active) TC.
1348     if (env->active_tc.CP0_TCHalt & 1) {
1349         mips_tc_sleep(env, env->current_tc);
1350     } else {
1351         mips_tc_wake(env, env->current_tc);
1352     }
1353 }
1354
1355 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1356 {
1357     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1358     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1359
1360     // TODO: Halt TC / Restart (if allocated+active) TC.
1361
1362     if (other_tc == other->current_tc)
1363         other->active_tc.CP0_TCHalt = arg1;
1364     else
1365         other->tcs[other_tc].CP0_TCHalt = arg1;
1366
1367     if (arg1 & 1) {
1368         mips_tc_sleep(other, other_tc);
1369     } else {
1370         mips_tc_wake(other, other_tc);
1371     }
1372 }
1373
1374 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1375 {
1376     env->active_tc.CP0_TCContext = arg1;
1377 }
1378
1379 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1380 {
1381     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1382     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1383
1384     if (other_tc == other->current_tc)
1385         other->active_tc.CP0_TCContext = arg1;
1386     else
1387         other->tcs[other_tc].CP0_TCContext = arg1;
1388 }
1389
1390 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1391 {
1392     env->active_tc.CP0_TCSchedule = arg1;
1393 }
1394
1395 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1396 {
1397     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1398     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1399
1400     if (other_tc == other->current_tc)
1401         other->active_tc.CP0_TCSchedule = arg1;
1402     else
1403         other->tcs[other_tc].CP0_TCSchedule = arg1;
1404 }
1405
1406 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1407 {
1408     env->active_tc.CP0_TCScheFBack = arg1;
1409 }
1410
1411 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1412 {
1413     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1414     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1415
1416     if (other_tc == other->current_tc)
1417         other->active_tc.CP0_TCScheFBack = arg1;
1418     else
1419         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1420 }
1421
1422 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1423 {
1424     /* Large physaddr (PABITS) not implemented */
1425     /* 1k pages not implemented */
1426     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1427 }
1428
1429 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1430 {
1431     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1432 }
1433
1434 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1435 {
1436     /* 1k pages not implemented */
1437     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1438 }
1439
1440 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1441 {
1442     /* SmartMIPS not implemented */
1443     /* Large physaddr (PABITS) not implemented */
1444     /* 1k pages not implemented */
1445     env->CP0_PageGrain = 0;
1446 }
1447
1448 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1449 {
1450     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1451 }
1452
1453 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1454 {
1455     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1456 }
1457
1458 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1459 {
1460     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1461 }
1462
1463 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1464 {
1465     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1466 }
1467
1468 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1469 {
1470     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1471 }
1472
1473 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1474 {
1475     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1476 }
1477
1478 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1479 {
1480     env->CP0_HWREna = arg1 & 0x0000000F;
1481 }
1482
1483 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1484 {
1485     cpu_mips_store_count(env, arg1);
1486 }
1487
1488 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1489 {
1490     target_ulong old, val;
1491
1492     /* 1k pages not implemented */
1493     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1494 #if defined(TARGET_MIPS64)
1495     val &= env->SEGMask;
1496 #endif
1497     old = env->CP0_EntryHi;
1498     env->CP0_EntryHi = val;
1499     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1500         sync_c0_entryhi(env, env->current_tc);
1501     }
1502     /* If the ASID changes, flush qemu's TLB.  */
1503     if ((old & 0xFF) != (val & 0xFF))
1504         cpu_mips_tlb_flush(env, 1);
1505 }
1506
1507 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1508 {
1509     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1510     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1511
1512     other->CP0_EntryHi = arg1;
1513     sync_c0_entryhi(other, other_tc);
1514 }
1515
1516 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1517 {
1518     cpu_mips_store_compare(env, arg1);
1519 }
1520
1521 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1522 {
1523     uint32_t val, old;
1524     uint32_t mask = env->CP0_Status_rw_bitmask;
1525
1526     val = arg1 & mask;
1527     old = env->CP0_Status;
1528     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1529     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1530         sync_c0_status(env, env, env->current_tc);
1531     } else {
1532         compute_hflags(env);
1533     }
1534
1535     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1536         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1537                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1538                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1539                 env->CP0_Cause);
1540         switch (env->hflags & MIPS_HFLAG_KSU) {
1541         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1542         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1543         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1544         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1545         }
1546     }
1547 }
1548
1549 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1550 {
1551     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1552     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1553
1554     other->CP0_Status = arg1 & ~0xf1000018;
1555     sync_c0_status(env, other, other_tc);
1556 }
1557
1558 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1559 {
1560     /* vectored interrupts not implemented, no performance counters. */
1561     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1562 }
1563
1564 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1565 {
1566     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1567     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1568 }
1569
1570 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1571 {
1572     uint32_t mask = 0x00C00300;
1573     uint32_t old = cpu->CP0_Cause;
1574     int i;
1575
1576     if (cpu->insn_flags & ISA_MIPS32R2) {
1577         mask |= 1 << CP0Ca_DC;
1578     }
1579
1580     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1581
1582     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1583         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1584             cpu_mips_stop_count(cpu);
1585         } else {
1586             cpu_mips_start_count(cpu);
1587         }
1588     }
1589
1590     /* Set/reset software interrupts */
1591     for (i = 0 ; i < 2 ; i++) {
1592         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1593             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1594         }
1595     }
1596 }
1597
1598 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1599 {
1600     mtc0_cause(env, arg1);
1601 }
1602
1603 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1604 {
1605     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1606     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1607
1608     mtc0_cause(other, arg1);
1609 }
1610
1611 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1612 {
1613     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1614     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1615
1616     return other->CP0_EPC;
1617 }
1618
1619 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1620 {
1621     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1622     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1623
1624     return other->CP0_EBase;
1625 }
1626
1627 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1628 {
1629     /* vectored interrupts not implemented */
1630     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1631 }
1632
1633 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1634 {
1635     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1636     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1637     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1638 }
1639
1640 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1641 {
1642     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1643     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1644
1645     switch (idx) {
1646     case 0: return other->CP0_Config0;
1647     case 1: return other->CP0_Config1;
1648     case 2: return other->CP0_Config2;
1649     case 3: return other->CP0_Config3;
1650     /* 4 and 5 are reserved.  */
1651     case 6: return other->CP0_Config6;
1652     case 7: return other->CP0_Config7;
1653     default:
1654         break;
1655     }
1656     return 0;
1657 }
1658
1659 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1660 {
1661     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1662 }
1663
1664 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1665 {
1666     /* tertiary/secondary caches not implemented */
1667     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1668 }
1669
1670 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1671 {
1672     target_long mask = env->CP0_LLAddr_rw_bitmask;
1673     arg1 = arg1 << env->CP0_LLAddr_shift;
1674     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1675 }
1676
1677 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1678 {
1679     /* Watch exceptions for instructions, data loads, data stores
1680        not implemented. */
1681     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1682 }
1683
1684 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1685 {
1686     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1687     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1688 }
1689
1690 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1691 {
1692     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1693     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1694 }
1695
1696 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1697 {
1698     env->CP0_Framemask = arg1; /* XXX */
1699 }
1700
1701 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1702 {
1703     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1704     if (arg1 & (1 << CP0DB_DM))
1705         env->hflags |= MIPS_HFLAG_DM;
1706     else
1707         env->hflags &= ~MIPS_HFLAG_DM;
1708 }
1709
1710 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1711 {
1712     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1713     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1714     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1715
1716     /* XXX: Might be wrong, check with EJTAG spec. */
1717     if (other_tc == other->current_tc)
1718         other->active_tc.CP0_Debug_tcstatus = val;
1719     else
1720         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1721     other->CP0_Debug = (other->CP0_Debug &
1722                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1723                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1724 }
1725
1726 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1727 {
1728     env->CP0_Performance0 = arg1 & 0x000007ff;
1729 }
1730
1731 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1732 {
1733     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1734 }
1735
1736 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1737 {
1738     env->CP0_DataLo = arg1; /* XXX */
1739 }
1740
1741 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1742 {
1743     env->CP0_TagHi = arg1; /* XXX */
1744 }
1745
1746 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1747 {
1748     env->CP0_DataHi = arg1; /* XXX */
1749 }
1750
1751 /* MIPS MT functions */
1752 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1753 {
1754     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1755     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1756
1757     if (other_tc == other->current_tc)
1758         return other->active_tc.gpr[sel];
1759     else
1760         return other->tcs[other_tc].gpr[sel];
1761 }
1762
1763 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1764 {
1765     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1766     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1767
1768     if (other_tc == other->current_tc)
1769         return other->active_tc.LO[sel];
1770     else
1771         return other->tcs[other_tc].LO[sel];
1772 }
1773
1774 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1775 {
1776     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1777     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1778
1779     if (other_tc == other->current_tc)
1780         return other->active_tc.HI[sel];
1781     else
1782         return other->tcs[other_tc].HI[sel];
1783 }
1784
1785 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1786 {
1787     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1788     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1789
1790     if (other_tc == other->current_tc)
1791         return other->active_tc.ACX[sel];
1792     else
1793         return other->tcs[other_tc].ACX[sel];
1794 }
1795
1796 target_ulong helper_mftdsp(CPUMIPSState *env)
1797 {
1798     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1799     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1800
1801     if (other_tc == other->current_tc)
1802         return other->active_tc.DSPControl;
1803     else
1804         return other->tcs[other_tc].DSPControl;
1805 }
1806
1807 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1808 {
1809     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1810     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1811
1812     if (other_tc == other->current_tc)
1813         other->active_tc.gpr[sel] = arg1;
1814     else
1815         other->tcs[other_tc].gpr[sel] = arg1;
1816 }
1817
1818 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1819 {
1820     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1821     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1822
1823     if (other_tc == other->current_tc)
1824         other->active_tc.LO[sel] = arg1;
1825     else
1826         other->tcs[other_tc].LO[sel] = arg1;
1827 }
1828
1829 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1830 {
1831     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1832     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1833
1834     if (other_tc == other->current_tc)
1835         other->active_tc.HI[sel] = arg1;
1836     else
1837         other->tcs[other_tc].HI[sel] = arg1;
1838 }
1839
1840 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1841 {
1842     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1843     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1844
1845     if (other_tc == other->current_tc)
1846         other->active_tc.ACX[sel] = arg1;
1847     else
1848         other->tcs[other_tc].ACX[sel] = arg1;
1849 }
1850
1851 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1852 {
1853     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1854     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1855
1856     if (other_tc == other->current_tc)
1857         other->active_tc.DSPControl = arg1;
1858     else
1859         other->tcs[other_tc].DSPControl = arg1;
1860 }
1861
1862 /* MIPS MT functions */
1863 target_ulong helper_dmt(void)
1864 {
1865     // TODO
1866      return 0;
1867 }
1868
1869 target_ulong helper_emt(void)
1870 {
1871     // TODO
1872     return 0;
1873 }
1874
1875 target_ulong helper_dvpe(CPUMIPSState *env)
1876 {
1877     CPUMIPSState *other_cpu = first_cpu;
1878     target_ulong prev = env->mvp->CP0_MVPControl;
1879
1880     do {
1881         /* Turn off all VPEs except the one executing the dvpe.  */
1882         if (other_cpu != env) {
1883             other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1884             mips_vpe_sleep(other_cpu);
1885         }
1886         other_cpu = other_cpu->next_cpu;
1887     } while (other_cpu);
1888     return prev;
1889 }
1890
1891 target_ulong helper_evpe(CPUMIPSState *env)
1892 {
1893     CPUMIPSState *other_cpu = first_cpu;
1894     target_ulong prev = env->mvp->CP0_MVPControl;
1895
1896     do {
1897         if (other_cpu != env
1898            /* If the VPE is WFI, don't disturb its sleep.  */
1899            && !mips_vpe_is_wfi(other_cpu)) {
1900             /* Enable the VPE.  */
1901             other_cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1902             mips_vpe_wake(other_cpu); /* And wake it up.  */
1903         }
1904         other_cpu = other_cpu->next_cpu;
1905     } while (other_cpu);
1906     return prev;
1907 }
1908 #endif /* !CONFIG_USER_ONLY */
1909
1910 void helper_fork(target_ulong arg1, target_ulong arg2)
1911 {
1912     // arg1 = rt, arg2 = rs
1913     arg1 = 0;
1914     // TODO: store to TC register
1915 }
1916
1917 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1918 {
1919     target_long arg1 = arg;
1920
1921     if (arg1 < 0) {
1922         /* No scheduling policy implemented. */
1923         if (arg1 != -2) {
1924             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1925                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1926                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1927                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1928                 helper_raise_exception(env, EXCP_THREAD);
1929             }
1930         }
1931     } else if (arg1 == 0) {
1932         if (0 /* TODO: TC underflow */) {
1933             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1934             helper_raise_exception(env, EXCP_THREAD);
1935         } else {
1936             // TODO: Deallocate TC
1937         }
1938     } else if (arg1 > 0) {
1939         /* Yield qualifier inputs not implemented. */
1940         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1941         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1942         helper_raise_exception(env, EXCP_THREAD);
1943     }
1944     return env->CP0_YQMask;
1945 }
1946
1947 #ifndef CONFIG_USER_ONLY
1948 /* TLB management */
1949 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1950 {
1951     /* Flush qemu's TLB and discard all shadowed entries.  */
1952     tlb_flush (env, flush_global);
1953     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1954 }
1955
1956 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1957 {
1958     /* Discard entries from env->tlb[first] onwards.  */
1959     while (env->tlb->tlb_in_use > first) {
1960         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1961     }
1962 }
1963
1964 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1965 {
1966     r4k_tlb_t *tlb;
1967
1968     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1969     tlb = &env->tlb->mmu.r4k.tlb[idx];
1970     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1971 #if defined(TARGET_MIPS64)
1972     tlb->VPN &= env->SEGMask;
1973 #endif
1974     tlb->ASID = env->CP0_EntryHi & 0xFF;
1975     tlb->PageMask = env->CP0_PageMask;
1976     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1977     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1978     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1979     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1980     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1981     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1982     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1983     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1984     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1985 }
1986
1987 void r4k_helper_tlbwi(CPUMIPSState *env)
1988 {
1989     int idx;
1990
1991     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1992
1993     /* Discard cached TLB entries.  We could avoid doing this if the
1994        tlbwi is just upgrading access permissions on the current entry;
1995        that might be a further win.  */
1996     r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
1997
1998     r4k_invalidate_tlb(env, idx, 0);
1999     r4k_fill_tlb(env, idx);
2000 }
2001
2002 void r4k_helper_tlbwr(CPUMIPSState *env)
2003 {
2004     int r = cpu_mips_get_random(env);
2005
2006     r4k_invalidate_tlb(env, r, 1);
2007     r4k_fill_tlb(env, r);
2008 }
2009
2010 void r4k_helper_tlbp(CPUMIPSState *env)
2011 {
2012     r4k_tlb_t *tlb;
2013     target_ulong mask;
2014     target_ulong tag;
2015     target_ulong VPN;
2016     uint8_t ASID;
2017     int i;
2018
2019     ASID = env->CP0_EntryHi & 0xFF;
2020     for (i = 0; i < env->tlb->nb_tlb; i++) {
2021         tlb = &env->tlb->mmu.r4k.tlb[i];
2022         /* 1k pages are not supported. */
2023         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2024         tag = env->CP0_EntryHi & ~mask;
2025         VPN = tlb->VPN & ~mask;
2026         /* Check ASID, virtual page number & size */
2027         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2028             /* TLB match */
2029             env->CP0_Index = i;
2030             break;
2031         }
2032     }
2033     if (i == env->tlb->nb_tlb) {
2034         /* No match.  Discard any shadow entries, if any of them match.  */
2035         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2036             tlb = &env->tlb->mmu.r4k.tlb[i];
2037             /* 1k pages are not supported. */
2038             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2039             tag = env->CP0_EntryHi & ~mask;
2040             VPN = tlb->VPN & ~mask;
2041             /* Check ASID, virtual page number & size */
2042             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2043                 r4k_mips_tlb_flush_extra (env, i);
2044                 break;
2045             }
2046         }
2047
2048         env->CP0_Index |= 0x80000000;
2049     }
2050 }
2051
2052 void r4k_helper_tlbr(CPUMIPSState *env)
2053 {
2054     r4k_tlb_t *tlb;
2055     uint8_t ASID;
2056     int idx;
2057
2058     ASID = env->CP0_EntryHi & 0xFF;
2059     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2060     tlb = &env->tlb->mmu.r4k.tlb[idx];
2061
2062     /* If this will change the current ASID, flush qemu's TLB.  */
2063     if (ASID != tlb->ASID)
2064         cpu_mips_tlb_flush (env, 1);
2065
2066     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2067
2068     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2069     env->CP0_PageMask = tlb->PageMask;
2070     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2071                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
2072     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2073                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
2074 }
2075
2076 void helper_tlbwi(CPUMIPSState *env)
2077 {
2078     env->tlb->helper_tlbwi(env);
2079 }
2080
2081 void helper_tlbwr(CPUMIPSState *env)
2082 {
2083     env->tlb->helper_tlbwr(env);
2084 }
2085
2086 void helper_tlbp(CPUMIPSState *env)
2087 {
2088     env->tlb->helper_tlbp(env);
2089 }
2090
2091 void helper_tlbr(CPUMIPSState *env)
2092 {
2093     env->tlb->helper_tlbr(env);
2094 }
2095
2096 /* Specials */
2097 target_ulong helper_di(CPUMIPSState *env)
2098 {
2099     target_ulong t0 = env->CP0_Status;
2100
2101     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2102     return t0;
2103 }
2104
2105 target_ulong helper_ei(CPUMIPSState *env)
2106 {
2107     target_ulong t0 = env->CP0_Status;
2108
2109     env->CP0_Status = t0 | (1 << CP0St_IE);
2110     return t0;
2111 }
2112
2113 static void debug_pre_eret(CPUMIPSState *env)
2114 {
2115     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2116         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2117                 env->active_tc.PC, env->CP0_EPC);
2118         if (env->CP0_Status & (1 << CP0St_ERL))
2119             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2120         if (env->hflags & MIPS_HFLAG_DM)
2121             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2122         qemu_log("\n");
2123     }
2124 }
2125
2126 static void debug_post_eret(CPUMIPSState *env)
2127 {
2128     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2129         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2130                 env->active_tc.PC, env->CP0_EPC);
2131         if (env->CP0_Status & (1 << CP0St_ERL))
2132             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2133         if (env->hflags & MIPS_HFLAG_DM)
2134             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2135         switch (env->hflags & MIPS_HFLAG_KSU) {
2136         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2137         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2138         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2139         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
2140         }
2141     }
2142 }
2143
2144 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2145 {
2146     env->active_tc.PC = error_pc & ~(target_ulong)1;
2147     if (error_pc & 1) {
2148         env->hflags |= MIPS_HFLAG_M16;
2149     } else {
2150         env->hflags &= ~(MIPS_HFLAG_M16);
2151     }
2152 }
2153
2154 void helper_eret(CPUMIPSState *env)
2155 {
2156     debug_pre_eret(env);
2157     if (env->CP0_Status & (1 << CP0St_ERL)) {
2158         set_pc(env, env->CP0_ErrorEPC);
2159         env->CP0_Status &= ~(1 << CP0St_ERL);
2160     } else {
2161         set_pc(env, env->CP0_EPC);
2162         env->CP0_Status &= ~(1 << CP0St_EXL);
2163     }
2164     compute_hflags(env);
2165     debug_post_eret(env);
2166     env->lladdr = 1;
2167 }
2168
2169 void helper_deret(CPUMIPSState *env)
2170 {
2171     debug_pre_eret(env);
2172     set_pc(env, env->CP0_DEPC);
2173
2174     env->hflags &= MIPS_HFLAG_DM;
2175     compute_hflags(env);
2176     debug_post_eret(env);
2177     env->lladdr = 1;
2178 }
2179 #endif /* !CONFIG_USER_ONLY */
2180
2181 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2182 {
2183     if ((env->hflags & MIPS_HFLAG_CP0) ||
2184         (env->CP0_HWREna & (1 << 0)))
2185         return env->CP0_EBase & 0x3ff;
2186     else
2187         helper_raise_exception(env, EXCP_RI);
2188
2189     return 0;
2190 }
2191
2192 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2193 {
2194     if ((env->hflags & MIPS_HFLAG_CP0) ||
2195         (env->CP0_HWREna & (1 << 1)))
2196         return env->SYNCI_Step;
2197     else
2198         helper_raise_exception(env, EXCP_RI);
2199
2200     return 0;
2201 }
2202
2203 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2204 {
2205     if ((env->hflags & MIPS_HFLAG_CP0) ||
2206         (env->CP0_HWREna & (1 << 2)))
2207         return env->CP0_Count;
2208     else
2209         helper_raise_exception(env, EXCP_RI);
2210
2211     return 0;
2212 }
2213
2214 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2215 {
2216     if ((env->hflags & MIPS_HFLAG_CP0) ||
2217         (env->CP0_HWREna & (1 << 3)))
2218         return env->CCRes;
2219     else
2220         helper_raise_exception(env, EXCP_RI);
2221
2222     return 0;
2223 }
2224
2225 void helper_pmon(CPUMIPSState *env, int function)
2226 {
2227     function /= 2;
2228     switch (function) {
2229     case 2: /* TODO: char inbyte(int waitflag); */
2230         if (env->active_tc.gpr[4] == 0)
2231             env->active_tc.gpr[2] = -1;
2232         /* Fall through */
2233     case 11: /* TODO: char inbyte (void); */
2234         env->active_tc.gpr[2] = -1;
2235         break;
2236     case 3:
2237     case 12:
2238         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2239         break;
2240     case 17:
2241         break;
2242     case 158:
2243         {
2244             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2245             printf("%s", fmt);
2246         }
2247         break;
2248     }
2249 }
2250
2251 void helper_wait(CPUMIPSState *env)
2252 {
2253     env->halted = 1;
2254     cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
2255     helper_raise_exception(env, EXCP_HLT);
2256 }
2257
2258 #if !defined(CONFIG_USER_ONLY)
2259
2260 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2261                                               target_ulong addr, int is_write,
2262                                               int is_user, uintptr_t retaddr);
2263
2264 #define MMUSUFFIX _mmu
2265 #define ALIGNED_ONLY
2266
2267 #define SHIFT 0
2268 #include "softmmu_template.h"
2269
2270 #define SHIFT 1
2271 #include "softmmu_template.h"
2272
2273 #define SHIFT 2
2274 #include "softmmu_template.h"
2275
2276 #define SHIFT 3
2277 #include "softmmu_template.h"
2278
2279 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2280                                 int is_write, int is_user, uintptr_t retaddr)
2281 {
2282     env->CP0_BadVAddr = addr;
2283     do_restore_state(env, retaddr);
2284     helper_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL);
2285 }
2286
2287 void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
2288               uintptr_t retaddr)
2289 {
2290     TranslationBlock *tb;
2291     int ret;
2292
2293     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2294     if (ret) {
2295         if (retaddr) {
2296             /* now we have a real cpu fault */
2297             tb = tb_find_pc(retaddr);
2298             if (tb) {
2299                 /* the PC is inside the translated code. It means that we have
2300                    a virtual CPU fault */
2301                 cpu_restore_state(tb, env, retaddr);
2302             }
2303         }
2304         helper_raise_exception_err(env, env->exception_index, env->error_code);
2305     }
2306 }
2307
2308 void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr,
2309                            int is_write, int is_exec, int unused, int size)
2310 {
2311     if (is_exec)
2312         helper_raise_exception(env, EXCP_IBE);
2313     else
2314         helper_raise_exception(env, EXCP_DBE);
2315 }
2316 #endif /* !CONFIG_USER_ONLY */
2317
2318 /* Complex FPU operations which may need stack space. */
2319
2320 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
2321 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
2322 #define FLOAT_TWO32 make_float32(1 << 30)
2323 #define FLOAT_TWO64 make_float64(1ULL << 62)
2324 #define FLOAT_QNAN32 0x7fbfffff
2325 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
2326 #define FLOAT_SNAN32 0x7fffffff
2327 #define FLOAT_SNAN64 0x7fffffffffffffffULL
2328
2329 /* convert MIPS rounding mode in FCR31 to IEEE library */
2330 static unsigned int ieee_rm[] = {
2331     float_round_nearest_even,
2332     float_round_to_zero,
2333     float_round_up,
2334     float_round_down
2335 };
2336
2337 #define RESTORE_ROUNDING_MODE \
2338     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
2339
2340 #define RESTORE_FLUSH_MODE \
2341     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2342
2343 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2344 {
2345     target_ulong arg1;
2346
2347     switch (reg) {
2348     case 0:
2349         arg1 = (int32_t)env->active_fpu.fcr0;
2350         break;
2351     case 25:
2352         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2353         break;
2354     case 26:
2355         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2356         break;
2357     case 28:
2358         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2359         break;
2360     default:
2361         arg1 = (int32_t)env->active_fpu.fcr31;
2362         break;
2363     }
2364
2365     return arg1;
2366 }
2367
2368 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
2369 {
2370     switch(reg) {
2371     case 25:
2372         if (arg1 & 0xffffff00)
2373             return;
2374         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2375                      ((arg1 & 0x1) << 23);
2376         break;
2377     case 26:
2378         if (arg1 & 0x007c0000)
2379             return;
2380         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2381         break;
2382     case 28:
2383         if (arg1 & 0x007c0000)
2384             return;
2385         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2386                      ((arg1 & 0x4) << 22);
2387         break;
2388     case 31:
2389         if (arg1 & 0x007c0000)
2390             return;
2391         env->active_fpu.fcr31 = arg1;
2392         break;
2393     default:
2394         return;
2395     }
2396     /* set rounding mode */
2397     RESTORE_ROUNDING_MODE;
2398     /* set flush-to-zero mode */
2399     RESTORE_FLUSH_MODE;
2400     set_float_exception_flags(0, &env->active_fpu.fp_status);
2401     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2402         helper_raise_exception(env, EXCP_FPE);
2403 }
2404
2405 static inline int ieee_ex_to_mips(int xcpt)
2406 {
2407     int ret = 0;
2408     if (xcpt) {
2409         if (xcpt & float_flag_invalid) {
2410             ret |= FP_INVALID;
2411         }
2412         if (xcpt & float_flag_overflow) {
2413             ret |= FP_OVERFLOW;
2414         }
2415         if (xcpt & float_flag_underflow) {
2416             ret |= FP_UNDERFLOW;
2417         }
2418         if (xcpt & float_flag_divbyzero) {
2419             ret |= FP_DIV0;
2420         }
2421         if (xcpt & float_flag_inexact) {
2422             ret |= FP_INEXACT;
2423         }
2424     }
2425     return ret;
2426 }
2427
2428 static inline void update_fcr31(CPUMIPSState *env)
2429 {
2430     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2431
2432     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2433     if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
2434         helper_raise_exception(env, EXCP_FPE);
2435     else
2436         UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2437 }
2438
2439 /* Float support.
2440    Single precition routines have a "s" suffix, double precision a
2441    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2442    paired single lower "pl", paired single upper "pu".  */
2443
2444 /* unary operations, modifying fp status  */
2445 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2446 {
2447     return float64_sqrt(fdt0, &env->active_fpu.fp_status);
2448 }
2449
2450 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2451 {
2452     return float32_sqrt(fst0, &env->active_fpu.fp_status);
2453 }
2454
2455 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2456 {
2457     uint64_t fdt2;
2458
2459     set_float_exception_flags(0, &env->active_fpu.fp_status);
2460     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2461     update_fcr31(env);
2462     return fdt2;
2463 }
2464
2465 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2466 {
2467     uint64_t fdt2;
2468
2469     set_float_exception_flags(0, &env->active_fpu.fp_status);
2470     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2471     update_fcr31(env);
2472     return fdt2;
2473 }
2474
2475 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2476 {
2477     uint64_t fdt2;
2478
2479     set_float_exception_flags(0, &env->active_fpu.fp_status);
2480     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2481     update_fcr31(env);
2482     return fdt2;
2483 }
2484
2485 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2486 {
2487     uint64_t dt2;
2488
2489     set_float_exception_flags(0, &env->active_fpu.fp_status);
2490     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2491     update_fcr31(env);
2492     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2493         dt2 = FLOAT_SNAN64;
2494     return dt2;
2495 }
2496
2497 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2498 {
2499     uint64_t dt2;
2500
2501     set_float_exception_flags(0, &env->active_fpu.fp_status);
2502     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2503     update_fcr31(env);
2504     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2505         dt2 = FLOAT_SNAN64;
2506     return dt2;
2507 }
2508
2509 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2510 {
2511     uint32_t fst2;
2512     uint32_t fsth2;
2513
2514     set_float_exception_flags(0, &env->active_fpu.fp_status);
2515     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2516     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2517     update_fcr31(env);
2518     return ((uint64_t)fsth2 << 32) | fst2;
2519 }
2520
2521 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2522 {
2523     uint32_t wt2;
2524     uint32_t wth2;
2525
2526     set_float_exception_flags(0, &env->active_fpu.fp_status);
2527     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2528     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2529     update_fcr31(env);
2530     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
2531         wt2 = FLOAT_SNAN32;
2532         wth2 = FLOAT_SNAN32;
2533     }
2534     return ((uint64_t)wth2 << 32) | wt2;
2535 }
2536
2537 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2538 {
2539     uint32_t fst2;
2540
2541     set_float_exception_flags(0, &env->active_fpu.fp_status);
2542     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2543     update_fcr31(env);
2544     return fst2;
2545 }
2546
2547 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2548 {
2549     uint32_t fst2;
2550
2551     set_float_exception_flags(0, &env->active_fpu.fp_status);
2552     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2553     update_fcr31(env);
2554     return fst2;
2555 }
2556
2557 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2558 {
2559     uint32_t fst2;
2560
2561     set_float_exception_flags(0, &env->active_fpu.fp_status);
2562     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2563     update_fcr31(env);
2564     return fst2;
2565 }
2566
2567 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2568 {
2569     uint32_t wt2;
2570
2571     set_float_exception_flags(0, &env->active_fpu.fp_status);
2572     wt2 = wt0;
2573     update_fcr31(env);
2574     return wt2;
2575 }
2576
2577 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2578 {
2579     uint32_t wt2;
2580
2581     set_float_exception_flags(0, &env->active_fpu.fp_status);
2582     wt2 = wth0;
2583     update_fcr31(env);
2584     return wt2;
2585 }
2586
2587 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2588 {
2589     uint32_t wt2;
2590
2591     set_float_exception_flags(0, &env->active_fpu.fp_status);
2592     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2593     update_fcr31(env);
2594     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2595         wt2 = FLOAT_SNAN32;
2596     return wt2;
2597 }
2598
2599 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2600 {
2601     uint32_t wt2;
2602
2603     set_float_exception_flags(0, &env->active_fpu.fp_status);
2604     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2605     update_fcr31(env);
2606     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2607         wt2 = FLOAT_SNAN32;
2608     return wt2;
2609 }
2610
2611 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2612 {
2613     uint64_t dt2;
2614
2615     set_float_exception_flags(0, &env->active_fpu.fp_status);
2616     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2617     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2618     RESTORE_ROUNDING_MODE;
2619     update_fcr31(env);
2620     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2621         dt2 = FLOAT_SNAN64;
2622     return dt2;
2623 }
2624
2625 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2626 {
2627     uint64_t dt2;
2628
2629     set_float_exception_flags(0, &env->active_fpu.fp_status);
2630     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2631     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2632     RESTORE_ROUNDING_MODE;
2633     update_fcr31(env);
2634     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2635         dt2 = FLOAT_SNAN64;
2636     return dt2;
2637 }
2638
2639 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2640 {
2641     uint32_t wt2;
2642
2643     set_float_exception_flags(0, &env->active_fpu.fp_status);
2644     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2645     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2646     RESTORE_ROUNDING_MODE;
2647     update_fcr31(env);
2648     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2649         wt2 = FLOAT_SNAN32;
2650     return wt2;
2651 }
2652
2653 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2654 {
2655     uint32_t wt2;
2656
2657     set_float_exception_flags(0, &env->active_fpu.fp_status);
2658     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2659     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2660     RESTORE_ROUNDING_MODE;
2661     update_fcr31(env);
2662     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2663         wt2 = FLOAT_SNAN32;
2664     return wt2;
2665 }
2666
2667 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2668 {
2669     uint64_t dt2;
2670
2671     set_float_exception_flags(0, &env->active_fpu.fp_status);
2672     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2673     update_fcr31(env);
2674     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2675         dt2 = FLOAT_SNAN64;
2676     return dt2;
2677 }
2678
2679 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2680 {
2681     uint64_t dt2;
2682
2683     set_float_exception_flags(0, &env->active_fpu.fp_status);
2684     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2685     update_fcr31(env);
2686     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2687         dt2 = FLOAT_SNAN64;
2688     return dt2;
2689 }
2690
2691 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2692 {
2693     uint32_t wt2;
2694
2695     set_float_exception_flags(0, &env->active_fpu.fp_status);
2696     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2697     update_fcr31(env);
2698     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2699         wt2 = FLOAT_SNAN32;
2700     return wt2;
2701 }
2702
2703 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2704 {
2705     uint32_t wt2;
2706
2707     set_float_exception_flags(0, &env->active_fpu.fp_status);
2708     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2709     update_fcr31(env);
2710     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2711         wt2 = FLOAT_SNAN32;
2712     return wt2;
2713 }
2714
2715 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2716 {
2717     uint64_t dt2;
2718
2719     set_float_exception_flags(0, &env->active_fpu.fp_status);
2720     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2721     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2722     RESTORE_ROUNDING_MODE;
2723     update_fcr31(env);
2724     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2725         dt2 = FLOAT_SNAN64;
2726     return dt2;
2727 }
2728
2729 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2730 {
2731     uint64_t dt2;
2732
2733     set_float_exception_flags(0, &env->active_fpu.fp_status);
2734     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2735     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2736     RESTORE_ROUNDING_MODE;
2737     update_fcr31(env);
2738     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2739         dt2 = FLOAT_SNAN64;
2740     return dt2;
2741 }
2742
2743 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2744 {
2745     uint32_t wt2;
2746
2747     set_float_exception_flags(0, &env->active_fpu.fp_status);
2748     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2749     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2750     RESTORE_ROUNDING_MODE;
2751     update_fcr31(env);
2752     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2753         wt2 = FLOAT_SNAN32;
2754     return wt2;
2755 }
2756
2757 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2758 {
2759     uint32_t wt2;
2760
2761     set_float_exception_flags(0, &env->active_fpu.fp_status);
2762     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2763     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2764     RESTORE_ROUNDING_MODE;
2765     update_fcr31(env);
2766     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2767         wt2 = FLOAT_SNAN32;
2768     return wt2;
2769 }
2770
2771 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2772 {
2773     uint64_t dt2;
2774
2775     set_float_exception_flags(0, &env->active_fpu.fp_status);
2776     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2777     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2778     RESTORE_ROUNDING_MODE;
2779     update_fcr31(env);
2780     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2781         dt2 = FLOAT_SNAN64;
2782     return dt2;
2783 }
2784
2785 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2786 {
2787     uint64_t dt2;
2788
2789     set_float_exception_flags(0, &env->active_fpu.fp_status);
2790     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2791     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2792     RESTORE_ROUNDING_MODE;
2793     update_fcr31(env);
2794     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2795         dt2 = FLOAT_SNAN64;
2796     return dt2;
2797 }
2798
2799 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2800 {
2801     uint32_t wt2;
2802
2803     set_float_exception_flags(0, &env->active_fpu.fp_status);
2804     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2805     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2806     RESTORE_ROUNDING_MODE;
2807     update_fcr31(env);
2808     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2809         wt2 = FLOAT_SNAN32;
2810     return wt2;
2811 }
2812
2813 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2814 {
2815     uint32_t wt2;
2816
2817     set_float_exception_flags(0, &env->active_fpu.fp_status);
2818     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2819     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2820     RESTORE_ROUNDING_MODE;
2821     update_fcr31(env);
2822     if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2823         wt2 = FLOAT_SNAN32;
2824     return wt2;
2825 }
2826
2827 /* unary operations, not modifying fp status  */
2828 #define FLOAT_UNOP(name)                                       \
2829 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2830 {                                                              \
2831     return float64_ ## name(fdt0);                             \
2832 }                                                              \
2833 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2834 {                                                              \
2835     return float32_ ## name(fst0);                             \
2836 }                                                              \
2837 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2838 {                                                              \
2839     uint32_t wt0;                                              \
2840     uint32_t wth0;                                             \
2841                                                                \
2842     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2843     wth0 = float32_ ## name(fdt0 >> 32);                       \
2844     return ((uint64_t)wth0 << 32) | wt0;                       \
2845 }
2846 FLOAT_UNOP(abs)
2847 FLOAT_UNOP(chs)
2848 #undef FLOAT_UNOP
2849
2850 /* MIPS specific unary operations */
2851 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2852 {
2853     uint64_t fdt2;
2854
2855     set_float_exception_flags(0, &env->active_fpu.fp_status);
2856     fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2857     update_fcr31(env);
2858     return fdt2;
2859 }
2860
2861 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2862 {
2863     uint32_t fst2;
2864
2865     set_float_exception_flags(0, &env->active_fpu.fp_status);
2866     fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2867     update_fcr31(env);
2868     return fst2;
2869 }
2870
2871 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2872 {
2873     uint64_t fdt2;
2874
2875     set_float_exception_flags(0, &env->active_fpu.fp_status);
2876     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2877     fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2878     update_fcr31(env);
2879     return fdt2;
2880 }
2881
2882 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2883 {
2884     uint32_t fst2;
2885
2886     set_float_exception_flags(0, &env->active_fpu.fp_status);
2887     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2888     fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2889     update_fcr31(env);
2890     return fst2;
2891 }
2892
2893 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2894 {
2895     uint64_t fdt2;
2896
2897     set_float_exception_flags(0, &env->active_fpu.fp_status);
2898     fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2899     update_fcr31(env);
2900     return fdt2;
2901 }
2902
2903 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2904 {
2905     uint32_t fst2;
2906
2907     set_float_exception_flags(0, &env->active_fpu.fp_status);
2908     fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2909     update_fcr31(env);
2910     return fst2;
2911 }
2912
2913 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2914 {
2915     uint32_t fst2;
2916     uint32_t fsth2;
2917
2918     set_float_exception_flags(0, &env->active_fpu.fp_status);
2919     fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2920     fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
2921     update_fcr31(env);
2922     return ((uint64_t)fsth2 << 32) | fst2;
2923 }
2924
2925 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2926 {
2927     uint64_t fdt2;
2928
2929     set_float_exception_flags(0, &env->active_fpu.fp_status);
2930     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2931     fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2932     update_fcr31(env);
2933     return fdt2;
2934 }
2935
2936 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2937 {
2938     uint32_t fst2;
2939
2940     set_float_exception_flags(0, &env->active_fpu.fp_status);
2941     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2942     fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2943     update_fcr31(env);
2944     return fst2;
2945 }
2946
2947 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2948 {
2949     uint32_t fst2;
2950     uint32_t fsth2;
2951
2952     set_float_exception_flags(0, &env->active_fpu.fp_status);
2953     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2954     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2955     fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2956     fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
2957     update_fcr31(env);
2958     return ((uint64_t)fsth2 << 32) | fst2;
2959 }
2960
2961 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2962
2963 /* binary operations */
2964 #define FLOAT_BINOP(name)                                          \
2965 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2966                                      uint64_t fdt0, uint64_t fdt1) \
2967 {                                                                  \
2968     uint64_t dt2;                                                  \
2969                                                                    \
2970     set_float_exception_flags(0, &env->active_fpu.fp_status);            \
2971     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2972     update_fcr31(env);                                             \
2973     if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID)                \
2974         dt2 = FLOAT_QNAN64;                                        \
2975     return dt2;                                                    \
2976 }                                                                  \
2977                                                                    \
2978 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2979                                      uint32_t fst0, uint32_t fst1) \
2980 {                                                                  \
2981     uint32_t wt2;                                                  \
2982                                                                    \
2983     set_float_exception_flags(0, &env->active_fpu.fp_status);            \
2984     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2985     update_fcr31(env);                                             \
2986     if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID)                \
2987         wt2 = FLOAT_QNAN32;                                        \
2988     return wt2;                                                    \
2989 }                                                                  \
2990                                                                    \
2991 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2992                                       uint64_t fdt0,               \
2993                                       uint64_t fdt1)               \
2994 {                                                                  \
2995     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2996     uint32_t fsth0 = fdt0 >> 32;                                   \
2997     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2998     uint32_t fsth1 = fdt1 >> 32;                                   \
2999     uint32_t wt2;                                                  \
3000     uint32_t wth2;                                                 \
3001                                                                    \
3002     set_float_exception_flags(0, &env->active_fpu.fp_status);            \
3003     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3004     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3005     update_fcr31(env);                                             \
3006     if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) {              \
3007         wt2 = FLOAT_QNAN32;                                        \
3008         wth2 = FLOAT_QNAN32;                                       \
3009     }                                                              \
3010     return ((uint64_t)wth2 << 32) | wt2;                           \
3011 }
3012
3013 FLOAT_BINOP(add)
3014 FLOAT_BINOP(sub)
3015 FLOAT_BINOP(mul)
3016 FLOAT_BINOP(div)
3017 #undef FLOAT_BINOP
3018
3019 /* ternary operations */
3020 #define FLOAT_TERNOP(name1, name2)                                        \
3021 uint64_t helper_float_ ## name1 ## name2 ## _d(CPUMIPSState *env,         \
3022                                                uint64_t fdt0,             \
3023                                                uint64_t fdt1,             \
3024                                                uint64_t fdt2)             \
3025 {                                                                         \
3026     fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status);          \
3027     return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status);          \
3028 }                                                                         \
3029                                                                           \
3030 uint32_t helper_float_ ## name1 ## name2 ## _s(CPUMIPSState *env,         \
3031                                                uint32_t fst0,             \
3032                                                uint32_t fst1,             \
3033                                                uint32_t fst2)             \
3034 {                                                                         \
3035     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
3036     return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
3037 }                                                                         \
3038                                                                           \
3039 uint64_t helper_float_ ## name1 ## name2 ## _ps(CPUMIPSState *env,        \
3040                                                 uint64_t fdt0,            \
3041                                                 uint64_t fdt1,            \
3042                                                 uint64_t fdt2)            \
3043 {                                                                         \
3044     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                                    \
3045     uint32_t fsth0 = fdt0 >> 32;                                          \
3046     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                                    \
3047     uint32_t fsth1 = fdt1 >> 32;                                          \
3048     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                                    \
3049     uint32_t fsth2 = fdt2 >> 32;                                          \
3050                                                                           \
3051     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
3052     fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status);       \
3053     fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
3054     fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status);       \
3055     return ((uint64_t)fsth2 << 32) | fst2;                                \
3056 }
3057
3058 FLOAT_TERNOP(mul, add)
3059 FLOAT_TERNOP(mul, sub)
3060 #undef FLOAT_TERNOP
3061
3062 /* negated ternary operations */
3063 #define FLOAT_NTERNOP(name1, name2)                                       \
3064 uint64_t helper_float_n ## name1 ## name2 ## _d(CPUMIPSState *env,        \
3065                                                 uint64_t fdt0,            \
3066                                                 uint64_t fdt1,            \
3067                                                 uint64_t fdt2)            \
3068 {                                                                         \
3069     fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status);          \
3070     fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status);          \
3071     return float64_chs(fdt2);                                             \
3072 }                                                                         \
3073                                                                           \
3074 uint32_t helper_float_n ## name1 ## name2 ## _s(CPUMIPSState *env,        \
3075                                                 uint32_t fst0,            \
3076                                                 uint32_t fst1,            \
3077                                                 uint32_t fst2)            \
3078 {                                                                         \
3079     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
3080     fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
3081     return float32_chs(fst2);                                             \
3082 }                                                                         \
3083                                                                           \
3084 uint64_t helper_float_n ## name1 ## name2 ## _ps(CPUMIPSState *env,       \
3085                                                  uint64_t fdt0,           \
3086                                                  uint64_t fdt1,           \
3087                                                  uint64_t fdt2)           \
3088 {                                                                         \
3089     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                                    \
3090     uint32_t fsth0 = fdt0 >> 32;                                          \
3091     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                                    \
3092     uint32_t fsth1 = fdt1 >> 32;                                          \
3093     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                                    \
3094     uint32_t fsth2 = fdt2 >> 32;                                          \
3095                                                                           \
3096     fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status);          \
3097     fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status);       \
3098     fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status);          \
3099     fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status);       \
3100     fst2 = float32_chs(fst2);                                             \
3101     fsth2 = float32_chs(fsth2);                                           \
3102     return ((uint64_t)fsth2 << 32) | fst2;                                \
3103 }
3104
3105 FLOAT_NTERNOP(mul, add)
3106 FLOAT_NTERNOP(mul, sub)
3107 #undef FLOAT_NTERNOP
3108
3109 /* MIPS specific binary operations */
3110 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3111 {
3112     set_float_exception_flags(0, &env->active_fpu.fp_status);
3113     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3114     fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
3115     update_fcr31(env);
3116     return fdt2;
3117 }
3118
3119 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3120 {
3121     set_float_exception_flags(0, &env->active_fpu.fp_status);
3122     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3123     fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
3124     update_fcr31(env);
3125     return fst2;
3126 }
3127
3128 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3129 {
3130     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3131     uint32_t fsth0 = fdt0 >> 32;
3132     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3133     uint32_t fsth2 = fdt2 >> 32;
3134
3135     set_float_exception_flags(0, &env->active_fpu.fp_status);
3136     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3137     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3138     fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
3139     fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
3140     update_fcr31(env);
3141     return ((uint64_t)fsth2 << 32) | fst2;
3142 }
3143
3144 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3145 {
3146     set_float_exception_flags(0, &env->active_fpu.fp_status);
3147     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3148     fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
3149     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3150     update_fcr31(env);
3151     return fdt2;
3152 }
3153
3154 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3155 {
3156     set_float_exception_flags(0, &env->active_fpu.fp_status);
3157     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3158     fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
3159     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3160     update_fcr31(env);
3161     return fst2;
3162 }
3163
3164 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3165 {
3166     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3167     uint32_t fsth0 = fdt0 >> 32;
3168     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3169     uint32_t fsth2 = fdt2 >> 32;
3170
3171     set_float_exception_flags(0, &env->active_fpu.fp_status);
3172     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3173     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3174     fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
3175     fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
3176     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3177     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3178     update_fcr31(env);
3179     return ((uint64_t)fsth2 << 32) | fst2;
3180 }
3181
3182 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3183 {
3184     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3185     uint32_t fsth0 = fdt0 >> 32;
3186     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3187     uint32_t fsth1 = fdt1 >> 32;
3188     uint32_t fst2;
3189     uint32_t fsth2;
3190
3191     set_float_exception_flags(0, &env->active_fpu.fp_status);
3192     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3193     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3194     update_fcr31(env);
3195     return ((uint64_t)fsth2 << 32) | fst2;
3196 }
3197
3198 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3199 {
3200     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3201     uint32_t fsth0 = fdt0 >> 32;
3202     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3203     uint32_t fsth1 = fdt1 >> 32;
3204     uint32_t fst2;
3205     uint32_t fsth2;
3206
3207     set_float_exception_flags(0, &env->active_fpu.fp_status);
3208     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3209     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3210     update_fcr31(env);
3211     return ((uint64_t)fsth2 << 32) | fst2;
3212 }
3213
3214 /* compare operations */
3215 #define FOP_COND_D(op, cond)                                   \
3216 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3217                          uint64_t fdt1, int cc)                \
3218 {                                                              \
3219     int c;                                                     \
3220     set_float_exception_flags(0, &env->active_fpu.fp_status);  \
3221     c = cond;                                                  \
3222     update_fcr31(env);                                         \
3223     if (c)                                                     \
3224         SET_FP_COND(cc, env->active_fpu);                      \
3225     else                                                       \
3226         CLEAR_FP_COND(cc, env->active_fpu);                    \
3227 }                                                              \
3228 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3229                             uint64_t fdt1, int cc)             \
3230 {                                                              \
3231     int c;                                                     \
3232     set_float_exception_flags(0, &env->active_fpu.fp_status);  \
3233     fdt0 = float64_abs(fdt0);                                  \
3234     fdt1 = float64_abs(fdt1);                                  \
3235     c = cond;                                                  \
3236     update_fcr31(env);                                         \
3237     if (c)                                                     \
3238         SET_FP_COND(cc, env->active_fpu);                      \
3239     else                                                       \
3240         CLEAR_FP_COND(cc, env->active_fpu);                    \
3241 }
3242
3243 /* NOTE: the comma operator will make "cond" to eval to false,
3244  * but float64_unordered_quiet() is still called. */
3245 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3246 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3247 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3248 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3249 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3250 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3251 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3252 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3253 /* NOTE: the comma operator will make "cond" to eval to false,
3254  * but float64_unordered() is still called. */
3255 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3256 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3257 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3258 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3259 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3260 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3261 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3262 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3263
3264 #define FOP_COND_S(op, cond)                                   \
3265 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3266                          uint32_t fst1, int cc)                \
3267 {                                                              \
3268     int c;                                                     \
3269     set_float_exception_flags(0, &env->active_fpu.fp_status);  \
3270     c = cond;                                                  \
3271     update_fcr31(env);                                         \
3272     if (c)                                                     \
3273         SET_FP_COND(cc, env->active_fpu);                      \
3274     else                                                       \
3275         CLEAR_FP_COND(cc, env->active_fpu);                    \
3276 }                                                              \
3277 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3278                             uint32_t fst1, int cc)             \
3279 {                                                              \
3280     int c;                                                     \
3281     set_float_exception_flags(0, &env->active_fpu.fp_status);  \
3282     fst0 = float32_abs(fst0);                                  \
3283     fst1 = float32_abs(fst1);                                  \
3284     c = cond;                                                  \
3285     update_fcr31(env);                                         \
3286     if (c)                                                     \
3287         SET_FP_COND(cc, env->active_fpu);                      \
3288     else                                                       \
3289         CLEAR_FP_COND(cc, env->active_fpu);                    \
3290 }
3291
3292 /* NOTE: the comma operator will make "cond" to eval to false,
3293  * but float32_unordered_quiet() is still called. */
3294 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3295 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3296 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3297 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3298 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3299 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3300 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3301 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3302 /* NOTE: the comma operator will make "cond" to eval to false,
3303  * but float32_unordered() is still called. */
3304 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3305 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3306 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3307 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3308 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3309 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3310 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3311 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3312
3313 #define FOP_COND_PS(op, condl, condh)                           \
3314 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3315                           uint64_t fdt1, int cc)                \
3316 {                                                               \
3317     uint32_t fst0, fsth0, fst1, fsth1;                          \
3318     int ch, cl;                                                 \
3319     set_float_exception_flags(0, &env->active_fpu.fp_status);   \
3320     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3321     fsth0 = fdt0 >> 32;                                         \
3322     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3323     fsth1 = fdt1 >> 32;                                         \
3324     cl = condl;                                                 \
3325     ch = condh;                                                 \
3326     update_fcr31(env);                                          \
3327     if (cl)                                                     \
3328         SET_FP_COND(cc, env->active_fpu);                       \
3329     else                                                        \
3330         CLEAR_FP_COND(cc, env->active_fpu);                     \
3331     if (ch)                                                     \
3332         SET_FP_COND(cc + 1, env->active_fpu);                   \
3333     else                                                        \
3334         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3335 }                                                               \
3336 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3337                              uint64_t fdt1, int cc)             \
3338 {                                                               \
3339     uint32_t fst0, fsth0, fst1, fsth1;                          \
3340     int ch, cl;                                                 \
3341     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3342     fsth0 = float32_abs(fdt0 >> 32);                            \
3343     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3344     fsth1 = float32_abs(fdt1 >> 32);                            \
3345     cl = condl;                                                 \
3346     ch = condh;                                                 \
3347     update_fcr31(env);                                          \
3348     if (cl)                                                     \
3349         SET_FP_COND(cc, env->active_fpu);                       \
3350     else                                                        \
3351         CLEAR_FP_COND(cc, env->active_fpu);                     \
3352     if (ch)                                                     \
3353         SET_FP_COND(cc + 1, env->active_fpu);                   \
3354     else                                                        \
3355         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3356 }
3357
3358 /* NOTE: the comma operator will make "cond" to eval to false,
3359  * but float32_unordered_quiet() is still called. */
3360 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3361                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3362 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3363                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3364 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3365                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3366 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3367                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3368 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3369                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3370 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3371                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3372 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3373                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3374 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3375                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3376 /* NOTE: the comma operator will make "cond" to eval to false,
3377  * but float32_unordered() is still called. */
3378 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3379                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3380 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3381                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3382 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3383                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3384 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3385                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3386 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3387                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3388 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3389                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3390 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3391                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3392 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3393                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))