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pci-assign: Fix multifunction support
[qemu-kvm.git] / hw / device-assignment.c
blob7f4a5ecf282c297ab0973ab4de1ea054c3befbcd
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 *
18 * Assign a PCI device from the host to a guest VM.
19 *
20 * Adapted for KVM by Qumranet.
21 *
22 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
23 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
24 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
25 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
26 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
27 */
28 #include <stdio.h>
29 #include <unistd.h>
30 #include <sys/io.h>
31 #include <sys/types.h>
32 #include <sys/stat.h>
33 #include "qemu-kvm.h"
34 #include "hw.h"
35 #include "pc.h"
36 #include "qemu-error.h"
37 #include "console.h"
38 #include "device-assignment.h"
39 #include "loader.h"
40 #include "monitor.h"
41 #include "range.h"
42 #include "sysemu.h"
43
44 #define MSIX_PAGE_SIZE 0x1000
45
46 /* From linux/ioport.h */
47 #define IORESOURCE_IO 0x00000100 /* Resource type */
48 #define IORESOURCE_MEM 0x00000200
49 #define IORESOURCE_IRQ 0x00000400
50 #define IORESOURCE_DMA 0x00000800
51 #define IORESOURCE_PREFETCH 0x00002000 /* No side effects */
52
53 /* #define DEVICE_ASSIGNMENT_DEBUG 1 */
54
55 #ifdef DEVICE_ASSIGNMENT_DEBUG
56 #define DEBUG(fmt, ...) \
57 do { \
58 fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
59 } while (0)
60 #else
61 #define DEBUG(fmt, ...) do { } while(0)
62 #endif
63
64 static void assigned_dev_load_option_rom(AssignedDevice *dev);
65
66 static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev);
67
68 static uint64_t assigned_dev_ioport_rw(AssignedDevRegion *dev_region,
69 target_phys_addr_t addr, int size,
70 uint64_t *data)
71 {
72 uint64_t val = 0;
73 int fd = dev_region->region->resource_fd;
74
75 if (fd >= 0) {
76 if (data) {
77 DEBUG("pwrite data=%x, size=%d, e_phys=%x, addr=%x\n",
78 *data, size, addr, addr);
79 if (pwrite(fd, data, size, addr) != size) {
80 fprintf(stderr, "%s - pwrite failed %s\n",
81 __func__, strerror(errno));
82 }
83 } else {
84 if (pread(fd, &val, size, addr) != size) {
85 fprintf(stderr, "%s - pread failed %s\n",
86 __func__, strerror(errno));
87 val = (1UL << (size * 8)) - 1;
88 }
89 DEBUG("pread val=%x, size=%d, e_phys=%x, addr=%x\n",
90 val, size, addr, addr);
91 }
92 } else {
93 uint32_t port = addr + dev_region->u.r_baseport;
94
95 if (data) {
96 DEBUG("out data=%x, size=%d, e_phys=%x, host=%x\n",
97 *data, size, addr, port);
98 switch (size) {
99 case 1:
100 outb(*data, port);
101 break;
102 case 2:
103 outw(*data, port);
104 break;
105 case 4:
106 outl(*data, port);
107 break;
108 }
109 } else {
110 switch (size) {
111 case 1:
112 val = inb(port);
113 break;
114 case 2:
115 val = inw(port);
116 break;
117 case 4:
118 val = inl(port);
119 break;
120 }
121 DEBUG("in data=%x, size=%d, e_phys=%x, host=%x\n",
122 val, size, addr, port);
123 }
124 }
125 return val;
126 }
127
128 static void assigned_dev_ioport_write(void *opaque, target_phys_addr_t addr,
129 uint64_t data, unsigned size)
130 {
131 assigned_dev_ioport_rw(opaque, addr, size, &data);
132 }
133
134 static uint64_t assigned_dev_ioport_read(void *opaque,
135 target_phys_addr_t addr, unsigned size)
136 {
137 return assigned_dev_ioport_rw(opaque, addr, size, NULL);
138 }
139
140 static uint32_t slow_bar_readb(void *opaque, target_phys_addr_t addr)
141 {
142 AssignedDevRegion *d = opaque;
143 uint8_t *in = d->u.r_virtbase + addr;
144 uint32_t r;
145
146 r = *in;
147 DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r);
148
149 return r;
150 }
151
152 static uint32_t slow_bar_readw(void *opaque, target_phys_addr_t addr)
153 {
154 AssignedDevRegion *d = opaque;
155 uint16_t *in = d->u.r_virtbase + addr;
156 uint32_t r;
157
158 r = *in;
159 DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r);
160
161 return r;
162 }
163
164 static uint32_t slow_bar_readl(void *opaque, target_phys_addr_t addr)
165 {
166 AssignedDevRegion *d = opaque;
167 uint32_t *in = d->u.r_virtbase + addr;
168 uint32_t r;
169
170 r = *in;
171 DEBUG("slow_bar_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, r);
172
173 return r;
174 }
175
176 static void slow_bar_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
177 {
178 AssignedDevRegion *d = opaque;
179 uint8_t *out = d->u.r_virtbase + addr;
180
181 DEBUG("slow_bar_writeb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr, val);
182 *out = val;
183 }
184
185 static void slow_bar_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
186 {
187 AssignedDevRegion *d = opaque;
188 uint16_t *out = d->u.r_virtbase + addr;
189
190 DEBUG("slow_bar_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr, val);
191 *out = val;
192 }
193
194 static void slow_bar_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
195 {
196 AssignedDevRegion *d = opaque;
197 uint32_t *out = d->u.r_virtbase + addr;
198
199 DEBUG("slow_bar_writel addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr, val);
200 *out = val;
201 }
202
203 static const MemoryRegionOps slow_bar_ops = {
204 .old_mmio = {
205 .read = { slow_bar_readb, slow_bar_readw, slow_bar_readl, },
206 .write = { slow_bar_writeb, slow_bar_writew, slow_bar_writel, },
207 },
208 .endianness = DEVICE_NATIVE_ENDIAN,
209 };
210
211 static void assigned_dev_iomem_setup(PCIDevice *pci_dev, int region_num,
212 pcibus_t e_size)
213 {
214 AssignedDevice *r_dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
215 AssignedDevRegion *region = &r_dev->v_addrs[region_num];
216 PCIRegion *real_region = &r_dev->real_device.regions[region_num];
217
218 if (e_size > 0) {
219 memory_region_init(&region->container, "assigned-dev-container",
220 e_size);
221 memory_region_add_subregion(&region->container, 0, &region->real_iomem);
222
223 /* deal with MSI-X MMIO page */
224 if (real_region->base_addr <= r_dev->msix_table_addr &&
225 real_region->base_addr + real_region->size >
226 r_dev->msix_table_addr) {
227 int offset = r_dev->msix_table_addr - real_region->base_addr;
228
229 memory_region_add_subregion_overlap(&region->container,
230 offset,
231 &r_dev->mmio,
232 1);
233 }
234 }
235 }
236
237 static const MemoryRegionOps assigned_dev_ioport_ops = {
238 .read = assigned_dev_ioport_read,
239 .write = assigned_dev_ioport_write,
240 .endianness = DEVICE_NATIVE_ENDIAN,
241 };
242
243 static void assigned_dev_ioport_setup(PCIDevice *pci_dev, int region_num,
244 pcibus_t size)
245 {
246 AssignedDevice *r_dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
247 AssignedDevRegion *region = &r_dev->v_addrs[region_num];
248 int r;
249
250 region->e_size = size;
251
252 if (region->region->resource_fd < 0) {
253 r = kvm_add_ioport_region(region->u.r_baseport, region->r_size,
254 pci_dev->qdev.hotplugged);
255 if (r < 0) {
256 fprintf(stderr, "%s: failed to enable ioport access (%m)\n",
257 __func__);
258 }
259 }
260 memory_region_init(&region->container, "assigned-dev-container", size);
261 memory_region_init_io(&region->real_iomem, &assigned_dev_ioport_ops,
262 r_dev->v_addrs + region_num,
263 "assigned-dev-iomem", size);
264 memory_region_add_subregion(&region->container, 0, &region->real_iomem);
265 }
266
267 static uint32_t assigned_dev_pci_read(PCIDevice *d, int pos, int len)
268 {
269 AssignedDevice *pci_dev = DO_UPCAST(AssignedDevice, dev, d);
270 uint32_t val;
271 ssize_t ret;
272 int fd = pci_dev->real_device.config_fd;
273
274 again:
275 ret = pread(fd, &val, len, pos);
276 if (ret != len) {
277 if ((ret < 0) && (errno == EINTR || errno == EAGAIN))
278 goto again;
279
280 fprintf(stderr, "%s: pread failed, ret = %zd errno = %d\n",
281 __func__, ret, errno);
282
283 exit(1);
284 }
285
286 return val;
287 }
288
289 static uint8_t assigned_dev_pci_read_byte(PCIDevice *d, int pos)
290 {
291 return (uint8_t)assigned_dev_pci_read(d, pos, 1);
292 }
293
294 static void assigned_dev_pci_write(PCIDevice *d, int pos, uint32_t val, int len)
295 {
296 AssignedDevice *pci_dev = DO_UPCAST(AssignedDevice, dev, d);
297 ssize_t ret;
298 int fd = pci_dev->real_device.config_fd;
299
300 again:
301 ret = pwrite(fd, &val, len, pos);
302 if (ret != len) {
303 if ((ret < 0) && (errno == EINTR || errno == EAGAIN))
304 goto again;
305
306 fprintf(stderr, "%s: pwrite failed, ret = %zd errno = %d\n",
307 __func__, ret, errno);
308
309 exit(1);
310 }
311
312 return;
313 }
314
315 static void assigned_dev_emulate_config_read(AssignedDevice *dev,
316 uint32_t offset, uint32_t len)
317 {
318 memset(dev->emulate_config_read + offset, 0xff, len);
319 }
320
321 static void assigned_dev_direct_config_read(AssignedDevice *dev,
322 uint32_t offset, uint32_t len)
323 {
324 memset(dev->emulate_config_read + offset, 0, len);
325 }
326
327 static void assigned_dev_direct_config_write(AssignedDevice *dev,
328 uint32_t offset, uint32_t len)
329 {
330 memset(dev->emulate_config_write + offset, 0, len);
331 }
332
333 static uint8_t pci_find_cap_offset(PCIDevice *d, uint8_t cap, uint8_t start)
334 {
335 int id;
336 int max_cap = 48;
337 int pos = start ? start : PCI_CAPABILITY_LIST;
338 int status;
339
340 status = assigned_dev_pci_read_byte(d, PCI_STATUS);
341 if ((status & PCI_STATUS_CAP_LIST) == 0)
342 return 0;
343
344 while (max_cap--) {
345 pos = assigned_dev_pci_read_byte(d, pos);
346 if (pos < 0x40)
347 break;
348
349 pos &= ~3;
350 id = assigned_dev_pci_read_byte(d, pos + PCI_CAP_LIST_ID);
351
352 if (id == 0xff)
353 break;
354 if (id == cap)
355 return pos;
356
357 pos += PCI_CAP_LIST_NEXT;
358 }
359 return 0;
360 }
361
362 static int assigned_dev_register_regions(PCIRegion *io_regions,
363 unsigned long regions_num,
364 AssignedDevice *pci_dev)
365 {
366 uint32_t i;
367 PCIRegion *cur_region = io_regions;
368
369 for (i = 0; i < regions_num; i++, cur_region++) {
370 if (!cur_region->valid)
371 continue;
372 pci_dev->v_addrs[i].num = i;
373
374 /* handle memory io regions */
375 if (cur_region->type & IORESOURCE_MEM) {
376 int t = cur_region->type & IORESOURCE_PREFETCH
377 ? PCI_BASE_ADDRESS_MEM_PREFETCH
378 : PCI_BASE_ADDRESS_SPACE_MEMORY;
379
380 /* map physical memory */
381 pci_dev->v_addrs[i].u.r_virtbase = mmap(NULL, cur_region->size,
382 PROT_WRITE | PROT_READ,
383 MAP_SHARED,
384 cur_region->resource_fd,
385 (off_t)0);
386
387 if (pci_dev->v_addrs[i].u.r_virtbase == MAP_FAILED) {
388 pci_dev->v_addrs[i].u.r_virtbase = NULL;
389 fprintf(stderr, "%s: Error: Couldn't mmap 0x%x!"
390 "\n", __func__,
391 (uint32_t) (cur_region->base_addr));
392 return -1;
393 }
394
395 pci_dev->v_addrs[i].r_size = cur_region->size;
396 pci_dev->v_addrs[i].e_size = 0;
397
398 /* add offset */
399 pci_dev->v_addrs[i].u.r_virtbase +=
400 (cur_region->base_addr & 0xFFF);
401
402 if (cur_region->size & 0xFFF) {
403 fprintf(stderr, "PCI region %d at address 0x%llx "
404 "has size 0x%x, which is not a multiple of 4K. "
405 "You might experience some performance hit "
406 "due to that.\n",
407 i, (unsigned long long)cur_region->base_addr,
408 cur_region->size);
409 memory_region_init_io(&pci_dev->v_addrs[i].real_iomem,
410 &slow_bar_ops, &pci_dev->v_addrs[i],
411 "assigned-dev-slow-bar",
412 cur_region->size);
413 } else {
414 void *virtbase = pci_dev->v_addrs[i].u.r_virtbase;
415 char name[32];
416 snprintf(name, sizeof(name), "%s.bar%d",
417 pci_dev->dev.qdev.info->name, i);
418 memory_region_init_ram_ptr(&pci_dev->v_addrs[i].real_iomem,
419 name, cur_region->size,
420 virtbase);
421 vmstate_register_ram(&pci_dev->v_addrs[i].real_iomem,
422 &pci_dev->dev.qdev);
423 }
424
425 assigned_dev_iomem_setup(&pci_dev->dev, i, cur_region->size);
426 pci_register_bar((PCIDevice *) pci_dev, i, t,
427 &pci_dev->v_addrs[i].container);
428 continue;
429 } else {
430 /* handle port io regions */
431 uint32_t val;
432 int ret;
433
434 /* Test kernel support for ioport resource read/write. Old
435 * kernels return EIO. New kernels only allow 1/2/4 byte reads
436 * so should return EINVAL for a 3 byte read */
437 ret = pread(pci_dev->v_addrs[i].region->resource_fd, &val, 3, 0);
438 if (ret >= 0) {
439 fprintf(stderr, "Unexpected return from I/O port read: %d\n",
440 ret);
441 abort();
442 } else if (errno != EINVAL) {
443 fprintf(stderr, "Using raw in/out ioport access (sysfs - %s)\n",
444 strerror(errno));
445 close(pci_dev->v_addrs[i].region->resource_fd);
446 pci_dev->v_addrs[i].region->resource_fd = -1;
447 }
448
449 pci_dev->v_addrs[i].u.r_baseport = cur_region->base_addr;
450 pci_dev->v_addrs[i].r_size = cur_region->size;
451 pci_dev->v_addrs[i].e_size = 0;
452
453 assigned_dev_ioport_setup(&pci_dev->dev, i, cur_region->size);
454 pci_register_bar((PCIDevice *) pci_dev, i,
455 PCI_BASE_ADDRESS_SPACE_IO,
456 &pci_dev->v_addrs[i].container);
457 }
458 }
459
460 /* success */
461 return 0;
462 }
463
464 static int get_real_id(const char *devpath, const char *idname, uint16_t *val)
465 {
466 FILE *f;
467 char name[128];
468 long id;
469
470 snprintf(name, sizeof(name), "%s%s", devpath, idname);
471 f = fopen(name, "r");
472 if (f == NULL) {
473 fprintf(stderr, "%s: %s: %m\n", __func__, name);
474 return -1;
475 }
476 if (fscanf(f, "%li\n", &id) == 1) {
477 *val = id;
478 } else {
479 return -1;
480 }
481 fclose(f);
482
483 return 0;
484 }
485
486 static int get_real_vendor_id(const char *devpath, uint16_t *val)
487 {
488 return get_real_id(devpath, "vendor", val);
489 }
490
491 static int get_real_device_id(const char *devpath, uint16_t *val)
492 {
493 return get_real_id(devpath, "device", val);
494 }
495
496 static int get_real_device(AssignedDevice *pci_dev, uint16_t r_seg,
497 uint8_t r_bus, uint8_t r_dev, uint8_t r_func)
498 {
499 char dir[128], name[128];
500 int fd, r = 0, v;
501 FILE *f;
502 unsigned long long start, end, size, flags;
503 uint16_t id;
504 struct stat statbuf;
505 PCIRegion *rp;
506 PCIDevRegions *dev = &pci_dev->real_device;
507
508 dev->region_number = 0;
509
510 snprintf(dir, sizeof(dir), "/sys/bus/pci/devices/%04x:%02x:%02x.%x/",
511 r_seg, r_bus, r_dev, r_func);
512
513 snprintf(name, sizeof(name), "%sconfig", dir);
514
515 if (pci_dev->configfd_name && *pci_dev->configfd_name) {
516 if (qemu_isdigit(pci_dev->configfd_name[0])) {
517 dev->config_fd = strtol(pci_dev->configfd_name, NULL, 0);
518 } else {
519 dev->config_fd = monitor_get_fd(cur_mon, pci_dev->configfd_name);
520 if (dev->config_fd < 0) {
521 fprintf(stderr, "%s: (%s) unkown\n", __func__,
522 pci_dev->configfd_name);
523 return 1;
524 }
525 }
526 } else {
527 dev->config_fd = open(name, O_RDWR);
528
529 if (dev->config_fd == -1) {
530 fprintf(stderr, "%s: %s: %m\n", __func__, name);
531 return 1;
532 }
533 }
534 again:
535 r = read(dev->config_fd, pci_dev->dev.config,
536 pci_config_size(&pci_dev->dev));
537 if (r < 0) {
538 if (errno == EINTR || errno == EAGAIN)
539 goto again;
540 fprintf(stderr, "%s: read failed, errno = %d\n", __func__, errno);
541 }
542
543 /* Restore or clear multifunction, this is always controlled by qemu */
544 if (pci_dev->dev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
545 pci_dev->dev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
546 } else {
547 pci_dev->dev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
548 }
549
550 /* Clear host resource mapping info. If we choose not to register a
551 * BAR, such as might be the case with the option ROM, we can get
552 * confusing, unwritable, residual addresses from the host here. */
553 memset(&pci_dev->dev.config[PCI_BASE_ADDRESS_0], 0, 24);
554 memset(&pci_dev->dev.config[PCI_ROM_ADDRESS], 0, 4);
555
556 snprintf(name, sizeof(name), "%sresource", dir);
557
558 f = fopen(name, "r");
559 if (f == NULL) {
560 fprintf(stderr, "%s: %s: %m\n", __func__, name);
561 return 1;
562 }
563
564 for (r = 0; r < PCI_ROM_SLOT; r++) {
565 if (fscanf(f, "%lli %lli %lli\n", &start, &end, &flags) != 3)
566 break;
567
568 rp = dev->regions + r;
569 rp->valid = 0;
570 rp->resource_fd = -1;
571 size = end - start + 1;
572 flags &= IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH;
573 if (size == 0 || (flags & ~IORESOURCE_PREFETCH) == 0)
574 continue;
575 if (flags & IORESOURCE_MEM) {
576 flags &= ~IORESOURCE_IO;
577 } else {
578 flags &= ~IORESOURCE_PREFETCH;
579 }
580 snprintf(name, sizeof(name), "%sresource%d", dir, r);
581 fd = open(name, O_RDWR);
582 if (fd == -1)
583 continue;
584 rp->resource_fd = fd;
585
586 rp->type = flags;
587 rp->valid = 1;
588 rp->base_addr = start;
589 rp->size = size;
590 pci_dev->v_addrs[r].region = rp;
591 DEBUG("region %d size %d start 0x%llx type %d resource_fd %d\n",
592 r, rp->size, start, rp->type, rp->resource_fd);
593 }
594
595 fclose(f);
596
597 /* read and fill vendor ID */
598 v = get_real_vendor_id(dir, &id);
599 if (v) {
600 return 1;
601 }
602 pci_dev->dev.config[0] = id & 0xff;
603 pci_dev->dev.config[1] = (id & 0xff00) >> 8;
604
605 /* read and fill device ID */
606 v = get_real_device_id(dir, &id);
607 if (v) {
608 return 1;
609 }
610 pci_dev->dev.config[2] = id & 0xff;
611 pci_dev->dev.config[3] = (id & 0xff00) >> 8;
612
613 /* dealing with virtual function device */
614 snprintf(name, sizeof(name), "%sphysfn/", dir);
615 if (!stat(name, &statbuf)) {
616 /* always provide the written value on readout */
617 assigned_dev_emulate_config_read(pci_dev, PCI_COMMAND, 2);
618 }
619
620 dev->region_number = r;
621 return 0;
622 }
623
624 static QLIST_HEAD(, AssignedDevice) devs = QLIST_HEAD_INITIALIZER(devs);
625
626 static void free_dev_irq_entries(AssignedDevice *dev)
627 {
628 int i;
629
630 for (i = 0; i < dev->irq_entries_nr; i++)
631 kvm_del_routing_entry(&dev->entry[i]);
632 g_free(dev->entry);
633 dev->entry = NULL;
634 dev->irq_entries_nr = 0;
635 }
636
637 static void free_assigned_device(AssignedDevice *dev)
638 {
639 int i;
640
641 if (dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) {
642 assigned_dev_unregister_msix_mmio(dev);
643 }
644 for (i = 0; i < dev->real_device.region_number; i++) {
645 PCIRegion *pci_region = &dev->real_device.regions[i];
646 AssignedDevRegion *region = &dev->v_addrs[i];
647
648 if (!pci_region->valid) {
649 continue;
650 }
651 if (pci_region->type & IORESOURCE_IO) {
652 if (pci_region->resource_fd < 0) {
653 kvm_remove_ioport_region(region->u.r_baseport, region->r_size,
654 dev->dev.qdev.hotplugged);
655 }
656 memory_region_del_subregion(&region->container,
657 &region->real_iomem);
658 memory_region_destroy(&region->real_iomem);
659 memory_region_destroy(&region->container);
660 } else if (pci_region->type & IORESOURCE_MEM) {
661 if (region->u.r_virtbase) {
662 memory_region_del_subregion(&region->container,
663 &region->real_iomem);
664
665 /* Remove MSI-X table subregion */
666 if (pci_region->base_addr <= dev->msix_table_addr &&
667 pci_region->base_addr + pci_region->size >
668 dev->msix_table_addr) {
669 memory_region_del_subregion(&region->container,
670 &dev->mmio);
671 }
672
673 memory_region_destroy(&region->real_iomem);
674 memory_region_destroy(&region->container);
675 if (munmap(region->u.r_virtbase,
676 (pci_region->size + 0xFFF) & 0xFFFFF000)) {
677 fprintf(stderr,
678 "Failed to unmap assigned device region: %s\n",
679 strerror(errno));
680 }
681 }
682 }
683 if (pci_region->resource_fd >= 0) {
684 close(pci_region->resource_fd);
685 }
686 }
687
688 if (dev->real_device.config_fd >= 0) {
689 close(dev->real_device.config_fd);
690 }
691
692 free_dev_irq_entries(dev);
693 }
694
695 static uint32_t calc_assigned_dev_id(AssignedDevice *dev)
696 {
697 return (uint32_t)dev->h_segnr << 16 | (uint32_t)dev->h_busnr << 8 |
698 (uint32_t)dev->h_devfn;
699 }
700
701 static void assign_failed_examine(AssignedDevice *dev)
702 {
703 char name[PATH_MAX], dir[PATH_MAX], driver[PATH_MAX] = {}, *ns;
704 uint16_t vendor_id, device_id;
705 int r;
706
707 sprintf(dir, "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/",
708 dev->host.seg, dev->host.bus, dev->host.dev, dev->host.func);
709
710 sprintf(name, "%sdriver", dir);
711
712 r = readlink(name, driver, sizeof(driver));
713 if ((r <= 0) || r >= sizeof(driver) || !(ns = strrchr(driver, '/'))) {
714 goto fail;
715 }
716
717 ns++;
718
719 if (get_real_vendor_id(dir, &vendor_id) ||
720 get_real_device_id(dir, &device_id)) {
721 goto fail;
722 }
723
724 fprintf(stderr, "*** The driver '%s' is occupying your device "
725 "%04x:%02x:%02x.%x.\n",
726 ns, dev->host.seg, dev->host.bus, dev->host.dev, dev->host.func);
727 fprintf(stderr, "***\n");
728 fprintf(stderr, "*** You can try the following commands to free it:\n");
729 fprintf(stderr, "***\n");
730 fprintf(stderr, "*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub/"
731 "new_id\n", vendor_id, device_id);
732 fprintf(stderr, "*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/"
733 "%s/unbind\n",
734 dev->host.seg, dev->host.bus, dev->host.dev, dev->host.func, ns);
735 fprintf(stderr, "*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/"
736 "pci-stub/bind\n",
737 dev->host.seg, dev->host.bus, dev->host.dev, dev->host.func);
738 fprintf(stderr, "*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub"
739 "/remove_id\n", vendor_id, device_id);
740 fprintf(stderr, "***\n");
741
742 return;
743
744 fail:
745 fprintf(stderr, "Couldn't find out why.\n");
746 }
747
748 static int assign_device(AssignedDevice *dev)
749 {
750 struct kvm_assigned_pci_dev assigned_dev_data;
751 int r;
752
753 /* Only pass non-zero PCI segment to capable module */
754 if (!kvm_check_extension(kvm_state, KVM_CAP_PCI_SEGMENT) &&
755 dev->h_segnr) {
756 fprintf(stderr, "Can't assign device inside non-zero PCI segment "
757 "as this KVM module doesn't support it.\n");
758 return -ENODEV;
759 }
760
761 memset(&assigned_dev_data, 0, sizeof(assigned_dev_data));
762 assigned_dev_data.assigned_dev_id = calc_assigned_dev_id(dev);
763 assigned_dev_data.segnr = dev->h_segnr;
764 assigned_dev_data.busnr = dev->h_busnr;
765 assigned_dev_data.devfn = dev->h_devfn;
766
767 /* We always enable the IOMMU unless disabled on the command line */
768 if (dev->features & ASSIGNED_DEVICE_USE_IOMMU_MASK) {
769 if (!kvm_check_extension(kvm_state, KVM_CAP_IOMMU)) {
770 fprintf(stderr, "No IOMMU found. Unable to assign device \"%s\"\n",
771 dev->dev.qdev.id);
772 return -ENODEV;
773 }
774 assigned_dev_data.flags |= KVM_DEV_ASSIGN_ENABLE_IOMMU;
775 }
776 if (!(dev->features & ASSIGNED_DEVICE_USE_IOMMU_MASK)) {
777 fprintf(stderr,
778 "WARNING: Assigning a device without IOMMU protection can "
779 "cause host memory corruption if the device issues DMA write "
780 "requests!\n");
781 }
782
783 r = kvm_assign_pci_device(kvm_state, &assigned_dev_data);
784 if (r < 0) {
785 fprintf(stderr, "Failed to assign device \"%s\" : %s\n",
786 dev->dev.qdev.id, strerror(-r));
787
788 switch (r) {
789 case -EBUSY:
790 assign_failed_examine(dev);
791 break;
792 default:
793 break;
794 }
795 }
796 return r;
797 }
798
799 static int assign_irq(AssignedDevice *dev)
800 {
801 struct kvm_assigned_irq assigned_irq_data;
802 int irq, r = 0;
803
804 /* Interrupt PIN 0 means don't use INTx */
805 if (assigned_dev_pci_read_byte(&dev->dev, PCI_INTERRUPT_PIN) == 0)
806 return 0;
807
808 irq = pci_map_irq(&dev->dev, dev->intpin);
809 irq = piix_get_irq(irq);
810
811 if (dev->girq == irq)
812 return r;
813
814 memset(&assigned_irq_data, 0, sizeof(assigned_irq_data));
815 assigned_irq_data.assigned_dev_id = calc_assigned_dev_id(dev);
816 assigned_irq_data.guest_irq = irq;
817 assigned_irq_data.host_irq = dev->real_device.irq;
818 if (dev->irq_requested_type) {
819 assigned_irq_data.flags = dev->irq_requested_type;
820 r = kvm_deassign_irq(kvm_state, &assigned_irq_data);
821 if (r) {
822 perror("assign_irq: deassign");
823 }
824 dev->irq_requested_type = 0;
825 }
826
827 assigned_irq_data.flags = KVM_DEV_IRQ_GUEST_INTX;
828 if (dev->features & ASSIGNED_DEVICE_PREFER_MSI_MASK &&
829 dev->cap.available & ASSIGNED_DEVICE_CAP_MSI)
830 assigned_irq_data.flags |= KVM_DEV_IRQ_HOST_MSI;
831 else
832 assigned_irq_data.flags |= KVM_DEV_IRQ_HOST_INTX;
833
834 r = kvm_assign_irq(kvm_state, &assigned_irq_data);
835 if (r < 0) {
836 fprintf(stderr, "Failed to assign irq for \"%s\": %s\n",
837 dev->dev.qdev.id, strerror(-r));
838 fprintf(stderr, "Perhaps you are assigning a device "
839 "that shares an IRQ with another device?\n");
840 return r;
841 }
842
843 dev->girq = irq;
844 dev->irq_requested_type = assigned_irq_data.flags;
845 return r;
846 }
847
848 static void deassign_device(AssignedDevice *dev)
849 {
850 struct kvm_assigned_pci_dev assigned_dev_data;
851 int r;
852
853 memset(&assigned_dev_data, 0, sizeof(assigned_dev_data));
854 assigned_dev_data.assigned_dev_id = calc_assigned_dev_id(dev);
855
856 r = kvm_deassign_pci_device(kvm_state, &assigned_dev_data);
857 if (r < 0)
858 fprintf(stderr, "Failed to deassign device \"%s\" : %s\n",
859 dev->dev.qdev.id, strerror(-r));
860 }
861
862 #if 0
863 AssignedDevInfo *get_assigned_device(int pcibus, int slot)
864 {
865 AssignedDevice *assigned_dev = NULL;
866 AssignedDevInfo *adev = NULL;
867
868 QLIST_FOREACH(adev, &adev_head, next) {
869 assigned_dev = adev->assigned_dev;
870 if (pci_bus_num(assigned_dev->dev.bus) == pcibus &&
871 PCI_SLOT(assigned_dev->dev.devfn) == slot)
872 return adev;
873 }
874
875 return NULL;
876 }
877 #endif
878
879 /* The pci config space got updated. Check if irq numbers have changed
880 * for our devices
881 */
882 void assigned_dev_update_irqs(void)
883 {
884 AssignedDevice *dev, *next;
885 int r;
886
887 dev = QLIST_FIRST(&devs);
888 while (dev) {
889 next = QLIST_NEXT(dev, next);
890 if (dev->irq_requested_type & KVM_DEV_IRQ_HOST_INTX) {
891 r = assign_irq(dev);
892 if (r < 0) {
893 qdev_unplug(&dev->dev.qdev);
894 }
895 }
896 dev = next;
897 }
898 }
899
900 static void assigned_dev_update_msi(PCIDevice *pci_dev)
901 {
902 struct kvm_assigned_irq assigned_irq_data;
903 AssignedDevice *assigned_dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
904 uint8_t ctrl_byte = pci_get_byte(pci_dev->config + pci_dev->msi_cap +
905 PCI_MSI_FLAGS);
906 int r;
907
908 memset(&assigned_irq_data, 0, sizeof assigned_irq_data);
909 assigned_irq_data.assigned_dev_id = calc_assigned_dev_id(assigned_dev);
910
911 /* Some guests gratuitously disable MSI even if they're not using it,
912 * try to catch this by only deassigning irqs if the guest is using
913 * MSI or intends to start. */
914 if ((assigned_dev->irq_requested_type & KVM_DEV_IRQ_GUEST_MSI) ||
915 (ctrl_byte & PCI_MSI_FLAGS_ENABLE)) {
916
917 assigned_irq_data.flags = assigned_dev->irq_requested_type;
918 free_dev_irq_entries(assigned_dev);
919 r = kvm_deassign_irq(kvm_state, &assigned_irq_data);
920 /* -ENXIO means no assigned irq */
921 if (r && r != -ENXIO)
922 perror("assigned_dev_update_msi: deassign irq");
923
924 assigned_dev->irq_requested_type = 0;
925 }
926
927 if (ctrl_byte & PCI_MSI_FLAGS_ENABLE) {
928 uint8_t *pos = pci_dev->config + pci_dev->msi_cap;
929
930 assigned_dev->entry = g_malloc0(sizeof(*(assigned_dev->entry)));
931 assigned_dev->entry->u.msi.address_lo =
932 pci_get_long(pos + PCI_MSI_ADDRESS_LO);
933 assigned_dev->entry->u.msi.address_hi = 0;
934 assigned_dev->entry->u.msi.data = pci_get_word(pos + PCI_MSI_DATA_32);
935 assigned_dev->entry->type = KVM_IRQ_ROUTING_MSI;
936 r = kvm_get_irq_route_gsi();
937 if (r < 0) {
938 perror("assigned_dev_update_msi: kvm_get_irq_route_gsi");
939 return;
940 }
941 assigned_dev->entry->gsi = r;
942
943 kvm_add_routing_entry(assigned_dev->entry);
944 if (kvm_commit_irq_routes() < 0) {
945 perror("assigned_dev_update_msi: kvm_commit_irq_routes");
946 assigned_dev->cap.state &= ~ASSIGNED_DEVICE_MSI_ENABLED;
947 return;
948 }
949 assigned_dev->irq_entries_nr = 1;
950
951 assigned_irq_data.guest_irq = assigned_dev->entry->gsi;
952 assigned_irq_data.flags = KVM_DEV_IRQ_HOST_MSI | KVM_DEV_IRQ_GUEST_MSI;
953 if (kvm_assign_irq(kvm_state, &assigned_irq_data) < 0) {
954 perror("assigned_dev_enable_msi: assign irq");
955 }
956
957 assigned_dev->girq = -1;
958 assigned_dev->irq_requested_type = assigned_irq_data.flags;
959 } else {
960 assign_irq(assigned_dev);
961 }
962 }
963
964 static int assigned_dev_update_msix_mmio(PCIDevice *pci_dev)
965 {
966 AssignedDevice *adev = DO_UPCAST(AssignedDevice, dev, pci_dev);
967 uint16_t entries_nr = 0, entries_max_nr;
968 int pos = 0, i, r = 0;
969 uint32_t msg_addr, msg_upper_addr, msg_data, msg_ctrl;
970 struct kvm_assigned_msix_nr msix_nr;
971 struct kvm_assigned_msix_entry msix_entry;
972 void *va = adev->msix_table_page;
973
974 pos = pci_find_capability(pci_dev, PCI_CAP_ID_MSIX);
975
976 entries_max_nr = *(uint16_t *)(pci_dev->config + pos + 2);
977 entries_max_nr &= PCI_MSIX_FLAGS_QSIZE;
978 entries_max_nr += 1;
979
980 /* Get the usable entry number for allocating */
981 for (i = 0; i < entries_max_nr; i++) {
982 memcpy(&msg_ctrl, va + i * 16 + 12, 4);
983 memcpy(&msg_data, va + i * 16 + 8, 4);
984 /* Ignore unused entry even it's unmasked */
985 if (msg_data == 0)
986 continue;
987 entries_nr ++;
988 }
989
990 if (entries_nr == 0) {
991 fprintf(stderr, "MSI-X entry number is zero!\n");
992 return -EINVAL;
993 }
994 msix_nr.assigned_dev_id = calc_assigned_dev_id(adev);
995 msix_nr.entry_nr = entries_nr;
996 r = kvm_assign_set_msix_nr(kvm_state, &msix_nr);
997 if (r != 0) {
998 fprintf(stderr, "fail to set MSI-X entry number for MSIX! %s\n",
999 strerror(-r));
1000 return r;
1001 }
1002
1003 free_dev_irq_entries(adev);
1004 adev->irq_entries_nr = entries_nr;
1005 adev->entry = g_malloc0(entries_nr * sizeof(*(adev->entry)));
1006
1007 msix_entry.assigned_dev_id = msix_nr.assigned_dev_id;
1008 entries_nr = 0;
1009 for (i = 0; i < entries_max_nr; i++) {
1010 if (entries_nr >= msix_nr.entry_nr)
1011 break;
1012 memcpy(&msg_ctrl, va + i * 16 + 12, 4);
1013 memcpy(&msg_data, va + i * 16 + 8, 4);
1014 if (msg_data == 0)
1015 continue;
1016
1017 memcpy(&msg_addr, va + i * 16, 4);
1018 memcpy(&msg_upper_addr, va + i * 16 + 4, 4);
1019
1020 r = kvm_get_irq_route_gsi();
1021 if (r < 0)
1022 return r;
1023
1024 adev->entry[entries_nr].gsi = r;
1025 adev->entry[entries_nr].type = KVM_IRQ_ROUTING_MSI;
1026 adev->entry[entries_nr].flags = 0;
1027 adev->entry[entries_nr].u.msi.address_lo = msg_addr;
1028 adev->entry[entries_nr].u.msi.address_hi = msg_upper_addr;
1029 adev->entry[entries_nr].u.msi.data = msg_data;
1030 DEBUG("MSI-X data 0x%x, MSI-X addr_lo 0x%x\n!", msg_data, msg_addr);
1031 kvm_add_routing_entry(&adev->entry[entries_nr]);
1032
1033 msix_entry.gsi = adev->entry[entries_nr].gsi;
1034 msix_entry.entry = i;
1035 r = kvm_assign_set_msix_entry(kvm_state, &msix_entry);
1036 if (r) {
1037 fprintf(stderr, "fail to set MSI-X entry! %s\n", strerror(-r));
1038 break;
1039 }
1040 DEBUG("MSI-X entry gsi 0x%x, entry %d\n!",
1041 msix_entry.gsi, msix_entry.entry);
1042 entries_nr ++;
1043 }
1044
1045 if (r == 0 && kvm_commit_irq_routes() < 0) {
1046 perror("assigned_dev_update_msix_mmio: kvm_commit_irq_routes");
1047 return -EINVAL;
1048 }
1049
1050 return r;
1051 }
1052
1053 static void assigned_dev_update_msix(PCIDevice *pci_dev)
1054 {
1055 struct kvm_assigned_irq assigned_irq_data;
1056 AssignedDevice *assigned_dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
1057 uint16_t ctrl_word = pci_get_word(pci_dev->config + pci_dev->msix_cap +
1058 PCI_MSIX_FLAGS);
1059 int r;
1060
1061 memset(&assigned_irq_data, 0, sizeof assigned_irq_data);
1062 assigned_irq_data.assigned_dev_id = calc_assigned_dev_id(assigned_dev);
1063
1064 /* Some guests gratuitously disable MSIX even if they're not using it,
1065 * try to catch this by only deassigning irqs if the guest is using
1066 * MSIX or intends to start. */
1067 if ((assigned_dev->irq_requested_type & KVM_DEV_IRQ_GUEST_MSIX) ||
1068 (ctrl_word & PCI_MSIX_FLAGS_ENABLE)) {
1069
1070 assigned_irq_data.flags = assigned_dev->irq_requested_type;
1071 free_dev_irq_entries(assigned_dev);
1072 r = kvm_deassign_irq(kvm_state, &assigned_irq_data);
1073 /* -ENXIO means no assigned irq */
1074 if (r && r != -ENXIO)
1075 perror("assigned_dev_update_msix: deassign irq");
1076
1077 assigned_dev->irq_requested_type = 0;
1078 }
1079
1080 if (ctrl_word & PCI_MSIX_FLAGS_ENABLE) {
1081 assigned_irq_data.flags = KVM_DEV_IRQ_HOST_MSIX |
1082 KVM_DEV_IRQ_GUEST_MSIX;
1083
1084 if (assigned_dev_update_msix_mmio(pci_dev) < 0) {
1085 perror("assigned_dev_update_msix_mmio");
1086 return;
1087 }
1088 if (kvm_assign_irq(kvm_state, &assigned_irq_data) < 0) {
1089 perror("assigned_dev_enable_msix: assign irq");
1090 return;
1091 }
1092 assigned_dev->girq = -1;
1093 assigned_dev->irq_requested_type = assigned_irq_data.flags;
1094 } else {
1095 assign_irq(assigned_dev);
1096 }
1097 }
1098
1099 static uint32_t assigned_dev_pci_read_config(PCIDevice *pci_dev,
1100 uint32_t address, int len)
1101 {
1102 AssignedDevice *assigned_dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
1103 uint32_t virt_val = pci_default_read_config(pci_dev, address, len);
1104 uint32_t real_val, emulate_mask, full_emulation_mask;
1105
1106 emulate_mask = 0;
1107 memcpy(&emulate_mask, assigned_dev->emulate_config_read + address, len);
1108 emulate_mask = le32_to_cpu(emulate_mask);
1109
1110 full_emulation_mask = 0xffffffff >> (32 - len * 8);
1111
1112 if (emulate_mask != full_emulation_mask) {
1113 real_val = assigned_dev_pci_read(pci_dev, address, len);
1114 return (virt_val & emulate_mask) | (real_val & ~emulate_mask);
1115 } else {
1116 return virt_val;
1117 }
1118 }
1119
1120 static void assigned_dev_pci_write_config(PCIDevice *pci_dev, uint32_t address,
1121 uint32_t val, int len)
1122 {
1123 AssignedDevice *assigned_dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
1124 uint32_t emulate_mask, full_emulation_mask;
1125
1126 pci_default_write_config(pci_dev, address, val, len);
1127
1128 if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
1129 if (range_covers_byte(address, len,
1130 pci_dev->msi_cap + PCI_MSI_FLAGS)) {
1131 assigned_dev_update_msi(pci_dev);
1132 }
1133 }
1134 if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) {
1135 if (range_covers_byte(address, len,
1136 pci_dev->msix_cap + PCI_MSIX_FLAGS + 1)) {
1137 assigned_dev_update_msix(pci_dev);
1138 }
1139 }
1140
1141 emulate_mask = 0;
1142 memcpy(&emulate_mask, assigned_dev->emulate_config_write + address, len);
1143 emulate_mask = le32_to_cpu(emulate_mask);
1144
1145 full_emulation_mask = 0xffffffff >> (32 - len * 8);
1146
1147 if (emulate_mask != full_emulation_mask) {
1148 if (emulate_mask) {
1149 val &= ~emulate_mask;
1150 val |= assigned_dev_pci_read(pci_dev, address, len) & emulate_mask;
1151 }
1152 assigned_dev_pci_write(pci_dev, address, val, len);
1153 }
1154 }
1155
1156 static void assigned_dev_setup_cap_read(AssignedDevice *dev, uint32_t offset,
1157 uint32_t len)
1158 {
1159 assigned_dev_direct_config_read(dev, offset, len);
1160 assigned_dev_emulate_config_read(dev, offset + PCI_CAP_LIST_NEXT, 1);
1161 }
1162
1163 static int assigned_device_pci_cap_init(PCIDevice *pci_dev)
1164 {
1165 AssignedDevice *dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
1166 PCIRegion *pci_region = dev->real_device.regions;
1167 int ret, pos;
1168
1169 /* Clear initial capabilities pointer and status copied from hw */
1170 pci_set_byte(pci_dev->config + PCI_CAPABILITY_LIST, 0);
1171 pci_set_word(pci_dev->config + PCI_STATUS,
1172 pci_get_word(pci_dev->config + PCI_STATUS) &
1173 ~PCI_STATUS_CAP_LIST);
1174
1175 /* Expose MSI capability
1176 * MSI capability is the 1st capability in capability config */
1177 pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSI, 0);
1178 if (pos != 0 && kvm_check_extension(kvm_state, KVM_CAP_ASSIGN_DEV_IRQ)) {
1179 dev->cap.available |= ASSIGNED_DEVICE_CAP_MSI;
1180 /* Only 32-bit/no-mask currently supported */
1181 if ((ret = pci_add_capability(pci_dev, PCI_CAP_ID_MSI, pos, 10)) < 0) {
1182 return ret;
1183 }
1184 pci_dev->msi_cap = pos;
1185
1186 pci_set_word(pci_dev->config + pos + PCI_MSI_FLAGS,
1187 pci_get_word(pci_dev->config + pos + PCI_MSI_FLAGS) &
1188 PCI_MSI_FLAGS_QMASK);
1189 pci_set_long(pci_dev->config + pos + PCI_MSI_ADDRESS_LO, 0);
1190 pci_set_word(pci_dev->config + pos + PCI_MSI_DATA_32, 0);
1191
1192 /* Set writable fields */
1193 pci_set_word(pci_dev->wmask + pos + PCI_MSI_FLAGS,
1194 PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
1195 pci_set_long(pci_dev->wmask + pos + PCI_MSI_ADDRESS_LO, 0xfffffffc);
1196 pci_set_word(pci_dev->wmask + pos + PCI_MSI_DATA_32, 0xffff);
1197 }
1198 /* Expose MSI-X capability */
1199 pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSIX, 0);
1200 /* Would really like to test kvm_check_extension(, KVM_CAP_DEVICE_MSIX),
1201 * but the kernel doesn't expose it. Instead do a dummy call to
1202 * KVM_ASSIGN_SET_MSIX_NR to see if it exists. */
1203 if (pos != 0 && kvm_assign_set_msix_nr(kvm_state, NULL) == -EFAULT) {
1204 int bar_nr;
1205 uint32_t msix_table_entry;
1206
1207 dev->cap.available |= ASSIGNED_DEVICE_CAP_MSIX;
1208 if ((ret = pci_add_capability(pci_dev, PCI_CAP_ID_MSIX, pos, 12)) < 0) {
1209 return ret;
1210 }
1211 pci_dev->msix_cap = pos;
1212
1213 pci_set_word(pci_dev->config + pos + PCI_MSIX_FLAGS,
1214 pci_get_word(pci_dev->config + pos + PCI_MSIX_FLAGS) &
1215 PCI_MSIX_FLAGS_QSIZE);
1216
1217 /* Only enable and function mask bits are writable */
1218 pci_set_word(pci_dev->wmask + pos + PCI_MSIX_FLAGS,
1219 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
1220
1221 msix_table_entry = pci_get_long(pci_dev->config + pos + PCI_MSIX_TABLE);
1222 bar_nr = msix_table_entry & PCI_MSIX_FLAGS_BIRMASK;
1223 msix_table_entry &= ~PCI_MSIX_FLAGS_BIRMASK;
1224 dev->msix_table_addr = pci_region[bar_nr].base_addr + msix_table_entry;
1225 }
1226
1227 /* Minimal PM support, nothing writable, device appears to NAK changes */
1228 if ((pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_PM, 0))) {
1229 uint16_t pmc;
1230 if ((ret = pci_add_capability(pci_dev, PCI_CAP_ID_PM, pos,
1231 PCI_PM_SIZEOF)) < 0) {
1232 return ret;
1233 }
1234
1235 assigned_dev_setup_cap_read(dev, pos, PCI_PM_SIZEOF);
1236
1237 pmc = pci_get_word(pci_dev->config + pos + PCI_CAP_FLAGS);
1238 pmc &= (PCI_PM_CAP_VER_MASK | PCI_PM_CAP_DSI);
1239 pci_set_word(pci_dev->config + pos + PCI_CAP_FLAGS, pmc);
1240
1241 /* assign_device will bring the device up to D0, so we don't need
1242 * to worry about doing that ourselves here. */
1243 pci_set_word(pci_dev->config + pos + PCI_PM_CTRL,
1244 PCI_PM_CTRL_NO_SOFT_RESET);
1245
1246 pci_set_byte(pci_dev->config + pos + PCI_PM_PPB_EXTENSIONS, 0);
1247 pci_set_byte(pci_dev->config + pos + PCI_PM_DATA_REGISTER, 0);
1248 }
1249
1250 if ((pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_EXP, 0))) {
1251 uint8_t version, size = 0;
1252 uint16_t type, devctl, lnksta;
1253 uint32_t devcap, lnkcap;
1254
1255 version = pci_get_byte(pci_dev->config + pos + PCI_EXP_FLAGS);
1256 version &= PCI_EXP_FLAGS_VERS;
1257 if (version == 1) {
1258 size = 0x14;
1259 } else if (version == 2) {
1260 /*
1261 * Check for non-std size, accept reduced size to 0x34,
1262 * which is what bcm5761 implemented, violating the
1263 * PCIe v3.0 spec that regs should exist and be read as 0,
1264 * not optionally provided and shorten the struct size.
1265 */
1266 size = MIN(0x3c, PCI_CONFIG_SPACE_SIZE - pos);
1267 if (size < 0x34) {
1268 fprintf(stderr,
1269 "%s: Invalid size PCIe cap-id 0x%x \n",
1270 __func__, PCI_CAP_ID_EXP);
1271 return -EINVAL;
1272 } else if (size != 0x3c) {
1273 fprintf(stderr,
1274 "WARNING, %s: PCIe cap-id 0x%x has "
1275 "non-standard size 0x%x; std size should be 0x3c \n",
1276 __func__, PCI_CAP_ID_EXP, size);
1277 }
1278 } else if (version == 0) {
1279 uint16_t vid, did;
1280 vid = pci_get_word(pci_dev->config + PCI_VENDOR_ID);
1281 did = pci_get_word(pci_dev->config + PCI_DEVICE_ID);
1282 if (vid == PCI_VENDOR_ID_INTEL && did == 0x10ed) {
1283 /*
1284 * quirk for Intel 82599 VF with invalid PCIe capability
1285 * version, should really be version 2 (same as PF)
1286 */
1287 size = 0x3c;
1288 }
1289 }
1290
1291 if (size == 0) {
1292 fprintf(stderr,
1293 "%s: Unsupported PCI express capability version %d\n",
1294 __func__, version);
1295 return -EINVAL;
1296 }
1297
1298 if ((ret = pci_add_capability(pci_dev, PCI_CAP_ID_EXP,
1299 pos, size)) < 0) {
1300 return ret;
1301 }
1302
1303 assigned_dev_setup_cap_read(dev, pos, size);
1304
1305 type = pci_get_word(pci_dev->config + pos + PCI_EXP_FLAGS);
1306 type = (type & PCI_EXP_FLAGS_TYPE) >> 4;
1307 if (type != PCI_EXP_TYPE_ENDPOINT &&
1308 type != PCI_EXP_TYPE_LEG_END && type != PCI_EXP_TYPE_RC_END) {
1309 fprintf(stderr,
1310 "Device assignment only supports endpoint assignment, "
1311 "device type %d\n", type);
1312 return -EINVAL;
1313 }
1314
1315 /* capabilities, pass existing read-only copy
1316 * PCI_EXP_FLAGS_IRQ: updated by hardware, should be direct read */
1317
1318 /* device capabilities: hide FLR */
1319 devcap = pci_get_long(pci_dev->config + pos + PCI_EXP_DEVCAP);
1320 devcap &= ~PCI_EXP_DEVCAP_FLR;
1321 pci_set_long(pci_dev->config + pos + PCI_EXP_DEVCAP, devcap);
1322
1323 /* device control: clear all error reporting enable bits, leaving
1324 * only a few host values. Note, these are
1325 * all writable, but not passed to hw.
1326 */
1327 devctl = pci_get_word(pci_dev->config + pos + PCI_EXP_DEVCTL);
1328 devctl = (devctl & (PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_PAYLOAD)) |
1329 PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
1330 pci_set_word(pci_dev->config + pos + PCI_EXP_DEVCTL, devctl);
1331 devctl = PCI_EXP_DEVCTL_BCR_FLR | PCI_EXP_DEVCTL_AUX_PME;
1332 pci_set_word(pci_dev->wmask + pos + PCI_EXP_DEVCTL, ~devctl);
1333
1334 /* Clear device status */
1335 pci_set_word(pci_dev->config + pos + PCI_EXP_DEVSTA, 0);
1336
1337 /* Link capabilities, expose links and latencues, clear reporting */
1338 lnkcap = pci_get_long(pci_dev->config + pos + PCI_EXP_LNKCAP);
1339 lnkcap &= (PCI_EXP_LNKCAP_SLS | PCI_EXP_LNKCAP_MLW |
1340 PCI_EXP_LNKCAP_ASPMS | PCI_EXP_LNKCAP_L0SEL |
1341 PCI_EXP_LNKCAP_L1EL);
1342 pci_set_long(pci_dev->config + pos + PCI_EXP_LNKCAP, lnkcap);
1343
1344 /* Link control, pass existing read-only copy. Should be writable? */
1345
1346 /* Link status, only expose current speed and width */
1347 lnksta = pci_get_word(pci_dev->config + pos + PCI_EXP_LNKSTA);
1348 lnksta &= (PCI_EXP_LNKSTA_CLS | PCI_EXP_LNKSTA_NLW);
1349 pci_set_word(pci_dev->config + pos + PCI_EXP_LNKSTA, lnksta);
1350
1351 if (version >= 2) {
1352 /* Slot capabilities, control, status - not needed for endpoints */
1353 pci_set_long(pci_dev->config + pos + PCI_EXP_SLTCAP, 0);
1354 pci_set_word(pci_dev->config + pos + PCI_EXP_SLTCTL, 0);
1355 pci_set_word(pci_dev->config + pos + PCI_EXP_SLTSTA, 0);
1356
1357 /* Root control, capabilities, status - not needed for endpoints */
1358 pci_set_word(pci_dev->config + pos + PCI_EXP_RTCTL, 0);
1359 pci_set_word(pci_dev->config + pos + PCI_EXP_RTCAP, 0);
1360 pci_set_long(pci_dev->config + pos + PCI_EXP_RTSTA, 0);
1361
1362 /* Device capabilities/control 2, pass existing read-only copy */
1363 /* Link control 2, pass existing read-only copy */
1364 }
1365 }
1366
1367 if ((pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_PCIX, 0))) {
1368 uint16_t cmd;
1369 uint32_t status;
1370
1371 /* Only expose the minimum, 8 byte capability */
1372 if ((ret = pci_add_capability(pci_dev, PCI_CAP_ID_PCIX, pos, 8)) < 0) {
1373 return ret;
1374 }
1375
1376 assigned_dev_setup_cap_read(dev, pos, 8);
1377
1378 /* Command register, clear upper bits, including extended modes */
1379 cmd = pci_get_word(pci_dev->config + pos + PCI_X_CMD);
1380 cmd &= (PCI_X_CMD_DPERR_E | PCI_X_CMD_ERO | PCI_X_CMD_MAX_READ |
1381 PCI_X_CMD_MAX_SPLIT);
1382 pci_set_word(pci_dev->config + pos + PCI_X_CMD, cmd);
1383
1384 /* Status register, update with emulated PCI bus location, clear
1385 * error bits, leave the rest. */
1386 status = pci_get_long(pci_dev->config + pos + PCI_X_STATUS);
1387 status &= ~(PCI_X_STATUS_BUS | PCI_X_STATUS_DEVFN);
1388 status |= (pci_bus_num(pci_dev->bus) << 8) | pci_dev->devfn;
1389 status &= ~(PCI_X_STATUS_SPL_DISC | PCI_X_STATUS_UNX_SPL |
1390 PCI_X_STATUS_SPL_ERR);
1391 pci_set_long(pci_dev->config + pos + PCI_X_STATUS, status);
1392 }
1393
1394 if ((pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_VPD, 0))) {
1395 /* Direct R/W passthrough */
1396 if ((ret = pci_add_capability(pci_dev, PCI_CAP_ID_VPD, pos, 8)) < 0) {
1397 return ret;
1398 }
1399
1400 assigned_dev_setup_cap_read(dev, pos, 8);
1401
1402 /* direct write for cap content */
1403 assigned_dev_direct_config_write(dev, pos + 2, 6);
1404 }
1405
1406 /* Devices can have multiple vendor capabilities, get them all */
1407 for (pos = 0; (pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_VNDR, pos));
1408 pos += PCI_CAP_LIST_NEXT) {
1409 uint8_t len = pci_get_byte(pci_dev->config + pos + PCI_CAP_FLAGS);
1410 /* Direct R/W passthrough */
1411 if ((ret = pci_add_capability(pci_dev, PCI_CAP_ID_VNDR,
1412 pos, len)) < 0) {
1413 return ret;
1414 }
1415
1416 assigned_dev_setup_cap_read(dev, pos, len);
1417
1418 /* direct write for cap content */
1419 assigned_dev_direct_config_write(dev, pos + 2, len - 2);
1420 }
1421
1422 /* If real and virtual capability list status bits differ, virtualize the
1423 * access. */
1424 if ((pci_get_word(pci_dev->config + PCI_STATUS) & PCI_STATUS_CAP_LIST) !=
1425 (assigned_dev_pci_read_byte(pci_dev, PCI_STATUS) &
1426 PCI_STATUS_CAP_LIST)) {
1427 dev->emulate_config_read[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1428 }
1429
1430 return 0;
1431 }
1432
1433 static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
1434 {
1435 AssignedDevice *adev = opaque;
1436 unsigned int offset = addr & 0xfff;
1437 void *page = adev->msix_table_page;
1438 uint32_t val = 0;
1439
1440 memcpy(&val, (void *)((char *)page + offset), 4);
1441
1442 return val;
1443 }
1444
1445 static uint32_t msix_mmio_readb(void *opaque, target_phys_addr_t addr)
1446 {
1447 return ((msix_mmio_readl(opaque, addr & ~3)) >>
1448 (8 * (addr & 3))) & 0xff;
1449 }
1450
1451 static uint32_t msix_mmio_readw(void *opaque, target_phys_addr_t addr)
1452 {
1453 return ((msix_mmio_readl(opaque, addr & ~3)) >>
1454 (8 * (addr & 3))) & 0xffff;
1455 }
1456
1457 static void msix_mmio_writel(void *opaque,
1458 target_phys_addr_t addr, uint32_t val)
1459 {
1460 AssignedDevice *adev = opaque;
1461 unsigned int offset = addr & 0xfff;
1462 void *page = adev->msix_table_page;
1463
1464 DEBUG("write to MSI-X entry table mmio offset 0x%lx, val 0x%x\n",
1465 addr, val);
1466 memcpy((void *)((char *)page + offset), &val, 4);
1467 }
1468
1469 static void msix_mmio_writew(void *opaque,
1470 target_phys_addr_t addr, uint32_t val)
1471 {
1472 msix_mmio_writel(opaque, addr & ~3,
1473 (val & 0xffff) << (8*(addr & 3)));
1474 }
1475
1476 static void msix_mmio_writeb(void *opaque,
1477 target_phys_addr_t addr, uint32_t val)
1478 {
1479 msix_mmio_writel(opaque, addr & ~3,
1480 (val & 0xff) << (8*(addr & 3)));
1481 }
1482
1483 static const MemoryRegionOps msix_mmio_ops = {
1484 .old_mmio = {
1485 .read = { msix_mmio_readb, msix_mmio_readw, msix_mmio_readl, },
1486 .write = { msix_mmio_writeb, msix_mmio_writew, msix_mmio_writel, },
1487 },
1488 .endianness = DEVICE_NATIVE_ENDIAN,
1489 };
1490
1491 static int assigned_dev_register_msix_mmio(AssignedDevice *dev)
1492 {
1493 dev->msix_table_page = mmap(NULL, 0x1000,
1494 PROT_READ|PROT_WRITE,
1495 MAP_ANONYMOUS|MAP_PRIVATE, 0, 0);
1496 if (dev->msix_table_page == MAP_FAILED) {
1497 fprintf(stderr, "fail allocate msix_table_page! %s\n",
1498 strerror(errno));
1499 return -EFAULT;
1500 }
1501 memset(dev->msix_table_page, 0, 0x1000);
1502 memory_region_init_io(&dev->mmio, &msix_mmio_ops, dev,
1503 "assigned-dev-msix", MSIX_PAGE_SIZE);
1504 return 0;
1505 }
1506
1507 static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev)
1508 {
1509 if (!dev->msix_table_page)
1510 return;
1511
1512 memory_region_destroy(&dev->mmio);
1513
1514 if (munmap(dev->msix_table_page, 0x1000) == -1) {
1515 fprintf(stderr, "error unmapping msix_table_page! %s\n",
1516 strerror(errno));
1517 }
1518 dev->msix_table_page = NULL;
1519 }
1520
1521 static const VMStateDescription vmstate_assigned_device = {
1522 .name = "pci-assign",
1523 .unmigratable = 1,
1524 };
1525
1526 static void reset_assigned_device(DeviceState *dev)
1527 {
1528 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
1529 AssignedDevice *adev = DO_UPCAST(AssignedDevice, dev, pci_dev);
1530 char reset_file[64];
1531 const char reset[] = "1";
1532 int fd, ret;
1533
1534 snprintf(reset_file, sizeof(reset_file),
1535 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/reset",
1536 adev->host.seg, adev->host.bus, adev->host.dev, adev->host.func);
1537
1538 /*
1539 * Issue a device reset via pci-sysfs. Note that we use write(2) here
1540 * and ignore the return value because some kernels have a bug that
1541 * returns 0 rather than bytes written on success, sending us into an
1542 * infinite retry loop using other write mechanisms.
1543 */
1544 fd = open(reset_file, O_WRONLY);
1545 if (fd != -1) {
1546 ret = write(fd, reset, strlen(reset));
1547 (void)ret;
1548 close(fd);
1549 }
1550
1551 /*
1552 * When a 0 is written to the command register, the device is logically
1553 * disconnected from the PCI bus. This avoids further DMA transfers.
1554 */
1555 assigned_dev_pci_write_config(pci_dev, PCI_COMMAND, 0, 2);
1556 }
1557
1558 static int assigned_initfn(struct PCIDevice *pci_dev)
1559 {
1560 AssignedDevice *dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
1561 uint8_t e_intx;
1562 int r;
1563
1564 if (!kvm_enabled()) {
1565 error_report("pci-assign: error: requires KVM support");
1566 return -1;
1567 }
1568
1569 if (!dev->host.seg && !dev->host.bus && !dev->host.dev && !dev->host.func) {
1570 error_report("pci-assign: error: no host device specified");
1571 return -1;
1572 }
1573
1574 /*
1575 * Set up basic config space access control. Will be further refined during
1576 * device initialization.
1577 */
1578 assigned_dev_emulate_config_read(dev, 0, PCI_CONFIG_SPACE_SIZE);
1579 assigned_dev_direct_config_read(dev, PCI_COMMAND, 2);
1580 assigned_dev_direct_config_read(dev, PCI_STATUS, 2);
1581 assigned_dev_direct_config_read(dev, PCI_REVISION_ID, 1);
1582 assigned_dev_direct_config_read(dev, PCI_CLASS_PROG, 3);
1583 assigned_dev_direct_config_read(dev, PCI_CACHE_LINE_SIZE, 1);
1584 assigned_dev_direct_config_read(dev, PCI_LATENCY_TIMER, 1);
1585 assigned_dev_direct_config_read(dev, PCI_BIST, 1);
1586 assigned_dev_direct_config_read(dev, PCI_CARDBUS_CIS, 4);
1587 assigned_dev_direct_config_read(dev, PCI_SUBSYSTEM_VENDOR_ID, 2);
1588 assigned_dev_direct_config_read(dev, PCI_SUBSYSTEM_ID, 2);
1589 assigned_dev_direct_config_read(dev, PCI_CAPABILITY_LIST + 1, 7);
1590 assigned_dev_direct_config_read(dev, PCI_MIN_GNT, 1);
1591 assigned_dev_direct_config_read(dev, PCI_MAX_LAT, 1);
1592 memcpy(dev->emulate_config_write, dev->emulate_config_read,
1593 sizeof(dev->emulate_config_read));
1594
1595 if (get_real_device(dev, dev->host.seg, dev->host.bus,
1596 dev->host.dev, dev->host.func)) {
1597 error_report("pci-assign: Error: Couldn't get real device (%s)!",
1598 dev->dev.qdev.id);
1599 goto out;
1600 }
1601
1602 if (assigned_device_pci_cap_init(pci_dev) < 0) {
1603 goto out;
1604 }
1605
1606 /* intercept MSI-X entry page in the MMIO */
1607 if (dev->cap.available & ASSIGNED_DEVICE_CAP_MSIX) {
1608 if (assigned_dev_register_msix_mmio(dev)) {
1609 goto out;
1610 }
1611 }
1612
1613 /* handle real device's MMIO/PIO BARs */
1614 if (assigned_dev_register_regions(dev->real_device.regions,
1615 dev->real_device.region_number,
1616 dev))
1617 goto out;
1618
1619 /* handle interrupt routing */
1620 e_intx = dev->dev.config[0x3d] - 1;
1621 dev->intpin = e_intx;
1622 dev->run = 0;
1623 dev->girq = -1;
1624 dev->h_segnr = dev->host.seg;
1625 dev->h_busnr = dev->host.bus;
1626 dev->h_devfn = PCI_DEVFN(dev->host.dev, dev->host.func);
1627
1628 /* assign device to guest */
1629 r = assign_device(dev);
1630 if (r < 0)
1631 goto out;
1632
1633 /* assign irq for the device */
1634 r = assign_irq(dev);
1635 if (r < 0)
1636 goto assigned_out;
1637
1638 assigned_dev_load_option_rom(dev);
1639 QLIST_INSERT_HEAD(&devs, dev, next);
1640
1641 add_boot_device_path(dev->bootindex, &pci_dev->qdev, NULL);
1642
1643 return 0;
1644
1645 assigned_out:
1646 deassign_device(dev);
1647 out:
1648 free_assigned_device(dev);
1649 return -1;
1650 }
1651
1652 static int assigned_exitfn(struct PCIDevice *pci_dev)
1653 {
1654 AssignedDevice *dev = DO_UPCAST(AssignedDevice, dev, pci_dev);
1655
1656 QLIST_REMOVE(dev, next);
1657 deassign_device(dev);
1658 free_assigned_device(dev);
1659 return 0;
1660 }
1661
1662 static int parse_hostaddr(DeviceState *dev, Property *prop, const char *str)
1663 {
1664 PCIHostDevice *ptr = qdev_get_prop_ptr(dev, prop);
1665 int rc;
1666
1667 rc = pci_parse_host_devaddr(str, &ptr->seg, &ptr->bus, &ptr->dev, &ptr->func);
1668 if (rc != 0)
1669 return -1;
1670 return 0;
1671 }
1672
1673 static int print_hostaddr(DeviceState *dev, Property *prop, char *dest, size_t len)
1674 {
1675 PCIHostDevice *ptr = qdev_get_prop_ptr(dev, prop);
1676
1677 return snprintf(dest, len, "%02x:%02x.%x", ptr->bus, ptr->dev, ptr->func);
1678 }
1679
1680 PropertyInfo qdev_prop_hostaddr = {
1681 .name = "pci-hostaddr",
1682 .type = -1,
1683 .size = sizeof(PCIHostDevice),
1684 .parse = parse_hostaddr,
1685 .print = print_hostaddr,
1686 };
1687
1688 static PCIDeviceInfo assign_info = {
1689 .qdev.name = "pci-assign",
1690 .qdev.desc = "pass through host pci devices to the guest",
1691 .qdev.size = sizeof(AssignedDevice),
1692 .qdev.vmsd = &vmstate_assigned_device,
1693 .qdev.reset = reset_assigned_device,
1694 .init = assigned_initfn,
1695 .exit = assigned_exitfn,
1696 .config_read = assigned_dev_pci_read_config,
1697 .config_write = assigned_dev_pci_write_config,
1698 .qdev.props = (Property[]) {
1699 DEFINE_PROP("host", AssignedDevice, host, qdev_prop_hostaddr, PCIHostDevice),
1700 DEFINE_PROP_BIT("iommu", AssignedDevice, features,
1701 ASSIGNED_DEVICE_USE_IOMMU_BIT, true),
1702 DEFINE_PROP_BIT("prefer_msi", AssignedDevice, features,
1703 ASSIGNED_DEVICE_PREFER_MSI_BIT, true),
1704 DEFINE_PROP_INT32("bootindex", AssignedDevice, bootindex, -1),
1705 DEFINE_PROP_STRING("configfd", AssignedDevice, configfd_name),
1706 DEFINE_PROP_END_OF_LIST(),
1707 },
1708 };
1709
1710 static void assign_register_devices(void)
1711 {
1712 pci_qdev_register(&assign_info);
1713 }
1714
1715 device_init(assign_register_devices)
1716
1717 /*
1718 * Scan the assigned devices for the devices that have an option ROM, and then
1719 * load the corresponding ROM data to RAM. If an error occurs while loading an
1720 * option ROM, we just ignore that option ROM and continue with the next one.
1721 */
1722 static void assigned_dev_load_option_rom(AssignedDevice *dev)
1723 {
1724 char name[32], rom_file[64];
1725 FILE *fp;
1726 uint8_t val;
1727 struct stat st;
1728 void *ptr;
1729
1730 /* If loading ROM from file, pci handles it */
1731 if (dev->dev.romfile || !dev->dev.rom_bar)
1732 return;
1733
1734 snprintf(rom_file, sizeof(rom_file),
1735 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/rom",
1736 dev->host.seg, dev->host.bus, dev->host.dev, dev->host.func);
1737
1738 if (stat(rom_file, &st)) {
1739 return;
1740 }
1741
1742 if (access(rom_file, F_OK)) {
1743 fprintf(stderr, "pci-assign: Insufficient privileges for %s\n",
1744 rom_file);
1745 return;
1746 }
1747
1748 /* Write "1" to the ROM file to enable it */
1749 fp = fopen(rom_file, "r+");
1750 if (fp == NULL) {
1751 return;
1752 }
1753 val = 1;
1754 if (fwrite(&val, 1, 1, fp) != 1) {
1755 goto close_rom;
1756 }
1757 fseek(fp, 0, SEEK_SET);
1758
1759 snprintf(name, sizeof(name), "%s.rom", dev->dev.qdev.info->name);
1760 memory_region_init_ram(&dev->dev.rom, name, st.st_size);
1761 vmstate_register_ram(&dev->dev.rom, &dev->dev.qdev);
1762 ptr = memory_region_get_ram_ptr(&dev->dev.rom);
1763 memset(ptr, 0xff, st.st_size);
1764
1765 if (!fread(ptr, 1, st.st_size, fp)) {
1766 fprintf(stderr, "pci-assign: Cannot read from host %s\n"
1767 "\tDevice option ROM contents are probably invalid "
1768 "(check dmesg).\n\tSkip option ROM probe with rombar=0, "
1769 "or load from file with romfile=\n", rom_file);
1770 memory_region_destroy(&dev->dev.rom);
1771 goto close_rom;
1772 }
1773
1774 pci_register_bar(&dev->dev, PCI_ROM_SLOT, 0, &dev->dev.rom);
1775 dev->dev.has_rom = true;
1776 close_rom:
1777 /* Write "0" to disable ROM */
1778 fseek(fp, 0, SEEK_SET);
1779 val = 0;
1780 if (!fwrite(&val, 1, 1, fp)) {
1781 DEBUG("%s\n", "Failed to disable pci-sysfs rom file");
1782 }
1783 fclose(fp);
1784 }
QEMU modified to work with kvm