cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "exec.h"
  21 #include "disas.h"
  22 #if !defined(TARGET_IA64)
  23 #include "tcg.h"
  24 #endif
  25 #include "kvm.h"
  26 #include "qemu-barrier.h"
  27
  28 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
  29 // Work around ugly bugs in glibc that mangle global register contents
  30 #undef env
  31 #define env cpu_single_env
  32 #endif
  33
  34 int tb_invalidated_flag;
  35
  36 //#define CONFIG_DEBUG_EXEC
  37
  38 int qemu_cpu_has_work(CPUState *env)
  39 {
  40     return cpu_has_work(env);
  41 }
  42
  43 void cpu_loop_exit(void)
  44 {
  45     env->current_tb = NULL;
  46     longjmp(env->jmp_env, 1);
  47 }
  48
  49 /* exit the current TB from a signal handler. The host registers are
  50    restored in a state compatible with the CPU emulator
  51  */
  52 #if defined(CONFIG_SOFTMMU)
  53 void cpu_resume_from_signal(CPUState *env1, void *puc)
  54 {
  55     env = env1;
  56
  57     /* XXX: restore cpu registers saved in host registers */
  58
  59     env->exception_index = -1;
  60     longjmp(env->jmp_env, 1);
  61 }
  62 #endif
  63
  64 /* Execute the code without caching the generated code. An interpreter
  65    could be used if available. */
  66 static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
  67 {
  68     unsigned long next_tb;
  69     TranslationBlock *tb;
  70
  71     /* Should never happen.
  72        We only end up here when an existing TB is too long.  */
  73     if (max_cycles > CF_COUNT_MASK)
  74         max_cycles = CF_COUNT_MASK;
  75
  76     tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
  77                      max_cycles);
  78     env->current_tb = tb;
  79     /* execute the generated code */
  80     next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
  81     env->current_tb = NULL;
  82
  83     if ((next_tb & 3) == 2) {
  84         /* Restore PC.  This may happen if async event occurs before
  85            the TB starts executing.  */
  86         cpu_pc_from_tb(env, tb);
  87     }
  88     tb_phys_invalidate(tb, -1);
  89     tb_free(tb);
  90 }
  91
  92 static TranslationBlock *tb_find_slow(target_ulong pc,
  93                                       target_ulong cs_base,
  94                                       uint64_t flags)
  95 {
  96     TranslationBlock *tb, **ptb1;
  97     unsigned int h;
  98     tb_page_addr_t phys_pc, phys_page1, phys_page2;
  99     target_ulong virt_page2;
 100
 101     tb_invalidated_flag = 0;
 102
 103     /* find translated block using physical mappings */
 104     phys_pc = get_page_addr_code(env, pc);
 105     phys_page1 = phys_pc & TARGET_PAGE_MASK;
 106     phys_page2 = -1;
 107     h = tb_phys_hash_func(phys_pc);
 108     ptb1 = &tb_phys_hash[h];
 109     for(;;) {
 110         tb = *ptb1;
 111         if (!tb)
 112             goto not_found;
 113         if (tb->pc == pc &&
 114             tb->page_addr[0] == phys_page1 &&
 115             tb->cs_base == cs_base &&
 116             tb->flags == flags) {
 117             /* check next page if needed */
 118             if (tb->page_addr[1] != -1) {
 119                 virt_page2 = (pc & TARGET_PAGE_MASK) +
 120                     TARGET_PAGE_SIZE;
 121                 phys_page2 = get_page_addr_code(env, virt_page2);
 122                 if (tb->page_addr[1] == phys_page2)
 123                     goto found;
 124             } else {
 125                 goto found;
 126             }
 127         }
 128         ptb1 = &tb->phys_hash_next;
 129     }
 130  not_found:
 131    /* if no translated code available, then translate it now */
 132     tb = tb_gen_code(env, pc, cs_base, flags, 0);
 133
 134  found:
 135     /* Move the last found TB to the head of the list */
 136     if (likely(*ptb1)) {
 137         *ptb1 = tb->phys_hash_next;
 138         tb->phys_hash_next = tb_phys_hash[h];
 139         tb_phys_hash[h] = tb;
 140     }
 141     /* we add the TB in the virtual pc hash table */
 142     env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
 143     return tb;
 144 }
 145
 146 static inline TranslationBlock *tb_find_fast(void)
 147 {
 148     TranslationBlock *tb;
 149     target_ulong cs_base, pc;
 150     int flags;
 151
 152     /* we record a subset of the CPU state. It will
 153        always be the same before a given translated block
 154        is executed. */
 155     cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
 156     tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
 157     if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
 158                  tb->flags != flags)) {
 159         tb = tb_find_slow(pc, cs_base, flags);
 160     }
 161     return tb;
 162 }
 163
 164 static CPUDebugExcpHandler *debug_excp_handler;
 165
 166 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
 167 {
 168     CPUDebugExcpHandler *old_handler = debug_excp_handler;
 169
 170     debug_excp_handler = handler;
 171     return old_handler;
 172 }
 173
 174 static void cpu_handle_debug_exception(CPUState *env)
 175 {
 176     CPUWatchpoint *wp;
 177
 178     if (!env->watchpoint_hit) {
 179         QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
 180             wp->flags &= ~BP_WATCHPOINT_HIT;
 181         }
 182     }
 183     if (debug_excp_handler) {
 184         debug_excp_handler(env);
 185     }
 186 }
 187
 188 /* main execution loop */
 189
 190 volatile sig_atomic_t exit_request;
 191
 192 int cpu_exec(CPUState *env1)
 193 {
 194     volatile host_reg_t saved_env_reg;
 195     int ret, interrupt_request;
 196     TranslationBlock *tb;
 197     uint8_t *tc_ptr;
 198     unsigned long next_tb;
 199
 200     if (env1->halted) {
 201         if (!cpu_has_work(env1)) {
 202             return EXCP_HALTED;
 203         }
 204
 205         env1->halted = 0;
 206     }
 207
 208     cpu_single_env = env1;
 209
 210     /* the access to env below is actually saving the global register's
 211        value, so that files not including target-xyz/exec.h are free to
 212        use it.  */
 213     QEMU_BUILD_BUG_ON (sizeof (saved_env_reg) != sizeof (env));
 214     saved_env_reg = (host_reg_t) env;
 215     barrier();
 216     env = env1;
 217
 218     if (unlikely(exit_request)) {
 219         env->exit_request = 1;
 220     }
 221
 222 #if defined(TARGET_I386)
 223     /* put eflags in CPU temporary format */
 224     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 225     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 226     CC_OP = CC_OP_EFLAGS;
 227     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 228 #elif defined(TARGET_SPARC)
 229 #elif defined(TARGET_M68K)
 230     env->cc_op = CC_OP_FLAGS;
 231     env->cc_dest = env->sr & 0xf;
 232     env->cc_x = (env->sr >> 4) & 1;
 233 #elif defined(TARGET_ALPHA)
 234 #elif defined(TARGET_ARM)
 235 #elif defined(TARGET_UNICORE32)
 236 #elif defined(TARGET_PPC)
 237 #elif defined(TARGET_LM32)
 238 #elif defined(TARGET_MICROBLAZE)
 239 #elif defined(TARGET_MIPS)
 240 #elif defined(TARGET_SH4)
 241 #elif defined(TARGET_CRIS)
 242 #elif defined(TARGET_S390X)
 243 #elif defined(TARGET_IA64)
 244     /* XXXXX */
 245 #else
 246 #error unsupported target CPU
 247 #endif
 248     env->exception_index = -1;
 249
 250     /* prepare setjmp context for exception handling */
 251     for(;;) {
 252         if (setjmp(env->jmp_env) == 0) {
 253 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
 254 #undef env
 255             env = cpu_single_env;
 256 #define env cpu_single_env
 257 #endif
 258             /* if an exception is pending, we execute it here */
 259             if (env->exception_index >= 0) {
 260                 if (env->exception_index >= EXCP_INTERRUPT) {
 261                     /* exit request from the cpu execution loop */
 262                     ret = env->exception_index;
 263                     if (ret == EXCP_DEBUG) {
 264                         cpu_handle_debug_exception(env);
 265                     }
 266                     break;
 267                 } else {
 268 #if defined(CONFIG_USER_ONLY)
 269                     /* if user mode only, we simulate a fake exception
 270                        which will be handled outside the cpu execution
 271                        loop */
 272 #if defined(TARGET_I386)
 273                     do_interrupt_user(env->exception_index,
 274                                       env->exception_is_int,
 275                                       env->error_code,
 276                                       env->exception_next_eip);
 277                     /* successfully delivered */
 278                     env->old_exception = -1;
 279 #endif
 280                     ret = env->exception_index;
 281                     break;
 282 #else
 283 #if defined(TARGET_I386)
 284                     /* simulate a real cpu exception. On i386, it can
 285                        trigger new exceptions, but we do not handle
 286                        double or triple faults yet. */
 287                     do_interrupt(env->exception_index,
 288                                  env->exception_is_int,
 289                                  env->error_code,
 290                                  env->exception_next_eip, 0);
 291                     /* successfully delivered */
 292                     env->old_exception = -1;
 293 #elif defined(TARGET_PPC)
 294                     do_interrupt(env);
 295 #elif defined(TARGET_LM32)
 296                     do_interrupt(env);
 297 #elif defined(TARGET_MICROBLAZE)
 298                     do_interrupt(env);
 299 #elif defined(TARGET_MIPS)
 300                     do_interrupt(env);
 301 #elif defined(TARGET_SPARC)
 302                     do_interrupt(env);
 303 #elif defined(TARGET_ARM)
 304                     do_interrupt(env);
 305 #elif defined(TARGET_UNICORE32)
 306                     do_interrupt(env);
 307 #elif defined(TARGET_SH4)
 308                     do_interrupt(env);
 309 #elif defined(TARGET_ALPHA)
 310                     do_interrupt(env);
 311 #elif defined(TARGET_CRIS)
 312                     do_interrupt(env);
 313 #elif defined(TARGET_M68K)
 314                     do_interrupt(0);
 315 #elif defined(TARGET_IA64)
 316                     do_interrupt(env);
 317 #elif defined(TARGET_S390X)
 318                     do_interrupt(env);
 319 #endif
 320                     env->exception_index = -1;
 321 #endif
 322                 }
 323             }
 324
 325             next_tb = 0; /* force lookup of first TB */
 326             for(;;) {
 327                 interrupt_request = env->interrupt_request;
 328                 if (unlikely(interrupt_request)) {
 329                     if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
 330                         /* Mask out external interrupts for this step. */
 331                         interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
 332                     }
 333                     if (interrupt_request & CPU_INTERRUPT_DEBUG) {
 334                         env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
 335                         env->exception_index = EXCP_DEBUG;
 336                         cpu_loop_exit();
 337                     }
 338 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
 339     defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
 340     defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
 341                     if (interrupt_request & CPU_INTERRUPT_HALT) {
 342                         env->interrupt_request &= ~CPU_INTERRUPT_HALT;
 343                         env->halted = 1;
 344                         env->exception_index = EXCP_HLT;
 345                         cpu_loop_exit();
 346                     }
 347 #endif
 348 #if defined(TARGET_I386)
 349                     if (interrupt_request & CPU_INTERRUPT_INIT) {
 350                             svm_check_intercept(SVM_EXIT_INIT);
 351                             do_cpu_init(env);
 352                             env->exception_index = EXCP_HALTED;
 353                             cpu_loop_exit();
 354                     } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
 355                             do_cpu_sipi(env);
 356                     } else if (env->hflags2 & HF2_GIF_MASK) {
 357                         if ((interrupt_request & CPU_INTERRUPT_SMI) &&
 358                             !(env->hflags & HF_SMM_MASK)) {
 359                             svm_check_intercept(SVM_EXIT_SMI);
 360                             env->interrupt_request &= ~CPU_INTERRUPT_SMI;
 361                             do_smm_enter();
 362                             next_tb = 0;
 363                         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
 364                                    !(env->hflags2 & HF2_NMI_MASK)) {
 365                             env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 366                             env->hflags2 |= HF2_NMI_MASK;
 367                             do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
 368                             next_tb = 0;
 369                         } else if (interrupt_request & CPU_INTERRUPT_MCE) {
 370                             env->interrupt_request &= ~CPU_INTERRUPT_MCE;
 371                             do_interrupt(EXCP12_MCHK, 0, 0, 0, 0);
 372                             next_tb = 0;
 373                         } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 374                                    (((env->hflags2 & HF2_VINTR_MASK) &&
 375                                      (env->hflags2 & HF2_HIF_MASK)) ||
 376                                     (!(env->hflags2 & HF2_VINTR_MASK) &&
 377                                      (env->eflags & IF_MASK &&
 378                                       !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
 379                             int intno;
 380                             svm_check_intercept(SVM_EXIT_INTR);
 381                             env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
 382                             intno = cpu_get_pic_interrupt(env);
 383                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
 384 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
 385 #undef env
 386                     env = cpu_single_env;
 387 #define env cpu_single_env
 388 #endif
 389                             do_interrupt(intno, 0, 0, 0, 1);
 390                             /* ensure that no TB jump will be modified as
 391                                the program flow was changed */
 392                             next_tb = 0;
 393 #if !defined(CONFIG_USER_ONLY)
 394                         } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
 395                                    (env->eflags & IF_MASK) &&
 396                                    !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 397                             int intno;
 398                             /* FIXME: this should respect TPR */
 399                             svm_check_intercept(SVM_EXIT_VINTR);
 400                             intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
 401                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
 402                             do_interrupt(intno, 0, 0, 0, 1);
 403                             env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
 404                             next_tb = 0;
 405 #endif
 406                         }
 407                     }
 408 #elif defined(TARGET_PPC)
 409 #if 0
 410                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
 411                         cpu_reset(env);
 412                     }
 413 #endif
 414                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 415                         ppc_hw_interrupt(env);
 416                         if (env->pending_interrupts == 0)
 417                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 418                         next_tb = 0;
 419                     }
 420 #elif defined(TARGET_LM32)
 421                     if ((interrupt_request & CPU_INTERRUPT_HARD)
 422                         && (env->ie & IE_IE)) {
 423                         env->exception_index = EXCP_IRQ;
 424                         do_interrupt(env);
 425                         next_tb = 0;
 426                     }
 427 #elif defined(TARGET_MICROBLAZE)
 428                     if ((interrupt_request & CPU_INTERRUPT_HARD)
 429                         && (env->sregs[SR_MSR] & MSR_IE)
 430                         && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
 431                         && !(env->iflags & (D_FLAG | IMM_FLAG))) {
 432                         env->exception_index = EXCP_IRQ;
 433                         do_interrupt(env);
 434                         next_tb = 0;
 435                     }
 436 #elif defined(TARGET_MIPS)
 437                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 438                         cpu_mips_hw_interrupts_pending(env)) {
 439                         /* Raise it */
 440                         env->exception_index = EXCP_EXT_INTERRUPT;
 441                         env->error_code = 0;
 442                         do_interrupt(env);
 443                         next_tb = 0;
 444                     }
 445 #elif defined(TARGET_SPARC)
 446                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 447                         if (cpu_interrupts_enabled(env) &&
 448                             env->interrupt_index > 0) {
 449                             int pil = env->interrupt_index & 0xf;
 450                             int type = env->interrupt_index & 0xf0;
 451
 452                             if (((type == TT_EXTINT) &&
 453                                   cpu_pil_allowed(env, pil)) ||
 454                                   type != TT_EXTINT) {
 455                                 env->exception_index = env->interrupt_index;
 456                                 do_interrupt(env);
 457                                 next_tb = 0;
 458                             }
 459                         }
 460                     }
 461 #elif defined(TARGET_ARM)
 462                     if (interrupt_request & CPU_INTERRUPT_FIQ
 463                         && !(env->uncached_cpsr & CPSR_F)) {
 464                         env->exception_index = EXCP_FIQ;
 465                         do_interrupt(env);
 466                         next_tb = 0;
 467                     }
 468                     /* ARMv7-M interrupt return works by loading a magic value
 469                        into the PC.  On real hardware the load causes the
 470                        return to occur.  The qemu implementation performs the
 471                        jump normally, then does the exception return when the
 472                        CPU tries to execute code at the magic address.
 473                        This will cause the magic PC value to be pushed to
 474                        the stack if an interrupt occurred at the wrong time.
 475                        We avoid this by disabling interrupts when
 476                        pc contains a magic address.  */
 477                     if (interrupt_request & CPU_INTERRUPT_HARD
 478                         && ((IS_M(env) && env->regs[15] < 0xfffffff0)
 479                             || !(env->uncached_cpsr & CPSR_I))) {
 480                         env->exception_index = EXCP_IRQ;
 481                         do_interrupt(env);
 482                         next_tb = 0;
 483                     }
 484 #elif defined(TARGET_UNICORE32)
 485                     if (interrupt_request & CPU_INTERRUPT_HARD
 486                         && !(env->uncached_asr & ASR_I)) {
 487                         do_interrupt(env);
 488                         next_tb = 0;
 489                     }
 490 #elif defined(TARGET_SH4)
 491                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 492                         do_interrupt(env);
 493                         next_tb = 0;
 494                     }
 495 #elif defined(TARGET_ALPHA)
 496                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 497                         do_interrupt(env);
 498                         next_tb = 0;
 499                     }
 500 #elif defined(TARGET_CRIS)
 501                     if (interrupt_request & CPU_INTERRUPT_HARD
 502                         && (env->pregs[PR_CCS] & I_FLAG)
 503                         && !env->locked_irq) {
 504                         env->exception_index = EXCP_IRQ;
 505                         do_interrupt(env);
 506                         next_tb = 0;
 507                     }
 508                     if (interrupt_request & CPU_INTERRUPT_NMI
 509                         && (env->pregs[PR_CCS] & M_FLAG)) {
 510                         env->exception_index = EXCP_NMI;
 511                         do_interrupt(env);
 512                         next_tb = 0;
 513                     }
 514 #elif defined(TARGET_M68K)
 515                     if (interrupt_request & CPU_INTERRUPT_HARD
 516                         && ((env->sr & SR_I) >> SR_I_SHIFT)
 517                             < env->pending_level) {
 518                         /* Real hardware gets the interrupt vector via an
 519                            IACK cycle at this point.  Current emulated
 520                            hardware doesn't rely on this, so we
 521                            provide/save the vector when the interrupt is
 522                            first signalled.  */
 523                         env->exception_index = env->pending_vector;
 524                         do_interrupt(1);
 525                         next_tb = 0;
 526                     }
 527 #elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
 528                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 529                         (env->psw.mask & PSW_MASK_EXT)) {
 530                         do_interrupt(env);
 531                         next_tb = 0;
 532                     }
 533 #endif
 534                    /* Don't use the cached interrupt_request value,
 535                       do_interrupt may have updated the EXITTB flag. */
 536                     if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
 537                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 538                         /* ensure that no TB jump will be modified as
 539                            the program flow was changed */
 540                         next_tb = 0;
 541                     }
 542                 }
 543                 if (unlikely(env->exit_request)) {
 544                     env->exit_request = 0;
 545                     env->exception_index = EXCP_INTERRUPT;
 546                     cpu_loop_exit();
 547                 }
 548 #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
 549                 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
 550                     /* restore flags in standard format */
 551 #if defined(TARGET_I386)
 552                     env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
 553                     log_cpu_state(env, X86_DUMP_CCOP);
 554                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 555 #elif defined(TARGET_M68K)
 556                     cpu_m68k_flush_flags(env, env->cc_op);
 557                     env->cc_op = CC_OP_FLAGS;
 558                     env->sr = (env->sr & 0xffe0)
 559                               | env->cc_dest | (env->cc_x << 4);
 560                     log_cpu_state(env, 0);
 561 #else
 562                     log_cpu_state(env, 0);
 563 #endif
 564                 }
 565 #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
 566                 spin_lock(&tb_lock);
 567                 tb = tb_find_fast();
 568                 /* Note: we do it here to avoid a gcc bug on Mac OS X when
 569                    doing it in tb_find_slow */
 570                 if (tb_invalidated_flag) {
 571                     /* as some TB could have been invalidated because
 572                        of memory exceptions while generating the code, we
 573                        must recompute the hash index here */
 574                     next_tb = 0;
 575                     tb_invalidated_flag = 0;
 576                 }
 577 #ifdef CONFIG_DEBUG_EXEC
 578                 qemu_log_mask(CPU_LOG_EXEC, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
 579                              (long)tb->tc_ptr, tb->pc,
 580                              lookup_symbol(tb->pc));
 581 #endif
 582                 /* see if we can patch the calling TB. When the TB
 583                    spans two pages, we cannot safely do a direct
 584                    jump. */
 585                 if (next_tb != 0 && tb->page_addr[1] == -1) {
 586                     tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
 587                 }
 588                 spin_unlock(&tb_lock);
 589
 590                 /* cpu_interrupt might be called while translating the
 591                    TB, but before it is linked into a potentially
 592                    infinite loop and becomes env->current_tb. Avoid
 593                    starting execution if there is a pending interrupt. */
 594                 env->current_tb = tb;
 595                 barrier();
 596                 if (likely(!env->exit_request)) {
 597                     tc_ptr = tb->tc_ptr;
 598                 /* execute the generated code */
 599 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
 600 #undef env
 601                     env = cpu_single_env;
 602 #define env cpu_single_env
 603 #endif
 604                     next_tb = tcg_qemu_tb_exec(tc_ptr);
 605                     if ((next_tb & 3) == 2) {
 606                         /* Instruction counter expired.  */
 607                         int insns_left;
 608                         tb = (TranslationBlock *)(long)(next_tb & ~3);
 609                         /* Restore PC.  */
 610                         cpu_pc_from_tb(env, tb);
 611                         insns_left = env->icount_decr.u32;
 612                         if (env->icount_extra && insns_left >= 0) {
 613                             /* Refill decrementer and continue execution.  */
 614                             env->icount_extra += insns_left;
 615                             if (env->icount_extra > 0xffff) {
 616                                 insns_left = 0xffff;
 617                             } else {
 618                                 insns_left = env->icount_extra;
 619                             }
 620                             env->icount_extra -= insns_left;
 621                             env->icount_decr.u16.low = insns_left;
 622                         } else {
 623                             if (insns_left > 0) {
 624                                 /* Execute remaining instructions.  */
 625                                 cpu_exec_nocache(insns_left, tb);
 626                             }
 627                             env->exception_index = EXCP_INTERRUPT;
 628                             next_tb = 0;
 629                             cpu_loop_exit();
 630                         }
 631                     }
 632                 }
 633                 env->current_tb = NULL;
 634                 /* reset soft MMU for next block (it can currently
 635                    only be set by a memory fault) */
 636             } /* for(;;) */
 637         }
 638     } /* for(;;) */
 639
 640
 641 #if defined(TARGET_I386)
 642     /* restore flags in standard format */
 643     env->eflags = env->eflags | helper_cc_compute_all(CC_OP) | (DF & DF_MASK);
 644 #elif defined(TARGET_ARM)
 645     /* XXX: Save/restore host fpu exception state?.  */
 646 #elif defined(TARGET_UNICORE32)
 647 #elif defined(TARGET_SPARC)
 648 #elif defined(TARGET_PPC)
 649 #elif defined(TARGET_LM32)
 650 #elif defined(TARGET_M68K)
 651     cpu_m68k_flush_flags(env, env->cc_op);
 652     env->cc_op = CC_OP_FLAGS;
 653     env->sr = (env->sr & 0xffe0)
 654               | env->cc_dest | (env->cc_x << 4);
 655 #elif defined(TARGET_MICROBLAZE)
 656 #elif defined(TARGET_MIPS)
 657 #elif defined(TARGET_SH4)
 658 #elif defined(TARGET_IA64)
 659 #elif defined(TARGET_ALPHA)
 660 #elif defined(TARGET_CRIS)
 661 #elif defined(TARGET_S390X)
 662     /* XXXXX */
 663 #else
 664 #error unsupported target CPU
 665 #endif
 666
 667     /* restore global registers */
 668     barrier();
 669     env = (void *) saved_env_reg;
 670
 671     /* fail safe : never use cpu_single_env outside cpu_exec() */
 672     cpu_single_env = NULL;
 673     return ret;
 674 }