2 * Copyright 2010-2011 INRIA Saclay
3 * Copyright 2012 Ecole Normale Superieure
5 * Use of this software is governed by the GNU LGPLv2.1 license
7 * Written by Sven Verdoolaege, INRIA Saclay - Ile-de-France,
8 * Parc Club Orsay Universite, ZAC des vignes, 4 rue Jacques Monod,
10 * and Ecole Normale Superieure, 45 rue d’Ulm, 75230 Paris, France
16 #include <isl/polynomial.h>
17 #include <isl/union_set.h>
22 #include <isl/schedule.h>
23 #include <isl/options.h>
24 #include <isl/ast_build.h>
28 #include "ppcg_options.h"
30 /* The fields stride, shift and shift_map only contain valid information
32 * If so, they express that current index is such that if you add shift,
33 * then the result is always a multiple of stride.
34 * shift_map contains the mapping
36 * i -> (i + shift)/stride
38 * Let D represent the initial shared_len dimensions of the computed schedule.
39 * The spaces of "lb" and "shift" are of the form
43 * "shift_map" is of the form
45 * [D -> i] -> [D -> (i + shift(D))/stride]
47 struct gpu_array_bound
{
53 isl_basic_map
*shift_map
;
56 /* A tile of an array.
58 * n is the dimension of the array.
59 * bound is an array of size "n" representing the lower bound
60 * and size for each index.
62 struct gpu_array_tile
{
64 struct gpu_array_bound
*bound
;
67 struct gpu_array_info
;
69 /* A group of array references in a kernel that should be handled together.
70 * If private_tile is not NULL, then it is mapped to registers.
71 * Otherwise, if shared_tile is not NULL, it is mapped to shared memory.
72 * Otherwise, it is accessed from global memory.
74 struct gpu_array_ref_group
{
75 /* The references in this group access this array. */
76 struct gpu_array_info
*array
;
77 /* Position of this group in the list of reference groups of array. */
80 /* The following fields are use during the construction of the groups.
81 * access is the combined access relation relative to the shared
82 * memory tiling. In particular, the domain of the map corresponds
83 * to the first shared_len dimensions of the computed schedule.
84 * write is set if any access in the group is a write.
89 /* The shared memory tile, NULL if none. */
90 struct gpu_array_tile
*shared_tile
;
92 /* The private memory tile, NULL if none. */
93 struct gpu_array_tile
*private_tile
;
95 /* References in this group; point to elements of a linked list. */
97 struct gpu_stmt_access
**refs
;
99 /* Last shared memory tile dimension that affects tile of this group. */
105 struct ppcg_options
*options
;
107 struct gpu_prog
*prog
;
109 /* tile, grid and block sizes for each kernel */
110 isl_union_map
*sizes
;
112 /* Identifier of current kernel. */
114 /* Pointer to the current kernel. */
115 struct ppcg_kernel
*kernel
;
117 /* First tile dimension. */
119 /* Number of tile dimensions. */
121 /* Number of initial parallel loops among tile dimensions. */
124 /* Number of dimensions determining shared memory. */
127 /* Number of rows in the untiled schedule. */
129 /* Number of rows in the tiled schedule. */
131 /* Number of rows in schedule after tiling/wrapping over threads. */
132 int thread_tiled_len
;
134 /* Global untiled schedule. */
135 isl_union_map
*sched
;
136 /* Local (per kernel launch) tiled schedule. */
137 isl_union_map
*tiled_sched
;
138 /* Local schedule per shared memory tile loop iteration. */
139 isl_union_map
*local_sched
;
141 /* Local tiled schedule projected onto the shared tile loops and
142 * the loops that will be wrapped over the threads,
143 * with all shared tile loops parametrized.
145 isl_union_map
*shared_sched
;
146 /* Projects out the loops that will be wrapped over the threads
149 isl_union_map
*shared_proj
;
151 /* A map that takes the range of shared_sched as input,
152 * wraps the appropriate loops over the threads and then projects
155 isl_map
*privatization
;
157 /* A map from the shared memory tile loops and the thread indices
158 * (as parameters) to the set of accessed memory elements that
159 * will be accessed through private copies.
161 isl_union_map
*private_access
;
163 /* The schedule for the current private/shared access
164 * (within print_private_access or print_shared_access).
167 /* The array reference group corresponding to copy_sched. */
168 struct gpu_array_ref_group
*copy_group
;
170 /* First loop to unroll (or -1 if none) in the current part of the
177 /* Note: in the input file, the sizes of the grid and the blocks
178 * are specified in the order x, y, z, but internally, the sizes
179 * are stored in reverse order, so that the last element always
180 * refers to the x dimension.
187 /* Print the name of the local copy of a given group of array references.
189 static __isl_give isl_printer
*print_array_name(__isl_take isl_printer
*p
,
190 struct gpu_array_ref_group
*group
)
194 if (group
->private_tile
)
195 p
= isl_printer_print_str(p
, "private_");
196 else if (group
->shared_tile
)
197 p
= isl_printer_print_str(p
, "shared_");
200 p
= isl_printer_print_str(p
, group
->array
->name
);
201 if (!global
&& group
->array
->n_group
> 1) {
202 p
= isl_printer_print_str(p
, "_");
203 p
= isl_printer_print_int(p
, group
->nr
);
209 /* Collect all references to the given array and store pointers to them
212 static void collect_references(struct gpu_prog
*prog
,
213 struct gpu_array_info
*array
)
219 for (i
= 0; i
< prog
->n_stmts
; ++i
) {
220 struct gpu_stmt
*stmt
= &prog
->stmts
[i
];
221 struct gpu_stmt_access
*access
;
223 for (access
= stmt
->accesses
; access
; access
= access
->next
) {
225 name
= isl_map_get_tuple_name(access
->access
,
227 if (name
&& !strcmp(array
->name
, name
))
233 array
->refs
= isl_alloc_array(prog
->ctx
, struct gpu_stmt_access
*, n
);
237 for (i
= 0; i
< prog
->n_stmts
; ++i
) {
238 struct gpu_stmt
*stmt
= &prog
->stmts
[i
];
239 struct gpu_stmt_access
*access
;
241 for (access
= stmt
->accesses
; access
; access
= access
->next
) {
243 name
= isl_map_get_tuple_name(access
->access
,
245 if (!name
|| strcmp(array
->name
, name
))
248 array
->refs
[n
++] = access
;
253 /* Create a gpu_array_tile for an array of dimension "n_index".
255 static struct gpu_array_tile
*create_tile(isl_ctx
*ctx
, int n_index
)
258 struct gpu_array_tile
*tile
;
260 tile
= isl_calloc_type(ctx
, struct gpu_array_tile
);
265 tile
->bound
= isl_alloc_array(ctx
, struct gpu_array_bound
, n_index
);
268 for (i
= 0; i
< n_index
; ++i
) {
269 isl_int_init(tile
->bound
[i
].size
);
270 tile
->bound
[i
].lb
= NULL
;
271 isl_int_init(tile
->bound
[i
].stride
);
272 tile
->bound
[i
].shift
= NULL
;
273 tile
->bound
[i
].shift_map
= NULL
;
279 static void *free_tile(struct gpu_array_tile
*tile
)
286 for (j
= 0; j
< tile
->n
; ++j
) {
287 isl_int_clear(tile
->bound
[j
].size
);
288 isl_int_clear(tile
->bound
[j
].stride
);
289 isl_aff_free(tile
->bound
[j
].lb
);
290 isl_aff_free(tile
->bound
[j
].shift
);
291 isl_basic_map_free(tile
->bound
[j
].shift_map
);
299 static struct pet_array
*find_array(struct ppcg_scop
*scop
,
300 __isl_keep isl_set
*accessed
)
305 id
= isl_set_get_tuple_id(accessed
);
307 for (i
= 0; i
< scop
->n_array
; ++i
) {
310 id_i
= isl_set_get_tuple_id(scop
->arrays
[i
]->extent
);
317 return i
< scop
->n_array
? scop
->arrays
[i
] : NULL
;
320 /* Compute and return the extent of "array", taking into account the set of
323 * In particular, the extent in the outer dimension is taken
324 * from "accessed", while then extent in the remaing dimensions
325 * are taken from array->extent.
327 * The extent in the outer dimension cannot be taken from array->extent
328 * because that may be unbounded. Furthermore, even if it is bounded,
329 * it may be larger than the piece of the array that is being accessed.
331 static __isl_give isl_set
*compute_extent(struct pet_array
*array
,
332 __isl_keep isl_set
*accessed
)
339 extent
= isl_set_copy(array
->extent
);
341 n_index
= isl_set_dim(accessed
, isl_dim_set
);
345 extent
= isl_set_project_out(extent
, isl_dim_set
, 0, 1);
346 outer
= isl_set_copy(accessed
);
347 outer
= isl_set_project_out(outer
, isl_dim_set
, 1, n_index
- 1);
348 extent
= isl_set_flat_product(outer
, extent
);
349 id
= isl_set_get_tuple_id(accessed
);
350 extent
= isl_set_set_tuple_id(extent
, id
);
355 /* Compute bounds on the host arrays based on the accessed elements
356 * and collect all references to the array.
358 * If the array is zero-dimensional, i.e., a scalar, we check
359 * whether it is read-only.
361 static int extract_array_info(__isl_take isl_set
*array
, void *user
)
364 struct gpu_prog
*prog
= (struct gpu_prog
*)user
;
368 struct pet_array
*pa
;
371 n_index
= isl_set_dim(array
, isl_dim_set
);
372 name
= isl_set_get_tuple_name(array
);
373 bounds
= isl_alloc_array(isl_set_get_ctx(array
),
374 isl_pw_aff
*, n_index
);
376 prog
->array
[prog
->n_array
].dim
= isl_set_get_space(array
);
377 prog
->array
[prog
->n_array
].name
= strdup(name
);
378 prog
->array
[prog
->n_array
].n_index
= n_index
;
379 prog
->array
[prog
->n_array
].bound
= bounds
;
381 pa
= find_array(prog
->scop
, array
);
384 prog
->array
[prog
->n_array
].type
= strdup(pa
->element_type
);
385 prog
->array
[prog
->n_array
].size
= pa
->element_size
;
386 prog
->array
[prog
->n_array
].local
= pa
->declared
&& !pa
->exposed
;
390 isl_union_map
*write
;
393 write
= isl_union_map_copy(prog
->write
);
394 space
= isl_set_universe(isl_set_get_space(array
));
395 write
= isl_union_map_intersect_range(write
,
396 isl_union_set_from_set(space
));
397 empty
= isl_union_map_is_empty(write
);
398 isl_union_map_free(write
);
400 prog
->array
[prog
->n_array
].read_only
= empty
;
403 extent
= compute_extent(pa
, array
);
404 for (i
= 0; i
< n_index
; ++i
) {
410 bound
= isl_set_dim_max(isl_set_copy(extent
), i
);
412 dom
= isl_pw_aff_domain(isl_pw_aff_copy(bound
));
413 ls
= isl_local_space_from_space(isl_set_get_space(dom
));
414 one
= isl_aff_zero_on_domain(ls
);
415 one
= isl_aff_add_constant_si(one
, 1);
416 bound
= isl_pw_aff_add(bound
, isl_pw_aff_alloc(dom
, one
));
417 bound
= isl_pw_aff_gist(bound
, isl_set_copy(prog
->context
));
421 prog
->array
[prog
->n_array
].extent
= extent
;
423 collect_references(prog
, &prog
->array
[prog
->n_array
]);
431 void collect_array_info(struct gpu_prog
*prog
)
433 isl_union_set
*arrays
;
435 arrays
= isl_union_map_range(isl_union_map_copy(prog
->read
));
436 arrays
= isl_union_set_union(arrays
,
437 isl_union_map_range(isl_union_map_copy(prog
->write
)));
438 arrays
= isl_union_set_coalesce(arrays
);
440 prog
->n_array
= isl_union_set_n_set(arrays
);
441 prog
->array
= isl_alloc_array(prog
->ctx
,
442 struct gpu_array_info
, prog
->n_array
);
445 isl_union_set_foreach_set(arrays
, &extract_array_info
, prog
);
446 isl_union_set_free(arrays
);
449 static void free_array_info(struct gpu_prog
*prog
)
453 for (i
= 0; i
< prog
->n_array
; ++i
) {
454 int n_index
= prog
->array
[i
].n_index
;
455 free(prog
->array
[i
].type
);
456 free(prog
->array
[i
].name
);
457 for (j
= 0; j
< n_index
; ++j
)
458 isl_pw_aff_free(prog
->array
[i
].bound
[j
]);
459 isl_space_free(prog
->array
[i
].dim
);
460 isl_set_free(prog
->array
[i
].extent
);
461 free(prog
->array
[i
].bound
);
462 free(prog
->array
[i
].refs
);
467 /* Check if a gpu array is a scalar. A scalar is a value that is not stored
468 * as an array or through a pointer reference, but as single data element. At
469 * the moment, scalars are represented as zero dimensional arrays.
471 int gpu_array_is_scalar(struct gpu_array_info
*array
)
473 return (array
->n_index
== 0);
476 /* Is "array" a read-only scalar?
478 int gpu_array_is_read_only_scalar(struct gpu_array_info
*array
)
480 return gpu_array_is_scalar(array
) && array
->read_only
;
483 /* Internal data structure for extract_size_of_type.
484 * "type" specifies the name of the space that we want to extract.
485 * "res" is used to store the subset of that space.
487 struct ppcg_extract_size_data
{
492 /* This function is called for each set in a union_set.
493 * If the name of the set matches data->type, we store the
496 static int extract_size_of_type(__isl_take isl_set
*size
, void *user
)
498 struct ppcg_extract_size_data
*data
= user
;
501 name
= isl_set_get_tuple_name(size
);
502 if (name
&& !strcmp(name
, data
->type
)) {
511 /* Given a union map { kernel[i] -> *[...] },
512 * return the range in the space called "type" for the kernel with
513 * sequence number "id".
515 static __isl_give isl_set
*extract_sizes(__isl_keep isl_union_map
*sizes
,
516 const char *type
, int id
)
520 isl_union_set
*local_sizes
;
521 struct ppcg_extract_size_data data
= { type
, NULL
};
526 space
= isl_union_map_get_space(sizes
);
527 space
= isl_space_set_from_params(space
);
528 space
= isl_space_add_dims(space
, isl_dim_set
, 1);
529 space
= isl_space_set_tuple_name(space
, isl_dim_set
, "kernel");
530 dom
= isl_set_universe(space
);
531 dom
= isl_set_fix_si(dom
, isl_dim_set
, 0, id
);
533 local_sizes
= isl_union_set_apply(isl_union_set_from_set(dom
),
534 isl_union_map_copy(sizes
));
535 isl_union_set_foreach_set(local_sizes
, &extract_size_of_type
, &data
);
536 isl_union_set_free(local_sizes
);
540 /* Given a singleton set, extract the first (at most *len) elements
541 * of the single integer tuple into *sizes and update *len if needed.
543 static void read_sizes_from_set(__isl_take isl_set
*set
, int *sizes
, int *len
)
552 dim
= isl_set_dim(set
, isl_dim_set
);
558 for (i
= 0; i
< *len
; ++i
) {
561 ok
= isl_set_plain_is_fixed(set
, isl_dim_set
, i
, &v
);
564 sizes
[i
] = isl_int_get_si(v
);
572 /* Extract user specified "tile" sizes from the "sizes" command line option,
573 * defaulting to option->tile_size in each dimension.
575 static void read_tile_sizes(struct gpu_gen
*gen
)
580 gen
->tile_size
= isl_alloc_array(gen
->ctx
, int, gen
->tile_len
);
581 assert(gen
->tile_size
);
582 for (n
= 0; n
< gen
->tile_len
; ++n
)
583 gen
->tile_size
[n
] = gen
->options
->tile_size
;
585 size
= extract_sizes(gen
->sizes
, "tile", gen
->kernel_id
);
586 read_sizes_from_set(size
, gen
->tile_size
, &gen
->tile_len
);
588 if (gen
->n_parallel
> gen
->tile_len
)
589 gen
->n_parallel
= gen
->tile_len
;
592 /* Extract user specified "block" sizes from the "sizes" command line option,
593 * after filling in some potentially useful defaults.
595 static void read_block_sizes(struct gpu_gen
*gen
)
601 gen
->n_block
= (n
<= 3) ? n
: 3;
602 switch (gen
->n_block
) {
604 gen
->block_dim
[0] = 512;
607 gen
->block_dim
[0] = 32;
608 gen
->block_dim
[1] = 16;
611 gen
->block_dim
[0] = 32;
612 gen
->block_dim
[1] = 4;
613 gen
->block_dim
[2] = 4;
617 size
= extract_sizes(gen
->sizes
, "block", gen
->kernel_id
);
618 read_sizes_from_set(size
, gen
->block_dim
, &gen
->n_block
);
621 /* Extract user specified "grid" sizes from the "sizes" command line option,
622 * after filling in some potentially useful defaults.
624 static void read_grid_sizes(struct gpu_gen
*gen
)
626 int n
= gen
->n_parallel
;
629 gen
->n_grid
= (n
<= 2) ? n
: 2;
630 switch (gen
->n_grid
) {
632 gen
->grid_dim
[0] = 32768;
635 gen
->grid_dim
[0] = 256;
636 gen
->grid_dim
[1] = 256;
640 size
= extract_sizes(gen
->sizes
, "grid", gen
->kernel_id
);
641 read_sizes_from_set(size
, gen
->grid_dim
, &gen
->n_grid
);
644 /* Extract user specified sizes from the "sizes" command line option
645 * after filling in some potentially useful defaults.
647 static void read_sizes(struct gpu_gen
*gen
)
649 read_tile_sizes(gen
);
650 read_block_sizes(gen
);
651 read_grid_sizes(gen
);
654 static void free_stmts(struct gpu_stmt
*stmts
, int n
)
658 for (i
= 0; i
< n
; ++i
) {
659 struct gpu_stmt_access
*access
, *next
;
661 for (access
= stmts
[i
].accesses
; access
; access
= next
) {
663 isl_map_free(access
->access
);
667 isl_id_free(stmts
[i
].id
);
672 void clear_gpu_gen(struct gpu_gen
*gen
)
674 isl_union_map_free(gen
->sizes
);
675 isl_union_map_free(gen
->sched
);
678 /* Construct a map from a domain of dimensionality "len"
679 * to a domain of dimensionality "len" + "tile_len" that tiles
680 * the "tile_len" coordinates starting at "first".
681 * In particular, [s_i] -> [s_i / tile_size[i], s_i % tile_size[i]].
682 * "dim" prescribes the parameters.
684 static __isl_give isl_map
*tile(__isl_take isl_space
*dim
, int len
,
685 int first
, int tile_len
, int *tile_size
)
695 dim
= isl_space_add_dims(dim
, isl_dim_in
, len
);
696 dim
= isl_space_add_dims(dim
, isl_dim_out
, len
+ tile_len
);
697 bmap
= isl_basic_map_universe(isl_space_copy(dim
));
698 ls
= isl_local_space_from_space(dim
);
700 for (i
= 0; i
< len
- tile_len
; ++i
) {
701 int j
= i
< first
? i
: i
+ tile_len
;
702 int k
= i
< first
? i
: i
+ 2 * tile_len
;
704 c
= isl_equality_alloc(isl_local_space_copy(ls
));
705 isl_int_set_si(v
, -1);
706 c
= isl_constraint_set_coefficient(c
, isl_dim_in
, j
, v
);
707 isl_int_set_si(v
, 1);
708 c
= isl_constraint_set_coefficient(c
, isl_dim_out
, k
, v
);
709 bmap
= isl_basic_map_add_constraint(bmap
, c
);
712 for (i
= 0; i
< tile_len
; ++i
) {
713 c
= isl_equality_alloc(isl_local_space_copy(ls
));
714 isl_int_set_si(v
, -1);
715 c
= isl_constraint_set_coefficient(c
, isl_dim_in
, first
+ i
, v
);
716 isl_int_set_si(v
, tile_size
[i
]);
717 c
= isl_constraint_set_coefficient(c
, isl_dim_out
,
719 isl_int_set_si(v
, 1);
720 c
= isl_constraint_set_coefficient(c
, isl_dim_out
,
721 first
+ i
+ tile_len
, v
);
722 bmap
= isl_basic_map_add_constraint(bmap
, c
);
724 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
725 isl_int_set_si(v
, 1);
726 c
= isl_constraint_set_coefficient(c
, isl_dim_out
,
727 first
+ i
+ tile_len
, v
);
728 bmap
= isl_basic_map_add_constraint(bmap
, c
);
730 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
731 isl_int_set_si(v
, -1);
732 c
= isl_constraint_set_coefficient(c
, isl_dim_out
,
733 first
+ i
+ tile_len
, v
);
734 isl_int_set_si(v
, tile_size
[i
] - 1);
735 c
= isl_constraint_set_constant(c
, v
);
736 bmap
= isl_basic_map_add_constraint(bmap
, c
);
739 isl_local_space_free(ls
);
742 return isl_map_from_basic_map(bmap
);
745 /* Construct a map from a domain of dimensionality "len"
746 * to a domain of dimensionality "len" + "wrap_len" that "wraps"
747 * the "wrap_len" coordinates starting at "first" according to "wrap_size".
748 * In particular, [s_i] -> [s_i, s_i % wrap_size[i]].
749 * To do so, we need extra variables corresponding to [s_i / wrap_size[i]],
750 * that are projected out at the end.
751 * "dim" prescribes the parameters.
753 static __isl_give isl_map
*wrap(__isl_take isl_space
*dim
, int len
,
754 int first
, int wrap_len
, int *wrap_size
)
761 dim
= isl_space_add_dims(dim
, isl_dim_in
, len
);
762 dim
= isl_space_add_dims(dim
, isl_dim_out
, len
+ 2 * wrap_len
);
763 bmap
= isl_basic_map_universe(isl_space_copy(dim
));
764 ls
= isl_local_space_from_space(dim
);
766 for (i
= 0; i
< len
; ++i
) {
767 int k
= i
< first
+ wrap_len
? i
: i
+ 2 * wrap_len
;
769 c
= isl_equality_alloc(isl_local_space_copy(ls
));
770 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, -1);
771 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, k
, 1);
772 bmap
= isl_basic_map_add_constraint(bmap
, c
);
775 for (i
= 0; i
< wrap_len
; ++i
) {
776 c
= isl_equality_alloc(isl_local_space_copy(ls
));
777 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
779 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
780 first
+ wrap_len
+ i
, 1);
781 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
782 first
+ 2 * wrap_len
+ i
, wrap_size
[i
]);
783 bmap
= isl_basic_map_add_constraint(bmap
, c
);
785 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
786 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
787 first
+ wrap_len
+ i
, 1);
788 bmap
= isl_basic_map_add_constraint(bmap
, c
);
790 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
791 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
,
792 first
+ wrap_len
+ i
, -1);
793 c
= isl_constraint_set_constant_si(c
, wrap_size
[i
] - 1);
794 bmap
= isl_basic_map_add_constraint(bmap
, c
);
797 isl_local_space_free(ls
);
799 bmap
= isl_basic_map_project_out(bmap
, isl_dim_out
,
800 first
+ 2 * wrap_len
, wrap_len
);
802 return isl_map_from_basic_map(bmap
);
805 /* Add "n" parameters named prefix%d.
807 static __isl_give isl_set
*add_params( __isl_take isl_set
*set
,
808 int n
, const char *prefix
)
814 nparam
= isl_set_dim(set
, isl_dim_param
);
815 set
= isl_set_add_dims(set
, isl_dim_param
, n
);
817 for (i
= 0; i
< n
; ++i
) {
818 snprintf(name
, sizeof(name
), "%s%d", prefix
, i
);
819 set
= isl_set_set_dim_name(set
, isl_dim_param
,
826 /* Equate the "n" dimensions of "set" starting at "first" to
827 * freshly created parameters named prefix%d.
829 static __isl_give isl_set
*parametrize(__isl_take isl_set
*set
,
830 int first
, int n
, const char *prefix
)
840 nparam
= isl_set_dim(set
, isl_dim_param
);
842 set
= add_params(set
, n
, prefix
);
844 dim
= isl_set_get_space(set
);
845 bset
= isl_basic_set_universe(isl_space_copy(dim
));
846 ls
= isl_local_space_from_space(dim
);
850 for (i
= 0; i
< n
; ++i
) {
851 c
= isl_equality_alloc(isl_local_space_copy(ls
));
852 isl_int_set_si(v
, -1);
853 c
= isl_constraint_set_coefficient(c
, isl_dim_param
,
855 isl_int_set_si(v
, 1);
856 c
= isl_constraint_set_coefficient(c
, isl_dim_set
, first
+ i
,
858 bset
= isl_basic_set_add_constraint(bset
, c
);
862 isl_local_space_free(ls
);
864 return isl_set_intersect(set
, isl_set_from_basic_set(bset
));
867 /* Given a parameter space "space", create a set of dimension "len"
868 * of which the "n" dimensions starting at "first" are equated to
869 * freshly created parameters named prefix%d.
871 static __isl_give isl_set
*parametrization(__isl_take isl_space
*space
,
872 int len
, int first
, int n
, const char *prefix
)
876 space
= isl_space_set_from_params(space
);
877 space
= isl_space_add_dims(space
, isl_dim_set
, len
);
878 set
= isl_set_universe(space
);
880 return parametrize(set
, first
, n
, prefix
);
883 /* Tile the B loops over the tile sizes and then tile/wrap
884 * the T1 loops over the blocks.
886 static __isl_give isl_union_map
*tile_schedule(struct gpu_gen
*gen
,
887 __isl_take isl_union_map
*sched
)
890 isl_map
*tiling
, *block_tiling
;
892 dim
= isl_union_map_get_space(sched
);
893 tiling
= tile(isl_space_copy(dim
), gen
->untiled_len
,
894 gen
->tile_first
, gen
->tile_len
, gen
->tile_size
);
896 if (gen
->options
->wrap
)
897 block_tiling
= wrap(dim
, gen
->untiled_len
+ gen
->tile_len
,
898 gen
->tile_first
, gen
->n_grid
, gen
->grid_dim
);
900 block_tiling
= tile(dim
, gen
->untiled_len
+ gen
->tile_len
,
901 gen
->tile_first
, gen
->n_grid
, gen
->grid_dim
);
903 gen
->tiled_len
= gen
->untiled_len
+ gen
->tile_len
+ gen
->n_grid
;
905 tiling
= isl_map_apply_range(tiling
, block_tiling
);
907 sched
= isl_union_map_apply_range(sched
,
908 isl_union_map_from_map(tiling
));
910 gen
->shared_len
= gen
->tile_first
+ gen
->tile_len
+ gen
->n_grid
;
915 /* Equate the "T1P" iterators in the tiled schedule "sched"
916 * to the block dimensions.
918 static __isl_give isl_union_map
*parametrize_tiled_schedule(
919 struct gpu_gen
*gen
, __isl_take isl_union_map
*sched
)
924 dim
= isl_union_map_get_space(sched
);
925 par
= parametrization(dim
, gen
->tiled_len
,
926 gen
->tile_first
+ gen
->n_grid
, gen
->n_grid
, "b");
927 sched
= isl_union_map_intersect_range(sched
,
928 isl_union_set_from_set(par
));
933 /* Tile/wrap the P1 loops over the threads.
935 static __isl_give isl_union_map
*thread_tile_schedule(struct gpu_gen
*gen
,
936 __isl_take isl_union_map
*sched
)
942 dim
= isl_union_map_get_space(sched
);
944 if (gen
->options
->wrap
)
945 tiling
= wrap(isl_space_copy(dim
), gen
->tiled_len
,
946 gen
->shared_len
, gen
->n_block
, gen
->block_dim
);
948 tiling
= tile(isl_space_copy(dim
), gen
->tiled_len
,
949 gen
->shared_len
, gen
->n_block
, gen
->block_dim
);
950 gen
->thread_tiled_len
= gen
->tiled_len
+ gen
->n_block
;
952 sched
= isl_union_map_apply_range(sched
,
953 isl_union_map_from_map(tiling
));
955 par
= parametrization(dim
, gen
->thread_tiled_len
,
956 gen
->tile_first
+ gen
->tile_len
+ gen
->n_grid
+ gen
->n_block
,
958 sched
= isl_union_map_intersect_range(sched
,
959 isl_union_set_from_set(par
));
961 gen
->shared_len
= gen
->tile_first
+ gen
->tile_len
+ gen
->n_grid
;
966 /* If the user asked for it, scale the shared memory tile loops
967 * (T1T and T2) of "sched" by gen->tile_size[i].
968 * If we are not performing "wrapping", then additionally scale the T1P
969 * loops by gen->grid_dim[i].
971 static __isl_give isl_union_map
*scale_tile_loops(struct gpu_gen
*gen
,
972 __isl_take isl_union_map
*sched
)
976 isl_basic_map
*scale
;
980 if (!gen
->options
->scale_tile_loops
)
983 dim
= isl_union_map_get_space(sched
);
984 dim
= isl_space_add_dims(dim
, isl_dim_in
, gen
->tiled_len
);
985 dim
= isl_space_add_dims(dim
, isl_dim_out
, gen
->tiled_len
);
986 scale
= isl_basic_map_universe(isl_space_copy(dim
));
987 ls
= isl_local_space_from_space(dim
);
989 for (i
= 0; i
< gen
->tiled_len
; ++i
) {
992 if (i
>= gen
->tile_first
&& i
< gen
->tile_first
+ gen
->n_grid
) {
993 f
= gen
->tile_size
[i
- gen
->tile_first
];
994 if (!gen
->options
->wrap
)
995 f
*= gen
->grid_dim
[i
- gen
->tile_first
];
996 } else if (i
>= gen
->tile_first
+ gen
->n_grid
&&
997 i
< gen
->tile_first
+ gen
->n_grid
+ gen
->tile_len
) {
998 f
= gen
->tile_size
[i
- (gen
->tile_first
+ gen
->n_grid
)];
1001 c
= isl_equality_alloc(isl_local_space_copy(ls
));
1002 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, f
);
1003 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
1004 scale
= isl_basic_map_add_constraint(scale
, c
);
1007 isl_local_space_free(ls
);
1009 sched
= isl_union_map_apply_range(sched
,
1010 isl_union_map_from_map(isl_map_from_basic_map(scale
)));
1015 /* If we are not performing "wrapping" and if the user asked for it,
1016 * scale the thread tile loops (P1T) of "sched" by gen->block_dim[i].
1018 static __isl_give isl_union_map
*scale_thread_tile_loops(struct gpu_gen
*gen
,
1019 __isl_take isl_union_map
*sched
)
1023 isl_basic_map
*scale
;
1025 isl_local_space
*ls
;
1027 if (gen
->options
->wrap
)
1029 if (!gen
->options
->scale_tile_loops
)
1032 dim
= isl_union_map_get_space(sched
);
1033 dim
= isl_space_add_dims(dim
, isl_dim_in
, gen
->thread_tiled_len
);
1034 dim
= isl_space_add_dims(dim
, isl_dim_out
, gen
->thread_tiled_len
);
1035 scale
= isl_basic_map_universe(isl_space_copy(dim
));
1036 ls
= isl_local_space_from_space(dim
);
1038 for (i
= 0; i
< gen
->thread_tiled_len
; ++i
) {
1041 if (i
>= gen
->shared_len
&&
1042 i
< gen
->shared_len
+ gen
->n_block
)
1043 f
= gen
->block_dim
[i
- gen
->shared_len
];
1045 c
= isl_equality_alloc(isl_local_space_copy(ls
));
1046 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, f
);
1047 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
1048 scale
= isl_basic_map_add_constraint(scale
, c
);
1051 isl_local_space_free(ls
);
1053 sched
= isl_union_map_apply_range(sched
,
1054 isl_union_map_from_map(isl_map_from_basic_map(scale
)));
1059 /* If we are not performing "wrapping" and if the user asked for it,
1060 * scale the "n_tile" loops starting at "first" of "sched" by gen->block_dim[i].
1062 static __isl_give isl_union_map
*scale_access_tile_loops(struct gpu_gen
*gen
,
1063 __isl_take isl_union_map
*sched
, int len
, int first
, int n_tile
)
1067 isl_basic_map
*scale
;
1069 isl_local_space
*ls
;
1071 if (gen
->options
->wrap
)
1073 if (!gen
->options
->scale_tile_loops
)
1076 dim
= isl_union_map_get_space(sched
);
1077 dim
= isl_space_add_dims(dim
, isl_dim_in
, len
);
1078 dim
= isl_space_add_dims(dim
, isl_dim_out
, len
);
1079 scale
= isl_basic_map_universe(isl_space_copy(dim
));
1080 ls
= isl_local_space_from_space(dim
);
1082 for (i
= 0; i
< len
; ++i
) {
1085 if (i
>= first
&& i
< first
+ n_tile
)
1086 f
= gen
->block_dim
[i
- first
];
1088 c
= isl_equality_alloc(isl_local_space_copy(ls
));
1089 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, f
);
1090 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
1091 scale
= isl_basic_map_add_constraint(scale
, c
);
1094 isl_local_space_free(ls
);
1096 sched
= isl_union_map_apply_range(sched
,
1097 isl_union_map_from_map(isl_map_from_basic_map(scale
)));
1102 /* Add "len" parameters p[i] called prefix%d,
1103 * with bounds to 0 <= p[i] < size[i].
1105 __isl_give isl_set
*add_bounded_parameters(__isl_take isl_set
*set
,
1106 int len
, int *size
, const char *prefix
)
1112 isl_basic_set
*bset
;
1114 isl_local_space
*ls
;
1117 nparam
= isl_set_dim(set
, isl_dim_param
);
1118 set
= isl_set_add_dims(set
, isl_dim_param
, len
);
1120 for (i
= 0; i
< len
; ++i
) {
1121 snprintf(name
, sizeof(name
), "%s%d", prefix
, i
);
1122 set
= isl_set_set_dim_name(set
, isl_dim_param
,
1126 dim
= isl_set_get_space(set
);
1127 bset
= isl_basic_set_universe(isl_space_copy(dim
));
1128 ls
= isl_local_space_from_space(dim
);
1132 for (i
= 0; i
< len
; ++i
) {
1133 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
1134 isl_int_set_si(v
, 1);
1135 c
= isl_constraint_set_coefficient(c
, isl_dim_param
, nparam
+ i
,
1137 bset
= isl_basic_set_add_constraint(bset
, c
);
1139 c
= isl_inequality_alloc(isl_local_space_copy(ls
));
1140 isl_int_set_si(v
, -1);
1141 c
= isl_constraint_set_coefficient(c
, isl_dim_param
, nparam
+ i
,
1143 isl_int_set_si(v
, size
[i
] - 1);
1144 c
= isl_constraint_set_constant(c
, v
);
1145 bset
= isl_basic_set_add_constraint(bset
, c
);
1149 isl_local_space_free(ls
);
1151 return isl_set_intersect(set
, isl_set_from_basic_set(bset
));
1154 /* Add "len" parameters p[i] called prefix%d,
1155 * with bounds to 0 <= p[i] < size[i].
1157 static __isl_give isl_set
*add_bounded_parameters_dynamic(
1158 __isl_take isl_set
*set
, __isl_keep isl_multi_pw_aff
*size
,
1164 isl_local_space
*ls
;
1167 len
= isl_multi_pw_aff_dim(size
, isl_dim_out
);
1168 nparam
= isl_set_dim(set
, isl_dim_param
);
1169 set
= isl_set_add_dims(set
, isl_dim_param
, len
);
1171 for (i
= 0; i
< len
; ++i
) {
1172 snprintf(name
, sizeof(name
), "%s%d", prefix
, i
);
1173 set
= isl_set_set_dim_name(set
, isl_dim_param
,
1177 space
= isl_space_params(isl_set_get_space(set
));
1178 ls
= isl_local_space_from_space(space
);
1179 for (i
= 0; i
< len
; ++i
) {
1180 isl_pw_aff
*param
, *size_i
, *zero
;
1183 param
= isl_pw_aff_var_on_domain(isl_local_space_copy(ls
),
1184 isl_dim_param
, nparam
+ i
);
1186 size_i
= isl_multi_pw_aff_get_pw_aff(size
, i
);
1187 bound
= isl_pw_aff_lt_set(isl_pw_aff_copy(param
), size_i
);
1188 set
= isl_set_intersect_params(set
, bound
);
1190 zero
= isl_pw_aff_zero_on_domain(isl_local_space_copy(ls
));
1191 bound
= isl_pw_aff_ge_set(param
, zero
);
1192 set
= isl_set_intersect_params(set
, bound
);
1194 isl_local_space_free(ls
);
1199 /* Given a mapping "sched" of the form
1201 * [D -> A] -> [D -> T(A)]
1203 * apply the mapping encoded in tile->bound[i].shift_map
1204 * to the range of "sched".
1205 * The mappings in tile->bound[i].shift_map are of the form
1207 * [D -> a] -> [D -> s(D,a)]
1209 * We first compose them with a mapping
1213 * (If tile->bound[i].shift_map is not set, then it is assumed to be
1214 * an identity mapping and then we use this second mapping instead.)
1217 * [D -> a] -> s(D,a)
1219 * We precompose them with a projection on the i th dimension to obtain
1221 * [D -> T] -> s(D,T)
1223 * and collect these into
1225 * [D -> T] -> S(D,T)
1227 * Introducing D in the range yields
1229 * [D -> T] -> [D -> S(D,T)]
1231 * and application to "sched" yields
1233 * [D -> A] -> [D -> S(D,T(A))]
1235 static __isl_give isl_map
*pre_shift(__isl_take isl_map
*sched
,
1236 struct gpu_array_tile
*tile
)
1239 isl_ctx
*ctx
= isl_map_get_ctx(sched
);
1240 isl_space
*space
, *space2
;
1242 isl_map
*map
, *id
, *pre_shift
;
1244 space
= isl_space_range(isl_map_get_space(sched
));
1245 space2
= isl_space_from_domain(isl_space_copy(space
));
1246 pre_shift
= isl_map_universe(space2
);
1247 space
= isl_space_domain(isl_space_unwrap(space
));
1248 id
= isl_map_identity(isl_space_map_from_set(isl_space_copy(space
)));
1249 space
= isl_space_from_domain(space
);
1250 space
= isl_space_add_dims(space
, isl_dim_out
, 1);
1251 def
= isl_basic_map_range_map(isl_basic_map_universe(space
));
1253 for (i
= 0; i
< tile
->n
; ++i
) {
1254 isl_basic_map
*bmap
, *drop
;
1257 space
= isl_space_alloc(ctx
, 0, tile
->n
, tile
->n
);
1258 proj
= isl_map_identity(space
);
1259 proj
= isl_map_project_out(proj
, isl_dim_out
,
1260 i
+ 1, tile
->n
- (i
+ 1));
1261 proj
= isl_map_project_out(proj
, isl_dim_out
, 0, i
);
1262 proj
= isl_map_product(isl_map_copy(id
), proj
);
1264 if (!tile
->bound
[i
].shift_map
)
1265 bmap
= isl_basic_map_copy(def
);
1267 bmap
= isl_basic_map_copy(tile
->bound
[i
].shift_map
);
1268 bmap
= isl_basic_map_apply_range(bmap
,
1269 isl_basic_map_copy(def
));
1272 map
= isl_map_from_basic_map(bmap
);
1273 map
= isl_map_apply_range(proj
, map
);
1274 pre_shift
= isl_map_flat_range_product(pre_shift
, map
);
1278 isl_basic_map_free(def
);
1280 space
= isl_space_domain(isl_map_get_space(pre_shift
));
1281 map
= isl_map_domain_map(isl_map_universe(isl_space_unwrap(space
)));
1282 pre_shift
= isl_map_range_product(map
, pre_shift
);
1284 sched
= isl_map_apply_range(sched
, pre_shift
);
1289 /* Given an access relation to a tile of an array, construct a map that
1290 * maps each element in the space of the access relation
1291 * to a copy of the tile shifted to the origin
1292 * (based on the lower bounds in group->private_tile or group->shared_tile).
1293 * If any of the indices is strided, then
1294 * {private,shared}_tile->bound[i].shift_map is applied to the index first.
1295 * The domain space of the resulting map is that of access "access",
1296 * while the range space is anonymous.
1297 * The resulting map only encodes the mapping to the shift tile and
1298 * not the constraints of "access".
1300 * Let the space of the access relation be
1304 * We first construct an identity relation on a wrapped copy of this space,
1305 * except that it strips off the name of array
1307 * [D -> A] -> [D -> T(A)] (1)
1309 * The bounds in tile->bound[i].lb are of the form
1313 * We collect them into
1317 * and then transform them into
1319 * [D -> T] -> T - B(D) (2)
1321 * Combining those two mappings (1) and (2) yields
1323 * [D -> A] -> T(A) - B(D)
1325 * If there are any strides, then (1) is first transformed into (1')
1327 * [D -> A] -> [D -> T'(A)] (1')
1329 * by a call to pre_shift.
1331 static __isl_give isl_map
*shift_access(__isl_take isl_map
*access
,
1332 struct gpu_array_ref_group
*group
)
1340 struct gpu_array_tile
*tile
;
1341 int n_index
= group
->array
->n_index
;
1343 tile
= group
->private_tile
;
1345 tile
= group
->shared_tile
;
1347 space
= isl_space_domain(isl_map_get_space(access
));
1348 space
= isl_space_map_from_set(space
);
1349 id1
= isl_map_identity(space
);
1350 space
= isl_space_range(isl_map_get_space(access
));
1351 space
= isl_space_map_from_set(space
);
1352 space
= isl_space_set_tuple_name(space
, isl_dim_out
, NULL
);
1353 id2
= isl_map_identity(space
);
1354 sched
= isl_map_product(id1
, id2
);
1356 space
= isl_space_unwrap(isl_space_range(isl_map_get_space(sched
)));
1357 space
= isl_space_from_domain(isl_space_domain(space
));
1358 shift
= isl_map_universe(space
);
1359 for (i
= 0; i
< n_index
; ++i
) {
1360 map
= isl_map_from_aff(isl_aff_copy(tile
->bound
[i
].lb
));
1361 shift
= isl_map_flat_range_product(shift
, map
);
1364 space
= isl_space_unwrap(isl_space_range(isl_map_get_space(sched
)));
1365 map
= isl_map_universe(space
);
1366 id1
= isl_map_range_map(isl_map_copy(map
));
1367 map
= isl_map_domain_map(map
);
1368 shift
= isl_map_neg(shift
);
1369 shift
= isl_map_apply_range(map
, shift
);
1370 shift
= isl_map_sum(id1
, shift
);
1372 for (i
= 0; i
< n_index
; ++i
)
1373 if (tile
->bound
[i
].shift_map
)
1377 sched
= pre_shift(sched
, tile
);
1379 sched
= isl_map_apply_range(sched
, shift
);
1381 isl_map_free(access
);
1386 /* Given a schedule that iterates over all elements in a piece of an array,
1387 * perform tiling/wrapping over the threads.
1389 * In particular, we tile the final iterators so that the final thread
1390 * dimension runs over the final array dimension.
1391 * However, if those final iterators have only a single iteration,
1392 * we try to tile earlier iterators instead.
1394 static __isl_give isl_map
*tile_access_schedule(struct gpu_gen
*gen
,
1395 __isl_take isl_map
*sched
)
1398 isl_union_map
*usched
;
1401 unsigned nvar
= isl_map_dim(sched
, isl_dim_out
);
1405 n_tile
= gen
->n_block
;
1406 if (n_tile
> nvar
) {
1408 sched
= isl_map_insert_dims(sched
,
1409 isl_dim_out
, 0, n_tile
- nvar
);
1410 for (i
= 0; i
< n_tile
- nvar
; ++i
)
1411 sched
= isl_map_fix_si(sched
, isl_dim_out
, i
, 0);
1415 first
= nvar
- n_tile
;
1417 for (; first
> 0; first
--)
1418 if (!isl_map_plain_is_fixed(sched
, isl_dim_out
,
1419 first
+ n_tile
- 1, NULL
))
1422 dim
= isl_map_get_space(sched
);
1423 dim
= isl_space_params(dim
);
1424 if (gen
->options
->wrap
)
1425 tiling
= wrap(isl_space_copy(dim
), nvar
, first
,
1426 n_tile
, gen
->block_dim
);
1428 tiling
= tile(isl_space_copy(dim
), nvar
, first
,
1429 n_tile
, gen
->block_dim
);
1430 sched
= isl_map_apply_range(sched
, tiling
);
1432 par
= parametrization(dim
, nvar
+ n_tile
, first
+ n_tile
, n_tile
, "t");
1433 sched
= isl_map_intersect_range(sched
, par
);
1435 usched
= isl_union_map_from_map(sched
);
1436 usched
= scale_access_tile_loops(gen
, usched
, nvar
+ n_tile
,
1438 sched
= isl_map_from_union_map(usched
);
1443 /* Given an index expression "pa" into a tile of an array, adjust the expression
1444 * to a shift of the tile to the origin
1445 * (based on the lower bounds in "bound".
1446 * If the index is strided, then we first add
1447 * bound->shift and divide by bound->stride.
1448 * In the end, we compute the gist with respect to "domain".
1450 * All of the input expression "pa", the set "domain" and
1451 * the output are expressed in terms of the AST schedule domain.
1452 * The expressions in "bound" are expressed
1453 * in terms of the first shared_len dimensions of the schedule computed by PPCG.
1454 * The mapping "sched2shared" maps the former domain to the latter domain.
1456 static __isl_give isl_pw_aff
*shift_index(__isl_take isl_pw_aff
*pa
,
1457 struct gpu_array_info
*array
,
1458 struct gpu_array_bound
*bound
, __isl_take isl_set
*domain
,
1459 __isl_take isl_map
*sched2shared
)
1463 isl_pw_multi_aff
*pma
;
1466 map
= isl_map_from_aff(isl_aff_copy(bound
->shift
));
1467 map
= isl_map_apply_range(isl_map_copy(sched2shared
), map
);
1468 pma
= isl_pw_multi_aff_from_map(map
);
1469 tmp
= isl_pw_multi_aff_get_pw_aff(pma
, 0);
1470 isl_pw_multi_aff_free(pma
);
1471 pa
= isl_pw_aff_add(pa
, tmp
);
1472 pa
= isl_pw_aff_scale_down(pa
, bound
->stride
);
1476 map
= isl_map_from_aff(isl_aff_copy(bound
->lb
));
1477 map
= isl_map_apply_range(sched2shared
, map
);
1478 pma
= isl_pw_multi_aff_from_map(map
);
1479 tmp
= isl_pw_multi_aff_get_pw_aff(pma
, 0);
1480 isl_pw_multi_aff_free(pma
);
1481 pa
= isl_pw_aff_sub(pa
, tmp
);
1482 pa
= isl_pw_aff_coalesce(pa
);
1483 pa
= isl_pw_aff_gist(pa
, domain
);
1488 /* Return the union of all read (read = 1) and/or write (write = 1)
1489 * access relations in the group.
1491 static __isl_give isl_union_map
*group_access_relation(
1492 struct gpu_array_ref_group
*group
, int read
, int write
)
1495 isl_union_map
*access
;
1497 access
= isl_union_map_empty(isl_map_get_space(group
->access
));
1498 for (i
= 0; i
< group
->n_ref
; ++i
) {
1501 if (!((read
&& group
->refs
[i
]->read
) ||
1502 (write
&& group
->refs
[i
]->write
)))
1504 map_i
= isl_map_copy(group
->refs
[i
]->access
);
1505 access
= isl_union_map_union(access
,
1506 isl_union_map_from_map(map_i
));
1512 /* Return a map from the first shared_len dimensions of the computed
1513 * schedule to the values of the given index "i"
1514 * of the elements in the array tile in global memory that corresponds
1515 * to the shared memory copy.
1516 * In particular, if a is the index, then the range of the map
1520 * is constrained as follows
1522 * tile_offset(D) <= a <= tile_offset(D) + tile_size - 1 (1)
1526 * 0 <= a <= array_size - 1 (2)
1529 * Note that if some stride has been detected (i.e., when
1530 * group->shared_tile->bound[i].shift is set), then offset and size (i.e.,
1531 * constraints (1)) apply to the shifted and scaled down copy of the tile.
1532 * These constraints therefore have to be mapped back to the original
1533 * array space using the inverse of the shift_map.
1535 static __isl_give isl_map
*group_tile_dim(struct gpu_array_ref_group
*group
,
1540 isl_map
*map
, *tile
, *gt
;
1543 map
= isl_map_from_aff(isl_aff_copy(group
->shared_tile
->bound
[i
].lb
));
1544 space
= isl_space_range(isl_map_get_space(map
));
1545 map
= isl_map_apply_range(map
, isl_map_lex_le(isl_space_copy(space
)));
1548 aff
= isl_aff_copy(group
->shared_tile
->bound
[i
].lb
);
1549 aff
= isl_aff_add_constant(aff
, group
->shared_tile
->bound
[i
].size
);
1550 map
= isl_map_from_aff(aff
);
1551 gt
= isl_map_lex_gt(space
);
1552 map
= isl_map_apply_range(map
, isl_map_copy(gt
));
1553 tile
= isl_map_intersect(tile
, map
);
1555 if (group
->shared_tile
->bound
[i
].shift
) {
1556 isl_basic_map
*shift
;
1557 shift
= isl_basic_map_copy(group
->shared_tile
->bound
[i
].shift_map
);
1558 shift
= isl_basic_map_reverse(shift
);
1559 tile
= isl_set_unwrap(isl_set_apply(isl_map_wrap(tile
),
1560 isl_map_from_basic_map(shift
)));
1563 tile
= isl_map_lower_bound_si(tile
, isl_dim_out
, 0, 0);
1565 bound
= isl_set_from_pw_aff(isl_pw_aff_copy(group
->array
->bound
[i
]));
1566 bound
= isl_set_apply(bound
, gt
);
1567 tile
= isl_map_intersect_range(tile
, bound
);
1572 /* Return a map from the first shared_len dimensions of the computed
1573 * schedule to the array tile in
1574 * global memory that corresponds to the shared memory copy.
1576 static __isl_give isl_map
*group_tile(struct gpu_array_ref_group
*group
)
1579 int n_index
= group
->array
->n_index
;
1582 tile
= group_tile_dim(group
, 0);
1583 for (i
= 1; i
< n_index
; ++i
) {
1586 tile_i
= group_tile_dim(group
, i
);
1587 tile
= isl_map_flat_range_product(tile
, tile_i
);
1590 tile
= isl_map_set_tuple_name(tile
, isl_dim_out
, group
->array
->name
);
1595 /* Given a mapping "sched" from the AST schedule to a domain,
1596 * return the corresponding mapping from the AST schedule to
1597 * to the first shared_len dimensions of the schedule computed by PPCG.
1599 static __isl_give isl_map
*compute_sched_to_shared(struct gpu_gen
*gen
,
1600 __isl_take isl_map
*sched
)
1602 isl_union_map
*umap
;
1606 space
= isl_space_range(isl_map_get_space(sched
));
1607 space
= isl_space_from_domain(space
);
1608 space
= isl_space_add_dims(space
, isl_dim_out
, gen
->shared_len
);
1610 umap
= isl_union_map_copy(gen
->shared_sched
);
1611 umap
= isl_union_map_apply_range(umap
,
1612 isl_union_map_copy(gen
->shared_proj
));
1613 map
= isl_union_map_extract_map(umap
, space
);
1614 isl_union_map_free(umap
);
1616 sched
= isl_map_apply_range(sched
, map
);
1617 sched
= isl_map_detect_equalities(sched
);
1622 /* Set unroll[j] if the input dimension j is involved in
1623 * the index expression represented by ma.
1625 static int check_unroll(__isl_take isl_set
*set
, __isl_take isl_multi_aff
*ma
,
1629 int n_in
= isl_multi_aff_dim(ma
, isl_dim_in
);
1630 int n_out
= isl_multi_aff_dim(ma
, isl_dim_out
);
1633 for (i
= 0; i
< n_out
; ++i
) {
1636 aff
= isl_multi_aff_get_aff(ma
, i
);
1637 for (j
= 0; j
< n_in
; ++j
)
1638 if (isl_aff_involves_dims(aff
, isl_dim_in
, j
, 1))
1644 isl_multi_aff_free(ma
);
1648 /* Given an array pos mapping input dimensions to the corresponding
1649 * output dimension, construct the corresponding map.
1651 static __isl_give isl_map
*permutation(__isl_take isl_space
*dim
,
1656 isl_basic_map
*bmap
;
1657 isl_local_space
*ls
;
1659 dim
= isl_space_add_dims(dim
, isl_dim_in
, len
);
1660 dim
= isl_space_add_dims(dim
, isl_dim_out
, len
);
1661 bmap
= isl_basic_map_universe(isl_space_copy(dim
));
1662 ls
= isl_local_space_from_space(dim
);
1664 for (i
= 0; i
< len
; ++i
) {
1665 c
= isl_equality_alloc(isl_local_space_copy(ls
));
1666 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
,
1668 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, pos
[i
],
1670 bmap
= isl_basic_map_add_constraint(bmap
, c
);
1672 isl_local_space_free(ls
);
1674 return isl_map_from_basic_map(bmap
);
1677 /* Find all loops involved in any of the index expressions for any of
1678 * the private accesses, move them innermost and then mark them as
1679 * requiring unrolling by setting gen->first_unroll.
1680 * The loops involved should all be parallel because of the checks
1681 * we performed in check_private_group_access. Moving them innermost
1682 * is therefore a valid transformation.
1684 * Loops up to gen->shared_len are generated before the mapping to
1685 * threads is applied. They should therefore be ignored.
1687 * We compute the hidden equalities of the schedule first
1688 * since we will need them in our calls to isl_pw_multi_aff_from_map
1689 * and because we want to make sure that the same equalities
1690 * are also available to the code generator.
1692 static __isl_give isl_union_map
*interchange_for_unroll(struct gpu_gen
*gen
,
1693 __isl_take isl_union_map
*sched
)
1696 int unroll
[gen
->thread_tiled_len
];
1697 int perm
[gen
->thread_tiled_len
];
1700 int len
= gen
->shared_len
+ gen
->n_parallel
+ gen
->n_block
;
1702 gen
->first_unroll
= -1;
1704 sched
= isl_union_map_detect_equalities(sched
);
1705 for (i
= 0; i
< gen
->thread_tiled_len
; ++i
)
1707 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
1708 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
1710 for (j
= 0; j
< array
->n_group
; ++j
) {
1711 isl_union_map
*access
;
1713 isl_pw_multi_aff
*pma
;
1715 if (!array
->groups
[j
]->private_tile
)
1718 access
= group_access_relation(array
->groups
[j
], 1, 1);
1719 access
= isl_union_map_apply_domain(access
,
1720 isl_union_map_copy(sched
));
1722 acc
= isl_map_from_union_map(access
);
1723 pma
= isl_pw_multi_aff_from_map(acc
);
1724 isl_pw_multi_aff_foreach_piece(pma
,
1725 &check_unroll
, unroll
);
1727 isl_pw_multi_aff_free(pma
);
1731 for (i
= gen
->shared_len
; i
< len
; ++i
)
1738 for (i
= len
; i
< gen
->thread_tiled_len
; ++i
)
1743 for (i
= 0; i
< gen
->shared_len
; ++i
)
1745 for (i
= gen
->shared_len
; i
< gen
->thread_tiled_len
; ++i
)
1748 gen
->first_unroll
= j
- gen
->shared_len
;
1749 for (i
= gen
->shared_len
; i
< len
; ++i
)
1753 dim
= isl_union_map_get_space(sched
);
1754 permute
= permutation(dim
, perm
, gen
->thread_tiled_len
);
1755 sched
= isl_union_map_apply_range(sched
,
1756 isl_union_map_from_map(permute
));
1761 /* Given a constraint
1763 * a(p,i) + j = g f(e)
1765 * or -a(p,i) - j = g f(e) if sign < 0,
1766 * store a(p,i) in bound->shift and g (stride) in bound->stride.
1767 * a(p,i) is assumed to be an expression in only the parameters
1768 * and the input dimensions.
1770 static void extract_stride(__isl_keep isl_constraint
*c
,
1771 struct gpu_array_bound
*bound
, isl_int stride
, int sign
)
1780 isl_int_set(bound
->stride
, stride
);
1782 space
= isl_constraint_get_space(c
);
1783 space
= isl_space_domain(space
);
1785 nparam
= isl_space_dim(space
, isl_dim_param
);
1786 nvar
= isl_space_dim(space
, isl_dim_set
);
1790 isl_constraint_get_constant(c
, &v
);
1793 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
1794 aff
= isl_aff_set_constant(aff
, v
);
1796 for (i
= 0; i
< nparam
; ++i
) {
1797 isl_constraint_get_coefficient(c
, isl_dim_param
, i
, &v
);
1798 if (isl_int_is_zero(v
))
1802 aff
= isl_aff_add_coefficient(aff
, isl_dim_param
, i
, v
);
1805 for (i
= 0; i
< nvar
; ++i
) {
1806 isl_constraint_get_coefficient(c
, isl_dim_in
, i
, &v
);
1807 if (isl_int_is_zero(v
))
1811 aff
= isl_aff_add_coefficient(aff
, isl_dim_in
, i
, v
);
1819 /* Given an equality constraint of a map with a single output dimension j,
1820 * check if the constraint is of the form
1822 * a(p,i) + j = g f(e)
1824 * with a(p,i) an expression in the parameters and input dimensions
1825 * and f(e) an expression in the existentially quantified variables.
1826 * If so, and if g is larger than any such g from a previously considered
1827 * constraint, then call extract_stride to record the stride information
1830 static int check_stride_constraint(__isl_take isl_constraint
*c
, void *user
)
1835 struct gpu_array_bound
*bound
= user
;
1838 isl_int_init(stride
);
1840 n_div
= isl_constraint_dim(c
, isl_dim_div
);
1841 isl_constraint_get_coefficient(c
, isl_dim_out
, 0, &v
);
1843 if (n_div
&& (isl_int_is_one(v
) || isl_int_is_negone(v
))) {
1844 int s
= isl_int_sgn(v
);
1845 isl_int_set_si(stride
, 0);
1846 for (i
= 0; i
< n_div
; ++i
) {
1847 isl_constraint_get_coefficient(c
, isl_dim_div
, i
, &v
);
1848 isl_int_gcd(stride
, stride
, v
);
1850 if (!isl_int_is_zero(stride
) &&
1851 isl_int_gt(stride
, bound
->stride
))
1852 extract_stride(c
, bound
, stride
, s
);
1855 isl_int_clear(stride
);
1858 isl_constraint_free(c
);
1862 /* Given contraints on an array index i, check if we can find
1863 * a shift a(p) and a stride g such that
1865 * a(p) + i = 0 mod g
1867 * If so, record the information in bound and apply the mapping
1868 * i -> (i + a(p))/g to the array index in bounds and return
1869 * the new constraints.
1870 * If not, simply return the original constraints.
1872 * If bounds is a subset of the space
1876 * then the bound recorded in bound->shift is of the form
1880 * with s(D) equal to a(p) above.
1881 * The mapping recorded in bound->shift_map is of the form
1883 * [D -> i] -> [D -> (i + S(D))/g]
1885 * This mapping is computed as follows.
1886 * We first introduce "i" in the domain through precomposition
1887 * with [D -> i] -> D obtaining
1891 * Adding [D -> i] -> i produces
1893 * [D -> i] -> i + s(D)
1895 * and the domain product with [D -> i] -> D yields
1897 * [D -> i] -> [D -> i + s(D)]
1899 * Composition with [D -> i] -> [D -> i/g] gives the desired result.
1901 static __isl_give isl_basic_map
*check_stride(struct gpu_array_bound
*bound
,
1902 __isl_take isl_basic_map
*bounds
)
1905 isl_basic_map
*hull
;
1906 isl_basic_map
*shift
, *id
, *bmap
, *scale
;
1907 isl_basic_set
*bset
;
1910 isl_int_set_si(bound
->stride
, -1);
1912 hull
= isl_basic_map_affine_hull(isl_basic_map_copy(bounds
));
1914 isl_basic_map_foreach_constraint(hull
, &check_stride_constraint
, bound
);
1916 isl_basic_map_free(hull
);
1918 if (isl_int_is_neg(bound
->stride
))
1921 shift
= isl_basic_map_from_aff(isl_aff_copy(bound
->shift
));
1922 space
= isl_basic_map_get_space(bounds
);
1923 bmap
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
1924 shift
= isl_basic_map_apply_range(bmap
, shift
);
1925 space
= isl_basic_map_get_space(bounds
);
1926 id
= isl_basic_map_range_map(isl_basic_map_universe(space
));
1927 shift
= isl_basic_map_sum(id
, shift
);
1928 space
= isl_basic_map_get_space(bounds
);
1929 id
= isl_basic_map_domain_map(isl_basic_map_universe(space
));
1930 shift
= isl_basic_map_range_product(id
, shift
);
1932 space
= isl_space_domain(isl_basic_map_get_space(bounds
));
1933 id
= isl_basic_map_identity(isl_space_map_from_set(space
));
1934 space
= isl_space_range(isl_basic_map_get_space(bounds
));
1935 aff
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
1936 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, 0, 1);
1937 aff
= isl_aff_scale_down(aff
, bound
->stride
);
1938 scale
= isl_basic_map_from_aff(aff
);
1939 scale
= isl_basic_map_product(id
, scale
);
1941 bound
->shift_map
= isl_basic_map_apply_range(shift
, scale
);
1942 bmap
= isl_basic_map_copy(bound
->shift_map
);
1943 bset
= isl_basic_set_apply(isl_basic_map_wrap(bounds
), bmap
);
1944 bounds
= isl_basic_set_unwrap(bset
);
1949 /* Data used in compute_array_dim_size and compute_size_in_direction.
1951 * pos is the position of the variable representing the array index,
1952 * i.e., the variable for which want to compute the size. This variable
1953 * is also the last variable in the set.
1955 struct gpu_size_info
{
1956 isl_basic_set
*bset
;
1957 struct gpu_array_bound
*bound
;
1961 /* Given a constraint from the basic set describing the bounds on
1962 * an array index, check if it is a lower bound, say m i >= b(x), and,
1963 * if so, check whether the expression "i - ceil(b(x)/m) + 1" has a constant
1964 * upper bound. If so, and if this bound is smaller than any bound
1965 * derived from earlier constraints, set the size to this bound on
1966 * the expression and the lower bound to ceil(b(x)/m).
1968 static int compute_size_in_direction(__isl_take isl_constraint
*c
, void *user
)
1970 struct gpu_size_info
*size
= user
;
1975 nparam
= isl_basic_set_dim(size
->bset
, isl_dim_param
);
1976 n_div
= isl_constraint_dim(c
, isl_dim_div
);
1978 if (isl_constraint_involves_dims(c
, isl_dim_div
, 0, n_div
)) {
1979 isl_constraint_free(c
);
1985 isl_constraint_get_coefficient(c
, isl_dim_set
, size
->pos
, &v
);
1987 if (isl_int_is_pos(v
)) {
1990 enum isl_lp_result res
;
1992 aff
= isl_constraint_get_bound(c
, isl_dim_set
, size
->pos
);
1993 aff
= isl_aff_ceil(aff
);
1995 lb
= isl_aff_copy(aff
);
1997 aff
= isl_aff_neg(aff
);
1998 aff
= isl_aff_add_coefficient_si(aff
, isl_dim_in
, size
->pos
, 1);
2000 res
= isl_basic_set_max(size
->bset
, aff
, &v
);
2003 if (res
== isl_lp_ok
) {
2004 isl_int_add_ui(v
, v
, 1);
2005 if (isl_int_is_neg(size
->bound
->size
) ||
2006 isl_int_lt(v
, size
->bound
->size
)) {
2007 isl_int_set(size
->bound
->size
, v
);
2008 lb
= isl_aff_drop_dims(lb
, isl_dim_in
,
2010 isl_aff_free(size
->bound
->lb
);
2011 size
->bound
->lb
= isl_aff_copy(lb
);
2018 isl_constraint_free(c
);
2023 /* Given a basic map "bounds" that maps parameters and input dimensions
2024 * to a single output dimension, look for an expression in the parameters
2025 * and input dimensions such that the range of the output dimension shifted
2026 * by this expression is a constant.
2028 * In particular, we currently only consider lower bounds on the output
2029 * dimension as candidate expressions.
2031 static int compute_array_dim_size(struct gpu_array_bound
*bound
,
2032 __isl_take isl_basic_map
*bounds
)
2034 struct gpu_size_info size
;
2036 bounds
= isl_basic_map_detect_equalities(bounds
);
2037 bounds
= check_stride(bound
, bounds
);
2039 isl_int_set_si(bound
->size
, -1);
2043 size
.pos
= isl_basic_map_dim(bounds
, isl_dim_in
);
2044 size
.bset
= isl_basic_map_wrap(bounds
);
2045 size
.bset
= isl_basic_set_flatten(size
.bset
);
2046 size
.bset
= isl_set_simple_hull(isl_basic_set_compute_divs(size
.bset
));
2047 isl_basic_set_foreach_constraint(size
.bset
, &compute_size_in_direction
,
2049 isl_basic_set_free(size
.bset
);
2051 return isl_int_is_nonneg(bound
->size
) ? 0 : -1;
2054 /* Check if we can find a memory tile for the given array
2055 * based on the given accesses, and if so, put the results in "tile".
2057 * We project the accesses on each index in turn and look for a parametric
2058 * offset such that the size is constant.
2060 static int can_tile(__isl_keep isl_map
*access
, struct gpu_array_tile
*tile
)
2064 for (i
= 0; i
< tile
->n
; ++i
) {
2066 isl_basic_map
*hull
;
2068 access_i
= isl_map_copy(access
);
2069 access_i
= isl_map_project_out(access_i
, isl_dim_out
, 0, i
);
2070 access_i
= isl_map_project_out(access_i
, isl_dim_out
,
2071 1, tile
->n
- (i
+ 1));
2072 access_i
= isl_map_compute_divs(access_i
);
2073 hull
= isl_map_simple_hull(access_i
);
2074 if (compute_array_dim_size(&tile
->bound
[i
], hull
) < 0)
2081 /* Construct a map with input the shared tile loops and the loops that
2082 * will be wrapped around the threads that relates these later loops
2083 * to the thread indices and then projects them out.
2085 static __isl_give isl_map
*compute_privatization(struct gpu_gen
*gen
)
2093 dim
= isl_union_map_get_space(gen
->shared_sched
);
2095 if (gen
->options
->wrap
)
2096 tiling
= wrap(isl_space_copy(dim
), gen
->shared_len
+ gen
->n_block
,
2097 gen
->shared_len
, gen
->n_block
, gen
->block_dim
);
2099 tiling
= tile(isl_space_copy(dim
), gen
->shared_len
+ gen
->n_block
,
2100 gen
->shared_len
, gen
->n_block
, gen
->block_dim
);
2104 par
= parametrization(dim
, gen
->shared_len
+ 2 * gen
->n_block
,
2105 gen
->tile_first
+ gen
->tile_len
+ gen
->n_grid
+ gen
->n_block
,
2108 priv
= isl_map_align_params(priv
, isl_set_get_space(par
));
2109 priv
= isl_map_intersect_range(priv
, par
);
2111 dim
= isl_map_get_space(priv
);
2112 dim
= isl_space_drop_dims(dim
, isl_dim_in
, 0, isl_space_dim(dim
, isl_dim_in
));
2113 dim
= isl_space_drop_dims(dim
, isl_dim_out
, 0, isl_space_dim(dim
, isl_dim_out
));
2114 proj
= projection(dim
, gen
->shared_len
+ 2 * gen
->n_block
,
2117 priv
= isl_map_apply_range(priv
, proj
);
2122 /* Construct a map from domain_dim to domain_dim that increments
2123 * the dimension at position "pos" and leaves all other dimensions
2126 static __isl_give isl_map
*next(__isl_take isl_space
*domain_dim
, int pos
)
2129 int len
= isl_space_dim(domain_dim
, isl_dim_set
);
2131 isl_basic_map
*next
;
2132 isl_local_space
*ls
;
2134 dim
= isl_space_map_from_set(domain_dim
);
2135 next
= isl_basic_map_universe(isl_space_copy(dim
));
2136 ls
= isl_local_space_from_space(dim
);
2138 for (i
= 0; i
< len
; ++i
) {
2141 c
= isl_equality_alloc(isl_local_space_copy(ls
));
2142 c
= isl_constraint_set_coefficient_si(c
, isl_dim_in
, i
, 1);
2143 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, i
, -1);
2145 c
= isl_constraint_set_constant_si(c
, 1);
2146 next
= isl_basic_map_add_constraint(next
, c
);
2149 isl_local_space_free(ls
);
2151 return isl_map_from_basic_map(next
);
2154 /* Check if the given access is coalesced.
2155 * That is, check whether incrementing the dimension that will get
2156 * wrapped over the last thread index results in incrementing
2157 * the last array index.
2159 * This function is only called for access relations without reuse.
2161 static int access_is_coalesced(struct gpu_gen
*gen
,
2162 __isl_keep isl_union_map
*access
)
2165 isl_map
*access_map
;
2166 isl_map
*next_thread_x
;
2167 isl_map
*next_element
;
2171 access
= isl_union_map_copy(access
);
2172 access
= isl_union_map_apply_domain(access
,
2173 isl_union_map_copy(gen
->tiled_sched
));
2174 access_map
= isl_map_from_union_map(access
);
2176 dim
= isl_map_get_space(access_map
);
2177 dim
= isl_space_domain(dim
);
2178 next_thread_x
= next(dim
, gen
->shared_len
+ gen
->n_block
- 1);
2180 dim
= isl_map_get_space(access_map
);
2181 dim
= isl_space_range(dim
);
2182 next_element
= next(dim
, isl_space_dim(dim
, isl_dim_set
) - 1);
2184 map
= isl_map_apply_domain(next_thread_x
, isl_map_copy(access_map
));
2185 map
= isl_map_apply_range(map
, access_map
);
2187 coalesced
= isl_map_is_subset(map
, next_element
);
2189 isl_map_free(next_element
);
2195 /* Given an access relation in terms of the first gen->shared_len + gen->n_block
2196 * dimensions of the computed schedule, check if it is bijective for
2197 * fixed values of the first gen->shared_len dimensions.
2198 * We perform this check by equating these dimensions to parameters.
2200 static int access_is_bijective(struct gpu_gen
*gen
, __isl_keep isl_map
*access
)
2206 access
= isl_map_copy(access
);
2207 space
= isl_space_params(isl_map_get_space(access
));
2208 par
= parametrization(space
, gen
->shared_len
+ gen
->n_block
,
2209 0, gen
->shared_len
, "s");
2210 access
= isl_map_intersect_domain(access
, par
);
2211 res
= isl_map_is_bijective(access
);
2212 isl_map_free(access
);
2217 /* Look for the last shared tile loop that affects the offset of "tile"
2218 * and return the result.
2219 * If there is no such loop, then return the index of the loop
2220 * before the first shared tile loop, in particular gen->tile_first - 1.
2222 static int compute_tile_last_shared(struct gpu_gen
*gen
,
2223 struct gpu_array_tile
*tile
)
2227 for (j
= gen
->shared_len
- 1; j
>= gen
->tile_first
; --j
) {
2228 for (i
= 0; i
< tile
->n
; ++i
) {
2232 lb
= tile
->bound
[i
].lb
;
2233 if (isl_aff_involves_dims(lb
, isl_dim_in
, j
, 1))
2236 shift
= tile
->bound
[i
].shift
;
2239 if (isl_aff_involves_dims(shift
, isl_dim_in
, j
, 1))
2249 /* Look for the last shared tile loop that affects the offset of the
2250 * shared or private tile and store the result in group->last_shared.
2251 * If there is no such loop, then group->last_shared is set to a value
2252 * before the first shared tile loop, in particular gen->tile_first - 1.
2253 * If there is no tile defined on the array reference group,
2254 * then set group->last_shared to gen->shared_len - 1.
2256 static void set_last_shared(struct gpu_gen
*gen
,
2257 struct gpu_array_ref_group
*group
)
2259 struct gpu_array_tile
*tile
;
2261 group
->last_shared
= gen
->shared_len
- 1;
2263 tile
= group
->private_tile
;
2265 tile
= group
->shared_tile
;
2269 group
->last_shared
= compute_tile_last_shared(gen
, tile
);
2272 /* Compute a privatized copy of all access relations from reference groups that
2273 * are mapped to private memory and store the result in gen->privatization.
2275 static void compute_private_access(struct gpu_gen
*gen
)
2278 isl_union_map
*private;
2280 if (!gen
->options
->use_private_memory
)
2283 private = isl_union_map_empty(isl_union_map_get_space(gen
->shared_sched
));
2285 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
2286 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
2288 if (gpu_array_is_read_only_scalar(array
))
2291 for (j
= 0; j
< array
->n_group
; ++j
) {
2292 if (!array
->groups
[j
]->private_tile
)
2295 private = isl_union_map_union(private,
2296 group_access_relation(array
->groups
[j
], 1, 1));
2300 if (isl_union_map_is_empty(private))
2301 isl_union_map_free(private);
2303 isl_union_map
*priv
;
2305 private = isl_union_map_apply_domain(private,
2306 isl_union_map_copy(gen
->shared_sched
));
2307 priv
= isl_union_map_from_map(isl_map_copy(gen
->privatization
));
2308 private = isl_union_map_apply_domain(private, priv
);
2309 gen
->private_access
= private;
2313 /* Compute the size of the tile specified by "tile"
2314 * in number of elements and put the result in *size.
2316 static void tile_size(struct gpu_array_tile
*tile
, isl_int
*size
)
2320 isl_int_set_si(*size
, 1);
2322 for (i
= 0; i
< tile
->n
; ++i
)
2323 isl_int_mul(*size
, *size
, tile
->bound
[i
].size
);
2326 /* If max_shared_memory is not set to infinity (-1), then make
2327 * sure that the total amount of shared memory required by the
2328 * array reference groups mapped to shared memory is no larger
2329 * than this maximum.
2331 * We apply a greedy approach and discard (keep in global memory)
2332 * those groups that would result in a total memory size that
2333 * is larger than the maximum.
2335 static void check_shared_memory_bound(struct gpu_gen
*gen
)
2340 if (gen
->options
->max_shared_memory
< 0)
2345 isl_int_set_si(left
, gen
->options
->max_shared_memory
);
2347 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
2348 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
2350 for (j
= 0; j
< array
->n_group
; ++j
) {
2351 struct gpu_array_ref_group
*group
;
2353 group
= array
->groups
[j
];
2354 if (!group
->shared_tile
)
2357 tile_size(group
->shared_tile
, &size
);
2358 isl_int_mul_ui(size
, size
, array
->size
);
2360 if (isl_int_le(size
, left
)) {
2361 isl_int_sub(left
, left
, size
);
2365 group
->shared_tile
= free_tile(group
->shared_tile
);
2369 isl_int_clear(size
);
2370 isl_int_clear(left
);
2373 /* Fill up the groups array with singleton groups, i.e., one group
2374 * per reference, initializing the array, access, write, n_ref and refs fields.
2375 * In particular the access field is initialized to the scheduled
2376 * access relation of the array reference.
2378 * Return the number of elements initialized, i.e., the number of
2379 * active references in the current kernel.
2381 static int populate_array_references(struct gpu_array_info
*array
,
2382 __isl_keep isl_union_map
*sched
, struct gpu_array_ref_group
**groups
)
2386 isl_ctx
*ctx
= isl_union_map_get_ctx(sched
);
2389 for (i
= 0; i
< array
->n_ref
; ++i
) {
2390 isl_union_map
*umap
;
2392 struct gpu_array_ref_group
*group
;
2393 struct gpu_stmt_access
*access
= array
->refs
[i
];
2395 map
= isl_map_copy(access
->access
);
2396 umap
= isl_union_map_from_map(map
);
2397 umap
= isl_union_map_apply_domain(umap
,
2398 isl_union_map_copy(sched
));
2400 if (isl_union_map_is_empty(umap
)) {
2401 isl_union_map_free(umap
);
2405 map
= isl_map_from_union_map(umap
);
2406 map
= isl_map_detect_equalities(map
);
2408 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
2410 group
->array
= array
;
2411 group
->access
= map
;
2412 group
->write
= access
->write
;
2413 group
->refs
= &array
->refs
[i
];
2416 groups
[n
++] = group
;
2422 /* If group->n_ref == 1, then group->refs was set by
2423 * populate_array_references to point directly into
2424 * group->array->refs and should not be freed.
2425 * If group->n_ref > 1, then group->refs was set by join_groups
2426 * to point to a newly allocated array.
2428 static void free_array_ref_group(struct gpu_array_ref_group
*group
)
2432 free_tile(group
->shared_tile
);
2433 free_tile(group
->private_tile
);
2434 isl_map_free(group
->access
);
2435 if (group
->n_ref
> 1)
2440 /* Given a map where the input dimensions represent the tile loops,
2441 * eliminate the innermost of those that have a fixed value
2442 * until we reach one that does not (obviously) have a fixed value.
2444 static __isl_give isl_map
*eliminate_fixed_inner_loops(
2445 __isl_take isl_map
*access
)
2449 n
= isl_map_dim(access
, isl_dim_in
);
2451 for (i
= n
- 1; i
>= 0; --i
) {
2452 if (!isl_map_plain_is_fixed(access
, isl_dim_in
, i
, NULL
))
2454 access
= isl_map_eliminate(access
, isl_dim_in
, i
, 1);
2459 /* Check if the access relations of group1 and group2 overlap within
2460 * the innermost loop. In particular, ignore any inner dimension
2461 * with a fixed value.
2462 * The copying to and from shared memory will be performed within
2463 * the innermost actual loop so we are only allowed to consider
2464 * the dimensions up to that innermost loop while checking whether
2465 * two access relations overlap.
2467 static int accesses_overlap(struct gpu_array_ref_group
*group1
,
2468 struct gpu_array_ref_group
*group2
)
2471 isl_map
*access1
, *access2
;
2473 access1
= isl_map_copy(group1
->access
);
2474 access1
= eliminate_fixed_inner_loops(access1
);
2475 access2
= isl_map_copy(group2
->access
);
2476 access2
= eliminate_fixed_inner_loops(access2
);
2477 access1
= isl_map_intersect(access1
, access2
);
2478 empty
= isl_map_is_empty(access1
);
2479 isl_map_free(access1
);
2484 /* Combine the given two groups into a single group, containing
2485 * the references of both groups.
2487 static struct gpu_array_ref_group
*join_groups(
2488 struct gpu_array_ref_group
*group1
,
2489 struct gpu_array_ref_group
*group2
)
2493 struct gpu_array_ref_group
*group
;
2495 ctx
= isl_map_get_ctx(group1
->access
);
2496 group
= isl_calloc_type(ctx
, struct gpu_array_ref_group
);
2498 group
->array
= group1
->array
;
2499 group
->access
= isl_map_union(isl_map_copy(group1
->access
),
2500 isl_map_copy(group2
->access
));
2501 group
->write
= group1
->write
|| group2
->write
;
2502 group
->n_ref
= group1
->n_ref
+ group2
->n_ref
;
2503 group
->refs
= isl_alloc_array(ctx
, struct gpu_stmt_access
*,
2505 assert(group
->refs
);
2506 for (i
= 0; i
< group1
->n_ref
; ++i
)
2507 group
->refs
[i
] = group1
->refs
[i
];
2508 for (i
= 0; i
< group2
->n_ref
; ++i
)
2509 group
->refs
[group1
->n_ref
+ i
] = group2
->refs
[i
];
2514 /* Combine the given two groups into a single group and free
2515 * the original two groups.
2517 static struct gpu_array_ref_group
*join_groups_and_free(
2518 struct gpu_array_ref_group
*group1
,
2519 struct gpu_array_ref_group
*group2
)
2521 struct gpu_array_ref_group
*group
;
2523 group
= join_groups(group1
, group2
);
2524 free_array_ref_group(group1
);
2525 free_array_ref_group(group2
);
2529 /* Compute the private and/or shared memory tiles for the array
2530 * reference group "group" of array "array".
2532 * If the array is a read-only scalar or if the user requested
2533 * not to use shared or private memory, then we do not need to do anything.
2535 * We only try to compute a shared memory tile if there is any reuse
2536 * or if the access is not coalesced.
2538 * For computing a private memory tile, we also require that there is
2539 * some reuse. Moreover, we require that the access is private
2540 * to the thread. That is, we check that any given array element
2541 * is only accessed by a single thread.
2542 * We compute an access relation that maps the shared tile loop iterators
2543 * and the shared point loop iterators that will be wrapped over the
2544 * threads to the array elements.
2545 * We actually check that those iterators that will be wrapped
2546 * partition the array space. This check is stricter than necessary
2547 * since several iterations may be mapped onto the same thread
2548 * and then they could be allowed to access the same memory elements,
2549 * but our check does not allow this situation.
2551 * We also check that the index expression only depends on parallel
2552 * loops. That way, we can move those loops innermost and unroll them.
2553 * Again, we use a test that is stricter than necessary.
2554 * We actually check whether the index expression only depends
2555 * on the iterators that are wrapped over the threads.
2556 * These are necessarily parallel, but there may be more parallel loops.
2558 * Combining the injectivity of the first test with the single-valuedness
2559 * of the second test, we simply test for bijectivity.
2561 * If it turns out we can use registers, we compute the private memory
2562 * tile size using can_tile, after introducing a dependence
2563 * on the thread indices.
2565 static void compute_group_bounds_core(struct gpu_gen
*gen
,
2566 struct gpu_array_ref_group
*group
)
2568 isl_ctx
*ctx
= isl_space_get_ctx(group
->array
->dim
);
2569 isl_union_map
*access
;
2570 int n_index
= group
->array
->n_index
;
2573 int use_shared
= gen
->options
->use_shared_memory
;
2574 int use_private
= gen
->options
->use_private_memory
;
2576 if (!use_shared
&& !use_private
)
2578 if (gpu_array_is_read_only_scalar(group
->array
))
2581 access
= group_access_relation(group
, 1, 1);
2582 no_reuse
= isl_union_map_is_injective(access
);
2584 if (use_shared
&& (!no_reuse
|| !access_is_coalesced(gen
, access
))) {
2585 group
->shared_tile
= create_tile(ctx
, group
->array
->n_index
);
2586 if (!can_tile(group
->access
, group
->shared_tile
))
2587 group
->shared_tile
= free_tile(group
->shared_tile
);
2590 if (!use_private
|| no_reuse
) {
2591 isl_union_map_free(access
);
2595 access
= isl_union_map_apply_domain(access
,
2596 isl_union_map_copy(gen
->shared_sched
));
2598 acc
= isl_map_from_union_map(access
);
2600 if (!access_is_bijective(gen
, acc
)) {
2605 group
->private_tile
= create_tile(gen
->ctx
, n_index
);
2606 acc
= isl_map_apply_domain(acc
, isl_map_copy(gen
->privatization
));
2607 if (!can_tile(acc
, group
->private_tile
))
2608 group
->private_tile
= free_tile(group
->private_tile
);
2613 /* Compute the private and/or shared memory tiles for the array
2614 * reference group "group" of array "array" and set last_shared.
2616 static void compute_group_bounds(struct gpu_gen
*gen
,
2617 struct gpu_array_ref_group
*group
)
2619 compute_group_bounds_core(gen
, group
);
2620 set_last_shared(gen
, group
);
2623 /* If two groups have overlapping access relations (as determined by
2624 * the "overlap" function) and if one of them involves a write,
2625 * then merge the two groups into one.
2626 * If "compute_bounds" is set, then call compute_group_bounds
2627 * on the merged groups.
2629 * Return the updated number of groups.
2631 static int group_writes(struct gpu_gen
*gen
,
2632 int n
, struct gpu_array_ref_group
**groups
,
2633 int (*overlap
)(struct gpu_array_ref_group
*group1
,
2634 struct gpu_array_ref_group
*group2
), int compute_bounds
)
2638 for (i
= 0; i
< n
; ++i
) {
2639 for (j
= n
- 1; j
> i
; --j
) {
2640 if (!groups
[i
]->write
&& !groups
[j
]->write
)
2643 if (!overlap(groups
[i
], groups
[j
]))
2646 groups
[i
] = join_groups_and_free(groups
[i
], groups
[j
]);
2648 compute_group_bounds(gen
, groups
[i
]);
2650 groups
[j
] = groups
[n
- 1];
2658 /* If two groups have overlapping access relations (within the innermost
2659 * loop) and if one of them involves a write, then merge the two groups
2662 * Return the updated number of groups.
2664 static int group_overlapping_writes(struct gpu_gen
*gen
,
2665 int n
, struct gpu_array_ref_group
**groups
)
2667 return group_writes(gen
, n
, groups
, &accesses_overlap
, 0);
2670 /* Check if the access relations of group1 and group2 overlap within
2671 * the outermost min(group1->last_shared, group2->last_shared) loops.
2673 static int last_shared_accesses_overlap(struct gpu_array_ref_group
*group1
,
2674 struct gpu_array_ref_group
*group2
)
2679 isl_map
*map_i
, *map_j
, *map
;
2681 last_shared
= group1
->last_shared
;
2682 if (group2
->last_shared
< last_shared
)
2683 last_shared
= group2
->last_shared
;
2684 map_i
= isl_map_copy(group1
->access
);
2685 dim
= isl_map_dim(map_i
, isl_dim_in
);
2686 map_i
= isl_map_eliminate(map_i
, isl_dim_in
,
2687 last_shared
+ 1, dim
- (last_shared
+ 1));
2688 map_j
= isl_map_copy(group2
->access
);
2689 map_j
= isl_map_eliminate(map_j
, isl_dim_in
,
2690 last_shared
+ 1, dim
- (last_shared
+ 1));
2691 map
= isl_map_intersect(map_i
, map_j
);
2692 empty
= isl_map_is_empty(map
);
2698 /* If two groups have overlapping access relations (within the outer
2699 * last_shared loops) and if one of them involves a write,
2700 * then merge the two groups into one.
2702 * Return the updated number of groups.
2704 static int group_last_shared_overlapping_writes(struct gpu_gen
*gen
, int n
,
2705 struct gpu_array_ref_group
**groups
)
2707 return group_writes(gen
, n
, groups
, &last_shared_accesses_overlap
, 1);
2710 /* Is the size of the tile specified by "tile" smaller than the sum of
2711 * the sizes of the tiles specified by "tile1" and "tile2"?
2713 static int smaller_tile(struct gpu_array_tile
*tile
,
2714 struct gpu_array_tile
*tile1
, struct gpu_array_tile
*tile2
)
2717 isl_int size
, size1
, size2
;
2720 isl_int_init(size1
);
2721 isl_int_init(size2
);
2723 tile_size(tile
, &size
);
2724 tile_size(tile1
, &size1
);
2725 tile_size(tile2
, &size2
);
2727 isl_int_sub(size
, size
, size1
);
2728 isl_int_sub(size
, size
, size2
);
2729 smaller
= isl_int_is_neg(size
);
2731 isl_int_clear(size2
);
2732 isl_int_clear(size1
);
2733 isl_int_clear(size
);
2738 /* Given an initial grouping of array references and shared memory tiles
2739 * for each group that allows for a shared memory tile, merge two groups
2740 * if both have a shared memory tile, the merged group also has
2741 * a shared memory tile and the size of the tile for the merge group
2742 * is smaller than the sum of the tile sizes of the individual groups.
2744 * If merging two groups decreases the "last_shared" dimension of
2745 * one or both of the two groups, then we need to check for overlapping
2748 * Return the number of groups after merging.
2750 static int group_common_shared_memory_tile(struct gpu_gen
*gen
,
2751 struct gpu_array_info
*array
, int n
,
2752 struct gpu_array_ref_group
**groups
)
2755 int recompute_overlap
= 0;
2756 isl_ctx
*ctx
= isl_space_get_ctx(array
->dim
);
2758 for (i
= 0; i
< n
; ++i
) {
2759 if (!groups
[i
]->shared_tile
)
2761 for (j
= n
- 1; j
> i
; --j
) {
2764 struct gpu_array_ref_group
*group
;
2766 if (!groups
[j
]->shared_tile
)
2769 map
= isl_map_intersect(isl_map_copy(groups
[i
]->access
),
2770 isl_map_copy(groups
[j
]->access
));
2771 empty
= isl_map_is_empty(map
);
2777 group
= join_groups(groups
[i
], groups
[j
]);
2778 compute_group_bounds(gen
, group
);
2779 if (!group
->shared_tile
||
2780 !smaller_tile(group
->shared_tile
,
2781 groups
[i
]->shared_tile
,
2782 groups
[j
]->shared_tile
)) {
2783 free_array_ref_group(group
);
2787 if (group
->last_shared
< groups
[i
]->last_shared
||
2788 group
->last_shared
< groups
[j
]->last_shared
)
2789 recompute_overlap
= 1;
2790 free_array_ref_group(groups
[i
]);
2791 free_array_ref_group(groups
[j
]);
2794 groups
[j
] = groups
[n
- 1];
2799 if (recompute_overlap
)
2800 n
= group_last_shared_overlapping_writes(gen
, n
, groups
);
2804 /* Set array->n_group and array->groups to n and groups.
2806 * Additionally, set the "nr" field of each group
2807 * and the "group" field of each reference in each group.
2809 static void set_array_groups(struct gpu_array_info
*array
,
2810 int n
, struct gpu_array_ref_group
**groups
)
2815 array
->groups
= groups
;
2817 for (i
= 0; i
< n
; ++i
) {
2820 for (j
= 0; j
< groups
[i
]->n_ref
; ++j
)
2821 groups
[i
]->refs
[j
]->group
= i
;
2825 /* Group array references that should be considered together when
2826 * deciding whether to access them from private, shared or global memory.
2828 * In particular, if two array references overlap and if one of them
2829 * is a write, then the two references are grouped together.
2830 * We first perform an initial grouping based only on the access relation.
2831 * After computing shared and private memory tiles, we check for
2832 * overlapping writes again, but this time taking into account
2833 * the "last_shared" property.
2835 * Furthermore, if two groups admit a shared memory tile and if the
2836 * combination of the two also admits a shared memory tile, we merge
2839 static void group_array_references(struct gpu_gen
*gen
,
2840 struct gpu_array_info
*array
, __isl_keep isl_union_map
*sched
)
2844 isl_ctx
*ctx
= isl_union_map_get_ctx(sched
);
2845 struct gpu_array_ref_group
**groups
;
2847 groups
= isl_calloc_array(ctx
, struct gpu_array_ref_group
*,
2851 n
= populate_array_references(array
, sched
, groups
);
2853 n
= group_overlapping_writes(gen
, n
, groups
);
2855 for (i
= 0; i
< n
; ++i
)
2856 compute_group_bounds(gen
, groups
[i
]);
2858 n
= group_last_shared_overlapping_writes(gen
, n
, groups
);
2860 n
= group_common_shared_memory_tile(gen
, array
, n
, groups
);
2862 set_array_groups(array
, n
, groups
);
2865 /* Take tiled_sched, project it onto the shared tile loops and
2866 * the loops that will be wrapped over the threads and
2867 * store the result in gen->shared_sched.
2868 * Also compute a projection that projects out the loops that will be
2869 * wrapped over the threads and store this projection in gen->shared_proj.
2871 static void compute_shared_sched(struct gpu_gen
*gen
)
2876 isl_union_map
*sched
;
2878 sched
= isl_union_map_copy(gen
->tiled_sched
);
2880 dim
= isl_union_map_get_space(sched
);
2881 proj
= projection(dim
, gen
->tiled_len
, gen
->shared_len
+ gen
->n_block
);
2882 sched
= isl_union_map_apply_range(sched
, isl_union_map_from_map(proj
));
2884 dim
= isl_union_map_get_space(sched
);
2885 proj
= projection(dim
, gen
->shared_len
+ gen
->n_block
, gen
->shared_len
);
2887 gen
->shared_sched
= sched
;
2888 gen
->shared_proj
= isl_union_map_from_map(proj
);
2891 /* Group references of all arrays in the program.
2893 static void group_references(struct gpu_gen
*gen
)
2896 isl_union_map
*sched
;
2898 sched
= isl_union_map_apply_range(isl_union_map_copy(gen
->shared_sched
),
2899 isl_union_map_copy(gen
->shared_proj
));
2901 for (i
= 0; i
< gen
->prog
->n_array
; ++i
)
2902 group_array_references(gen
, &gen
->prog
->array
[i
], sched
);
2904 isl_union_map_free(sched
);
2907 /* Free all array information that is local to the current kernel.
2909 static void free_local_array_info(struct gpu_gen
*gen
)
2913 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
2914 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
2916 for (j
= 0; j
< array
->n_group
; ++j
)
2917 free_array_ref_group(array
->groups
[j
]);
2918 free(array
->groups
);
2922 /* Compute the effective grid size as a list of the sizes in each dimension.
2924 * The grid size specified by the user or set by default
2925 * in read_grid_sizes() and applied in tile_schedule(),
2926 * may be too large for the given code in the sense that
2927 * it may contain blocks that don't need to execute anything.
2928 * We therefore don't return this grid size, but instead the
2929 * smallest grid size that ensures that all blocks that actually
2930 * execute code are included in the grid.
2932 * We first extract a description of the grid, i.e., the possible values
2933 * of the block ids, from gen->tiled_sched.
2934 * The block ids are parameters in gen->tiled_sched.
2935 * We simply need to change them into set dimensions.
2937 * Then, for each block dimension, we compute the maximal value of the block id
2940 static __isl_give isl_multi_pw_aff
*extract_grid_size(struct gpu_gen
*gen
,
2941 struct ppcg_kernel
*kernel
)
2945 isl_multi_pw_aff
*mpa
;
2947 grid
= isl_union_map_params(isl_union_map_copy(gen
->tiled_sched
));
2948 grid
= isl_set_from_params(grid
);
2949 grid
= isl_set_add_dims(grid
, isl_dim_set
, gen
->n_grid
);
2950 for (i
= 0; i
< gen
->n_grid
; ++i
) {
2954 snprintf(name
, sizeof(name
), "b%d", i
);
2955 pos
= isl_set_find_dim_by_name(grid
, isl_dim_param
, name
);
2957 grid
= isl_set_equate(grid
, isl_dim_param
, pos
, isl_dim_set
, i
);
2958 grid
= isl_set_project_out(grid
, isl_dim_param
, pos
, 1);
2961 mpa
= isl_multi_pw_aff_zero(isl_set_get_space(grid
));
2962 for (i
= 0; i
< gen
->n_grid
; ++i
) {
2967 bound
= isl_set_dim_max(isl_set_copy(grid
), i
);
2968 bound
= isl_pw_aff_coalesce(bound
);
2969 bound
= isl_pw_aff_gist(bound
, isl_set_copy(kernel
->context
));
2971 space
= isl_pw_aff_get_domain_space(bound
);
2972 one
= isl_aff_zero_on_domain(isl_local_space_from_space(space
));
2973 one
= isl_aff_add_constant_si(one
, 1);
2974 bound
= isl_pw_aff_add(bound
, isl_pw_aff_from_aff(one
));
2975 mpa
= isl_multi_pw_aff_set_pw_aff(mpa
, i
, bound
);
2982 void ppcg_kernel_free(void *user
)
2984 struct ppcg_kernel
*kernel
= user
;
2990 isl_multi_pw_aff_free(kernel
->grid_size
);
2991 isl_set_free(kernel
->context
);
2992 isl_union_set_free(kernel
->arrays
);
2993 isl_space_free(kernel
->space
);
2994 isl_ast_node_free(kernel
->tree
);
2996 for (i
= 0; i
< kernel
->n_array
; ++i
)
2997 isl_pw_aff_list_free(kernel
->array
[i
].bound
);
2998 free(kernel
->array
);
3000 for (i
= 0; i
< kernel
->n_var
; ++i
) {
3001 free(kernel
->var
[i
].name
);
3002 isl_vec_free(kernel
->var
[i
].size
);
3009 static void create_kernel_var(isl_ctx
*ctx
, struct gpu_array_ref_group
*group
,
3010 struct ppcg_kernel_var
*var
)
3013 struct gpu_array_tile
*tile
;
3017 var
->array
= group
->array
;
3019 tile
= group
->private_tile
;
3020 var
->type
= ppcg_access_private
;
3022 tile
= group
->shared_tile
;
3023 var
->type
= ppcg_access_shared
;
3026 p
= isl_printer_to_str(ctx
);
3027 p
= print_array_name(p
, group
);
3028 var
->name
= isl_printer_get_str(p
);
3029 isl_printer_free(p
);
3031 var
->size
= isl_vec_alloc(ctx
, group
->array
->n_index
);
3033 for (j
= 0; j
< group
->array
->n_index
; ++j
)
3034 var
->size
= isl_vec_set_element(var
->size
, j
,
3035 tile
->bound
[j
].size
);
3038 static void create_kernel_vars(struct gpu_gen
*gen
, struct ppcg_kernel
*kernel
)
3043 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
3044 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
3046 for (j
= 0; j
< array
->n_group
; ++j
) {
3047 struct gpu_array_ref_group
*group
= array
->groups
[j
];
3048 if (group
->private_tile
|| group
->shared_tile
)
3054 kernel
->var
= isl_calloc_array(gen
->ctx
, struct ppcg_kernel_var
, n
);
3055 assert(kernel
->var
);
3058 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
3059 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
3061 for (j
= 0; j
< array
->n_group
; ++j
) {
3062 struct gpu_array_ref_group
*group
= array
->groups
[j
];
3063 if (!group
->private_tile
&& !group
->shared_tile
)
3065 create_kernel_var(gen
->ctx
, group
, &kernel
->var
[n
]);
3071 /* The sizes of the arrays on the host that have been computed by
3072 * extract_array_info may depend on the parameters. Use the extra
3073 * constraints on the parameters that are valid at "host_domain"
3074 * to simplify these expressions and store the results in kernel->array.
3076 static void localize_bounds(struct gpu_gen
*gen
, struct ppcg_kernel
*kernel
,
3077 __isl_keep isl_set
*host_domain
)
3082 kernel
->array
= isl_calloc_array(gen
->ctx
,
3083 struct gpu_local_array_info
, gen
->prog
->n_array
);
3084 assert(kernel
->array
);
3085 kernel
->n_array
= gen
->prog
->n_array
;
3087 context
= isl_set_copy(host_domain
);
3088 context
= isl_set_params(context
);
3090 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
3091 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
3092 isl_pw_aff_list
*local
;
3094 if (array
->n_group
== 0)
3097 local
= isl_pw_aff_list_alloc(gen
->ctx
, array
->n_index
);
3099 for (j
= 0; j
< array
->n_index
; ++j
) {
3102 pwaff
= isl_pw_aff_copy(array
->bound
[j
]);
3103 pwaff
= isl_pw_aff_gist(pwaff
, isl_set_copy(context
));
3104 local
= isl_pw_aff_list_add(local
, pwaff
);
3107 kernel
->array
[i
].bound
= local
;
3109 isl_set_free(context
);
3112 /* Find the element in gen->stmt that has the given "id".
3113 * Return NULL if no such gpu_stmt can be found.
3115 static struct gpu_stmt
*find_stmt(struct gpu_prog
*prog
, __isl_keep isl_id
*id
)
3119 for (i
= 0; i
< prog
->n_stmts
; ++i
) {
3120 if (id
== prog
->stmts
[i
].id
)
3124 return i
< prog
->n_stmts
? &prog
->stmts
[i
] : NULL
;
3127 /* Set gen->tile_len and gen->n_parallel to those of the statement
3128 * affected by the first map (part of the schedule)
3129 * on which this function is called.
3130 * Because of the way the schedule is constructed, the other statements
3131 * in the list, if any, should have the same values for these properties.
3133 static int extract_tile_len(__isl_take isl_map
*map
, void *user
)
3135 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3137 struct gpu_stmt
*stmt
;
3139 id
= isl_map_get_tuple_id(map
, isl_dim_in
);
3140 stmt
= find_stmt(gen
->prog
, id
);
3146 isl_die(gen
->ctx
, isl_error_unknown
,
3147 "statement not found", return -1);
3149 gen
->tile_len
= stmt
->tile_len
;
3150 gen
->n_parallel
= stmt
->n_parallel
;
3155 void ppcg_kernel_stmt_free(void *user
)
3158 struct ppcg_kernel_stmt
*stmt
= user
;
3163 switch (stmt
->type
) {
3164 case ppcg_kernel_copy
:
3165 isl_ast_expr_free(stmt
->u
.c
.index
);
3166 isl_ast_expr_free(stmt
->u
.c
.local_index
);
3168 case ppcg_kernel_domain
:
3169 for (i
= 0; i
< stmt
->u
.d
.n_access
; ++i
) {
3170 isl_ast_expr_list_free(stmt
->u
.d
.access
[i
].index
);
3171 free(stmt
->u
.d
.access
[i
].local_name
);
3173 free(stmt
->u
.d
.access
);
3175 case ppcg_kernel_sync
:
3182 /* Set the options of "context" to
3184 * { space -> [x] : x >= first }
3186 static __isl_give isl_ast_build
*set_unroll(
3187 __isl_take isl_ast_build
*build
, __isl_take isl_space
*space
,
3194 ctx
= isl_ast_build_get_ctx(build
);
3196 space
= isl_space_from_domain(space
);
3197 space
= isl_space_add_dims(space
, isl_dim_out
, 1);
3198 space
= isl_space_set_tuple_name(space
, isl_dim_out
, "unroll");
3199 unroll
= isl_map_universe(space
);
3200 unroll
= isl_map_lower_bound_si(unroll
, isl_dim_out
, 0, first
);
3201 opt
= isl_union_map_from_map(unroll
);
3203 build
= isl_ast_build_set_options(build
, opt
);
3208 /* Return a list of isl_ids of the form "prefix%d".
3210 static __isl_give isl_id_list
*generate_names(isl_ctx
*ctx
,
3211 int n
, const char *prefix
)
3217 names
= isl_id_list_alloc(ctx
, n
);
3218 for (i
= 0; i
< n
; ++i
) {
3221 snprintf(name
, sizeof(name
), "%s%d", prefix
, i
);
3222 id
= isl_id_alloc(ctx
, name
, NULL
);
3223 names
= isl_id_list_add(names
, id
);
3229 /* Extend the schedule "schedule" with the part of "extension"
3230 * starting at "first" up to "len".
3232 static __isl_give isl_union_map
*extend_schedule(
3233 __isl_take isl_union_map
*schedule
,
3234 __isl_take isl_union_map
*extension
, int first
, int len
)
3238 isl_union_map
*umap
;
3241 space
= isl_union_map_get_space(schedule
);
3242 space
= isl_space_set_from_params(space
);
3243 space
= isl_space_add_dims(space
, isl_dim_set
, len
);
3244 proj
= isl_set_identity(isl_set_universe(space
));
3245 proj
= isl_map_project_out(proj
, isl_dim_out
, 0, first
);
3246 extension
= isl_union_map_apply_range(extension
,
3247 isl_union_map_from_map(proj
));
3249 schedule
= isl_union_map_range_product(schedule
, extension
);
3254 /* This function is called for each access to an array in each instance
3255 * in the kernel of some statement in the original code.
3256 * Replace that access by an access to global, shared or private memory
3257 * and store the results in *kernel_access.
3259 * Since the array in shared or private memory is just
3260 * a shifted copy of part of the original array, we simply need
3261 * to subtract the lower bound, which was computed in can_tile.
3262 * If any of the indices is strided, then we first add
3263 * shared_tile->bound[i].shift and divide by shared_tile->bound[i].stride.
3265 * If the given array is accessed directly from global memory,
3266 * we don't need to perform any shifting and simply simplify
3267 * the expression in the context of the domain instead.
3269 * If the array space (range of access) has no name, then we are
3270 * accessing an iterator in the original program.
3272 * The input stmt_access->access relation maps the iteration domain
3273 * of the current statement to an array element.
3274 * The first step is to reformulate
3275 * this access relation in terms of the loop iterators of the generated
3276 * code through precomposition with gen->stmt_it.
3278 * The expressions in "tile" are formulated in terms of the first
3279 * gen->shared_len dimensions of the computed schedule using the mapping
3280 * sched2shared which maps the loop iterators to these dimensions.
3282 static void compute_index_expression(struct gpu_gen
*gen
,
3283 struct ppcg_kernel_access
*kernel_access
,
3284 struct gpu_stmt_access
*stmt_access
, __isl_keep isl_map
*stmt_it
,
3285 __isl_keep isl_map
*sched2shared
, __isl_keep isl_ast_build
*build
)
3288 isl_pw_multi_aff
*pma
;
3291 struct gpu_array_tile
*tile
= NULL
;
3293 if (isl_map_has_tuple_name(stmt_access
->access
, isl_dim_out
)) {
3296 struct gpu_array_ref_group
*group
;
3299 name
= isl_map_get_tuple_name(stmt_access
->access
, isl_dim_out
);
3301 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
3302 if (strcmp(name
, gen
->prog
->array
[i
].name
))
3304 kernel_access
->array
= &gen
->prog
->array
[i
];
3305 kernel_access
->local_array
= &gen
->kernel
->array
[i
];
3307 assert(kernel_access
->array
);
3308 group
= kernel_access
->array
->groups
[stmt_access
->group
];
3309 p
= isl_printer_to_str(gen
->ctx
);
3310 p
= print_array_name(p
, group
);
3311 kernel_access
->local_name
= isl_printer_get_str(p
);
3312 isl_printer_free(p
);
3313 tile
= group
->private_tile
;
3314 kernel_access
->type
= ppcg_access_private
;
3316 tile
= group
->shared_tile
;
3317 kernel_access
->type
= ppcg_access_shared
;
3321 kernel_access
->type
= ppcg_access_global
;
3323 n_index
= isl_map_dim(stmt_access
->access
, isl_dim_out
);
3324 kernel_access
->index
= isl_ast_expr_list_alloc(gen
->ctx
, n_index
);
3329 access
= isl_map_copy(stmt_access
->access
);
3330 access
= isl_map_apply_range(isl_map_copy(stmt_it
), access
);
3331 pma
= isl_pw_multi_aff_from_map(access
);
3332 pma
= isl_pw_multi_aff_coalesce(pma
);
3334 for (i
= 0; i
< n_index
; ++i
) {
3339 index
= isl_pw_multi_aff_get_pw_aff(pma
, i
);
3341 if (!kernel_access
->array
) {
3343 domain
= isl_map_domain(isl_map_copy(stmt_it
));
3344 index
= isl_pw_aff_coalesce(index
);
3345 index
= isl_pw_aff_gist(index
, domain
);
3347 domain
= isl_map_domain(isl_map_copy(stmt_it
));
3348 index
= shift_index(index
, kernel_access
->array
,
3349 &tile
->bound
[i
], domain
,
3350 isl_map_copy(sched2shared
));
3353 expr
= isl_ast_build_expr_from_pw_aff(build
, index
);
3355 kernel_access
->index
= isl_ast_expr_list_add(
3356 kernel_access
->index
, expr
);
3359 isl_pw_multi_aff_free(pma
);
3362 /* This function is called for each instance of a user statement
3365 * We attach a struct ppcg_kernel_stmt to the "node", containing
3366 * local information about the accesses.
3367 * This information is computed from stmt_it, which expresses the domain
3368 * elements in terms of the generated loops, and sched2shared,
3369 * which expresses the first shared_len dimensions of the schedule
3370 * computed by PPCG in terms of the generated loops.
3372 static __isl_give isl_ast_node
*at_each_domain(__isl_take isl_ast_node
*node
,
3373 __isl_keep isl_ast_build
*build
, void *user
)
3375 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3376 struct ppcg_kernel_stmt
*stmt
;
3378 isl_map
*stmt_it
, *sched2shared
;
3379 isl_ast_expr
*expr
, *arg
;
3380 isl_union_map
*schedule
;
3382 struct gpu_stmt_access
*access
;
3384 stmt
= isl_calloc_type(gen
->ctx
, struct ppcg_kernel_stmt
);
3386 return isl_ast_node_free(node
);
3388 expr
= isl_ast_node_user_get_expr(node
);
3389 arg
= isl_ast_expr_get_op_arg(expr
, 0);
3390 id
= isl_ast_expr_get_id(arg
);
3392 schedule
= isl_ast_build_get_schedule(build
);
3393 stmt_it
= isl_map_reverse(isl_map_from_union_map(schedule
));
3394 sched2shared
= compute_sched_to_shared(gen
, isl_map_copy(stmt_it
));
3396 stmt
->type
= ppcg_kernel_domain
;
3397 stmt
->u
.d
.stmt
= find_stmt(gen
->prog
, id
);
3398 if (!stmt
->u
.d
.stmt
)
3402 for (access
= stmt
->u
.d
.stmt
->accesses
; access
; access
= access
->next
)
3405 stmt
->u
.d
.access
= isl_calloc_array(gen
->ctx
,
3406 struct ppcg_kernel_access
, n
);
3407 if (!stmt
->u
.d
.access
)
3410 stmt
->u
.d
.n_access
= n
;
3412 access
= stmt
->u
.d
.stmt
->accesses
;
3413 for (i
= 0; i
< n
; ++i
, access
= access
->next
) {
3414 compute_index_expression(gen
, &stmt
->u
.d
.access
[i
], access
,
3415 stmt_it
, sched2shared
, build
);
3419 isl_map_free(stmt_it
);
3420 isl_map_free(sched2shared
);
3421 isl_ast_expr_free(arg
);
3422 isl_ast_expr_free(expr
);
3424 id
= isl_id_alloc(gen
->ctx
, NULL
, stmt
);
3425 id
= isl_id_set_free_user(id
, &ppcg_kernel_stmt_free
);
3426 return isl_ast_node_set_annotation(node
, id
);
3429 isl_map_free(stmt_it
);
3430 ppcg_kernel_stmt_free(stmt
);
3431 isl_map_free(sched2shared
);
3432 return isl_ast_node_free(node
);
3435 /* This function is called when code has been generated for the shared
3436 * tile loops. The "schedule" refers only to the original statements.
3438 * We extend the schedule with that part of gen->local_sched that hasn't
3439 * been taken into account yet. This introduces parameters referring
3440 * to thread ids in the schedule, so we add them (with the appropriate
3441 * bounds to the context as well).
3442 * Finally, we set the appropriate unrolling options
3443 * if gen->first_unroll is set.
3445 static __isl_give isl_ast_node
*create_domain_leaf(
3446 __isl_take isl_union_map
*schedule
, __isl_take isl_ast_build
*build
,
3449 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3451 isl_union_map
*sched
;
3454 isl_id_list
*iterators
;
3457 schedule
= extend_schedule(schedule
,
3458 isl_union_map_copy(gen
->local_sched
),
3459 gen
->shared_len
, gen
->thread_tiled_len
);
3461 space
= isl_ast_build_get_schedule_space(build
);
3462 set
= isl_set_universe(space
);
3463 set
= add_bounded_parameters(set
, gen
->n_block
, gen
->block_dim
, "t");
3464 build
= isl_ast_build_restrict(build
, set
);
3466 n
= gen
->thread_tiled_len
- gen
->shared_len
;
3468 if (gen
->first_unroll
>= 0) {
3469 space
= isl_space_set_alloc(gen
->ctx
, 0, n
);
3470 build
= set_unroll(build
, space
, gen
->first_unroll
);
3472 iterators
= generate_names(gen
->ctx
, n
, "c");
3473 build
= isl_ast_build_set_iterators(build
, iterators
);
3474 build
= isl_ast_build_set_at_each_domain(build
, &at_each_domain
, gen
);
3475 tree
= isl_ast_build_ast_from_schedule(build
, schedule
);
3476 isl_ast_build_free(build
);
3481 /* This function is called for each statement node in the AST of the code
3482 * for copying to or from shared/private memory.
3483 * Attach a pointer to a ppcg_kernel_stmt representing the copy
3484 * statement to the node.
3485 * The statement name is {read,write}_{shared,private}_<array>.
3487 * The schedule is of the form
3491 * where A refers to a piece of an array and T to the corresponding
3492 * shifted tile. We split this schedule into mappings L -> A and L -> T
3493 * and store the corresponding expressions in stmt->index and stmt->local_index,
3494 * where stmt points to the ppcg_kernel_stmt that is attached to the node.
3496 static __isl_give isl_ast_node
*attach_copy_stmt(__isl_take isl_ast_node
*node
,
3497 __isl_keep isl_ast_build
*build
, void *user
)
3499 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3500 struct ppcg_kernel_stmt
*stmt
;
3504 isl_map
*access
, *local_access
, *map
;
3505 isl_pw_multi_aff
*pma
;
3509 stmt
= isl_calloc_type(gen
->ctx
, struct ppcg_kernel_stmt
);
3511 return isl_ast_node_free(node
);
3513 access
= isl_map_from_union_map(isl_ast_build_get_schedule(build
));
3514 name
= isl_map_get_tuple_name(access
, isl_dim_in
);
3515 stmt
->u
.c
.read
= !strncmp(name
, "read", 4);
3516 access
= isl_map_reverse(access
);
3517 space
= isl_space_unwrap(isl_space_range(isl_map_get_space(access
)));
3518 local_access
= isl_map_copy(access
);
3520 map
= isl_map_domain_map(isl_map_universe(isl_space_copy(space
)));
3521 id
= isl_map_get_tuple_id(access
, isl_dim_out
);
3522 map
= isl_map_set_tuple_id(map
, isl_dim_in
, id
);
3523 access
= isl_map_apply_range(access
, map
);
3524 pma
= isl_pw_multi_aff_from_map(access
);
3525 expr
= isl_ast_build_call_from_pw_multi_aff(build
, pma
);
3526 stmt
->u
.c
.index
= expr
;
3528 map
= isl_map_range_map(isl_map_universe(space
));
3529 id
= isl_map_get_tuple_id(local_access
, isl_dim_out
);
3530 map
= isl_map_set_tuple_id(map
, isl_dim_in
, id
);
3531 local_access
= isl_map_apply_range(local_access
, map
);
3532 pma
= isl_pw_multi_aff_from_map(local_access
);
3533 expr
= isl_ast_build_call_from_pw_multi_aff(build
, pma
);
3534 stmt
->u
.c
.local_index
= expr
;
3536 stmt
->u
.c
.array
= gen
->copy_group
->array
;
3537 array_index
= stmt
->u
.c
.array
- gen
->prog
->array
;
3538 stmt
->u
.c
.local_array
= &gen
->kernel
->array
[array_index
];
3539 stmt
->type
= ppcg_kernel_copy
;
3541 id
= isl_id_alloc(gen
->ctx
, NULL
, stmt
);
3542 id
= isl_id_set_free_user(id
, &ppcg_kernel_stmt_free
);
3543 return isl_ast_node_set_annotation(node
, id
);
3546 /* Given a schedule of the form
3550 * (with S the first shared_len dimensions of the computed schedule,
3551 * A the array and L the schedule correponding to the generated loops),
3552 * indicating where the copying the array elements that need to be copied,
3553 * construct code for performing the copying.
3555 * "group" is the array reference group that is being copied
3556 * "type" is either "read" or "write"
3557 * private is set if copying needs to be performed to/from registers
3559 * We first construct a mapping to a shifted tile of the array,
3561 * [S -> A] -> T(S,A) (1)
3563 * If private is set, then we also use this mapping as a schedule
3564 * (which is already thread-specific and will be completely unrolled).
3565 * Otherwise, we wrap/tile the range over the threads.
3568 * [S -> A] -> T'(S,A)
3570 * Combined with the given schedule, we have
3572 * [S -> A] -> [L -> T'(S,A)] (2)
3574 * From the shifted tile mapping, we construct a mapping
3576 * [S -> A] -> [A -> T(S,A)]
3578 * and apply it to the schedule (2), obtaining
3580 * [A -> T(S(L),A)] -> [L -> T'(S(L),A)]
3582 * Note that we can project out S because it is uniquely defined by L.
3584 static __isl_give isl_ast_node
*copy_access(struct gpu_gen
*gen
,
3585 __isl_take isl_map
*sched
,
3586 const char *type
, struct gpu_array_ref_group
*group
,
3587 __isl_take isl_ast_build
*build
, int private)
3589 const char *array_name
;
3590 const char *mem
= private ? "private" : "shared";
3594 isl_map
*schedule
, *shift
, *map
;
3596 isl_id_list
*iterators
;
3599 shift
= isl_set_unwrap(isl_map_domain(isl_map_copy(sched
)));
3600 array_name
= isl_map_get_tuple_name(shift
, isl_dim_out
);
3601 shift
= shift_access(shift
, group
);
3603 schedule
= isl_map_copy(shift
);
3605 schedule
= tile_access_schedule(gen
, schedule
);
3607 n
= isl_map_dim(schedule
, isl_dim_out
);
3608 set
= isl_set_universe(isl_ast_build_get_schedule_space(build
));
3609 set
= add_bounded_parameters(set
, gen
->n_block
, gen
->block_dim
, "t");
3611 schedule
= isl_map_range_product(sched
, schedule
);
3614 name
= isl_alloc_array(gen
->ctx
, char,
3615 strlen(type
) + sizeof("_private_") + strlen(array_name
) + 20);
3616 if (group
->array
->n_group
> 1)
3617 sprintf(name
, "%s_%s_%s_%d", type
, mem
, array_name
, group
->nr
);
3619 sprintf(name
, "%s_%s_%s", type
, mem
, array_name
);
3620 shift
= isl_map_set_tuple_name(shift
,
3621 isl_dim_out
, name
+ strlen(type
) + 1);
3623 space
= isl_space_domain(isl_map_get_space(shift
));
3624 map
= isl_map_range_map(isl_map_universe(isl_space_unwrap(space
)));
3625 map
= isl_map_range_product(map
, shift
);
3627 schedule
= isl_map_apply_domain(schedule
, map
);
3629 schedule
= isl_map_set_tuple_name(schedule
, isl_dim_in
, name
);
3632 build
= isl_ast_build_restrict(build
, set
);
3634 gen
->copy_group
= group
;
3637 space
= isl_space_range(isl_map_get_space(schedule
));
3638 space
= isl_space_range(isl_space_unwrap(space
));
3639 build
= set_unroll(build
, space
, 0);
3641 iterators
= generate_names(gen
->ctx
, n
, "c");
3642 build
= isl_ast_build_set_iterators(build
, iterators
);
3643 build
= isl_ast_build_set_at_each_domain(build
, &attach_copy_stmt
, gen
);
3644 tree
= isl_ast_build_ast_from_schedule(build
,
3645 isl_union_map_from_map(schedule
));
3646 isl_ast_build_free(build
);
3651 /* Return code for reading into or writing from shared memory
3652 * the given array reference group.
3654 * If we are performing a read from global memory to shared memory and
3655 * if the array involved is not a scalar, then we copy
3656 * the entire tile to shared memory. This may result in some extra
3657 * elements getting copied, but it should lead to simpler code
3658 * (which means that fewer registers may be needed) and less divergence.
3660 * Otherwise, we only copy the elements that will be read or have been written
3664 * The input "sched" is of the form.
3668 * with S the first shared_len dimensions of the computed schedule,
3669 * A the array and L the schedule correponding to the generated loops.
3671 * We first drop "type",
3675 * If the above conditions are satisfied, we project out A,
3680 * and then introduce the group tile [S -> T], resulting in
3684 static __isl_give isl_ast_node
*copy_group_shared_accesses(
3685 struct gpu_gen
*gen
, struct gpu_array_ref_group
*group
,
3686 __isl_take isl_map
*sched
, __isl_take isl_ast_build
*build
)
3690 isl_union_map
*access
;
3692 type
= isl_map_get_tuple_name(sched
, isl_dim_in
);
3693 read
= !strcmp(type
, "read");
3695 sched
= isl_map_reset_tuple_id(sched
, isl_dim_in
);
3697 if (read
&& group
->array
->n_index
> 0) {
3701 space
= isl_space_domain(isl_map_get_space(sched
));
3702 space
= isl_space_unwrap(space
);
3703 map
= isl_map_domain_map(isl_map_universe(space
));
3704 sched
= isl_map_apply_domain(sched
, map
);
3706 map
= group_tile(group
);
3707 map
= isl_map_reverse(isl_map_domain_map(map
));
3708 sched
= isl_map_apply_domain(sched
, map
);
3711 return copy_access(gen
, sched
, type
, group
, build
, 0);
3714 /* Return code for reading into or writing from private memory
3715 * the given array reference group.
3717 * Let S be the first shared_len dimensions of the computed schedule,
3718 * D the iteration domains, A the array and L the schedule correponding
3719 * to the generated loops.
3720 * "sched" is of the form
3724 * where type is either "read" or "write".
3725 * We apply the privatization D -> S(t), with t the thread ids,
3726 * to the access relation D -> A to obtain the privatized access relation
3730 * We drop the type from "sched" and intersect with the privatized access
3731 * relation to obtain
3735 static __isl_give isl_ast_node
*copy_group_private_accesses(
3736 struct gpu_gen
*gen
, struct gpu_array_ref_group
*group
,
3737 __isl_take isl_map
*sched
, __isl_take isl_ast_build
*build
)
3741 isl_union_map
*priv
;
3742 isl_union_map
*access
;
3743 isl_map
*access_map
;
3745 type
= isl_map_get_tuple_name(sched
, isl_dim_in
);
3746 read
= !strcmp(type
, "read");
3748 priv
= isl_union_map_from_map(isl_map_copy(gen
->privatization
));
3749 priv
= isl_union_map_apply_range(isl_union_map_copy(gen
->shared_sched
),
3752 access
= group_access_relation(group
, read
, !read
);
3753 access
= isl_union_map_apply_domain(access
, priv
);
3754 access_map
= isl_map_from_union_map(access
);
3756 sched
= isl_map_reset_tuple_id(sched
, isl_dim_in
);
3757 sched
= isl_map_intersect_domain(sched
, isl_map_wrap(access_map
));
3759 return copy_access(gen
, sched
, type
, group
, build
, 1);
3762 /* Return code for reading into or writing from shared or private memory.
3764 * "schedule" is of the form
3768 * with S be the first shared_len dimensions of the computed schedule,
3769 * A the array and L the schedule correponding to the generated loops.
3770 * The array reference group is attached to "type".
3772 static __isl_give isl_ast_node
*create_access_leaf(
3773 struct gpu_gen
*gen
, __isl_take isl_map
*schedule
,
3774 __isl_take isl_ast_build
*build
)
3776 struct gpu_array_ref_group
*group
;
3779 id
= isl_map_get_tuple_id(schedule
, isl_dim_in
);
3780 group
= isl_id_get_user(id
);
3783 if (group
->private_tile
)
3784 return copy_group_private_accesses(gen
, group
, schedule
,
3787 return copy_group_shared_accesses(gen
, group
, schedule
,
3791 /* Create a domain node representing a synchronization.
3793 static __isl_give isl_ast_node
*create_sync_leaf(
3794 struct gpu_gen
*gen
, __isl_take isl_map
*schedule
,
3795 __isl_take isl_ast_build
*build
)
3797 struct ppcg_kernel_stmt
*stmt
;
3803 isl_map_free(schedule
);
3805 stmt
= isl_calloc_type(gen
->ctx
, struct ppcg_kernel_stmt
);
3809 stmt
->type
= ppcg_kernel_sync
;
3811 space
= isl_ast_build_get_schedule_space(build
);
3812 space
= isl_space_from_domain(space
);
3813 space
= isl_space_set_tuple_name(space
, isl_dim_out
, "sync");
3814 expr
= isl_ast_build_call_from_pw_multi_aff(build
,
3815 isl_pw_multi_aff_from_multi_aff(isl_multi_aff_zero(space
)));
3816 node
= isl_ast_node_alloc_user(expr
);
3817 isl_ast_build_free(build
);
3819 id
= isl_id_alloc(gen
->ctx
, NULL
, stmt
);
3820 id
= isl_id_set_free_user(id
, &ppcg_kernel_stmt_free
);
3821 return isl_ast_node_set_annotation(node
, id
);
3824 /* This function is called during the code generation at the point
3825 * where the schedule domain element is completely determined by
3826 * the generated code. The input schedule contains the original
3827 * statements as well as synchronization and copy "statements".
3828 * The latter are scheduled at different points than any of the original
3829 * statements, so they will only arrive here in isolation.
3831 * If the current schedule only refers to a single statement,
3832 * we check if it is a copy or synchronization statement and
3833 * call the appropriate functions.
3834 * Otherwise, we assume we are dealing with the original statements
3835 * and we call create_domain_leaf.
3837 static __isl_give isl_ast_node
*create_kernel_leaf(
3838 __isl_take isl_ast_build
*build
, void *user
)
3840 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
3842 isl_union_map
*schedule
;
3845 schedule
= isl_ast_build_get_schedule(build
);
3847 if (isl_union_map_n_map(schedule
) != 1)
3848 return create_domain_leaf(schedule
, build
, user
);
3850 map
= isl_map_from_union_map(schedule
);
3851 name
= isl_map_get_tuple_name(map
, isl_dim_in
);
3852 if (!strcmp(name
, "read") || !strcmp(name
, "write"))
3853 return create_access_leaf(gen
, map
, build
);
3854 if (!strcmp(name
, "sync"))
3855 return create_sync_leaf(gen
, map
, build
);
3857 return create_domain_leaf(isl_union_map_from_map(map
), build
, user
);
3860 /* Mark all odd schedule dimensions as "atomic" (when the even dimensions
3861 * have value 0) and all even schedule dimensions as "unroll".
3863 * That is, the options look as follows
3865 * { [0, b, 0, d, ..., 0] -> atomic[i] : exists a : i = 2 a + 1;
3866 * [a, b, c, d, ..., z] -> unroll[i] : exists a : i = 2 a }
3868 * The even positions are used to be able to schedule copying blocks
3869 * and synchronization before or after each level of the shared memory
3870 * tile loops and we want to make sure that code for these is generated
3871 * separately (within each level).
3873 static __isl_give isl_ast_build
*set_atomic_and_unroll(
3874 __isl_take isl_ast_build
*build
,
3875 __isl_take isl_space
*space
, int sched_len
)
3881 isl_local_space
*ls
;
3884 ctx
= isl_ast_build_get_ctx(build
);
3886 space
= isl_space_params(space
);
3887 space
= isl_space_add_dims(space
, isl_dim_set
, sched_len
);
3888 space
= isl_space_from_domain(space
);
3889 space
= isl_space_add_dims(space
, isl_dim_out
, 2);
3890 map
= isl_map_universe(isl_space_copy(space
));
3891 for (i
= 0; i
< sched_len
; i
+= 2)
3892 map
= isl_map_fix_si(map
, isl_dim_in
, i
, 0);
3893 ls
= isl_local_space_from_space(isl_map_get_space(map
));
3894 c
= isl_equality_alloc(ls
);
3895 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, 0, 1);
3896 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, 1, 2);
3897 c
= isl_constraint_set_constant_si(c
, 1);
3898 map
= isl_map_add_constraint(map
, c
);
3899 map
= isl_map_project_out(map
, isl_dim_out
, 1, 1);
3900 map
= isl_map_set_tuple_name(map
, isl_dim_out
, "atomic");
3901 opt
= isl_union_map_from_map(map
);
3903 map
= isl_map_universe(space
);
3904 ls
= isl_local_space_from_space(isl_map_get_space(map
));
3905 c
= isl_equality_alloc(ls
);
3906 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, 0, 1);
3907 c
= isl_constraint_set_coefficient_si(c
, isl_dim_out
, 1, 2);
3908 map
= isl_map_add_constraint(map
, c
);
3909 map
= isl_map_project_out(map
, isl_dim_out
, 1, 1);
3910 map
= isl_map_set_tuple_name(map
, isl_dim_out
, "unroll");
3911 opt
= isl_union_map_add_map(opt
, map
);
3913 build
= isl_ast_build_set_options(build
, opt
);
3918 /* Return a map that maps a space of dimension gen->shared_len
3919 * to its last dimensions starting at gen->tile_first.
3920 * The range is of dimension
3922 * 2 * (gen->shared_len - gen->tile_first) + 1
3924 * The input dimensions are mapped to the odd dimensions in the output,
3925 * while the even dimensions (except 2*pos) are fixed to 0.
3926 * Output dimension 2*pos (if pos >= 0) is fixed to "val".
3927 * If pos >= 0, then only the pos first dimensions starting at gen->tile_first
3928 * are mapped to the output. The remaining input dimensions are projected
3929 * out and the corresponding output dimensions are fixed to 0.
3931 static __isl_give isl_map
*insert_even(struct gpu_gen
*gen
,
3932 __isl_take isl_space
*space
, int pos
, int val
)
3937 space
= isl_space_set_from_params(space
);
3938 space
= isl_space_add_dims(space
, isl_dim_set
, gen
->shared_len
);
3939 space
= isl_space_map_from_set(space
);
3940 proj
= isl_map_identity(space
);
3941 proj
= isl_map_project_out(proj
, isl_dim_out
, 0, gen
->tile_first
);
3942 n
= gen
->shared_len
- gen
->tile_first
;
3943 for (i
= 0; i
<= n
; ++i
) {
3944 proj
= isl_map_insert_dims(proj
, isl_dim_out
, 2 * i
, 1);
3946 proj
= isl_map_fix_si(proj
, isl_dim_out
, 2 * i
, val
);
3948 proj
= isl_map_fix_si(proj
, isl_dim_out
, 2 * i
, 0);
3954 proj
= isl_map_eliminate(proj
, isl_dim_in
, gen
->tile_first
+ pos
,
3955 gen
->shared_len
- (gen
->tile_first
+ pos
));
3956 for (i
= pos
; i
< n
; ++i
)
3957 proj
= isl_map_fix_si(proj
, isl_dim_out
, 2 * i
+ 1, 0);
3962 /* Given the AST context schedule "schedule" and the mapping from
3963 * domains to the shared tile loops "shared_sched", add a schedule
3964 * for a synchronization operation at position "val" of loop level "pos".
3966 * schedule is of the form
3970 * (with D the iteration domains and L the already generated loops),
3971 * while shared_sched is of the form
3975 * We combine them into
3981 * [s_0,...] -> [0,s_{tile_first},0,..., val, 0, 0, ... 0]
3983 * and use the result as a schedule for "sync".
3985 static __isl_give isl_union_map
*add_sync_schedule(struct gpu_gen
*gen
,
3986 __isl_take isl_union_map
*res
, __isl_keep isl_union_map
*schedule
,
3987 __isl_keep isl_union_map
*shared_sched
, int pos
, int val
)
3990 isl_map
*proj
, *map
;
3992 shared_sched
= isl_union_map_copy(shared_sched
);
3993 schedule
= isl_union_map_copy(schedule
);
3995 space
= isl_union_map_get_space(shared_sched
);
3996 schedule
= isl_union_map_apply_domain(shared_sched
, schedule
);
3997 map
= isl_map_from_union_map(schedule
);
3999 proj
= insert_even(gen
, space
, pos
, val
);
4000 map
= isl_map_apply_range(map
, proj
);
4001 map
= isl_map_from_range(isl_map_wrap(map
));
4002 map
= isl_map_set_tuple_name(map
, isl_dim_in
, "sync");
4004 res
= isl_union_map_add_map(res
, map
);
4009 /* Given the AST context schedule "schedule" and the mapping from
4010 * domains to the shared tile loops "shared_sched", add a schedule
4011 * for copying an array reference group to/from shared/private memory.
4012 * "read" is set if data should be copied from global memory
4013 * to shared/private memory.
4014 * "k" represents the current group
4015 * "s" is the total number of groups
4017 * We schedule an operation before or after the innermost loop
4018 * of "shared_sched" that affects the tile of the array reference group.
4020 * schedule is of the form
4024 * (with D the iteration domains and L the already generated loops),
4025 * while shared_sched is of the form
4029 * We first compute the access relation for the reference group
4033 * and combine it with shared_sched into
4037 * If this results in an empty relation, no copying needs to be performed
4039 * Otherwise, we invert the relation and combine it with "schedule" into
4043 * The actual additional piece of the schedule is obtained from combining
4049 * [s_0,...] -> [0,s_{tile_first},0,..., val, 0, 0, ... 0]
4051 * The position of "val" corresponds to the innermost loop that affects
4052 * the tile and the value indicates where the copying is scheduled
4053 * with respect to the actual kernel code (at value 0).
4054 * Reads are schedule before the code, writes to global memory from
4055 * private memory are scheduled at values 1 to s, writes to global
4056 * memory from shared memory are scheduled at values s + 2 to 2 * s + 1.
4058 * If we are scheduling a read from global memory to shared memory,
4059 * we insert a synchronization before the kernel code (at the innermost
4061 * If we are scheduling a write to global memory, then we add
4062 * a synchronization after all writes (at value 2 *s + 2).
4063 * However, there is no need for a synchronization after the outermost loop.
4064 * A write to global memory from private memory at the innermost level
4065 * does not require a synchronization, because it is covered by
4066 * the synchronization after the kernel inserted by body_schedule.
4068 static __isl_give isl_union_map
*add_group_schedule(struct gpu_gen
*gen
,
4069 __isl_take isl_union_map
*res
, __isl_keep isl_union_map
*schedule
,
4070 __isl_keep isl_union_map
*shared_sched
,
4071 struct gpu_array_ref_group
*group
, int read
, int k
, int s
)
4076 isl_union_map
*access
;
4077 isl_map
*map
, *proj
, *access_map
;
4080 access
= group_access_relation(group
, read
, !read
);
4081 access
= isl_union_map_range_product(isl_union_map_copy(shared_sched
),
4084 if (isl_union_map_is_empty(access
)) {
4085 isl_union_map_free(access
);
4089 access
= isl_union_map_reverse(access
);
4090 access
= isl_union_map_apply_range(access
,
4091 isl_union_map_copy(schedule
));
4092 access_map
= isl_map_from_union_map(access
);
4094 space
= isl_space_copy(group
->array
->dim
);
4095 space
= isl_space_from_range(space
);
4096 space
= isl_space_add_dims(space
, isl_dim_in
, gen
->shared_len
);
4097 map
= isl_map_domain_map(isl_map_universe(space
));
4099 space
= isl_union_map_get_space(schedule
);
4100 pos
= group
->last_shared
+ 1 - gen
->tile_first
;
4104 else if (group
->private_tile
)
4107 val
= 1 + s
+ 1 + k
;
4108 proj
= insert_even(gen
, space
, pos
, val
);
4109 map
= isl_map_apply_range(map
, proj
);
4111 access_map
= isl_map_range_product(access_map
, map
);
4113 id
= isl_id_alloc(gen
->ctx
, read
? "read" : "write", group
);
4114 access_map
= isl_map_set_tuple_id(access_map
, isl_dim_in
, id
);
4116 res
= isl_union_map_add_map(res
, access_map
);
4118 n
= gen
->shared_len
- gen
->tile_first
;
4120 if (!group
->private_tile
)
4121 res
= add_sync_schedule(gen
, res
, schedule
,
4122 shared_sched
, n
, -1);
4126 if (pos
== n
&& group
->private_tile
)
4128 res
= add_sync_schedule(gen
, res
, schedule
, shared_sched
,
4135 /* Return a schedule for the shared tile loops based on the current
4136 * AST context schedule.
4138 * We create a "shared_sched" that maps the domains to the first
4139 * shared_len dimensions of the computed schedule, project out the
4140 * first tile_first dimensions (as these are already covered by
4141 * the host code) and insert "statement-level" dimensions at even
4142 * positions so that we can schedule copy blocks and synchronization
4143 * before/after each level.
4145 * In particular, copy blocks are inserted inside the innermost
4146 * level that affect the tile. For the copying to global memory,
4147 * those from private memory are scheduled before those from shared
4148 * memory such that synchronization can be inserted between the two
4149 * at the innermost level.
4150 * Synchronization is inserted at the innermost level before the
4151 * actual kernel code if there is any copying from global memory
4152 * to shared memory. It is inserted unconditionally at the innermost
4153 * level after the actual kernel code and the copying to global memory
4154 * from private memory (if any). Finally, it is inserted after
4155 * any copying to global memory, except at the outermost level
4156 * and at the innermost level if there is no copying from shared
4157 * memory. The copying from private memory is covered by the unconditional
4158 * synchronization at the innermost level.
4160 static __isl_give isl_union_map
*body_schedule(struct gpu_gen
*gen
,
4161 __isl_take isl_union_map
*schedule
)
4165 isl_union_map
*shared_sched
;
4166 isl_union_map
*sched
;
4167 isl_map
*proj
, *map
;
4170 shared_sched
= isl_union_map_copy(gen
->tiled_sched
);
4171 proj
= projection(isl_union_map_get_space(shared_sched
),
4172 gen
->tiled_len
, gen
->shared_len
);
4173 shared_sched
= isl_union_map_apply_range(shared_sched
,
4174 isl_union_map_from_map(proj
));
4175 space
= isl_union_map_get_space(shared_sched
);
4176 proj
= insert_even(gen
, space
, -1, 0);
4177 sched
= isl_union_map_apply_range(isl_union_map_copy(shared_sched
),
4178 isl_union_map_from_map(proj
));
4180 res
= isl_union_map_range_product(isl_union_map_copy(schedule
), sched
);
4183 for (i
= 0; i
< gen
->prog
->n_array
; ++i
)
4184 s
+= gen
->prog
->array
[i
].n_group
;
4187 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
4188 struct gpu_array_info
*array
= &gen
->prog
->array
[i
];
4190 for (j
= 0; j
< array
->n_group
; ++j
) {
4191 struct gpu_array_ref_group
*group
;
4193 group
= array
->groups
[j
];
4194 if (!group
->private_tile
&& !group
->shared_tile
)
4196 res
= add_group_schedule(gen
, res
, schedule
,
4197 shared_sched
, group
, 0, k
, s
);
4198 res
= add_group_schedule(gen
, res
, schedule
,
4199 shared_sched
, group
, 1, k
, s
);
4204 res
= add_sync_schedule(gen
, res
, schedule
, shared_sched
,
4205 gen
->shared_len
- gen
->tile_first
, 1 + s
);
4207 isl_union_map_free(shared_sched
);
4208 isl_union_map_free(schedule
);
4213 /* Generate code for "kernel" in the given "context".
4215 * We first generate code for the shared tile loops (T1T, T1P and T2)
4216 * in a context that includes the block ids.
4217 * Within each iteration of these loops an additional code generation
4218 * is performed (within create_kernel_leaf) for the rest of the schedule
4219 * in a context that includes the thread ids.
4221 static __isl_give isl_ast_node
*generate_kernel(struct gpu_gen
*gen
,
4222 __isl_keep isl_ast_build
*build
, __isl_keep isl_set
*host_domain
,
4223 __isl_keep isl_multi_pw_aff
*grid_size
)
4227 isl_id_list
*iterators
;
4228 isl_union_map
*schedule
;
4232 schedule
= isl_ast_build_get_schedule(build
);
4234 build
= isl_ast_build_copy(build
);
4235 build
= isl_ast_build_restrict(build
, isl_set_copy(host_domain
));
4236 space
= isl_ast_build_get_schedule_space(build
);
4237 set
= isl_set_universe(isl_space_copy(space
));
4238 set
= add_bounded_parameters_dynamic(set
, grid_size
, "b");
4239 build
= isl_ast_build_restrict(build
, set
);
4241 schedule
= body_schedule(gen
, schedule
);
4243 sched_len
= 2 * (gen
->shared_len
- gen
->tile_first
) + 1;
4245 build
= set_atomic_and_unroll(build
, space
, sched_len
);
4246 iterators
= generate_names(gen
->ctx
, sched_len
, "g");
4247 build
= isl_ast_build_set_iterators(build
, iterators
);
4248 build
= isl_ast_build_set_create_leaf(build
, &create_kernel_leaf
, gen
);
4249 tree
= isl_ast_build_ast_from_schedule(build
, schedule
);
4250 isl_ast_build_free(build
);
4255 /* Attach "id" to the given node.
4257 static __isl_give isl_ast_node
*attach_id(__isl_take isl_ast_node
*node
,
4258 __isl_keep isl_ast_build
*build
, void *user
)
4262 node
= isl_ast_node_set_annotation(node
, id
);
4267 /* Construct an AST node for performing a kernel launch and attach
4268 * the information about the kernel to that node.
4270 * The kernel AST has been constructed in the context of the range
4271 * of "schedule". In particular, the grid size has been computed
4272 * in the context. We therefore still need to make sure that these
4273 * constraints are expressed in the code. We do this by creating a schedule
4275 * kernel[] -> [S -> []]
4277 * where S is the schedule domain, i.e., the range of "schedule".
4278 * The AST generation will then create a single call surrounded by
4279 * all the condition in "S" that have not been expressed yet.
4281 * The kernel information is attached to this node in attach_id.
4283 static __isl_give isl_ast_node
*construct_launch(
4284 __isl_take isl_ast_build
*build
, __isl_take isl_union_map
*schedule
,
4285 __isl_take
struct ppcg_kernel
*kernel
)
4289 isl_union_set
*domain
;
4294 ctx
= isl_ast_build_get_ctx(build
);
4296 id
= isl_id_alloc(ctx
, NULL
, kernel
);
4297 id
= isl_id_set_free_user(id
, &ppcg_kernel_free
);
4299 domain
= isl_union_map_range(schedule
);
4300 set
= isl_set_from_union_set(domain
);
4301 map
= isl_map_from_domain(set
);
4302 map
= isl_map_from_range(isl_map_wrap(map
));
4303 map
= isl_map_set_tuple_name(map
, isl_dim_in
, "kernel");
4304 schedule
= isl_union_map_from_map(map
);
4306 build
= isl_ast_build_set_at_each_domain(build
, &attach_id
, id
);
4307 node
= isl_ast_build_ast_from_schedule(build
, schedule
);
4308 isl_ast_build_free(build
);
4313 /* This function is called for each leaf in the AST of the host code.
4314 * We first specialize the schedule to the site of the leaf, compute
4315 * the size of shared memory and then construct the body of host code
4316 * and the associated kernel.
4318 * The necessary information for printing the kernel launch is
4319 * stored in a struct ppcg_kernel and attached to the leaf node
4320 * created to represent the launch.
4322 static __isl_give isl_ast_node
*create_host_leaf(
4323 __isl_take isl_ast_build
*build
, void *user
)
4325 struct gpu_gen
*gen
= (struct gpu_gen
*) user
;
4328 struct ppcg_kernel
*kernel
;
4329 isl_set
*host_domain
;
4330 isl_union_map
*schedule
;
4331 isl_union_map
*local_sched
;
4332 isl_union_map
*access
;
4333 isl_union_set
*domain
;
4336 schedule
= isl_ast_build_get_schedule(build
);
4338 isl_union_map_foreach_map(schedule
, &extract_tile_len
, gen
);
4341 domain
= isl_union_map_domain(isl_union_map_copy(schedule
));
4343 local_sched
= isl_union_map_copy(gen
->sched
);
4344 local_sched
= isl_union_map_intersect_domain(local_sched
, domain
);
4345 access
= isl_union_map_union(isl_union_map_copy(gen
->prog
->read
),
4346 isl_union_map_copy(gen
->prog
->write
));
4347 access
= isl_union_map_apply_domain(access
,
4348 isl_union_map_copy(local_sched
));
4350 gen
->tiled_sched
= tile_schedule(gen
, local_sched
);
4351 gen
->tiled_sched
= parametrize_tiled_schedule(gen
, gen
->tiled_sched
);
4352 gen
->tiled_sched
= scale_tile_loops(gen
, gen
->tiled_sched
);
4354 kernel
= gen
->kernel
= isl_calloc_type(gen
->ctx
, struct ppcg_kernel
);
4358 kernel
->id
= gen
->kernel_id
++;
4359 kernel
->n_block
= gen
->n_block
;
4360 for (i
= 0; i
< gen
->n_block
; ++i
)
4361 kernel
->block_dim
[i
] = gen
->block_dim
[i
];
4362 kernel
->n_grid
= gen
->n_grid
;
4363 for (i
= 0; i
< gen
->n_grid
; ++i
)
4364 kernel
->grid_dim
[i
] = gen
->grid_dim
[i
];
4365 kernel
->context
= isl_union_map_params(isl_union_map_copy(schedule
));
4366 kernel
->grid_size
= extract_grid_size(gen
, kernel
);
4367 kernel
->arrays
= isl_union_map_range(access
);
4368 kernel
->space
= isl_ast_build_get_schedule_space(build
);
4370 gen
->local_sched
= isl_union_map_copy(gen
->tiled_sched
);
4372 gen
->local_sched
= thread_tile_schedule(gen
, gen
->local_sched
);
4373 gen
->local_sched
= scale_thread_tile_loops(gen
, gen
->local_sched
);
4375 gen
->private_access
= NULL
;
4376 compute_shared_sched(gen
);
4377 gen
->privatization
= compute_privatization(gen
);
4378 group_references(gen
);
4379 compute_private_access(gen
);
4380 check_shared_memory_bound(gen
);
4381 host_domain
= isl_set_from_union_set(isl_union_map_range(
4382 isl_union_map_copy(schedule
)));
4383 localize_bounds(gen
, kernel
, host_domain
);
4385 gen
->local_sched
= interchange_for_unroll(gen
, gen
->local_sched
);
4387 kernel
->tree
= generate_kernel(gen
, build
, host_domain
,
4389 create_kernel_vars(gen
, kernel
);
4391 free_local_array_info(gen
);
4392 isl_map_free(gen
->privatization
);
4393 isl_union_map_free(gen
->private_access
);
4394 isl_union_map_free(gen
->local_sched
);
4395 isl_union_map_free(gen
->tiled_sched
);
4396 isl_union_map_free(gen
->shared_sched
);
4397 isl_union_map_free(gen
->shared_proj
);
4398 isl_set_free(host_domain
);
4399 free(gen
->tile_size
);
4401 node
= construct_launch(build
, schedule
, kernel
);
4405 isl_union_map_free(schedule
);
4409 /* Use isl to generate code for the outer gen->tile_first loops
4410 * of the global schedule in gen->sched, resulting in the host code.
4411 * Within each iteration of this partial schedule, i.e., for each kernel
4412 * launch, create_host_leaf takes care of generating the kernel code.
4414 static __isl_give isl_ast_node
*generate_host_code(struct gpu_gen
*gen
)
4416 isl_ast_build
*build
;
4418 isl_union_map
*sched
;
4420 isl_id_list
*iterators
;
4422 sched
= isl_union_map_copy(gen
->sched
);
4423 proj
= projection(isl_union_map_get_space(sched
),
4424 gen
->untiled_len
, gen
->tile_first
);
4425 sched
= isl_union_map_apply_range(sched
, isl_union_map_from_map(proj
));
4427 isl_options_set_ast_build_group_coscheduled(gen
->ctx
, 1);
4428 build
= isl_ast_build_from_context(isl_set_copy(gen
->prog
->context
));
4429 iterators
= generate_names(gen
->ctx
, gen
->tile_first
, "h");
4430 build
= isl_ast_build_set_iterators(build
, iterators
);
4431 build
= isl_ast_build_set_create_leaf(build
, &create_host_leaf
, gen
);
4432 tree
= isl_ast_build_ast_from_schedule(build
, sched
);
4433 isl_ast_build_free(build
);
4438 __isl_give isl_union_map
*extract_sizes_from_str(isl_ctx
*ctx
, const char *str
)
4442 return isl_union_map_read_from_str(ctx
, str
);
4445 /* Information about the outermost tilable bands in the forest of bands.
4447 * tile_len and n_parallel are only sets on band_info structures
4448 * that correspond to outermost bands. For other bands (in particular,
4449 * ancestors of the outermost bands), n_parallal is set to 0.
4451 * prefix is the (padded) schedule leading up to the outermost tilable bands.
4453 * tile_first is the number of schedule dimensions in prefix.
4455 * suffix is the schedule of the outermost tilable bands and their descendants.
4458 struct gpu_gen
*gen
;
4462 isl_union_map
*prefix
;
4463 isl_union_map
*suffix
;
4466 /* Set tile_len and n_parallel of the statement to that of
4467 * their outermost band, recorded in the band_info.
4469 static int set_stmt_tile_len(__isl_take isl_map
*map
, void *user
)
4471 struct band_info
*info
= user
;
4472 struct gpu_stmt
*stmt
;
4475 id
= isl_map_get_tuple_id(map
, isl_dim_in
);
4476 stmt
= find_stmt(info
->gen
->prog
, id
);
4479 stmt
->tile_len
= info
->tile_len
;
4480 stmt
->n_parallel
= info
->n_parallel
;
4487 static void list_select_outer_band(struct gpu_gen
*gen
,
4488 __isl_take isl_band_list
*list
, int pos
, struct band_info
*list_info
);
4490 /* Check if this band has any parallel loops. If so, take it as
4491 * the outermost tilable band. If not, continue looking for the
4492 * outermost tilable band in the children of the current band.
4494 static void band_select_outer_band(struct gpu_gen
*gen
,
4495 __isl_take isl_band
*band
, int pos
, struct band_info
*info
)
4497 int n
= isl_band_n_member(band
);
4500 for (n_parallel
= 0; n_parallel
< n
; ++n_parallel
)
4501 if (!isl_band_member_is_zero_distance(band
, n_parallel
))
4504 info
->n_parallel
= n_parallel
;
4507 info
->tile_first
= pos
;
4509 info
->prefix
= isl_band_get_prefix_schedule(band
);
4510 info
->suffix
= isl_union_map_flat_range_product(
4511 isl_band_get_partial_schedule(band
),
4512 isl_band_get_suffix_schedule(band
));
4513 isl_union_map_foreach_map(info
->prefix
,
4514 &set_stmt_tile_len
, info
);
4515 } else if (isl_band_has_children(band
)) {
4516 isl_band_list
*children
;
4517 children
= isl_band_get_children(band
);
4518 list_select_outer_band(gen
, children
, pos
+ n
, info
);
4521 info
->tile_first
= pos
+ n
;
4523 info
->prefix
= isl_union_map_flat_range_product(
4524 isl_band_get_prefix_schedule(band
),
4525 isl_band_get_partial_schedule(band
));
4526 info
->suffix
= isl_band_get_suffix_schedule(band
);
4527 isl_union_map_foreach_map(info
->prefix
,
4528 &set_stmt_tile_len
, info
);
4531 isl_band_free(band
);
4534 /* Comparison function that returns a non-zero value for band_infos
4535 * with different tile_len fields or different n_parallel fields.
4537 static int cmp_band(const void *p1
, const void *p2
)
4539 const struct band_info
*info1
= p1
;
4540 const struct band_info
*info2
= p2
;
4542 if (info1
->tile_len
!= info2
->tile_len
)
4543 return info1
->tile_len
- info2
->tile_len
;
4545 return info1
->n_parallel
- info2
->n_parallel
;
4548 /* Extend "umap" with coordinates with fixed value "val"
4549 * to a total length of "dst_len", assuming the original dimension is "src_len".
4551 static __isl_give isl_union_map
*extend_range(
4552 __isl_take isl_union_map
*umap
, int src_len
, int dst_len
, int val
)
4558 dim
= isl_union_map_get_space(umap
);
4559 map
= isl_map_reverse(projection(dim
, dst_len
, src_len
));
4560 for (i
= src_len
; i
< dst_len
; ++i
)
4561 map
= isl_map_fix_si(map
, isl_dim_out
, i
, val
);
4563 umap
= isl_union_map_apply_range(umap
, isl_union_map_from_map(map
));
4568 /* Group bands with the same values for tile_len and n_parallel.
4569 * The prefix schedule is then extended with a fixed coordinate that
4570 * is different for each such group.
4571 * Note that the actual values for this coordinate are not important.
4572 * The bands have already been effectively separated at a higher level
4573 * or they are independent and may be executed in parallel.
4574 * The list of band_info has been sorted before this functions is called.
4576 static void separate_bands(struct band_info
*info
, int n
)
4581 for (i
= 0; i
< n
; ++i
) {
4582 int l
= info
[i
].tile_first
;
4585 (info
[i
].tile_len
!= info
[i
- 1].tile_len
||
4586 info
[i
].n_parallel
!= info
[i
- 1].n_parallel
))
4589 info
[i
].prefix
= extend_range(info
[i
].prefix
,
4591 info
[i
].tile_first
= l
+ 1;
4595 /* Select the outermost bands in the elements of the list, align
4596 * their prefix schedules, separate bands with different values
4597 * for tile_len and/or n_parallel and then combine the resulting
4598 * prefix and suffix schedules into a single pair of prefix and
4599 * suffix schedules for the entire list.
4601 static void list_select_outer_band(struct gpu_gen
*gen
,
4602 __isl_take isl_band_list
*list
, int pos
, struct band_info
*list_info
)
4606 int n
= isl_band_list_n_band(list
);
4607 isl_ctx
*ctx
= isl_band_list_get_ctx(list
);
4608 struct band_info
*info
;
4610 isl_union_map
*prefix
;
4611 isl_union_map
*suffix
;
4614 info
= isl_calloc_array(ctx
, struct band_info
, n
);
4618 for (i
= 0; i
< n
; ++i
) {
4619 band
= isl_band_list_get_band(list
, i
);
4620 band_select_outer_band(gen
, band
, pos
, &info
[i
]);
4621 if (info
[i
].tile_first
> max_tile_first
)
4622 max_tile_first
= info
[i
].tile_first
;
4625 for (i
= 0; i
< n
; ++i
) {
4626 if (info
[i
].tile_first
== max_tile_first
)
4628 info
[i
].prefix
= extend_range(info
[i
].prefix
,
4629 info
[i
].tile_first
, max_tile_first
, 0);
4630 info
[i
].tile_first
= max_tile_first
;
4633 qsort(info
, n
, sizeof(struct band_info
), &cmp_band
);
4635 for (i
= 0; i
< n
- 1; ++i
)
4636 if (info
[i
].tile_len
!= info
[i
+ 1].tile_len
||
4637 info
[i
].n_parallel
!= info
[i
+ 1].n_parallel
)
4641 separate_bands(info
, n
);
4643 prefix
= info
[0].prefix
;
4644 suffix
= info
[0].suffix
;
4646 for (i
= 1; i
< n
; ++i
) {
4647 prefix
= isl_union_map_union(prefix
, info
[i
].prefix
);
4648 suffix
= isl_union_map_union(suffix
, info
[i
].suffix
);
4651 list_info
->tile_first
= info
[0].tile_first
;
4652 list_info
->tile_len
= -1;
4653 list_info
->prefix
= prefix
;
4654 list_info
->suffix
= suffix
;
4656 isl_band_list_free(list
);
4660 /* Select the outermost tilable band that (by construction)
4661 * has at least one parallel loop.
4662 * The starting position of the aligned band is stored in the pair
4664 * The sizes and number of parallel loops may be different in different
4665 * parts of the band forest and are therefore stored in the gpu_stmts.
4667 * Return the complete schedule, with the tilable bands aligned
4668 * at gen->tile_first and padded with zero, if needed.
4670 static __isl_give isl_union_map
*select_outer_tilable_band(struct gpu_gen
*gen
,
4671 __isl_keep isl_schedule
*schedule
)
4673 isl_band_list
*list
;
4674 struct band_info info
;
4676 gen
->n_parallel
= 0;
4679 list
= isl_schedule_get_band_forest(schedule
);
4681 list_select_outer_band(gen
, list
, 0, &info
);
4683 gen
->tile_first
= info
.tile_first
;
4684 info
.suffix
= align_range(info
.suffix
);
4686 return isl_union_map_flat_range_product(info
.prefix
, info
.suffix
);
4689 /* Set gen->untiled_len to the number of scheduling dimensions
4690 * for the schedule of the first domain.
4691 * We assume here that this number is the same for all domains.
4693 static int set_untiled_len(__isl_take isl_map
*map
, void *user
)
4695 unsigned *untiled_len
= user
;
4697 *untiled_len
= isl_map_dim(map
, isl_dim_out
);
4703 /* Compute an appropriate schedule based on the accesses in
4704 * gen->read and gen->write.
4706 * We use the dependences in gen->prog->scop to compute
4707 * a schedule that has a parallel loop in each tilable band.
4708 * Finally, we select the outermost tilable band.
4710 static void compute_schedule(struct gpu_gen
*gen
)
4712 isl_union_set
*domain
;
4713 isl_union_map
*dep_raw
, *dep
;
4714 isl_union_map
*sched
;
4715 isl_schedule
*schedule
;
4717 dep_raw
= isl_union_map_copy(gen
->prog
->scop
->dep_flow
);
4719 dep
= isl_union_map_copy(gen
->prog
->scop
->dep_false
);
4720 dep
= isl_union_map_union(dep
, dep_raw
);
4721 dep
= isl_union_map_coalesce(dep
);
4723 domain
= isl_union_set_copy(gen
->prog
->scop
->domain
);
4724 domain
= isl_union_set_intersect_params(domain
,
4725 isl_set_copy(gen
->prog
->scop
->context
));
4726 schedule
= isl_union_set_compute_schedule(isl_union_set_copy(domain
),
4727 isl_union_map_copy(dep
), dep
);
4728 if (gen
->options
->debug
->dump_schedule
)
4729 isl_schedule_dump(schedule
);
4731 sched
= select_outer_tilable_band(gen
, schedule
);
4733 isl_union_map_foreach_map(sched
, &set_untiled_len
, &gen
->untiled_len
);
4734 sched
= isl_union_map_intersect_domain(sched
, domain
);
4737 isl_schedule_free(schedule
);
4740 /* Compute the sets of array elements that need to be copied in and out.
4742 * In particular, for each array that is written anywhere in gen->prog and
4743 * that is visible outside the corresponding scop, we copy out its entire
4746 * Any array elements that is read without first being written needs
4747 * to be copied in. Furthermore, if there are any array elements that
4748 * are copied out, but that are not written inside gen->prog, then
4749 * they also need to be copied in to ensure that the value after execution
4750 * is the same as the value before execution.
4751 * While computing the set of array elements that
4752 * are copied out but not written, we intersect both sets with the context.
4753 * This helps in those cases where the arrays are declared with a fixed size,
4754 * while the accesses are parametric and the context assigns a fixed value
4755 * to the parameters.
4757 static void compute_copy_in_and_out(struct gpu_gen
*gen
)
4760 isl_union_set
*write
;
4761 isl_union_set
*copy_in
, *copy_out
;
4762 isl_union_set
*not_written
;
4763 isl_union_map
*uninitialized
;
4765 write
= isl_union_map_range(isl_union_map_copy(gen
->prog
->write
));
4766 write
= isl_union_set_intersect_params(write
,
4767 isl_set_copy(gen
->prog
->context
));
4768 copy_out
= isl_union_set_empty(isl_union_set_get_space(write
));
4770 for (i
= 0; i
< gen
->prog
->n_array
; ++i
) {
4775 if (gen
->prog
->array
[i
].local
)
4778 space
= isl_space_copy(gen
->prog
->array
[i
].dim
);
4779 write_i
= isl_union_set_extract_set(write
, space
);
4780 empty
= isl_set_fast_is_empty(write_i
);
4781 isl_set_free(write_i
);
4785 write_i
= isl_set_copy(gen
->prog
->array
[i
].extent
);
4786 copy_out
= isl_union_set_add_set(copy_out
, write_i
);
4789 copy_out
= isl_union_set_intersect_params(copy_out
,
4790 isl_set_copy(gen
->prog
->context
));
4792 gen
->prog
->copy_out
= isl_union_set_copy(copy_out
);
4794 uninitialized
= isl_union_map_copy(gen
->prog
->scop
->live_in
);
4795 copy_in
= isl_union_map_range(uninitialized
);
4797 not_written
= isl_union_set_subtract(copy_out
, write
);
4798 copy_in
= isl_union_set_union(copy_in
, not_written
);
4799 gen
->prog
->copy_in
= copy_in
;
4802 static struct gpu_stmt_access
**expr_extract_access(struct pet_expr
*expr
,
4803 struct gpu_stmt_access
**next_access
)
4805 struct gpu_stmt_access
*access
;
4806 isl_ctx
*ctx
= isl_map_get_ctx(expr
->acc
.access
);
4808 access
= isl_alloc_type(ctx
, struct gpu_stmt_access
);
4810 access
->next
= NULL
;
4811 access
->read
= expr
->acc
.read
;
4812 access
->write
= expr
->acc
.write
;
4813 access
->access
= isl_map_copy(expr
->acc
.access
);
4815 *next_access
= access
;
4816 next_access
= &(*next_access
)->next
;
4820 static struct gpu_stmt_access
**expr_extract_accesses(struct pet_expr
*expr
,
4821 struct gpu_stmt_access
**next_access
)
4825 for (i
= 0; i
< expr
->n_arg
; ++i
)
4826 next_access
= expr_extract_accesses(expr
->args
[i
],
4829 if (expr
->type
== pet_expr_access
)
4830 next_access
= expr_extract_access(expr
, next_access
);
4835 static void pet_stmt_extract_accesses(struct gpu_stmt
*stmt
)
4837 struct gpu_stmt_access
**next_access
= &stmt
->accesses
;
4839 stmt
->accesses
= NULL
;
4840 expr_extract_accesses(stmt
->body
, next_access
);
4843 /* Return an array of gpu_stmt representing the statements in "scop".
4845 static struct gpu_stmt
*extract_stmts(isl_ctx
*ctx
, struct ppcg_scop
*scop
,
4846 __isl_keep isl_set
*context
)
4849 struct gpu_stmt
*stmts
;
4851 stmts
= isl_calloc_array(ctx
, struct gpu_stmt
, scop
->n_stmt
);
4854 for (i
= 0; i
< scop
->n_stmt
; ++i
) {
4855 struct gpu_stmt
*s
= &stmts
[i
];
4857 s
->id
= isl_set_get_tuple_id(scop
->stmts
[i
]->domain
);
4858 s
->body
= scop
->stmts
[i
]->body
;
4859 pet_stmt_extract_accesses(s
);
4865 /* Replace the scop in the "input" file by equivalent code
4866 * that uses the GPU. "scop" is assumed to correspond to this scop.
4868 * We first compute a schedule that respects the dependences
4869 * of the original program and select the outermost band
4870 * of tilable dimensions that has at least one parallel loop.
4871 * We then have three blocks of dimensions
4875 * The tilable band "B" is first tiled according to "tile" sizes, resulting
4880 * For each iteration of the T loop and for each array, we compute
4881 * the array elements accessed by that iteration, construct a rectangular
4882 * box around it and shift it to the origin. The result is used
4883 * as shared memory for the array.
4885 * We then split off at most 2 parallel loops from the T loops and
4886 * at most 3 parallel loops from the P loops
4890 * The T1/P1 loops are then tiled or "wrapped" over the blocks/threads,
4891 * according to "grid"/"block" sizes.
4893 * H T1T T1P T2 P1T P1P P2 G
4895 * Finally, the T1P and P1P iterators are equated to the block and
4896 * thread dimensions respectively and so are effectively removed.
4897 * The H loops are run on the host. The T1T, T2, P1T, P2 and G loops
4898 * are run on the GPU.
4900 * Code is generated in three stages. We first generate code for the
4901 * host (the H loops), with iterators h%d. Then, for each leaf node
4902 * of the resulting AST, we generate code for the shared loops (up to
4903 * and including T2), with iterators g%d and after equating the H loops
4904 * to h%d parameters and the T1P loops to the block dimensions.
4905 * Finally, we generate code for the remaining loops in a similar fashion.
4907 __isl_give isl_ast_node
*generate_gpu(isl_ctx
*ctx
, struct gpu_prog
*prog
,
4908 struct ppcg_options
*options
)
4910 isl_union_map
*sched
;
4919 gen
.sizes
= extract_sizes_from_str(ctx
, options
->sizes
);
4920 gen
.options
= options
;
4922 compute_schedule(&gen
);
4923 compute_copy_in_and_out(&gen
);
4926 tree
= generate_host_code(&gen
);
4928 clear_gpu_gen(&gen
);
4933 struct gpu_prog
*gpu_prog_alloc(isl_ctx
*ctx
, struct ppcg_scop
*scop
)
4935 struct gpu_prog
*prog
;
4940 prog
= isl_calloc_type(ctx
, struct gpu_prog
);
4945 prog
->context
= isl_set_copy(scop
->context
);
4946 prog
->n_stmts
= scop
->n_stmt
;
4947 prog
->stmts
= extract_stmts(ctx
, scop
, prog
->context
);
4948 prog
->read
= isl_union_map_copy(scop
->reads
);
4949 prog
->write
= isl_union_map_copy(scop
->writes
);
4951 collect_array_info(prog
);
4956 void gpu_prog_free(struct gpu_prog
*prog
)
4960 free_array_info(prog
);
4961 free_stmts(prog
->stmts
, prog
->n_stmts
);
4962 isl_union_set_free(prog
->copy_in
);
4963 isl_union_set_free(prog
->copy_out
);
4964 isl_union_map_free(prog
->read
);
4965 isl_union_map_free(prog
->write
);
4966 isl_set_free(prog
->context
);