| blob | 9d07b509f70bd438192321d5db04ca1d6b6f1c44 |
1 ; RUN: opt %loadPolly -polly-opt-isl -polly-pattern-matching-based-opts=true \
2 ; RUN: -polly-target-throughput-vector-fma=1 \
3 ; RUN: -polly-target-latency-vector-fma=8 \
4 ; RUN: -analyze -polly-ast -polly-target-1st-cache-level-associativity=8 \
5 ; RUN: -polly-target-2nd-cache-level-associativity=8 \
6 ; RUN: -polly-target-1st-cache-level-size=32768 \
7 ; RUN: -polly-target-vector-register-bitwidth=256 \
8 ; RUN: -polly-target-2nd-cache-level-size=262144 < %s \
9 ; RUN: | FileCheck %s
10 ;
11 ; opt %loadPolly -polly-opt-isl -polly-pattern-matching-based-opts=true \
12 ; -polly-target-throughput-vector-fma=1 \
13 ; -polly-target-latency-vector-fma=8 \
14 ; -polly-codegen -polly-target-1st-cache-level-associativity=8 \
15 ; -polly-target-2nd-cache-level-associativity=8 \
16 ; -polly-target-1st-cache-level-size=32768 \
17 ; -polly-target-vector-register-bitwidth=256 \
18 ; -polly-target-2nd-cache-level-size=262144 -gvn -licm -slp-vectorizer \
19 ; -mcpu=corei7 -stats -S < %s 2>&1 | FileCheck %s --check-prefix=AUTO-VECTORIZATION
20 ;
21 ;
22 ; /* We isolate a set of partial tile prefixes, which contains only partial
23 ; tile prefixes that have exactly Mr x Nr iterations of the two innermost
24 ; loops produced by the optimization of the matrix multiplication. Mr and
25 ; Nr are parameters of the micro-kernel (see getMicroKernelParams and
26 ; getMacroKernelParams from lib/Transform/ScheduleOptimizer.cpp for
27 ; details). This test check that in case of parametric bounds it helps to
28 ; get rid of the conditional expressions of the unrolled innermost loops,
29 ; which prevents stores and loads of the unrolled loops from being sunk
30 ; and hoisted. Otherwise, it causes a run-time regression in comparison
31 ; to the vectorized code with sunk and hoisted memory accesses. */
32 ;
33 ; /* C := A * B + C */
34 ; for (i = 0; i < _PB_NI; i++)
35 ; for (j = 0; j < _PB_NJ; j++)
36 ; for (k = 0; k < _PB_NK; ++k)
37 ; C[i][j] += A[i][k] * B[k][j];
38 ;
39 ; CHECK: if (ni >= 1) {
40 ; CHECK-NEXT: // Inter iteration alias-free
41 ; CHECK-NEXT: // 1st level tiling - Tiles
42 ; CHECK-NEXT: for (int c0 = 0; c0 <= floord(nj - 1, 2048); c0 += 1)
43 ; CHECK-NEXT: for (int c1 = 0; c1 <= floord(nk - 1, 256); c1 += 1) {
44 ; CHECK-NEXT: for (int c3 = 2048 * c0; c3 <= min(nj - 1, 2048 * c0 + 2047); c3 += 1)
45 ; CHECK-NEXT: for (int c4 = 256 * c1; c4 <= min(nk - 1, 256 * c1 + 255); c4 += 1)
46 ; CHECK-NEXT: CopyStmt_0(0, c3, c4);
47 ; CHECK-NEXT: for (int c2 = 0; c2 <= floord(ni - 1, 96); c2 += 1) {
48 ; CHECK-NEXT: if (c0 == 0)
49 ; CHECK-NEXT: for (int c3 = 96 * c2; c3 <= min(ni - 1, 96 * c2 + 95); c3 += 1)
50 ; CHECK-NEXT: for (int c5 = 256 * c1; c5 <= min(nk - 1, 256 * c1 + 255); c5 += 1)
51 ; CHECK-NEXT: CopyStmt_1(c3, 0, c5);
52 ; CHECK-NEXT: // 1st level tiling - Points
53 ; CHECK-NEXT: // Register tiling - Tiles
54 ; CHECK-NEXT: {
55 ; CHECK-NEXT: if (ni >= 96 * c2 + 4)
56 ; CHECK-NEXT: for (int c3 = 0; c3 <= min(255, -256 * c0 + nj / 8 - 1); c3 += 1) {
57 ; CHECK-NEXT: for (int c4 = 0; c4 <= min(23, -24 * c2 + ni / 4 - 1); c4 += 1)
58 ; CHECK-NEXT: for (int c5 = 0; c5 <= min(255, nk - 256 * c1 - 1); c5 += 1) {
59 ; CHECK-NEXT: // Register tiling - Points
60 ; CHECK-NEXT: {
61 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 2048 * c0 + 8 * c3, 256 * c1 + c5);
62 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 2048 * c0 + 8 * c3 + 1, 256 * c1 + c5);
63 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 2048 * c0 + 8 * c3 + 2, 256 * c1 + c5);
64 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 2048 * c0 + 8 * c3 + 3, 256 * c1 + c5);
65 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 2048 * c0 + 8 * c3 + 4, 256 * c1 + c5);
66 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 2048 * c0 + 8 * c3 + 5, 256 * c1 + c5);
67 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 2048 * c0 + 8 * c3 + 6, 256 * c1 + c5);
68 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 2048 * c0 + 8 * c3 + 7, 256 * c1 + c5);
69 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 2048 * c0 + 8 * c3, 256 * c1 + c5);
70 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 2048 * c0 + 8 * c3 + 1, 256 * c1 + c5);
71 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 2048 * c0 + 8 * c3 + 2, 256 * c1 + c5);
72 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 2048 * c0 + 8 * c3 + 3, 256 * c1 + c5);
73 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 2048 * c0 + 8 * c3 + 4, 256 * c1 + c5);
74 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 2048 * c0 + 8 * c3 + 5, 256 * c1 + c5);
75 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 2048 * c0 + 8 * c3 + 6, 256 * c1 + c5);
76 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 2048 * c0 + 8 * c3 + 7, 256 * c1 + c5);
77 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 2048 * c0 + 8 * c3, 256 * c1 + c5);
78 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 2048 * c0 + 8 * c3 + 1, 256 * c1 + c5);
79 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 2048 * c0 + 8 * c3 + 2, 256 * c1 + c5);
80 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 2048 * c0 + 8 * c3 + 3, 256 * c1 + c5);
81 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 2048 * c0 + 8 * c3 + 4, 256 * c1 + c5);
82 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 2048 * c0 + 8 * c3 + 5, 256 * c1 + c5);
83 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 2048 * c0 + 8 * c3 + 6, 256 * c1 + c5);
84 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 2048 * c0 + 8 * c3 + 7, 256 * c1 + c5);
85 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 2048 * c0 + 8 * c3, 256 * c1 + c5);
86 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 2048 * c0 + 8 * c3 + 1, 256 * c1 + c5);
87 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 2048 * c0 + 8 * c3 + 2, 256 * c1 + c5);
88 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 2048 * c0 + 8 * c3 + 3, 256 * c1 + c5);
89 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 2048 * c0 + 8 * c3 + 4, 256 * c1 + c5);
90 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 2048 * c0 + 8 * c3 + 5, 256 * c1 + c5);
91 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 2048 * c0 + 8 * c3 + 6, 256 * c1 + c5);
92 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 2048 * c0 + 8 * c3 + 7, 256 * c1 + c5);
93 ; CHECK-NEXT: }
94 ; CHECK-NEXT: }
95 ; CHECK-NEXT: if (96 * c2 + 95 >= ni)
96 ; CHECK-NEXT: for (int c5 = 0; c5 <= min(255, nk - 256 * c1 - 1); c5 += 1) {
97 ; CHECK-NEXT: // Register tiling - Points
98 ; CHECK-NEXT: for (int c6 = 0; c6 < ni % 4; c6 += 1)
99 ; CHECK-NEXT: for (int c7 = 0; c7 <= 7; c7 += 1)
100 ; CHECK-NEXT: Stmt_for_body6(-((ni + 4) % 4) + ni + c6, 2048 * c0 + 8 * c3 + c7, 256 * c1 + c5);
101 ; CHECK-NEXT: }
102 ; CHECK-NEXT: }
103 ; CHECK-NEXT: if (96 * c2 + 3 >= ni || (2048 * c0 + 2047 >= nj && nj % 8 >= 1))
104 ; CHECK-NEXT: for (int c3 = 0; c3 <= min(255, -256 * c0 + (nj - 1) / 8); c3 += 1)
105 ; CHECK-NEXT: if (96 * c2 + 3 >= ni || 2048 * c0 + 8 * c3 + 7 >= nj)
106 ; CHECK-NEXT: for (int c4 = 0; c4 <= min(23, -24 * c2 + (ni - 1) / 4); c4 += 1)
107 ; CHECK-NEXT: if ((ni >= 96 * c2 + 4 && 2048 * c0 + 8 * c3 + 7 >= nj) || 1)
108 ; CHECK-NEXT: for (int c5 = 0; c5 <= min(255, nk - 256 * c1 - 1); c5 += 1) {
109 ; CHECK-NEXT: // Register tiling - Points
110 ; CHECK-NEXT: for (int c6 = 0; c6 <= min(3, ni - 96 * c2 - 4 * c4 - 1); c6 += 1)
111 ; CHECK-NEXT: for (int c7 = 0; c7 <= min(7, nj - 2048 * c0 - 8 * c3 - 1); c7 += 1)
112 ; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + c6, 2048 * c0 + 8 * c3 + c7, 256 * c1 + c5);
113 ; CHECK-NEXT: }
114 ; CHECK-NEXT: }
115 ; CHECK-NEXT: }
116 ; CHECK-NEXT: }
117 ; CHECK-NEXT: }
118 ;
120 ; AUTO-VECTORIZATION: fmul <4 x double>
121 ; AUTO-VECTORIZATION: fadd <4 x double>
123 ; AUTO-VECTORIZATION: 36 SLP - Number of vector instructions generated
124 ; AUTO-VECTORIZATION: 453 licm - Number of instructions hoisted out of loop
125 ; AUTO-VECTORIZATION: 2 licm - Number of load insts hoisted or sunk
126 ; AUTO-VECTORIZATION: 32 licm - Number of memory locations promoted to registers
127 ;
128 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
129 target triple = "x86_64-unknown-unknown"
131 define internal void @kernel_gemm(i32 %ni, i32 %nj, i32 %nk, double %alpha, double %beta, [1024 x double]* %C, [1024 x double]* %A, [1024 x double]* %B) #0 {
132 entry:
133 br label %entry.split
135 entry.split: ; preds = %entry
136 %cmp39 = icmp sgt i32 %ni, 0
137 br i1 %cmp39, label %for.cond1.preheader.lr.ph, label %for.end22
139 for.cond1.preheader.lr.ph: ; preds = %entry.split
140 br label %for.cond1.preheader
142 for.cond1.preheader: ; preds = %for.inc20, %for.cond1.preheader.lr.ph
143 %indvars.iv45 = phi i64 [ 0, %for.cond1.preheader.lr.ph ], [ %indvars.iv.next46, %for.inc20 ]
144 %cmp237 = icmp sgt i32 %nj, 0
145 br i1 %cmp237, label %for.cond4.preheader.lr.ph, label %for.inc20
147 for.cond4.preheader.lr.ph: ; preds = %for.cond1.preheader
148 br label %for.cond4.preheader
150 for.cond4.preheader: ; preds = %for.inc17, %for.cond4.preheader.lr.ph
151 %indvars.iv41 = phi i64 [ 0, %for.cond4.preheader.lr.ph ], [ %indvars.iv.next42, %for.inc17 ]
152 %cmp535 = icmp sgt i32 %nk, 0
153 br i1 %cmp535, label %for.body6.lr.ph, label %for.inc17
155 for.body6.lr.ph: ; preds = %for.cond4.preheader
156 br label %for.body6
158 for.body6: ; preds = %for.body6, %for.body6.lr.ph
159 %indvars.iv = phi i64 [ 0, %for.body6.lr.ph ], [ %indvars.iv.next, %for.body6 ]
160 %arrayidx8 = getelementptr inbounds [1024 x double], [1024 x double]* %A, i64 %indvars.iv45, i64 %indvars.iv
161 %tmp = load double, double* %arrayidx8, align 8
162 %arrayidx12 = getelementptr inbounds [1024 x double], [1024 x double]* %B, i64 %indvars.iv, i64 %indvars.iv41
163 %tmp1 = load double, double* %arrayidx12, align 8
164 %mul = fmul double %tmp, %tmp1
165 %arrayidx16 = getelementptr inbounds [1024 x double], [1024 x double]* %C, i64 %indvars.iv45, i64 %indvars.iv41
166 %tmp2 = load double, double* %arrayidx16, align 8
167 %add = fadd double %tmp2, %mul
168 store double %add, double* %arrayidx16, align 8
169 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
170 %wide.trip.count = zext i32 %nk to i64
171 %exitcond = icmp ne i64 %indvars.iv.next, %wide.trip.count
172 br i1 %exitcond, label %for.body6, label %for.cond4.for.inc17_crit_edge
174 for.cond4.for.inc17_crit_edge: ; preds = %for.body6
175 br label %for.inc17
177 for.inc17: ; preds = %for.cond4.for.inc17_crit_edge, %for.cond4.preheader
178 %indvars.iv.next42 = add nuw nsw i64 %indvars.iv41, 1
179 %wide.trip.count43 = zext i32 %nj to i64
180 %exitcond44 = icmp ne i64 %indvars.iv.next42, %wide.trip.count43
181 br i1 %exitcond44, label %for.cond4.preheader, label %for.cond1.for.inc20_crit_edge
183 for.cond1.for.inc20_crit_edge: ; preds = %for.inc17
184 br label %for.inc20
186 for.inc20: ; preds = %for.cond1.for.inc20_crit_edge, %for.cond1.preheader
187 %indvars.iv.next46 = add nuw nsw i64 %indvars.iv45, 1
188 %wide.trip.count47 = zext i32 %ni to i64
189 %exitcond48 = icmp ne i64 %indvars.iv.next46, %wide.trip.count47
190 br i1 %exitcond48, label %for.cond1.preheader, label %for.cond.for.end22_crit_edge
192 for.cond.for.end22_crit_edge: ; preds = %for.inc20
193 br label %for.end22
195 for.end22: ; preds = %for.cond.for.end22_crit_edge, %entry.split
196 ret void
197 }
199 attributes #0 = { nounwind uwtable "target-cpu"="x86-64" "target-features"="+aes,+avx,+cmov,+cx16,+fxsr,+mmx,+pclmul,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" }