| blob | 8401203d012984d587287c239f2386541937a435 |
2 /*
3 * Copyright (c) 2001 Opsycon AB (www.opsycon.se)
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Opsycon AB, Sweden.
16 * 4. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
20 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 */
33 #ifndef _KERNEL
34 #define _KERNEL
35 #endif
37 #include <asm.h>
38 #include <regnum.h>
39 #include <cpu.h>
40 #include <pte.h>
42 #include "pmon/dev/ns16550.h"
43 #include "target/prid.h"
44 #include "target/sbd.h"
45 #include "target/bonito.h"
46 #include "target/via686b.h"
47 #include "target/i8254.h"
48 #include "target/isapnpreg.h"
49 #define DEBUG_LOCORE
51 #ifdef DEBUG_LOCORE
52 #define TTYDBG(x) \
53 .rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop
54 #else
55 #define TTYDBG(x)
56 #endif
58 #define PRINTSTR(x) \
59 .rdata;98: .asciz x; .text; la a0, 98b; bal stringserial; nop
61 #define CONFIG_CACHE_64K_4WAY 1
63 #define tmpsize s1
64 #define msize s2
65 #define bonito s4
66 #define dbg s5
67 #define sdCfg s6
69 #define CP0_CONFIG $16
70 #define CP0_TAGLO $28
71 #define CP0_TAGHI $29
73 #define DDR100 0x1d441091
74 /*
75 #define DDR100 0x0c011091*/
76 #define DDR266 0x0410435e
77 #define DDR300 0x041453df
79 /*
80 * Register usage:
81 *
82 * s0 link versus load offset, used to relocate absolute adresses.
83 * s1 free
84 * s2 memory size.
85 * s3 free.
86 * s4 Bonito base address.
87 * s5 dbg.
88 * s6 sdCfg.
89 * s7 rasave.
90 * s8 L3 Cache size.
91 */
94 .set noreorder
95 .globl _start
96 .globl start
97 .globl __main
98 _start:
99 start:
100 .globl stack
101 stack = start - 0x4000 /* Place PMON stack below PMON start in RAM */
103 /* NOTE!! Not more that 16 instructions here!!! Right now it's FULL! */
104 mtc0 zero, COP_0_STATUS_REG
105 mtc0 zero, COP_0_CAUSE_REG
106 li t0, SR_BOOT_EXC_VEC /* Exception to Boostrap Location */
107 mtc0 t0, COP_0_STATUS_REG
108 la sp, stack
109 la gp, _gp
111 bal uncached /* Switch to uncached address space */
112 nop
114 bal locate /* Get current execute address */
115 nop
117 uncached:
118 or ra, UNCACHED_MEMORY_ADDR
119 j ra
120 nop
122 /*
123 * Reboot vector usable from outside pmon.
124 */
125 .align 8
126 ext_map_and_reboot:
127 bal CPU_TLBClear
128 nop
130 li a0, 0xc0000000
131 li a1, 0x40000000
132 bal CPU_TLBInit
133 nop
134 la v0, tgt_reboot
135 la v1, start
136 subu v0, v1
137 lui v1, 0xffc0
138 addu v0, v1
139 jr v0
140 nop
142 /*
143 * Exception vectors here for rom, before we are up and running. Catch
144 * whatever comes up before we have a fully fledged exception handler.
145 */
146 .align 9 /* bfc00200 */
147 la a0, v200_msg
148 bal stringserial
149 nop
150 b exc_common
152 .align 7 /* bfc00280 */
153 la a0, v280_msg
154 bal stringserial
155 nop
156 b exc_common
158 /* Cache error */
159 .align 8 /* bfc00300 */
160 PRINTSTR("\r\nPANIC! Unexpected Cache Error exception! ")
161 mfc0 a0, COP_0_CACHE_ERR
162 bal hexserial
163 nop
164 b exc_common
166 /* General exception */
167 .align 7 /* bfc00380 */
168 la a0, v380_msg
169 bal stringserial
170 nop
171 b exc_common
173 .align 8 /* bfc00400 */
174 la a0, v400_msg
175 bal stringserial
176 nop
180 exc_common:
181 PRINTSTR("\r\nCAUSE=")
182 mfc0 a0, COP_0_CAUSE_REG
183 bal hexserial
184 nop
185 PRINTSTR("\r\nSTATUS=")
186 mfc0 a0, COP_0_STATUS_REG
187 bal hexserial
188 nop
189 PRINTSTR("\r\nERRORPC=")
190 mfc0 a0, COP_0_ERROR_PC
191 bal hexserial
192 nop
193 PRINTSTR("\r\nEPC=")
194 mfc0 a0, COP_0_EXC_PC
195 bal hexserial
196 nop
197 PRINTSTR("\r\nDERR0=")
198 cfc0 a0, COP_0_DERR_0
199 bal hexserial
200 nop
201 PRINTSTR("\r\nDERR1=")
202 cfc0 a0, COP_0_DERR_1
203 bal hexserial
204 nop
206 // b ext_map_and_reboot
207 nop
209 .align 8
210 nop
211 .align 8
212 .word read
213 .word write
214 .word open
215 .word close
216 .word nullfunction
217 .word printf
218 .word vsprintf
219 .word nullfunction
220 .word nullfunction
221 .word getenv
222 .word nullfunction
223 .word nullfunction
224 .word nullfunction
225 .word nullfunction
228 /*
229 * We get here from executing a bal to get the PC value of the current execute
230 * location into ra. Check to see if we run from ROM or if this is ramloaded.
231 */
232 locate:
233 la s0,start
234 subu s0,ra,s0
235 and s0,0xffff0000
237 li t0,SR_BOOT_EXC_VEC
238 mtc0 t0,COP_0_STATUS_REG
239 mtc0 zero,COP_0_CAUSE_REG
240 .set noreorder
242 li bonito,PHYS_TO_UNCACHED(BONITO_REG_BASE)
244 #define MOD_MASK 0x00000003
245 #define MOD_B 0x00000000 /* byte "modifier" */
246 #define MOD_H 0x00000001 /* halfword "modifier" */
247 #define MOD_W 0x00000002 /* word "modifier" */
248 #if __mips64
249 # define MOD_D 0x00000003 /* doubleword "modifier" */
250 #endif
252 #define OP_MASK 0x000000fc
253 #define OP_EXIT 0x00000000 /* exit (status) */
254 #define OP_DELAY 0x00000008 /* delay (cycles) */
255 #define OP_RD 0x00000010 /* read (addr) */
256 #define OP_WR 0x00000014 /* write (addr, val) */
257 #define OP_RMW 0x00000018 /* read-modify-write (addr, and, or) */
258 #define OP_WAIT 0x00000020 /* wait (addr, mask, value) */
260 #define WR_INIT(mod,addr,val) \
261 .word OP_WR|mod,PHYS_TO_UNCACHED(addr);\
262 .word (val),0
264 #define RD_INIT(mod,addr) \
265 .word OP_RD|mod,PHYS_TO_UNCACHED(addr);\
266 .word 0,0
268 #define RMW_INIT(mod,addr,and,or) \
269 .word OP_RMW|mod,PHYS_TO_UNCACHED(addr);\
270 .word (and),(or)
272 #define WAIT_INIT(mod,addr,and,or) \
273 .word OP_WAIT|mod,PHYS_TO_UNCACHED(addr);\
274 .word (mask),(val)
276 #define DELAY_INIT(cycles) \
277 .word OP_DELAY,(cycles);\
278 .word 0,0
280 #define EXIT_INIT(status) \
281 .word OP_EXIT,(status);\
282 .word 0,0
284 #define BONITO_INIT(r,v) WR_INIT(MOD_W,BONITO_BASE+/**/r,v)
285 #define BONITO_BIS(r,b) RMW_INIT(MOD_W,BONITO_BASE+(r),~0,b)
286 #define BONITO_BIC(r,b) RMW_INIT(MOD_W,BONITO_BASE+(r),~(b),0)
287 #define BONITO_RMW(r,c,s) RMW_INIT(MOD_W,BONITO_BASE+(r),~(c),s)
289 #define CFGADDR(idsel,function,reg) ((1<<(11+(idsel)))+((function)<<8)+(reg))
290 #define _ISABWR_INIT(mod,function,isabreg,val) \
291 WR_INIT(MOD_W,BONITO_BASE+BONITO_PCIMAP_CFG,CFGADDR(PCI_IDSEL_VIA686B,function,isabreg)>>16) ; \
292 RD_INIT(MOD_W,BONITO_BASE+BONITO_PCIMAP_CFG) ; \
293 WR_INIT(mod,PCI_CFG_SPACE+(CFGADDR(PCI_IDSEL_VIA686B,function,isabreg)&0xffff),val)
295 #define _ISABRD_INIT(mod,function,isabreg) \
296 WR_INIT(MOD_W,BONITO_BASE+BONITO_PCIMAP_CFG,CFGADDR(PCI_IDSEL_VIA686B,function,isabreg)>>16) ; \
297 RD_INIT(MOD_W,BONITO_BASE+BONITO_PCIMAP_CFG) ; \
298 RD_INIT(mod,PCI_CFG_SPACE+(CFGADDR(PCI_IDSEL_VIA686B,function,isabreg)&0xffff))
301 #define _ISAWR_INIT(isareg,val) \
302 WR_INIT(MOD_B,PCI_IO_SPACE+(isareg),val)
304 #define _ISARD_INIT(isareg) \
305 RD_INIT(MOD_B,PCI_IO_SPACE+(isareg))
308 #define ISABBWR_INIT(function,isabreg,val) \
309 _ISABWR_INIT(MOD_B,function,(isabreg),val)
310 #define ISABHWR_INIT(function,isabreg,val) \
311 _ISABWR_INIT(MOD_H,function,(isabreg),val)
312 #define ISABWWR_INIT(function,isabreg,val) \
313 _ISABWR_INIT(MOD_W,function,isabreg,val)
314 #define ISAWR_INIT(isareg,val) \
315 _ISAWR_INIT(isareg,val)
316 #define ISARD_INIT(isareg) \
317 _ISARD_INIT(isareg)
319 bal 1f
320 nop
322 /* bonito endianess */
323 BONITO_BIC(BONITO_BONPONCFG,BONITO_BONPONCFG_CPUBIGEND)
324 BONITO_BIC(BONITO_BONGENCFG,BONITO_BONGENCFG_BYTESWAP|BONITO_BONGENCFG_MSTRBYTESWAP)
325 BONITO_BIS(BONITO_BONPONCFG, BONITO_BONPONCFG_IS_ARBITER)
327 /*
328 * In certain situations it is possible for the Bonito ASIC
329 * to come up with the PCI registers uninitialised, so do them here
330 */
331 #define PCI_CLASS_BRIDGE 0x06
332 #define PCI_CLASS_SHIFT 24
333 #define PCI_SUBCLASS_BRIDGE_HOST 0x00
334 #define PCI_SUBCLASS_SHIFT 16
335 #define PCI_COMMAND_IO_ENABLE 0x00000001
336 #define PCI_COMMAND_MEM_ENABLE 0x00000002
337 #define PCI_COMMAND_MASTER_ENABLE 0x00000004
338 #define PCI_COMMAND_STATUS_REG 0x04
339 #define PCI_MAP_IO 0X00000001
340 #define PCI_CFG_SPACE BONITO_PCICFG_BASE
342 BONITO_INIT(BONITO_PCICLASS,(PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT) | (PCI_SUBCLASS_BRIDGE_HOST << PCI_SUBCLASS_SHIFT))
343 BONITO_INIT(BONITO_PCICMD, BONITO_PCICMD_PERR_CLR|BONITO_PCICMD_SERR_CLR|BONITO_PCICMD_MABORT_CLR|BONITO_PCICMD_MTABORT_CLR|BONITO_PCICMD_TABORT_CLR|BONITO_PCICMD_MPERR_CLR)
344 //BONITO_INIT(BONITO_PCILTIMER, 0)
345 BONITO_INIT(BONITO_PCILTIMER, 255)
346 BONITO_INIT(BONITO_PCIBASE0, 0)
347 BONITO_INIT(BONITO_PCIBASE1, 0)
348 BONITO_INIT(BONITO_PCIBASE2, 0)
349 BONITO_INIT(BONITO_PCIEXPRBASE, 0)
350 BONITO_INIT(BONITO_PCIINT, 0)
352 BONITO_BIS(BONITO_PCICMD, BONITO_PCICMD_PERRRESPEN)
354 BONITO_BIS(BONITO_PCICMD, PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE)
356 BONITO_BIC(BONITO_BONGENCFG, 0x80) #½ûÖ¹iobc
358 #BONITO_BIS(BONITO_BONGENCFG, BONITO_BONGENCFG_BUSERREN)
360 /* Set debug mode */
361 BONITO_BIS(BONITO_BONGENCFG, BONITO_BONGENCFG_DEBUGMODE)
363 /******** added to init southbridge*/
365 /* Set the SMB base address */
366 ISABWWR_INIT(4, SMBUS_IO_BASE_ADDR, SMBUS_IO_BASE_VALUE | 0x1)
367 /* enable the host controller */
368 ISABHWR_INIT(4, SMBUS_HOST_CONFIG_ADDR, SMBUS_HOST_CONFIG_ENABLE_BIT)
369 /* enable the SMB IO ports */
370 ISABBWR_INIT(4, PCI_COMMAND_STATUS_REG, PCI_COMMAND_IO_ENABLE)
372 /* 15us ISA bus refresh clock */
373 #define ISAREFRESH (PT_CRYSTAL/(1000000/15))
374 ISARD_INIT(CTC_PORT+PT_CONTROL)
376 /* program i8254 ISA refresh counter */
377 ISAWR_INIT(CTC_PORT+PT_CONTROL,PTCW_SC(PT_REFRESH)|PTCW_16B|PTCW_MODE(MODE_RG))
378 ISAWR_INIT(CTC_PORT+PT_REFRESH, ISAREFRESH & 0xff)
379 ISAWR_INIT(CTC_PORT+PT_REFRESH, ISAREFRESH >> 8)
382 EXIT_INIT(0)
385 #define Init_Op 0
386 #define Init_A0 4
387 #define Init_A1 8
388 #define Init_A2 12
389 #define Init_Size 16
391 1: move a0,ra
392 reginit: /* local name */
393 lw t3, Init_Op(a0)
394 lw t0, Init_A0(a0)
395 and t4,t3,OP_MASK
398 /*
399 * EXIT(STATUS)
400 */
401 bne t4, OP_EXIT, 8f
402 nop
403 move v0,t0
404 b .done
405 nop
407 /*
408 * DELAY(CYCLES)
409 */
410 8: bne t4, OP_DELAY, 8f
411 nop
412 1: bnez t0,1b
413 subu t0,1
414 b .next
415 nop
416 /*
417 * READ(ADDR)
418 */
419 8: bne t4,OP_RD,8f
420 nop
421 and t4,t3,MOD_MASK
423 bne t4,MOD_B,1f
424 nop
425 lbu t5,0(t0)
426 b .next
427 nop
428 1: bne t4,MOD_H,1f
429 nop
430 lhu t5,0(t0)
431 b .next
432 nop
433 1: bne t4,MOD_W,1f
434 nop
435 #if __mips64
436 lwu t5,0(t0)
437 #else
438 lw t5,0(t0)
439 #endif
440 b .next
441 nop
442 1:
443 #if __mips64
444 lw t5,0(t0)
445 b .next
446 nop
447 #else
448 b .fatal
449 nop
450 #endif
452 /*
453 * WRITE(ADDR,VAL)
454 */
455 8: bne t4,OP_WR,8f
456 nop
457 lw t1,Init_A1(a0)
458 and t4,t3,MOD_MASK
460 bne t4,MOD_B,1f
461 nop
462 sb t1,0(t0)
463 b .next
464 nop
465 1: bne t4,MOD_H,1f
466 nop
467 sh t1,0(t0)
468 b .next
469 nop
470 1: bne t4,MOD_W,1f
471 nop
472 sw t1,0(t0)
473 b .next
474 nop
476 1:
477 #if __mips64
478 sd t1,0(t0)
479 b .next
480 nop
481 #else
482 b .fatal
483 nop
484 #endif
487 /*
488 * RMW(ADDR,AND,OR)
489 */
490 8: bne t4,OP_RMW,8f
491 nop
492 lw t1,Init_A1(a0)
493 lw t2,Init_A2(a0)
494 and t4,t3,MOD_MASK
496 bne t4,MOD_B,1f
497 nop
498 lbu t4,0(t0)
499 and t4,t1
500 or t4,t2
501 sb t4,0(t0)
502 b .next
503 nop
504 1: bne t4,MOD_H,1f
505 nop
506 lhu t4,0(t0)
507 and t4,t1
508 or t4,t2
509 sh t4,0(t0)
510 b .next
511 nop
512 1: bne t4,MOD_W,1f
513 nop
514 lw t4,0(t0)
515 and t4,t1
516 or t4,t2
517 sw t4,0(t0)
518 b .next
519 nop
521 1:
522 #if __mips64
523 ld t4,0(t0)
524 and t4,t1
525 or t4,t2
526 sd t4,0(t0)
527 b .next
528 nop
529 #else
530 b .fatal
531 nop
532 #endif
535 /*
536 * WAIT(ADDR,MASK,VAL)
537 */
538 8: bne t4,OP_WAIT,8f
539 nop
540 lw t1,Init_A1(a0)
541 lw t2,Init_A2(a0)
542 and t4,t3,MOD_MASK
544 bne t4,MOD_B,1f
545 nop
546 3: lbu t4,0(t0)
547 and t4,t1
548 bne t4,t2,3b
549 nop
550 b .next
551 nop
552 1: bne t4,MOD_H,1f
553 nop
554 3: lhu t4,0(t0)
555 and t4,t1
556 bne t4,t2,3b
557 nop
558 b .next
559 nop
560 1: bne t4,MOD_W,1f
561 nop
562 3: lw t4,0(t0)
563 and t4,t1
564 bne t4,t2,3b
565 nop
566 b .next
567 nop
568 1:
569 #if __mips64
570 3: ld t4,0(t0)
571 and t4,t1
572 bne t4,t2,3b
573 nop
574 b .next
575 nop
576 #else
577 b .fatal
578 nop
579 #endif
582 .next: addu a0,Init_Size
583 b reginit
584 nop
586 8:
587 .fatal: b .done
588 nop
589 bal stuck
590 nop
591 .done:
593 bal superio_init
594 nop
596 bal initserial
597 nop
599 PRINTSTR("\r\nPMON2000 MIPS Initializing. Standby...\r\n")
600 PRINTSTR("ERRORPC=")
601 mfc0 a0, COP_0_ERROR_PC
602 bal hexserial
603 nop
605 PRINTSTR(" CONFIG=")
606 mfc0 a0, COP_0_CONFIG
607 bal hexserial
608 nop
609 PRINTSTR("\r\n")
611 PRINTSTR(" PRID=")
612 mfc0 a0, COP_0_PRID
613 bal hexserial
614 nop
615 PRINTSTR("\r\n")
617 #undef QCHDBG
618 #ifdef QCHDBG
619 b .nodimm
620 nop
621 #else
622 #include "i2c.S"
623 beqz msize,.nodimm
624 nop
625 b cfgnow
626 nop
627 #endif
629 /*
630 * Now determine DRAM configuration and size by
631 * reading the I2C EEROM on the DIMMS
632 */
633 PRINTSTR("DIMM read\r\n")
635 /* only one memory slot, slave address is 1010000b */
637 li a1, 0x0
638 1:
639 li a0,0xa1
640 bal i2cread
641 nop
643 # save a1
644 move t1, a1
646 #print
647 move a0, v0
648 bal hexserial
649 nop
651 PRINTSTR("\r\n")
653 # restore a1
654 move a1,t1
655 addiu a1,a1,1
657 li v0, 0x20
658 bleu a1, v0, 1b
659 nop
661 li msize,0
662 # set some parameters for DDR333
663 # rank number and DDR type field will be filled later
664 # to check: fix TCAS?
665 li sdCfg, 0x341043df
667 li a0,0xa1
669 /* read DIMM memory type (must be DDRAM) */
670 #li a1,2
671 #bal i2cread
672 #nop
673 #bne v0,7,.nodimm
674 #nop
675 PRINTSTR("read memory type\r\n")
677 /* read DIMM number of rows */
678 li a0,0xa1
679 li a1,3
680 bal i2cread
681 nop
682 move a0, v0
683 subu v0, 12
684 move s1, v0
686 bgtu v0, 2,.nodimm
687 nop
688 PRINTSTR("read number of rows\r\n")
690 2: /* read DIMM number of cols */
691 li a0,0xa1
692 li a1,4
693 bal i2cread
694 nop
696 subu v0, 8
697 bgtu v0, 4,.nodimm
698 nop
700 move t1, s1
702 bne t1, 0, 10f
703 nop
704 bne v0, 2, 20f
705 nop
706 li v0, 0
707 b .ddrtype
708 nop
709 20: bne v0, 1, 21f
710 nop
711 li v0, 1
712 b .ddrtype
713 nop
714 21: bne v0, 0, 22f
715 nop
716 li v0, 2
717 b .ddrtype
718 nop
719 22: bne v0, 3, 33f
720 nop
721 li v0, 3
722 b .ddrtype
723 nop
724 10: bne t1, 1, 11f
725 nop
726 bne v0, 3, 20f
727 nop
728 li v0, 4
729 b .ddrtype
730 nop
731 20: bne v0, 2, 21f
732 nop
733 li v0, 5
734 b .ddrtype
735 nop
736 21: bne v0, 1, 22f
737 nop
738 li v0, 6
739 b .ddrtype
740 nop
741 22: bne v0, 4, 33f
742 nop
743 li v0, 7
744 b .ddrtype
745 nop
746 11: bne t1, 2, 33f
747 nop
748 bne v0, 4, 20f
749 nop
750 li v0, 8
751 b .ddrtype
752 nop
753 20: bne v0, 3, 21f
754 nop
755 li v0, 9
756 b .ddrtype
757 nop
758 21: bne v0, 2, 33f
759 nop
760 li v0, 10
761 b .ddrtype
762 nop
763 33: PRINTSTR("DDR type not supported!\r\n");
764 34: b 34b
765 nop
767 .ddrtype:
768 #bit 25:22 is DDR type field
769 sll v0, 22
770 and v0,0x03c00000
771 or sdCfg,v0
773 /* read DIMM memory size per side */
774 li a0,0xa1
775 li a1,31
776 bal i2cread
777 nop
778 beqz v0,.nodimm
779 nop
780 sll tmpsize,v0,22 # multiply by 4M
781 PRINTSTR("read memory size per side\r\n")
783 2: /* read DIMM number of blocks-per-ddrram */
784 li a1,17
785 bal i2cread
786 nop
787 beq v0,2,2f
788 nop
789 bne v0,4,.nodimm
790 nop
791 PRINTSTR("read blocks per ddrram\r\n")
793 2: /* read DIMM number of sides (banks) */
794 li a1,5
795 bal i2cread
796 nop
797 beq v0,1,2f
798 nop
799 bne v0,2,.nodimm
800 nop
801 sll tmpsize,1 # msize *= 2
802 or sdCfg, 0x1<<27
803 PRINTSTR("read number of sides\r\n")
805 2: /* read DIMM width */
806 li a1,6
807 bal i2cread
808 nop
809 bleu v0,36,2f
810 nop
811 bgtu v0,72,.nodimm
812 nop
813 PRINTSTR("read width\r\n")
815 2: addu msize,tmpsize
816 b 2f
817 nop
819 .nodimm:
820 move dbg,a0
821 PRINTSTR ("\r\nNo DIMM in slot ")
822 move a0,dbg
823 bal hexserial
824 nop
825 PRINTSTR("\r\n")
826 move a0,dbg
827 li msize,0x10000000
828 li sdCfg,0x255043df /* zgj-8-7-14-13 */
829 # li sdCfg,0x3d9043df
830 cfgnow:
831 2:
832 PRINTSTR("DIMM SIZE=")
833 move a0,msize
834 bal hexserial
835 nop
836 PRINTSTR("\r\n")
838 li t0, 0xbff00008
839 sd sdCfg, 0(t0)
841 #### gx 2006-03-17: mode ####
842 #li t1,0x20
843 li t1,0x28
844 li t0, 0xbff00000
845 sw t1,0(t0)
846 nop
847 li t1,0x0
848 li t0, 0xbff00000
849 sw t1,0x30(t0)
850 nop
852 PRINTSTR("sdcfg=");
853 move a0,sdCfg
854 bal hexserial
855 nop
856 PRINTSTR("\r\n");
857 PRINTSTR("msize=");
858 move a0,msize
859 bal hexserial
860 nop
861 PRINTSTR("\r\n")
863 skipdimm:
865 li t1,0 # accumulate pcimembasecfg settings
867 /* set bar0 mask and translation to point to SDRAM */
868 sub t0,msize,1
869 not t0
870 srl t0,BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT
871 and t0,BONITO_PCIMEMBASECFG_MEMBASE0_MASK
872 or t1,t0
874 li t0,0x00000000
875 srl t0,BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT
876 and t0,BONITO_PCIMEMBASECFG_MEMBASE0_TRANS
877 or t1,t0
878 or t1,BONITO_PCIMEMBASECFG_MEMBASE0_CACHED
880 /* set bar1 to minimum size to conserve PCI space */
881 li t0, ~0
882 srl t0,BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT
883 and t0,BONITO_PCIMEMBASECFG_MEMBASE1_MASK
884 or t1,t0
886 li t0,0x00000000
887 srl t0,BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT
888 and t0,BONITO_PCIMEMBASECFG_MEMBASE1_TRANS
889 or t1,t0
890 or t1,BONITO_PCIMEMBASECFG_MEMBASE1_CACHED
892 sw t1,BONITO_PCIMEMBASECFG(bonito)
894 /* enable configuration cycles now */
895 lw t0,BONITO_BONPONCFG(bonito)
896 and t0,~BONITO_BONPONCFG_CONFIG_DIS
897 sw t0,BONITO_BONPONCFG(bonito)
899 PRINTSTR("Init SDRAM Done!\r\n");
900 /*
901 * Reset and initialize caches to a known state.
902 */
903 #define IndexStoreTagI 0x08
904 #define IndexStoreTagD 0x09
905 #define IndexStoreTagS 0x0b
906 #define IndexStoreTagT 0x0a
907 #define FillI 0x14
909 /*
910 * RM7000 config register bits.
911 */
912 #define CF_7_SE (1 << 3) /* Secondary cache enable */
913 #define CF_7_SC (1 << 31) /* Secondary cache not present */
914 #define CF_7_TE (1 << 12) /* Tertiary cache enable */
915 #define CF_7_TC (1 << 17) /* Tertiary cache not present */
916 #define CF_7_TS (3 << 20) /* Tertiary cache size */
917 #define CF_7_TS_AL 20 /* Shift to align */
918 #define NOP8 nop;nop;nop;nop;nop;nop;nop;nop
919 do_caches:
920 TTYDBG("Sizing caches...\r\n");
922 mfc0 t3, COP_0_CONFIG /* t3 = original config */
923 and t3, 0xffffeff0 /* Make sure coherency is OK */
925 and t3, ~(CF_7_TE|CF_7_SE|CF_7_TC|CF_7_SC) /* disable L2/L3 cache */
926 mtc0 t3, COP_0_CONFIG
928 li t2, 4096
930 srl t1, t3, 9
931 and t1, 3
932 sllv s3, t2, t1 /* s3 = I cache size */
934 #ifdef CONFIG_CACHE_64K_4WAY
935 sll s3,2
936 #endif
938 and t1, t3, 0x20
939 srl t1, t1, 1
940 addu s4, t1, 16 /* s4 = I cache line size */
942 srl t1, t3, 6
943 and t1, 3
944 sllv s5, t2, t1 /* s5 = D cache size */
946 #ifdef CONFIG_CACHE_64K_4WAY
947 sll s5,2
948 #endif
950 and t1, t3, 0x10
951 addu s6, t1, 16 /* s6 = D cache line size */
952 TTYDBG("Init caches...\r\n")
954 li s7, 0 /* no L2 cache */
955 li s8, 0 /* no L3 cache */
957 #if 0
958 mfc0 a0, COP_0_PRID
959 li a1, 0x6301
960 bne a0,a1,1f
961 nop
962 #endif
963 TTYDBG("godson2 caches found\r\n")
964 bal godson2_cache_init
965 nop
967 /* close L2 cache */
968 li a0, 0xbfe00164
969 sw zero, 0(a0);
971 mfc0 a0,COP_0_CONFIG
972 and a0,a0,~((1<<12) | 3)
973 or a0,a0,2
974 mtc0 a0,COP_0_CONFIG
976 #ifdef DEBUG_LOCORE
977 TTYDBG("Init caches done, cfg = ")
978 mfc0 a0, COP_0_CONFIG
979 bal hexserial
980 nop
981 TTYDBG("\r\n\r\n")
982 #endif
984 /* zhb */
985 #if 0
986 /* li t0, 0 */
987 /* li t1, 0x90000 */
988 /*1: addiu t0, 1 */
989 /* bne t0, t1, 1b */
990 nop
992 TTYDBG("Testing memory...\r\n")
994 li t7, 10
995 tmem:
996 li t0, 0xa0000000+1*1024*1024
997 li t1, 0xa0000000
998 li t2, 0xffffffff
999 1:
1000 sw t2, 0(t1)
1001 lw t3, 0(t1)
1002 bne t3, t2, 1f
1003 nop
1004 not t2
1005 sw t2, 0(t1)
1006 lw t3, 0(t1)
1007 bne t3, t2, 1f
1008 nop
1009 not t2
1010 subu t2, 1
1011 addu t1, 4
1012 beq t1, t0, 2f
1013 nop
1014 and t4, t1, 0x000fffff
1015 bnez t4, skipdot
1016 li a0, '.'
1017 bal tgt_putchar
1018 nop
1019 skipdot:
1020 b 1b
1021 nop
1022 1:
1023 TTYDBG("Memory test failed at ");
1024 move a0, t1
1025 bal hexserial
1026 nop
1027 TTYDBG("\r\nWrite=");
1028 move a0, t2
1029 bal hexserial
1030 nop
1031 TTYDBG("\r\nRead=");
1032 move a0, t3
1033 bal hexserial
1034 nop
1035 1:
1036 b 1b
1037 nop
1038 2:
1039 TTYDBG("Testing ok...\r\n");
1040 sub t7,1
1041 beqz t7, 1f
1042 nop
1043 b tmem
1044 nop
1045 1:
1046 b 1b
1047 nop
1048 #endif
1049 #include "machine/newtest/mydebug.S"
1050 bootnow:
1051 TTYDBG("Copy PMON to execute location...\r\n")
1052 #ifdef DEBUG_LOCORE
1053 TTYDBG(" start = 0x")
1054 la a0, start
1055 bal hexserial
1056 nop
1057 TTYDBG("\r\n s0 = 0x")
1058 move a0, s0
1059 bal hexserial
1060 nop
1061 TTYDBG("\r\n")
1062 #endif
1063 la a0, start
1064 li a1, 0xbfc00000
1065 la a2, _edata
1066 or a0, 0xa0000000
1067 or a2, 0xa0000000
1068 subu t1, a2, a0
1069 srl t1, t1, 2
1071 move t0, a0
1072 move t1, a1
1073 move t2, a2
1075 /* copy text section */
1077 1: and t3,t0,0x0000ffff
1078 bnez t3,2f
1079 nop
1080 move a0,t0
1081 bal hexserial
1082 nop
1083 li a0,'\r'
1084 bal tgt_putchar
1085 nop
1086 2: lw t3, 0(t1)
1087 nop
1088 sw t3, 0(t0)
1089 addu t0, 4
1090 addu t1, 4
1091 bne t2, t0, 1b
1092 nop
1094 PRINTSTR("\ncopy text section done.\r\n")
1096 /* Clear BSS */
1097 la a0, _edata
1098 la a2, _end
1099 2: sw zero, 0(a0)
1100 bne a2, a0, 2b
1101 addu a0, 4
1104 TTYDBG("Copy PMON to execute location done.\r\n")
1105 /* zhb */
1106 #if 0
1107 zhb:
1108 TTYDBG("Testing...\r\n")
1109 la a0, start
1110 li a1, 0xbfc00000
1111 la a2, _edata
1112 or a0, 0xa0000000
1113 or a2, 0xa0000000
1114 /* subu s6, a2, a0*/
1115 /* srl s6, s6, 2*/
1117 move t0, a0
1118 move t1, a1
1119 move t2, a2
1120 /* copy text section */
1122 1: lw t4, 0(t1)
1123 nop
1124 lw t5, 0(t0)
1125 addu t0, 4
1126 addu t1, 4
1127 beq t4, t5, 2f
1128 nop
1129 move a0, t0
1130 subu a0, 4
1131 bal hexserial
1132 nop
1133 TTYDBG (" ")
1134 move a0, t4
1135 bal hexserial
1136 nop
1137 TTYDBG (" ")
1138 move a0, t5
1139 bal hexserial
1140 nop
1141 TTYDBG ("\r\n")
1142 2: bne t2, t0, 1b
1143 nop
1144 TTYDBG ("test ok!\r\n")
1145 /*
1146 3: beqz zero, 3b
1147 nop
1148 */
1149 #endif
1153 TTYDBG("sp=");
1154 move a0, sp
1155 bal hexserial
1156 nop
1158 li a0, 4096*1024
1159 sw a0, CpuTertiaryCacheSize /* Set L3 cache size */
1161 #if 0
1162 mfc0 a0,COP_0_CONFIG
1163 and a0,a0,0xfffffff8
1164 or a0,a0,0x3
1165 mtc0 a0,COP_0_CONFIG
1166 #endif
1168 move a0,msize
1169 srl a0,20
1170 /* pass pointer to kseg1 tgt_putchar */
1171 la a1, tgt_putchar
1172 addu a1,a1,s0
1174 la a2, stringserial
1175 addu a2,a2,s0
1177 la v0, initmips
1178 jalr v0
1179 nop
1180 stuck:
1181 #ifdef DEBUG_LOCORE
1182 TTYDBG("Dumping GT64240 setup.\r\n")
1183 TTYDBG("offset----data------------------------.\r\n")
1184 li s3, 0
1185 1:
1186 move a0, s3
1187 bal hexserial
1188 nop
1189 TTYDBG(": ")
1190 2:
1191 add a0, s3, bonito
1192 lw a0, 0(a0)
1193 bal hexserial
1194 addiu s3, 4
1195 TTYDBG(" ")
1196 li a0, 0xfff
1197 and a0, s3
1198 beqz a0, 3f
1199 li a0, 0x01f
1200 and a0, s3
1201 bnez a0, 2b
1202 TTYDBG("\r\n")
1203 b 1b
1204 nop
1205 3:
1206 b 3b
1207 nop
1209 #else
1210 b stuck
1211 nop
1212 #endif
1213 /*
1214 * Clear the TLB. Normally called from start.S.
1215 */
1216 #if __mips64
1217 #define MTC0 dmtc0
1218 #else
1219 #define MTC0 mtc0
1220 #endif
1221 LEAF(CPU_TLBClear)
1222 li a3, 0 # First TLB index.
1224 li a2, PG_SIZE_4K
1225 MTC0 a2, COP_0_TLB_PG_MASK # Whatever...
1227 1:
1228 MTC0 zero, COP_0_TLB_HI # Clear entry high.
1229 MTC0 zero, COP_0_TLB_LO0 # Clear entry low0.
1230 MTC0 zero, COP_0_TLB_LO1 # Clear entry low1.
1232 mtc0 a3, COP_0_TLB_INDEX # Set the index.
1233 addiu a3, 1
1234 li a2, 64
1235 nop
1236 nop
1237 tlbwi # Write the TLB
1239 bne a3, a2, 1b
1240 nop
1242 jr ra
1243 nop
1244 END(CPU_TLBClear)
1246 /*
1247 * Set up the TLB. Normally called from start.S.
1248 */
1249 LEAF(CPU_TLBInit)
1250 li a3, 0 # First TLB index.
1252 li a2, PG_SIZE_16M
1253 MTC0 a2, COP_0_TLB_PG_MASK # All pages are 16Mb.
1255 1:
1256 and a2, a0, PG_SVPN
1257 MTC0 a2, COP_0_TLB_HI # Set up entry high.
1259 move a2, a0
1260 srl a2, a0, PG_SHIFT
1261 and a2, a2, PG_FRAME
1262 ori a2, PG_IOPAGE
1263 MTC0 a2, COP_0_TLB_LO0 # Set up entry low0.
1264 addu a2, (0x01000000 >> PG_SHIFT)
1265 MTC0 a2, COP_0_TLB_LO1 # Set up entry low1.
1267 mtc0 a3, COP_0_TLB_INDEX # Set the index.
1268 addiu a3, 1
1269 li a2, 0x02000000
1270 subu a1, a2
1271 nop
1272 tlbwi # Write the TLB
1274 bgtz a1, 1b
1275 addu a0, a2 # Step address 32Mb.
1277 jr ra
1278 nop
1279 END(CPU_TLBInit)
1281 LEAF(stringserial)
1282 move a2, ra
1283 addu a1, a0, s0
1284 lbu a0, 0(a1)
1285 1:
1286 beqz a0, 2f
1287 nop
1288 bal tgt_putchar
1289 addiu a1, 1
1290 b 1b
1291 lbu a0, 0(a1)
1293 2:
1294 j a2
1295 nop
1296 END(stringserial)
1298 LEAF(outstring)
1299 move a2, ra
1300 move a1, a0
1301 lbu a0, 0(a1)
1302 1:
1303 beqz a0, 2f
1304 nop
1305 bal tgt_putchar
1306 addiu a1, 1
1307 b 1b
1308 lbu a0, 0(a1)
1310 2:
1311 j a2
1312 nop
1313 END(outstring)
1315 LEAF(hexserial)
1316 move a2, ra
1317 move a1, a0
1318 li a3, 7
1319 1:
1320 rol a0, a1, 4
1321 move a1, a0
1322 and a0, 0xf
1323 la v0, hexchar
1324 addu v0, s0
1325 addu v0, a0
1326 bal tgt_putchar
1327 lbu a0, 0(v0)
1329 bnez a3, 1b
1330 addu a3, -1
1332 j a2
1333 nop
1334 END(hexserial)
1336 LEAF(tgt_putchar)
1337 la v0, COM1_BASE_ADDR
1338 # la v0, COM3_BASE_ADDR
1339 1:
1340 lbu v1, NSREG(NS16550_LSR)(v0)
1341 and v1, LSR_TXRDY
1342 beqz v1, 1b
1343 nop
1345 sb a0, NSREG(NS16550_DATA)(v0)
1347 move v1, v0
1348 la v0, COM3_BASE_ADDR
1349 # bne v0, v1, 1b
1350 nop
1352 j ra
1353 nop
1354 END(tgt_putchar)
1356 /* baud rate definitions, matching include/termios.h */
1357 #define B0 0
1358 #define B50 50
1359 #define B75 75
1360 #define B110 110
1361 #define B134 134
1362 #define B150 150
1363 #define B200 200
1364 #define B300 300
1365 #define B600 600
1366 #define B1200 1200
1367 #define B1800 1800
1368 #define B2400 2400
1369 #define B4800 4800
1370 #define B9600 9600
1371 #define B19200 19200
1372 #define B38400 38400
1373 #define B57600 57600
1374 #define B115200 115200
1376 LEAF(initserial)
1377 la v0, COM1_BASE_ADDR
1378 # la v0, COM3_BASE_ADDR
1379 1:
1380 li v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4
1381 sb v1, NSREG(NS16550_FIFO)(v0)
1382 li v1, CFCR_DLAB
1383 sb v1, NSREG(NS16550_CFCR)(v0)
1384 li v1, NS16550HZ/(16*CONS_BAUD)/2
1385 sb v1, NSREG(NS16550_DATA)(v0)
1386 srl v1, 8
1387 sb v1, NSREG(NS16550_IER)(v0)
1388 li v1, CFCR_8BITS
1389 sb v1, NSREG(NS16550_CFCR)(v0)
1390 li v1, MCR_DTR|MCR_RTS
1391 sb v1, NSREG(NS16550_MCR)(v0)
1392 li v1, 0x0
1393 sb v1, NSREG(NS16550_IER)(v0)
1395 nop
1397 j ra
1398 nop
1399 END(initserial)
1401 /* a0: slave address
1402 a1: reg off
1403 */
1404 LEAF(i2cread)
1405 /* set device address */
1406 li v0, 0xbfd00000 + SMBUS_HOST_ADDRESS
1408 sb a0, 0(v0);
1410 /* store register offset */
1411 li v0, 0xbfd00000 + SMBUS_HOST_COMMAND
1412 sb a1, 0(v0);
1414 /* read byte data protocol */
1415 li v0, 0x08
1416 li v1, 0xbfd00000 + SMBUS_HOST_CONTROL
1417 sb v0, 0(v1);
1419 /* make sure SMB host ready to start, important!--zfx */
1420 li v1, 0xbfd00000 + SMBUS_HOST_STATUS
1421 lbu v0, 0(v1)
1422 andi v0,v0, 0x1f
1423 beqz v0,1f
1424 nop
1425 sb v0, 0(v1)
1426 lbu v0, 0(v1) #flush the write
1427 1:
1429 /* start */
1430 li v1, 0xbfd00000 + SMBUS_HOST_CONTROL
1431 lbu v0, 0(v1)
1432 ori v0, v0, 0x40
1433 sb v0, 0(v1);
1435 /* wait */
1436 li v1, 0xbfd00000 + SMBUS_HOST_STATUS
1437 1:
1439 #if 0
1440 /* delay */
1441 li a0, 0x1000
1442 2:
1443 bnez a0,2b
1444 addiu a0, -1
1445 #endif
1447 lbu v0, 0(v1)
1448 andi v0, SMBUS_HOST_STATUS_BUSY
1449 bnez v0, 1b #IDEL ?
1450 nop
1452 li v1, 0xbfd00000 + SMBUS_HOST_STATUS
1453 lbu v0, 0(v1)
1454 andi v0,v0, 0x1f
1455 beqz v0,1f
1456 nop
1457 sb v0, 0(v1) #reset
1458 lbu v0, 0(v1) #flush the write
1459 1:
1461 li v1, 0xbfd00000 + SMBUS_HOST_DATA0
1462 lbu v0, 0(v1)
1464 jr ra
1465 nop
1466 END(i2cread)
1469 __main:
1470 j ra
1471 nop
1474 .rdata
1475 transmit_pat_msg:
1476 .asciz "\r\nInvalid transmit pattern. Must be DDDD or DDxDDx\r\n"
1477 v200_msg:
1478 .asciz "\r\nPANIC! Unexpected TLB refill exception!\r\n"
1479 v280_msg:
1480 .asciz "\r\nPANIC! Unexpected XTLB refill exception!\r\n"
1481 v380_msg:
1482 .asciz "\r\nPANIC! Unexpected General exception!\r\n"
1483 v400_msg:
1484 .asciz "\r\nPANIC! Unexpected Interrupt exception!\r\n"
1485 hexchar:
1486 .ascii "0123456789abcdef"
1488 .text
1489 .align 2
1490 /*
1491 * I2C Functions used in early startup code to get SPD info from
1492 * SDRAM modules. This code must be entirely PIC and RAM independent.
1493 */
1495 /* Delay macro */
1496 #define DELAY(count) \
1497 li v0, count; \
1498 99: \
1499 bnz vo, 99b;\
1500 addiu v0, -1
1503 #define I2C_INT_ENABLE 0x80
1504 #define I2C_ENABLE 0x40
1505 #define I2C_ACK 0x04
1506 #define I2C_INT_FLAG 0x08
1507 #define I2C_STOP_BIT 0x10
1508 #define I2C_START_BIT 0x20
1510 #define I2C_AMOD_RD 0x01
1512 #define BUS_ERROR 0x00
1513 #define START_CONDITION_TRA 0x08
1514 #define RSTART_CONDITION_TRA 0x10
1515 #define ADDR_AND_WRITE_BIT_TRA_ACK_REC 0x18
1516 #define ADDR_AND_READ_BIT_TRA_ACK_REC 0x40
1517 #define SLAVE_REC_WRITE_DATA_ACK_TRA 0x28
1518 #define MAS_REC_READ_DATA_ACK_NOT_TRA 0x58
1520 #define Index_Store_Tag_D 0x05
1521 #define Index_Invalidate_I 0x00
1522 #define Index_Writeback_Inv_D 0x01
1523 #define Index_Store_Tag_S 0x0b
1524 #define Index_Writeback_Inv_S 0x03
1526 LEAF(nullfunction)
1527 jr ra
1528 nop
1529 END(nullfunction)
1531 LEAF(godson2_cache_init)
1532 ####part 2####
1533 cache_detect_2way:
1534 mfc0 t4, CP0_CONFIG
1535 andi t5, t4, 0x0e00
1536 srl t5, t5, 9
1537 andi t6, t4, 0x01c0
1538 srl t6, t6, 6
1539 addiu t6, t6, 11
1540 addiu t5, t5, 11
1541 addiu t4, $0, 1
1542 sllv t6, t4, t6
1543 srl t6,1
1544 sllv t5, t4, t5
1545 srl t5,1
1546 addiu t7, $0, 2
1547 ####part 3####
1548 lui a0, 0x8000
1549 addu a1, $0, t5
1550 addu a2, $0, t6
1551 cache_init_d2way:
1552 #a0=0x80000000, a1=icache_size, a2=dcache_size
1553 #a3, v0 and v1 used as local registers
1554 mtc0 $0, CP0_TAGHI
1555 addu v0, $0, a0
1556 addu v1, a0, a2
1557 1: slt a3, v0, v1
1558 beq a3, $0, 1f
1559 nop
1560 mtc0 $0, CP0_TAGLO
1561 cache Index_Store_Tag_D, 0x0(v0)
1562 mtc0 $0, CP0_TAGLO
1563 cache Index_Store_Tag_D, 0x1(v0)
1564 mtc0 $0, CP0_TAGLO
1565 cache Index_Store_Tag_D, 0x2(v0)
1566 mtc0 $0, CP0_TAGLO
1567 cache Index_Store_Tag_D, 0x3(v0)
1568 beq $0, $0, 1b
1569 addiu v0, v0, 0x20
1571 #if 1
1572 1:
1573 cache_init_l24way:
1574 mtc0 $0, CP0_TAGHI
1575 addu v0, $0, a0
1576 addu v1, a0, 128*1024
1577 1: slt a3, v0, v1
1578 beq a3, $0, 1f
1579 nop
1580 mtc0 $0, CP0_TAGLO
1581 cache Index_Store_Tag_S, 0x0(v0)
1582 mtc0 $0, CP0_TAGLO
1583 cache Index_Store_Tag_S, 0x1(v0)
1584 mtc0 $0, CP0_TAGLO
1585 cache Index_Store_Tag_S, 0x2(v0)
1586 mtc0 $0, CP0_TAGLO
1587 cache Index_Store_Tag_S, 0x3(v0)
1588 beq $0, $0, 1b
1589 addiu v0, v0, 0x20
1592 1:
1593 cache_flush_4way:
1594 addu v0, $0, a0
1595 addu v1, a0, 128*1024
1596 1: slt a3, v0, v1
1597 beq a3, $0, 1f
1598 nop
1599 cache Index_Writeback_Inv_S, 0x0(v0)
1600 cache Index_Writeback_Inv_S, 0x1(v0)
1601 cache Index_Writeback_Inv_S, 0x2(v0)
1602 cache Index_Writeback_Inv_S, 0x3(v0)
1603 beq $0, $0, 1b
1604 addiu v0, v0, 0x20
1605 # endif
1607 1:
1608 cache_flush_i2way:
1609 addu v0, $0, a0
1610 addu v1, a0, a1
1611 1: slt a3, v0, v1
1612 beq a3, $0, 1f
1613 nop
1614 cache Index_Invalidate_I, 0x0(v0)
1615 # cache Index_Invalidate_I, 0x1(v0)
1616 # cache Index_Invalidate_I, 0x2(v0)
1617 # cache Index_Invalidate_I, 0x3(v0)
1618 beq $0, $0, 1b
1619 addiu v0, v0, 0x20
1620 1:
1621 cache_flush_d2way:
1622 addu v0, $0, a0
1623 addu v1, a0, a2
1624 1: slt a3, v0, v1
1625 beq a3, $0, 1f
1626 nop
1627 cache Index_Writeback_Inv_D, 0x0(v0)
1628 cache Index_Writeback_Inv_D, 0x1(v0)
1629 cache Index_Writeback_Inv_D, 0x2(v0)
1630 cache Index_Writeback_Inv_D, 0x3(v0)
1631 beq $0, $0, 1b
1632 addiu v0, v0, 0x20
1633 1:
1634 cache_init_finish:
1635 nop
1636 jr ra
1637 nop
1639 cache_init_panic:
1640 TTYDBG("cache init panic\r\n");
1641 1: b 1b
1642 nop
1643 .end godson2_cache_init
1645 #define PCICONF_WRITEB(dev,func,reg,data) \
1646 li a0,CFGADDR(dev,func,reg); \
1647 li a1,PHYS_TO_UNCACHED(PCI_CFG_SPACE); \
1648 and a2,a0,0xffff; \
1649 or a1,a2; \
1650 srl a0,16; \
1651 li a2,BONITO_BASE+BONITO_PCIMAP_CFG; \
1652 sw a0,BONITO_PCIMAP_CFG(bonito); \
1653 lw zero,BONITO_PCIMAP_CFG(bonito); \
1654 or a0,zero,data; \
1655 sb a0,(a1);
1657 #define PCICONF_WRITEW(dev,func,reg,data) \
1658 li a0,CFGADDR(dev,func,reg); \
1659 li a1,PHYS_TO_UNCACHED(PCI_CFG_SPACE); \
1660 and a2,a0,0xffff; \
1661 or a1,a2; \
1662 srl a0,16; \
1663 li a2,BONITO_BASE+BONITO_PCIMAP_CFG; \
1664 sw a0,BONITO_PCIMAP_CFG(bonito); \
1665 lw zero,BONITO_PCIMAP_CFG(bonito); \
1666 or a0,zero,data; \
1667 sw a0,(a1);
1668 #define PCICONF_ORB(dev,func,reg,data) \
1669 li a0,CFGADDR(dev,func,reg); \
1670 li a1,PHYS_TO_UNCACHED(PCI_CFG_SPACE); \
1671 and a2,a0,0xffff; \
1672 or a1,a2; \
1673 srl a0,16; \
1674 li a2,BONITO_BASE+BONITO_PCIMAP_CFG; \
1675 sw a0,BONITO_PCIMAP_CFG(bonito); \
1676 lw zero,BONITO_PCIMAP_CFG(bonito); \
1677 lbu a2,(a1); \
1678 ori a2,data; \
1679 sw a0,BONITO_PCIMAP_CFG(bonito); \
1680 lw zero,BONITO_PCIMAP_CFG(bonito); \
1681 sb a2,(a1);
1682 #define SUPERIO_WR(idx,data) \
1683 li v0,BONITO_PCIIO_BASE_VA+0x3f0; \
1684 or v1,zero,idx; \
1685 sb v1,(v0); \
1686 or v1,zero,data; \
1687 sb v1,1(v0);
1689 #define E2_EPP 2
1690 #define E2_S1 (1<<2)
1691 #define E2_S2 (1<<3)
1692 #define E2_FLOPPY (1<<4)
1694 LEAF(superio_init)
1696 PCICONF_WRITEW(PCI_IDSEL_VIA686B,0,4,7);
1697 /*positive decode*/
1698 PCICONF_ORB(PCI_IDSEL_VIA686B,0,0x81,0x80);
1699 PCICONF_WRITEB(PCI_IDSEL_VIA686B,0,0x83,0x80|0x1| 0x8);
1700 PCICONF_WRITEB(PCI_IDSEL_VIA686B,0,0x85,3);
1701 /* enable RTC/PS2/KBC */
1702 PCICONF_WRITEB(PCI_IDSEL_VIA686B,0,0x5A,7);
1704 SUPERIO_WR(0xe2,E2_S2|E2_S1|E2_EPP|E2_FLOPPY) /*enable serial and floppy */
1705 SUPERIO_WR(0xe3,0x3f0>>2) /*floppy base address*/
1706 SUPERIO_WR(0xe6,0x378>>2) /*parallel port*/
1707 SUPERIO_WR(0xe7,0x3f8>>2) /*set serial port1 base addr 0x3f8*/
1708 SUPERIO_WR(0xe8,0x2f8>>2) /*set serial port2 base addr 0x2f8*/
1709 SUPERIO_WR(0xee,0xc0) /* both ports on high speed*/
1711 PCICONF_WRITEB(PCI_IDSEL_VIA686B,0,0x85,1)
1712 jr ra
1713 nop
1714 END(superio_init)