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[openocd/ztw.git] / src / flash / nor / stm32x.h
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1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifndef STM32X_H
24 #define STM32X_H
26 struct stm32x_options
28 uint16_t RDP;
29 uint16_t user_options;
30 uint16_t protection[4];
33 struct stm32x_flash_bank
35 struct stm32x_options option_bytes;
36 struct working_area *write_algorithm;
37 int ppage_size;
38 int probed;
41 /* stm32x register locations */
43 #define STM32_FLASH_ACR 0x40022000
44 #define STM32_FLASH_KEYR 0x40022004
45 #define STM32_FLASH_OPTKEYR 0x40022008
46 #define STM32_FLASH_SR 0x4002200C
47 #define STM32_FLASH_CR 0x40022010
48 #define STM32_FLASH_AR 0x40022014
49 #define STM32_FLASH_OBR 0x4002201C
50 #define STM32_FLASH_WRPR 0x40022020
52 /* option byte location */
54 #define STM32_OB_RDP 0x1FFFF800
55 #define STM32_OB_USER 0x1FFFF802
56 #define STM32_OB_DATA0 0x1FFFF804
57 #define STM32_OB_DATA1 0x1FFFF806
58 #define STM32_OB_WRP0 0x1FFFF808
59 #define STM32_OB_WRP1 0x1FFFF80A
60 #define STM32_OB_WRP2 0x1FFFF80C
61 #define STM32_OB_WRP3 0x1FFFF80E
63 /* FLASH_CR register bits */
65 #define FLASH_PG (1 << 0)
66 #define FLASH_PER (1 << 1)
67 #define FLASH_MER (1 << 2)
68 #define FLASH_OPTPG (1 << 4)
69 #define FLASH_OPTER (1 << 5)
70 #define FLASH_STRT (1 << 6)
71 #define FLASH_LOCK (1 << 7)
72 #define FLASH_OPTWRE (1 << 9)
74 /* FLASH_SR register bits */
76 #define FLASH_BSY (1 << 0)
77 #define FLASH_PGERR (1 << 2)
78 #define FLASH_WRPRTERR (1 << 4)
79 #define FLASH_EOP (1 << 5)
81 /* STM32_FLASH_OBR bit definitions (reading) */
83 #define OPT_ERROR 0
84 #define OPT_READOUT 1
85 #define OPT_RDWDGSW 2
86 #define OPT_RDRSTSTOP 3
87 #define OPT_RDRSTSTDBY 4
89 /* register unlock keys */
91 #define KEY1 0x45670123
92 #define KEY2 0xCDEF89AB
94 struct stm32x_mem_layout {
95 uint32_t sector_start;
96 uint32_t sector_size;
99 #endif /* STM32X_H */