src/target/armv7m.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV7M_COMMON_H
  27 #define ARMV7M_COMMON_H
  28
  29 #include <target/arm_adi_v5.h>
  30 #include <target/armv4_5.h>
  31
  32 /* define for enabling armv7 gdb workarounds */
  33 #if 1
  34 #define ARMV7_GDB_HACKS
  35 #endif
  36
  37 enum armv7m_mode
  38 {
  39         ARMV7M_MODE_THREAD = 0,
  40         ARMV7M_MODE_USER_THREAD = 1,
  41         ARMV7M_MODE_HANDLER = 2,
  42         ARMV7M_MODE_ANY = -1
  43 };
  44
  45 extern char *armv7m_mode_strings[];
  46
  47 enum armv7m_regtype
  48 {
  49         ARMV7M_REGISTER_CORE_GP,
  50         ARMV7M_REGISTER_CORE_SP,
  51         ARMV7M_REGISTER_MEMMAP
  52 };
  53
  54 char *armv7m_exception_string(int number);
  55
  56 /* offsets into armv7m core register cache */
  57 enum
  58 {
  59         /* for convenience, the first set of indices match
  60          * the Cortex-M3 DCRSR selectors
  61          */
  62         ARMV7M_R0,
  63         ARMV7M_R1,
  64         ARMV7M_R2,
  65         ARMV7M_R3,
  66
  67         ARMV7M_R4,
  68         ARMV7M_R5,
  69         ARMV7M_R6,
  70         ARMV7M_R7,
  71
  72         ARMV7M_R8,
  73         ARMV7M_R9,
  74         ARMV7M_R10,
  75         ARMV7M_R11,
  76
  77         ARMV7M_R12,
  78         ARMV7M_R13,
  79         ARMV7M_R14,
  80         ARMV7M_PC = 15,
  81
  82         ARMV7M_xPSR = 16,
  83         ARMV7M_MSP,
  84         ARMV7M_PSP,
  85
  86         /* this next set of indices is arbitrary */
  87         ARMV7M_PRIMASK,
  88         ARMV7M_BASEPRI,
  89         ARMV7M_FAULTMASK,
  90         ARMV7M_CONTROL,
  91 };
  92
  93 #define ARMV7M_COMMON_MAGIC 0x2A452A45
  94
  95 struct armv7m_common
  96 {
  97         int common_magic;
  98         struct reg_cache *core_cache;
  99         enum armv7m_mode core_mode;
 100         int exception_number;
 101         struct swjdp_common swjdp_info;
 102
 103         /* Direct processor core register read and writes */
 104         int (*load_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
 105         int (*store_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
 106         /* register cache to processor synchronization */
 107         int (*read_core_reg)(struct target *target, unsigned num);
 108         int (*write_core_reg)(struct target *target, unsigned num);
 109
 110         int (*examine_debug_reason)(struct target *target);
 111         void (*post_debug_entry)(struct target *target);
 112
 113         void (*pre_restore_context)(struct target *target);
 114         void (*post_restore_context)(struct target *target);
 115 };
 116
 117 static inline struct armv7m_common *
 118 target_to_armv7m(struct target *target)
 119 {
 120         return target->arch_info;
 121 }
 122
 123 struct armv7m_algorithm
 124 {
 125         int common_magic;
 126
 127         enum armv7m_mode core_mode;
 128 };
 129
 130 struct armv7m_core_reg
 131 {
 132         uint32_t num;
 133         enum armv7m_regtype type;
 134         struct target *target;
 135         struct armv7m_common *armv7m_common;
 136 };
 137
 138 struct reg_cache *armv7m_build_reg_cache(struct target *target);
 139 enum armv7m_mode armv7m_number_to_mode(int number);
 140 int armv7m_mode_to_number(enum armv7m_mode mode);
 141
 142 int armv7m_arch_state(struct target *target);
 143 int armv7m_get_gdb_reg_list(struct target *target,
 144                 struct reg **reg_list[], int *reg_list_size);
 145
 146 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
 147
 148 int armv7m_run_algorithm(struct target *target,
 149                 int num_mem_params, struct mem_param *mem_params,
 150                 int num_reg_params, struct reg_param *reg_params,
 151                 uint32_t entry_point, uint32_t exit_point,
 152                 int timeout_ms, void *arch_info);
 153
 154 int armv7m_invalidate_core_regs(struct target *target);
 155
 156 int armv7m_restore_context(struct target *target);
 157
 158 int armv7m_checksum_memory(struct target *target,
 159                 uint32_t address, uint32_t count, uint32_t* checksum);
 160 int armv7m_blank_check_memory(struct target *target,
 161                 uint32_t address, uint32_t count, uint32_t* blank);
 162
 163 extern const struct command_registration armv7m_command_handlers[];
 164
 165 /* Thumb mode instructions
 166  */
 167
 168 /* Move to Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 169  * Rd: destination register
 170  * SYSm: source special register
 171  */
 172 #define ARMV7M_T_MRS(Rd, SYSm)  ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
 173
 174 /* Move from Register from Special Register  (Thumb mode) 32 bit Thumb2 instruction
 175  * Rd: source register
 176  * SYSm: destination special register
 177  */
 178 #define ARMV7M_T_MSR(SYSm, Rn)  ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
 179
 180 /* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
 181  * special-purpose register values  (Thumb mode) 16 bit Thumb2 instruction
 182  * Rd: source register
 183  * IF:
 184  */
 185 #define I_FLAG 2
 186 #define F_FLAG 1
 187 #define ARMV7M_T_CPSID(IF)      ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
 188 #define ARMV7M_T_CPSIE(IF)      ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
 189
 190 /* Breakpoint (Thumb mode) v5 onwards
 191  * Im: immediate value used by debugger
 192  */
 193 #define ARMV7M_T_BKPT(Im)       ((0xBE00 | Im) | ((0xBE00 | Im) << 16))
 194
 195 /* Store register (Thumb mode)
 196  * Rd: source register
 197  * Rn: base register
 198  */
 199 #define ARMV7M_T_STR(Rd, Rn)    ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
 200
 201 /* Load register (Thumb state)
 202  * Rd: destination register
 203  * Rn: base register
 204  */
 205 #define ARMV7M_T_LDR(Rd, Rn)    ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
 206
 207 /* Load multiple (Thumb state)
 208  * Rn: base register
 209  * List: for each bit in list: store register
 210  */
 211 #define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
 212
 213 /* Load register with PC relative addressing
 214  * Rd: register to load
 215  */
 216 #define ARMV7M_T_LDR_PCREL(Rd)  ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
 217
 218 /* Move hi register (Thumb mode)
 219  * Rd: destination register
 220  * Rm: source register
 221  */
 222 #define ARMV7M_T_MOV(Rd, Rm)    ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
 223
 224 /* No operation (Thumb mode)
 225  */
 226 #define ARMV7M_T_NOP    (0x46c0 | (0x46c0 << 16))
 227
 228 /* Move immediate to register (Thumb state)
 229  * Rd: destination register
 230  * Im: 8-bit immediate value
 231  */
 232 #define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
 233
 234 /* Branch and Exchange
 235  * Rm: register containing branch target
 236  */
 237 #define ARMV7M_T_BX(Rm)         ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
 238
 239 /* Branch (Thumb state)
 240  * Imm: Branch target
 241  */
 242 #define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
 243
 244 #endif /* ARMV7M_H */