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allow multiple bitbang interfaces
[openocd/ztw.git] / src / flash / nor / cfi.c
blobab2dca1f2a8a2f32f6b4cc619f379477d8bfa9cf
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include "cfi.h"
28 #include "non_cfi.h"
29 #include <target/arm.h>
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32
33
34 #define CFI_MAX_BUS_WIDTH 4
35 #define CFI_MAX_CHIP_WIDTH 4
36
37 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
38 #define CFI_MAX_INTEL_CODESIZE 256
39
40 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
41 {
42 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
43 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
44 };
45
46 /* CFI fixups foward declarations */
47 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
48 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
49 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
50
51 /* fixup after reading cmdset 0002 primary query table */
52 static const struct cfi_fixup cfi_0002_fixups[] = {
53 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
54 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
55 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
56 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
57 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
58 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
59 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
60 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
61 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
62 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
63 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
64 {0, 0, NULL, NULL}
65 };
66
67 /* fixup after reading cmdset 0001 primary query table */
68 static const struct cfi_fixup cfi_0001_fixups[] = {
69 {0, 0, NULL, NULL}
70 };
71
72 static struct cfi_flash_bank *cfi_bank_data(struct flash_bank *bank)
73 {
74 return (struct cfi_flash_bank *)flash_bank_data(bank);
75 }
76
77 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
78 {
79 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
80 const struct cfi_fixup *f;
81
82 for (f = fixups; f->fixup; f++)
83 {
84 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
85 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
86 {
87 f->fixup(bank, f->param);
88 }
89 }
90 }
91
92 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
93 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
94 {
95 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
96
97 if (cfi_info->x16_as_x8) offset *= 2;
98
99 /* while the sector list isn't built, only accesses to sector 0 work */
100 if (sector == 0)
101 return bank->base + offset * bank->bus_width;
102 else
103 {
104 if (!bank->sectors)
105 {
106 LOG_ERROR("BUG: sector list not yet built");
107 exit(-1);
108 }
109 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
110 }
111
112 }
113
114 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
115 {
116 int i;
117
118 /* clear whole buffer, to ensure bits that exceed the bus_width
119 * are set to zero
120 */
121 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
122 cmd_buf[i] = 0;
123
124 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
125 {
126 for (i = bank->bus_width; i > 0; i--)
127 {
128 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
129 }
130 }
131 else
132 {
133 for (i = 1; i <= bank->bus_width; i++)
134 {
135 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
136 }
137 }
138 }
139
140 /* read unsigned 8-bit value from the bank
141 * flash banks are expected to be made of similar chips
142 * the query result should be the same for all
143 */
144 static uint8_t cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset)
145 {
146 struct target *target = bank->target;
147 uint8_t data[CFI_MAX_BUS_WIDTH];
148
149 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
150
151 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
152 return data[0];
153 else
154 return data[bank->bus_width - 1];
155 }
156
157 /* read unsigned 8-bit value from the bank
158 * in case of a bank made of multiple chips,
159 * the individual values are ORed
160 */
161 static uint8_t cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset)
162 {
163 struct target *target = bank->target;
164 uint8_t data[CFI_MAX_BUS_WIDTH];
165 int i;
166
167 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
168
169 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
170 {
171 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
172 data[0] |= data[i];
173
174 return data[0];
175 }
176 else
177 {
178 uint8_t value = 0;
179 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
180 value |= data[bank->bus_width - 1 - i];
181
182 return value;
183 }
184 }
185
186 static uint16_t cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset)
187 {
188 struct target *target = bank->target;
189 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
190 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
191
192 if (cfi_info->x16_as_x8)
193 {
194 uint8_t i;
195 for (i = 0;i < 2;i++)
196 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
197 &data[i*bank->bus_width]);
198 }
199 else
200 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
201
202 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
203 return data[0] | data[bank->bus_width] << 8;
204 else
205 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
206 }
207
208 static uint32_t cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset)
209 {
210 struct target *target = bank->target;
211 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
212 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
213
214 if (cfi_info->x16_as_x8)
215 {
216 uint8_t i;
217 for (i = 0;i < 4;i++)
218 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
219 &data[i*bank->bus_width]);
220 }
221 else
222 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
223
224 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
225 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
226 else
227 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
228 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
229 }
230
231 static void cfi_intel_clear_status_register(struct flash_bank *bank)
232 {
233 struct target *target = bank->target;
234 uint8_t command[8];
235
236 if (target->state != TARGET_HALTED)
237 {
238 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
239 exit(-1);
240 }
241
242 cfi_command(bank, 0x50, command);
243 target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
244 }
245
246 uint8_t cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout)
247 {
248 uint8_t status;
249
250 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
251 {
252 LOG_DEBUG("status: 0x%x", status);
253 alive_sleep(1);
254 }
255
256 /* mask out bit 0 (reserved) */
257 status = status & 0xfe;
258
259 LOG_DEBUG("status: 0x%x", status);
260
261 if ((status & 0x80) != 0x80)
262 {
263 LOG_ERROR("timeout while waiting for WSM to become ready");
264 }
265 else if (status != 0x80)
266 {
267 LOG_ERROR("status register: 0x%x", status);
268 if (status & 0x2)
269 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
270 if (status & 0x4)
271 LOG_ERROR("Program suspended");
272 if (status & 0x8)
273 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
274 if (status & 0x10)
275 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
276 if (status & 0x20)
277 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
278 if (status & 0x40)
279 LOG_ERROR("Block Erase Suspended");
280
281 cfi_intel_clear_status_register(bank);
282 }
283
284 return status;
285 }
286
287 int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
288 {
289 uint8_t status, oldstatus;
290 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
291
292 oldstatus = cfi_get_u8(bank, 0, 0x0);
293
294 do {
295 status = cfi_get_u8(bank, 0, 0x0);
296 if ((status ^ oldstatus) & 0x40) {
297 if (status & cfi_info->status_poll_mask & 0x20) {
298 oldstatus = cfi_get_u8(bank, 0, 0x0);
299 status = cfi_get_u8(bank, 0, 0x0);
300 if ((status ^ oldstatus) & 0x40) {
301 LOG_ERROR("dq5 timeout, status: 0x%x", status);
302 return(ERROR_FLASH_OPERATION_FAILED);
303 } else {
304 LOG_DEBUG("status: 0x%x", status);
305 return(ERROR_OK);
306 }
307 }
308 } else { /* no toggle: finished, OK */
309 LOG_DEBUG("status: 0x%x", status);
310 return(ERROR_OK);
311 }
312
313 oldstatus = status;
314 alive_sleep(1);
315 } while (timeout-- > 0);
316
317 LOG_ERROR("timeout, status: 0x%x", status);
318
319 return(ERROR_FLASH_BUSY);
320 }
321
322 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
323 {
324 int retval;
325 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
326 struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
327 struct target *target = bank->target;
328 uint8_t command[8];
329
330 cfi_info->pri_ext = pri_ext;
331
332 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
333 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
334 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
335
336 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
337 {
338 cfi_command(bank, 0xf0, command);
339 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
340 {
341 return retval;
342 }
343 cfi_command(bank, 0xff, command);
344 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
345 {
346 return retval;
347 }
348 LOG_ERROR("Could not read bank flash bank information");
349 return ERROR_FLASH_BANK_INVALID;
350 }
351
352 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
353 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
354
355 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
356
357 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
358 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
359 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
360
361 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
362 pri_ext->feature_support,
363 pri_ext->suspend_cmd_support,
364 pri_ext->blk_status_reg_mask);
365
366 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
367 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
368
369 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
370 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
371 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
372
373 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
374 if (pri_ext->num_protection_fields != 1)
375 {
376 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
377 }
378
379 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
380 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
381 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
382
383 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
384
385 return ERROR_OK;
386 }
387
388 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
389 {
390 int retval;
391 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
392 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
393 struct target *target = bank->target;
394 uint8_t command[8];
395
396 cfi_info->pri_ext = pri_ext;
397
398 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
399 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
400 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
401
402 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
403 {
404 cfi_command(bank, 0xf0, command);
405 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
406 {
407 return retval;
408 }
409 LOG_ERROR("Could not read spansion bank information");
410 return ERROR_FLASH_BANK_INVALID;
411 }
412
413 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
414 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
415
416 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
417
418 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
419 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
420 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
421 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
422 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
423 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
424 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
425 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
426 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
427 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
428 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
429
430 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
431 pri_ext->EraseSuspend, pri_ext->BlkProt);
432
433 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
434 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
435
436 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
437
438
439 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
440 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
441 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
442
443 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
444
445 /* default values for implementation specific workarounds */
446 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
447 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
448 pri_ext->_reversed_geometry = 0;
449
450 return ERROR_OK;
451 }
452
453 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
454 {
455 int retval;
456 struct cfi_atmel_pri_ext atmel_pri_ext;
457 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
458 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
459 struct target *target = bank->target;
460 uint8_t command[8];
461
462 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
463 * but a different primary extended query table.
464 * We read the atmel table, and prepare a valid AMD/Spansion query table.
465 */
466
467 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
468
469 cfi_info->pri_ext = pri_ext;
470
471 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
472 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
473 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
474
475 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
476 {
477 cfi_command(bank, 0xf0, command);
478 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
479 {
480 return retval;
481 }
482 LOG_ERROR("Could not read atmel bank information");
483 return ERROR_FLASH_BANK_INVALID;
484 }
485
486 pri_ext->pri[0] = atmel_pri_ext.pri[0];
487 pri_ext->pri[1] = atmel_pri_ext.pri[1];
488 pri_ext->pri[2] = atmel_pri_ext.pri[2];
489
490 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
491 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
492
493 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
494
495 pri_ext->major_version = atmel_pri_ext.major_version;
496 pri_ext->minor_version = atmel_pri_ext.minor_version;
497
498 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
499 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
500 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
501 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
502
503 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
504 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
505
506 if (atmel_pri_ext.features & 0x02)
507 pri_ext->EraseSuspend = 2;
508
509 if (atmel_pri_ext.bottom_boot)
510 pri_ext->TopBottom = 2;
511 else
512 pri_ext->TopBottom = 3;
513
514 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
515 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
516
517 return ERROR_OK;
518 }
519
520 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
521 {
522 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
523
524 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
525 {
526 return cfi_read_atmel_pri_ext(bank);
527 }
528 else
529 {
530 return cfi_read_spansion_pri_ext(bank);
531 }
532 }
533
534 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
535 {
536 int printed;
537 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
538 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
539
540 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
541 buf += printed;
542 buf_size -= printed;
543
544 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
545 pri_ext->pri[1], pri_ext->pri[2],
546 pri_ext->major_version, pri_ext->minor_version);
547 buf += printed;
548 buf_size -= printed;
549
550 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
551 (pri_ext->SiliconRevision) >> 2,
552 (pri_ext->SiliconRevision) & 0x03);
553 buf += printed;
554 buf_size -= printed;
555
556 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
557 pri_ext->EraseSuspend,
558 pri_ext->BlkProt);
559 buf += printed;
560 buf_size -= printed;
561
562 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
563 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
564 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
565
566 return ERROR_OK;
567 }
568
569 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
570 {
571 int printed;
572 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
573 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
574
575 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
576 buf += printed;
577 buf_size -= printed;
578
579 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
580 buf += printed;
581 buf_size -= printed;
582
583 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
584 buf += printed;
585 buf_size -= printed;
586
587 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
588 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
589 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
590 buf += printed;
591 buf_size -= printed;
592
593 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
594
595 return ERROR_OK;
596 }
597
598 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
599 */
600 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
601 {
602 struct cfi_flash_bank *cfi_info;
603
604 if (CMD_ARGC < 6)
605 {
606 LOG_WARNING("incomplete flash_bank cfi configuration");
607 return ERROR_FLASH_BANK_INVALID;
608 }
609
610 uint16_t chip_width, bus_width;
611 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], bus_width);
612 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[4], chip_width);
613
614 if ((chip_width > CFI_MAX_CHIP_WIDTH)
615 || (bus_width > CFI_MAX_BUS_WIDTH))
616 {
617 LOG_ERROR("chip and bus width have to specified in bytes");
618 return ERROR_FLASH_BANK_INVALID;
619 }
620
621 cfi_info = malloc(sizeof(struct cfi_flash_bank));
622 cfi_info->probed = 0;
623
624 struct flash_bank *bank = flash_bank_from_object(object);
625 set_flash_bank_data(bank, cfi_info);
626
627 cfi_info->write_algorithm = NULL;
628
629 cfi_info->x16_as_x8 = 0;
630 cfi_info->jedec_probe = 0;
631 cfi_info->not_cfi = 0;
632
633 for (unsigned i = 6; i < CMD_ARGC; i++)
634 {
635 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
636 {
637 cfi_info->x16_as_x8 = 1;
638 }
639 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
640 {
641 cfi_info->jedec_probe = 1;
642 }
643 }
644
645 cfi_info->write_algorithm = NULL;
646
647 /* bank wasn't probed yet */
648 cfi_info->qry[0] = -1;
649
650 return ERROR_OK;
651 }
652
653 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
654 {
655 int retval;
656 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
657 struct target *target = bank->target;
658 uint8_t command[8];
659 int i;
660
661 cfi_intel_clear_status_register(bank);
662
663 for (i = first; i <= last; i++)
664 {
665 cfi_command(bank, 0x20, command);
666 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
667 {
668 return retval;
669 }
670
671 cfi_command(bank, 0xd0, command);
672 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
673 {
674 return retval;
675 }
676
677 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
678 bank->sectors[i].is_erased = 1;
679 else
680 {
681 cfi_command(bank, 0xff, command);
682 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
683 {
684 return retval;
685 }
686
687 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
688 return ERROR_FLASH_OPERATION_FAILED;
689 }
690 }
691
692 cfi_command(bank, 0xff, command);
693 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
694
695 }
696
697 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
698 {
699 int retval;
700 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
701 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
702 struct target *target = bank->target;
703 uint8_t command[8];
704 int i;
705
706 for (i = first; i <= last; i++)
707 {
708 cfi_command(bank, 0xaa, command);
709 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
710 {
711 return retval;
712 }
713
714 cfi_command(bank, 0x55, command);
715 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
716 {
717 return retval;
718 }
719
720 cfi_command(bank, 0x80, command);
721 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
722 {
723 return retval;
724 }
725
726 cfi_command(bank, 0xaa, command);
727 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
728 {
729 return retval;
730 }
731
732 cfi_command(bank, 0x55, command);
733 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
734 {
735 return retval;
736 }
737
738 cfi_command(bank, 0x30, command);
739 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
740 {
741 return retval;
742 }
743
744 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
745 bank->sectors[i].is_erased = 1;
746 else
747 {
748 cfi_command(bank, 0xf0, command);
749 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
750 {
751 return retval;
752 }
753
754 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
755 return ERROR_FLASH_OPERATION_FAILED;
756 }
757 }
758
759 cfi_command(bank, 0xf0, command);
760 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
761 }
762
763 static int cfi_erase(struct flash_bank *bank, int first, int last)
764 {
765 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
766
767 if (bank->target->state != TARGET_HALTED)
768 {
769 LOG_ERROR("Target not halted");
770 return ERROR_TARGET_NOT_HALTED;
771 }
772
773 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
774 {
775 return ERROR_FLASH_SECTOR_INVALID;
776 }
777
778 if (cfi_info->qry[0] != 'Q')
779 return ERROR_FLASH_BANK_NOT_PROBED;
780
781 switch (cfi_info->pri_id)
782 {
783 case 1:
784 case 3:
785 return cfi_intel_erase(bank, first, last);
786 break;
787 case 2:
788 return cfi_spansion_erase(bank, first, last);
789 break;
790 default:
791 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
792 break;
793 }
794
795 return ERROR_OK;
796 }
797
798 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
799 {
800 int retval;
801 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
802 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
803 struct target *target = bank->target;
804 uint8_t command[8];
805 int retry = 0;
806 int i;
807
808 /* if the device supports neither legacy lock/unlock (bit 3) nor
809 * instant individual block locking (bit 5).
810 */
811 if (!(pri_ext->feature_support & 0x28))
812 return ERROR_FLASH_OPERATION_FAILED;
813
814 cfi_intel_clear_status_register(bank);
815
816 for (i = first; i <= last; i++)
817 {
818 cfi_command(bank, 0x60, command);
819 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
820 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
821 {
822 return retval;
823 }
824 if (set)
825 {
826 cfi_command(bank, 0x01, command);
827 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
828 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
829 {
830 return retval;
831 }
832 bank->sectors[i].is_protected = 1;
833 }
834 else
835 {
836 cfi_command(bank, 0xd0, command);
837 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
838 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
839 {
840 return retval;
841 }
842 bank->sectors[i].is_protected = 0;
843 }
844
845 /* instant individual block locking doesn't require reading of the status register */
846 if (!(pri_ext->feature_support & 0x20))
847 {
848 /* Clear lock bits operation may take up to 1.4s */
849 cfi_intel_wait_status_busy(bank, 1400);
850 }
851 else
852 {
853 uint8_t block_status;
854 /* read block lock bit, to verify status */
855 cfi_command(bank, 0x90, command);
856 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
857 {
858 return retval;
859 }
860 block_status = cfi_get_u8(bank, i, 0x2);
861
862 if ((block_status & 0x1) != set)
863 {
864 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
865 cfi_command(bank, 0x70, command);
866 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
867 {
868 return retval;
869 }
870 cfi_intel_wait_status_busy(bank, 10);
871
872 if (retry > 10)
873 return ERROR_FLASH_OPERATION_FAILED;
874 else
875 {
876 i--;
877 retry++;
878 }
879 }
880 }
881 }
882
883 /* if the device doesn't support individual block lock bits set/clear,
884 * all blocks have been unlocked in parallel, so we set those that should be protected
885 */
886 if ((!set) && (!(pri_ext->feature_support & 0x20)))
887 {
888 for (i = 0; i < bank->num_sectors; i++)
889 {
890 if (bank->sectors[i].is_protected == 1)
891 {
892 cfi_intel_clear_status_register(bank);
893
894 cfi_command(bank, 0x60, command);
895 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
896 {
897 return retval;
898 }
899
900 cfi_command(bank, 0x01, command);
901 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
902 {
903 return retval;
904 }
905
906 cfi_intel_wait_status_busy(bank, 100);
907 }
908 }
909 }
910
911 cfi_command(bank, 0xff, command);
912 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
913 }
914
915 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
916 {
917 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
918
919 if (bank->target->state != TARGET_HALTED)
920 {
921 LOG_ERROR("Target not halted");
922 return ERROR_TARGET_NOT_HALTED;
923 }
924
925 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
926 {
927 return ERROR_FLASH_SECTOR_INVALID;
928 }
929
930 if (cfi_info->qry[0] != 'Q')
931 return ERROR_FLASH_BANK_NOT_PROBED;
932
933 switch (cfi_info->pri_id)
934 {
935 case 1:
936 case 3:
937 cfi_intel_protect(bank, set, first, last);
938 break;
939 default:
940 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
941 break;
942 }
943
944 return ERROR_OK;
945 }
946
947 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
948 static void cfi_add_byte(struct flash_bank *bank, uint8_t *word, uint8_t byte)
949 {
950 /* struct target *target = bank->target; */
951
952 int i;
953
954 /* NOTE:
955 * The data to flash must not be changed in endian! We write a bytestrem in
956 * target byte order already. Only the control and status byte lane of the flash
957 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
958 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
959 */
960
961 #if 0
962 if (target->endianness == TARGET_LITTLE_ENDIAN)
963 {
964 #endif
965 /* shift bytes */
966 for (i = 0; i < bank->bus_width - 1; i++)
967 word[i] = word[i + 1];
968 word[bank->bus_width - 1] = byte;
969 #if 0
970 }
971 else
972 {
973 /* shift bytes */
974 for (i = bank->bus_width - 1; i > 0; i--)
975 word[i] = word[i - 1];
976 word[0] = byte;
977 }
978 #endif
979 }
980
981 /* Convert code image to target endian */
982 /* FIXME create general block conversion fcts in target.c?) */
983 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
984 {
985 uint32_t i;
986 for (i = 0; i< count; i++)
987 {
988 target_buffer_set_u32(target, dest, *src);
989 dest += 4;
990 src++;
991 }
992 }
993
994 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
995 {
996 struct target *target = bank->target;
997
998 uint8_t buf[CFI_MAX_BUS_WIDTH];
999 cfi_command(bank, cmd, buf);
1000 switch (bank->bus_width)
1001 {
1002 case 1 :
1003 return buf[0];
1004 break;
1005 case 2 :
1006 return target_buffer_get_u16(target, buf);
1007 break;
1008 case 4 :
1009 return target_buffer_get_u32(target, buf);
1010 break;
1011 default :
1012 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1013 return 0;
1014 }
1015 }
1016
1017 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1018 {
1019 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
1020 struct target *target = bank->target;
1021 struct reg_param reg_params[7];
1022 struct arm_algorithm armv4_5_info;
1023 struct working_area *source;
1024 uint32_t buffer_size = 32768;
1025 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1026
1027 /* algorithm register usage:
1028 * r0: source address (in RAM)
1029 * r1: target address (in Flash)
1030 * r2: count
1031 * r3: flash write command
1032 * r4: status byte (returned to host)
1033 * r5: busy test pattern
1034 * r6: error test pattern
1035 */
1036
1037 static const uint32_t word_32_code[] = {
1038 0xe4904004, /* loop: ldr r4, [r0], #4 */
1039 0xe5813000, /* str r3, [r1] */
1040 0xe5814000, /* str r4, [r1] */
1041 0xe5914000, /* busy: ldr r4, [r1] */
1042 0xe0047005, /* and r7, r4, r5 */
1043 0xe1570005, /* cmp r7, r5 */
1044 0x1afffffb, /* bne busy */
1045 0xe1140006, /* tst r4, r6 */
1046 0x1a000003, /* bne done */
1047 0xe2522001, /* subs r2, r2, #1 */
1048 0x0a000001, /* beq done */
1049 0xe2811004, /* add r1, r1 #4 */
1050 0xeafffff2, /* b loop */
1051 0xeafffffe /* done: b -2 */
1052 };
1053
1054 static const uint32_t word_16_code[] = {
1055 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1056 0xe1c130b0, /* strh r3, [r1] */
1057 0xe1c140b0, /* strh r4, [r1] */
1058 0xe1d140b0, /* busy ldrh r4, [r1] */
1059 0xe0047005, /* and r7, r4, r5 */
1060 0xe1570005, /* cmp r7, r5 */
1061 0x1afffffb, /* bne busy */
1062 0xe1140006, /* tst r4, r6 */
1063 0x1a000003, /* bne done */
1064 0xe2522001, /* subs r2, r2, #1 */
1065 0x0a000001, /* beq done */
1066 0xe2811002, /* add r1, r1 #2 */
1067 0xeafffff2, /* b loop */
1068 0xeafffffe /* done: b -2 */
1069 };
1070
1071 static const uint32_t word_8_code[] = {
1072 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1073 0xe5c13000, /* strb r3, [r1] */
1074 0xe5c14000, /* strb r4, [r1] */
1075 0xe5d14000, /* busy ldrb r4, [r1] */
1076 0xe0047005, /* and r7, r4, r5 */
1077 0xe1570005, /* cmp r7, r5 */
1078 0x1afffffb, /* bne busy */
1079 0xe1140006, /* tst r4, r6 */
1080 0x1a000003, /* bne done */
1081 0xe2522001, /* subs r2, r2, #1 */
1082 0x0a000001, /* beq done */
1083 0xe2811001, /* add r1, r1 #1 */
1084 0xeafffff2, /* b loop */
1085 0xeafffffe /* done: b -2 */
1086 };
1087 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1088 const uint32_t *target_code_src;
1089 uint32_t target_code_size;
1090 int retval = ERROR_OK;
1091
1092
1093 cfi_intel_clear_status_register(bank);
1094
1095 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1096 armv4_5_info.core_mode = ARM_MODE_SVC;
1097 armv4_5_info.core_state = ARM_STATE_ARM;
1098
1099 /* If we are setting up the write_algorith, we need target_code_src */
1100 /* if not we only need target_code_size. */
1101
1102 /* However, we don't want to create multiple code paths, so we */
1103 /* do the unecessary evaluation of target_code_src, which the */
1104 /* compiler will probably nicely optimize away if not needed */
1105
1106 /* prepare algorithm code for target endian */
1107 switch (bank->bus_width)
1108 {
1109 case 1 :
1110 target_code_src = word_8_code;
1111 target_code_size = sizeof(word_8_code);
1112 break;
1113 case 2 :
1114 target_code_src = word_16_code;
1115 target_code_size = sizeof(word_16_code);
1116 break;
1117 case 4 :
1118 target_code_src = word_32_code;
1119 target_code_size = sizeof(word_32_code);
1120 break;
1121 default:
1122 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1123 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1124 }
1125
1126 /* flash write code */
1127 if (!cfi_info->write_algorithm)
1128 {
1129 if (target_code_size > sizeof(target_code))
1130 {
1131 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1132 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1133 }
1134 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1135
1136 /* Get memory for block write handler */
1137 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1138 if (retval != ERROR_OK)
1139 {
1140 LOG_WARNING("No working area available, can't do block memory writes");
1141 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1142 };
1143
1144 /* write algorithm code to working area */
1145 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1146 if (retval != ERROR_OK)
1147 {
1148 LOG_ERROR("Unable to write block write code to target");
1149 goto cleanup;
1150 }
1151 }
1152
1153 /* Get a workspace buffer for the data to flash starting with 32k size.
1154 Half size until buffer would be smaller 256 Bytem then fail back */
1155 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1156 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1157 {
1158 buffer_size /= 2;
1159 if (buffer_size <= 256)
1160 {
1161 LOG_WARNING("no large enough working area available, can't do block memory writes");
1162 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1163 goto cleanup;
1164 }
1165 };
1166
1167 /* setup algo registers */
1168 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1169 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1170 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1171 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1172 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1173 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1174 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1175
1176 /* prepare command and status register patterns */
1177 write_command_val = cfi_command_val(bank, 0x40);
1178 busy_pattern_val = cfi_command_val(bank, 0x80);
1179 error_pattern_val = cfi_command_val(bank, 0x7e);
1180
1181 LOG_INFO("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1182
1183 /* Programming main loop */
1184 while (count > 0)
1185 {
1186 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1187 uint32_t wsm_error;
1188
1189 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1190 {
1191 goto cleanup;
1192 }
1193
1194 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1195 buf_set_u32(reg_params[1].value, 0, 32, address);
1196 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1197
1198 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1199 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1200 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1201
1202 LOG_INFO("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1203
1204 /* Execute algorithm, assume breakpoint for last instruction */
1205 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1206 cfi_info->write_algorithm->address,
1207 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1208 10000, /* 10s should be enough for max. 32k of data */
1209 &armv4_5_info);
1210
1211 /* On failure try a fall back to direct word writes */
1212 if (retval != ERROR_OK)
1213 {
1214 cfi_intel_clear_status_register(bank);
1215 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1216 retval = ERROR_FLASH_OPERATION_FAILED;
1217 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1218 /* FIXME To allow fall back or recovery, we must save the actual status
1219 somewhere, so that a higher level code can start recovery. */
1220 goto cleanup;
1221 }
1222
1223 /* Check return value from algo code */
1224 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1225 if (wsm_error)
1226 {
1227 /* read status register (outputs debug inforation) */
1228 cfi_intel_wait_status_busy(bank, 100);
1229 cfi_intel_clear_status_register(bank);
1230 retval = ERROR_FLASH_OPERATION_FAILED;
1231 goto cleanup;
1232 }
1233
1234 buffer += thisrun_count;
1235 address += thisrun_count;
1236 count -= thisrun_count;
1237 }
1238
1239 /* free up resources */
1240 cleanup:
1241 if (source)
1242 target_free_working_area(target, source);
1243
1244 if (cfi_info->write_algorithm)
1245 {
1246 target_free_working_area(target, cfi_info->write_algorithm);
1247 cfi_info->write_algorithm = NULL;
1248 }
1249
1250 destroy_reg_param(&reg_params[0]);
1251 destroy_reg_param(&reg_params[1]);
1252 destroy_reg_param(&reg_params[2]);
1253 destroy_reg_param(&reg_params[3]);
1254 destroy_reg_param(&reg_params[4]);
1255 destroy_reg_param(&reg_params[5]);
1256 destroy_reg_param(&reg_params[6]);
1257
1258 return retval;
1259 }
1260
1261 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1262 {
1263 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
1264 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1265 struct target *target = bank->target;
1266 struct reg_param reg_params[10];
1267 struct arm_algorithm armv4_5_info;
1268 struct working_area *source;
1269 uint32_t buffer_size = 32768;
1270 uint32_t status;
1271 int retval, retvaltemp;
1272 int exit_code = ERROR_OK;
1273
1274 /* input parameters - */
1275 /* R0 = source address */
1276 /* R1 = destination address */
1277 /* R2 = number of writes */
1278 /* R3 = flash write command */
1279 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1280 /* output parameters - */
1281 /* R5 = 0x80 ok 0x00 bad */
1282 /* temp registers - */
1283 /* R6 = value read from flash to test status */
1284 /* R7 = holding register */
1285 /* unlock registers - */
1286 /* R8 = unlock1_addr */
1287 /* R9 = unlock1_cmd */
1288 /* R10 = unlock2_addr */
1289 /* R11 = unlock2_cmd */
1290
1291 static const uint32_t word_32_code[] = {
1292 /* 00008100 <sp_32_code>: */
1293 0xe4905004, /* ldr r5, [r0], #4 */
1294 0xe5889000, /* str r9, [r8] */
1295 0xe58ab000, /* str r11, [r10] */
1296 0xe5883000, /* str r3, [r8] */
1297 0xe5815000, /* str r5, [r1] */
1298 0xe1a00000, /* nop */
1299 /* */
1300 /* 00008110 <sp_32_busy>: */
1301 0xe5916000, /* ldr r6, [r1] */
1302 0xe0257006, /* eor r7, r5, r6 */
1303 0xe0147007, /* ands r7, r4, r7 */
1304 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1305 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1306 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1307 0xe5916000, /* ldr r6, [r1] */
1308 0xe0257006, /* eor r7, r5, r6 */
1309 0xe0147007, /* ands r7, r4, r7 */
1310 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1311 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1312 0x1a000004, /* bne 8154 <sp_32_done> */
1313 /* */
1314 /* 00008140 <sp_32_cont>: */
1315 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1316 0x03a05080, /* moveq r5, #128 ; 0x80 */
1317 0x0a000001, /* beq 8154 <sp_32_done> */
1318 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1319 0xeaffffe8, /* b 8100 <sp_32_code> */
1320 /* */
1321 /* 00008154 <sp_32_done>: */
1322 0xeafffffe /* b 8154 <sp_32_done> */
1323 };
1324
1325 static const uint32_t word_16_code[] = {
1326 /* 00008158 <sp_16_code>: */
1327 0xe0d050b2, /* ldrh r5, [r0], #2 */
1328 0xe1c890b0, /* strh r9, [r8] */
1329 0xe1cab0b0, /* strh r11, [r10] */
1330 0xe1c830b0, /* strh r3, [r8] */
1331 0xe1c150b0, /* strh r5, [r1] */
1332 0xe1a00000, /* nop (mov r0,r0) */
1333 /* */
1334 /* 00008168 <sp_16_busy>: */
1335 0xe1d160b0, /* ldrh r6, [r1] */
1336 0xe0257006, /* eor r7, r5, r6 */
1337 0xe0147007, /* ands r7, r4, r7 */
1338 0x0a000007, /* beq 8198 <sp_16_cont> */
1339 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1340 0x0afffff9, /* beq 8168 <sp_16_busy> */
1341 0xe1d160b0, /* ldrh r6, [r1] */
1342 0xe0257006, /* eor r7, r5, r6 */
1343 0xe0147007, /* ands r7, r4, r7 */
1344 0x0a000001, /* beq 8198 <sp_16_cont> */
1345 0xe3a05000, /* mov r5, #0 ; 0x0 */
1346 0x1a000004, /* bne 81ac <sp_16_done> */
1347 /* */
1348 /* 00008198 <sp_16_cont>: */
1349 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1350 0x03a05080, /* moveq r5, #128 ; 0x80 */
1351 0x0a000001, /* beq 81ac <sp_16_done> */
1352 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1353 0xeaffffe8, /* b 8158 <sp_16_code> */
1354 /* */
1355 /* 000081ac <sp_16_done>: */
1356 0xeafffffe /* b 81ac <sp_16_done> */
1357 };
1358
1359 static const uint32_t word_16_code_dq7only[] = {
1360 /* <sp_16_code>: */
1361 0xe0d050b2, /* ldrh r5, [r0], #2 */
1362 0xe1c890b0, /* strh r9, [r8] */
1363 0xe1cab0b0, /* strh r11, [r10] */
1364 0xe1c830b0, /* strh r3, [r8] */
1365 0xe1c150b0, /* strh r5, [r1] */
1366 0xe1a00000, /* nop (mov r0,r0) */
1367 /* */
1368 /* <sp_16_busy>: */
1369 0xe1d160b0, /* ldrh r6, [r1] */
1370 0xe0257006, /* eor r7, r5, r6 */
1371 0xe2177080, /* ands r7, #0x80 */
1372 0x1afffffb, /* bne 8168 <sp_16_busy> */
1373 /* */
1374 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1375 0x03a05080, /* moveq r5, #128 ; 0x80 */
1376 0x0a000001, /* beq 81ac <sp_16_done> */
1377 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1378 0xeafffff0, /* b 8158 <sp_16_code> */
1379 /* */
1380 /* 000081ac <sp_16_done>: */
1381 0xeafffffe /* b 81ac <sp_16_done> */
1382 };
1383
1384 static const uint32_t word_8_code[] = {
1385 /* 000081b0 <sp_16_code_end>: */
1386 0xe4d05001, /* ldrb r5, [r0], #1 */
1387 0xe5c89000, /* strb r9, [r8] */
1388 0xe5cab000, /* strb r11, [r10] */
1389 0xe5c83000, /* strb r3, [r8] */
1390 0xe5c15000, /* strb r5, [r1] */
1391 0xe1a00000, /* nop (mov r0,r0) */
1392 /* */
1393 /* 000081c0 <sp_8_busy>: */
1394 0xe5d16000, /* ldrb r6, [r1] */
1395 0xe0257006, /* eor r7, r5, r6 */
1396 0xe0147007, /* ands r7, r4, r7 */
1397 0x0a000007, /* beq 81f0 <sp_8_cont> */
1398 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1399 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1400 0xe5d16000, /* ldrb r6, [r1] */
1401 0xe0257006, /* eor r7, r5, r6 */
1402 0xe0147007, /* ands r7, r4, r7 */
1403 0x0a000001, /* beq 81f0 <sp_8_cont> */
1404 0xe3a05000, /* mov r5, #0 ; 0x0 */
1405 0x1a000004, /* bne 8204 <sp_8_done> */
1406 /* */
1407 /* 000081f0 <sp_8_cont>: */
1408 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1409 0x03a05080, /* moveq r5, #128 ; 0x80 */
1410 0x0a000001, /* beq 8204 <sp_8_done> */
1411 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1412 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1413 /* */
1414 /* 00008204 <sp_8_done>: */
1415 0xeafffffe /* b 8204 <sp_8_done> */
1416 };
1417
1418 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1419 armv4_5_info.core_mode = ARM_MODE_SVC;
1420 armv4_5_info.core_state = ARM_STATE_ARM;
1421
1422 int target_code_size;
1423 const uint32_t *target_code_src;
1424
1425 switch (bank->bus_width)
1426 {
1427 case 1 :
1428 target_code_src = word_8_code;
1429 target_code_size = sizeof(word_8_code);
1430 break;
1431 case 2 :
1432 /* Check for DQ5 support */
1433 if( cfi_info->status_poll_mask & (1 << 5) )
1434 {
1435 target_code_src = word_16_code;
1436 target_code_size = sizeof(word_16_code);
1437 }
1438 else
1439 {
1440 /* No DQ5 support. Use DQ7 DATA# polling only. */
1441 target_code_src = word_16_code_dq7only;
1442 target_code_size = sizeof(word_16_code_dq7only);
1443 }
1444 break;
1445 case 4 :
1446 target_code_src = word_32_code;
1447 target_code_size = sizeof(word_32_code);
1448 break;
1449 default:
1450 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1451 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1452 }
1453
1454 /* flash write code */
1455 if (!cfi_info->write_algorithm)
1456 {
1457 uint8_t *target_code;
1458
1459 /* convert bus-width dependent algorithm code to correct endiannes */
1460 target_code = malloc(target_code_size);
1461 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1462
1463 /* allocate working area */
1464 retval = target_alloc_working_area(target, target_code_size,
1465 &cfi_info->write_algorithm);
1466 if (retval != ERROR_OK)
1467 {
1468 free(target_code);
1469 return retval;
1470 }
1471
1472 /* write algorithm code to working area */
1473 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1474 target_code_size, target_code)) != ERROR_OK)
1475 {
1476 free(target_code);
1477 return retval;
1478 }
1479
1480 free(target_code);
1481 }
1482 /* the following code still assumes target code is fixed 24*4 bytes */
1483
1484 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1485 {
1486 buffer_size /= 2;
1487 if (buffer_size <= 256)
1488 {
1489 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1490 if (cfi_info->write_algorithm)
1491 target_free_working_area(target, cfi_info->write_algorithm);
1492
1493 LOG_WARNING("not enough working area available, can't do block memory writes");
1494 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1495 }
1496 };
1497
1498 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1499 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1500 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1501 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1502 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1503 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1504 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1505 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1506 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1507 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1508
1509 while (count > 0)
1510 {
1511 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1512
1513 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1514
1515 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1516 buf_set_u32(reg_params[1].value, 0, 32, address);
1517 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1518 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1519 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1520 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1521 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1522 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1523 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1524
1525 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1526 cfi_info->write_algorithm->address,
1527 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1528 10000, &armv4_5_info);
1529
1530 status = buf_get_u32(reg_params[5].value, 0, 32);
1531
1532 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1533 {
1534 LOG_DEBUG("status: 0x%" PRIx32 , status);
1535 exit_code = ERROR_FLASH_OPERATION_FAILED;
1536 break;
1537 }
1538
1539 buffer += thisrun_count;
1540 address += thisrun_count;
1541 count -= thisrun_count;
1542 }
1543
1544 target_free_all_working_areas(target);
1545
1546 destroy_reg_param(&reg_params[0]);
1547 destroy_reg_param(&reg_params[1]);
1548 destroy_reg_param(&reg_params[2]);
1549 destroy_reg_param(&reg_params[3]);
1550 destroy_reg_param(&reg_params[4]);
1551 destroy_reg_param(&reg_params[5]);
1552 destroy_reg_param(&reg_params[6]);
1553 destroy_reg_param(&reg_params[7]);
1554 destroy_reg_param(&reg_params[8]);
1555 destroy_reg_param(&reg_params[9]);
1556
1557 return exit_code;
1558 }
1559
1560 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1561 {
1562 int retval;
1563 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
1564 struct target *target = bank->target;
1565 uint8_t command[8];
1566
1567 cfi_intel_clear_status_register(bank);
1568 cfi_command(bank, 0x40, command);
1569 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1570 {
1571 return retval;
1572 }
1573
1574 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1575 {
1576 return retval;
1577 }
1578
1579 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1580 {
1581 cfi_command(bank, 0xff, command);
1582 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1583 {
1584 return retval;
1585 }
1586
1587 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1588 return ERROR_FLASH_OPERATION_FAILED;
1589 }
1590
1591 return ERROR_OK;
1592 }
1593
1594 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1595 {
1596 int retval;
1597 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
1598 struct target *target = bank->target;
1599 uint8_t command[8];
1600
1601 /* Calculate buffer size and boundary mask */
1602 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1603 uint32_t buffermask = buffersize-1;
1604 uint32_t bufferwsize;
1605
1606 /* Check for valid range */
1607 if (address & buffermask)
1608 {
1609 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1610 bank->base, address, cfi_info->max_buf_write_size);
1611 return ERROR_FLASH_OPERATION_FAILED;
1612 }
1613 switch (bank->chip_width)
1614 {
1615 case 4 : bufferwsize = buffersize / 4; break;
1616 case 2 : bufferwsize = buffersize / 2; break;
1617 case 1 : bufferwsize = buffersize; break;
1618 default:
1619 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1620 return ERROR_FLASH_OPERATION_FAILED;
1621 }
1622
1623 bufferwsize/=(bank->bus_width / bank->chip_width);
1624
1625
1626 /* Check for valid size */
1627 if (wordcount > bufferwsize)
1628 {
1629 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1630 return ERROR_FLASH_OPERATION_FAILED;
1631 }
1632
1633 /* Write to flash buffer */
1634 cfi_intel_clear_status_register(bank);
1635
1636 /* Initiate buffer operation _*/
1637 cfi_command(bank, 0xE8, command);
1638 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1639 {
1640 return retval;
1641 }
1642 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1643 {
1644 cfi_command(bank, 0xff, command);
1645 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1646 {
1647 return retval;
1648 }
1649
1650 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1651 return ERROR_FLASH_OPERATION_FAILED;
1652 }
1653
1654 /* Write buffer wordcount-1 and data words */
1655 cfi_command(bank, bufferwsize-1, command);
1656 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1657 {
1658 return retval;
1659 }
1660
1661 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1662 {
1663 return retval;
1664 }
1665
1666 /* Commit write operation */
1667 cfi_command(bank, 0xd0, command);
1668 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1669 {
1670 return retval;
1671 }
1672 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1673 {
1674 cfi_command(bank, 0xff, command);
1675 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1676 {
1677 return retval;
1678 }
1679
1680 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1681 return ERROR_FLASH_OPERATION_FAILED;
1682 }
1683
1684 return ERROR_OK;
1685 }
1686
1687 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1688 {
1689 int retval;
1690 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
1691 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1692 struct target *target = bank->target;
1693 uint8_t command[8];
1694
1695 cfi_command(bank, 0xaa, command);
1696 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1697 {
1698 return retval;
1699 }
1700
1701 cfi_command(bank, 0x55, command);
1702 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1703 {
1704 return retval;
1705 }
1706
1707 cfi_command(bank, 0xa0, command);
1708 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1709 {
1710 return retval;
1711 }
1712
1713 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1714 {
1715 return retval;
1716 }
1717
1718 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1719 {
1720 cfi_command(bank, 0xf0, command);
1721 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1722 {
1723 return retval;
1724 }
1725
1726 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1727 return ERROR_FLASH_OPERATION_FAILED;
1728 }
1729
1730 return ERROR_OK;
1731 }
1732
1733 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1734 {
1735 int retval;
1736 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
1737 struct target *target = bank->target;
1738 uint8_t command[8];
1739 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1740
1741 /* Calculate buffer size and boundary mask */
1742 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1743 uint32_t buffermask = buffersize-1;
1744 uint32_t bufferwsize;
1745
1746 /* Check for valid range */
1747 if (address & buffermask)
1748 {
1749 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1750 return ERROR_FLASH_OPERATION_FAILED;
1751 }
1752 switch (bank->chip_width)
1753 {
1754 case 4 : bufferwsize = buffersize / 4; break;
1755 case 2 : bufferwsize = buffersize / 2; break;
1756 case 1 : bufferwsize = buffersize; break;
1757 default:
1758 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1759 return ERROR_FLASH_OPERATION_FAILED;
1760 }
1761
1762 bufferwsize/=(bank->bus_width / bank->chip_width);
1763
1764 /* Check for valid size */
1765 if (wordcount > bufferwsize)
1766 {
1767 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1768 return ERROR_FLASH_OPERATION_FAILED;
1769 }
1770
1771 // Unlock
1772 cfi_command(bank, 0xaa, command);
1773 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1774 {
1775 return retval;
1776 }
1777
1778 cfi_command(bank, 0x55, command);
1779 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1780 {
1781 return retval;
1782 }
1783
1784 // Buffer load command
1785 cfi_command(bank, 0x25, command);
1786 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1787 {
1788 return retval;
1789 }
1790
1791 /* Write buffer wordcount-1 and data words */
1792 cfi_command(bank, bufferwsize-1, command);
1793 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1794 {
1795 return retval;
1796 }
1797
1798 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1799 {
1800 return retval;
1801 }
1802
1803 /* Commit write operation */
1804 cfi_command(bank, 0x29, command);
1805 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1806 {
1807 return retval;
1808 }
1809
1810 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1811 {
1812 cfi_command(bank, 0xf0, command);
1813 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1814 {
1815 return retval;
1816 }
1817
1818 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1819 return ERROR_FLASH_OPERATION_FAILED;
1820 }
1821
1822 return ERROR_OK;
1823 }
1824
1825 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1826 {
1827 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
1828
1829 switch (cfi_info->pri_id)
1830 {
1831 case 1:
1832 case 3:
1833 return cfi_intel_write_word(bank, word, address);
1834 break;
1835 case 2:
1836 return cfi_spansion_write_word(bank, word, address);
1837 break;
1838 default:
1839 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1840 break;
1841 }
1842
1843 return ERROR_FLASH_OPERATION_FAILED;
1844 }
1845
1846 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1847 {
1848 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
1849
1850 switch (cfi_info->pri_id)
1851 {
1852 case 1:
1853 case 3:
1854 return cfi_intel_write_words(bank, word, wordcount, address);
1855 break;
1856 case 2:
1857 return cfi_spansion_write_words(bank, word, wordcount, address);
1858 break;
1859 default:
1860 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1861 break;
1862 }
1863
1864 return ERROR_FLASH_OPERATION_FAILED;
1865 }
1866
1867 int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1868 {
1869 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
1870 struct target *target = bank->target;
1871 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1872 uint32_t write_p, copy_p;
1873 int align; /* number of unaligned bytes */
1874 int blk_count; /* number of bus_width bytes for block copy */
1875 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1876 int i;
1877 int retval;
1878
1879 if (bank->target->state != TARGET_HALTED)
1880 {
1881 LOG_ERROR("Target not halted");
1882 return ERROR_TARGET_NOT_HALTED;
1883 }
1884
1885 if (offset + count > bank->size)
1886 return ERROR_FLASH_DST_OUT_OF_BANK;
1887
1888 if (cfi_info->qry[0] != 'Q')
1889 return ERROR_FLASH_BANK_NOT_PROBED;
1890
1891 /* start at the first byte of the first word (bus_width size) */
1892 write_p = address & ~(bank->bus_width - 1);
1893 if ((align = address - write_p) != 0)
1894 {
1895 LOG_INFO("Fixup %d unaligned head bytes", align);
1896
1897 for (i = 0; i < bank->bus_width; i++)
1898 current_word[i] = 0;
1899 copy_p = write_p;
1900
1901 /* copy bytes before the first write address */
1902 for (i = 0; i < align; ++i, ++copy_p)
1903 {
1904 uint8_t byte;
1905 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1906 {
1907 return retval;
1908 }
1909 cfi_add_byte(bank, current_word, byte);
1910 }
1911
1912 /* add bytes from the buffer */
1913 for (; (i < bank->bus_width) && (count > 0); i++)
1914 {
1915 cfi_add_byte(bank, current_word, *buffer++);
1916 count--;
1917 copy_p++;
1918 }
1919
1920 /* if the buffer is already finished, copy bytes after the last write address */
1921 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1922 {
1923 uint8_t byte;
1924 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1925 {
1926 return retval;
1927 }
1928 cfi_add_byte(bank, current_word, byte);
1929 }
1930
1931 retval = cfi_write_word(bank, current_word, write_p);
1932 if (retval != ERROR_OK)
1933 return retval;
1934 write_p = copy_p;
1935 }
1936
1937 /* handle blocks of bus_size aligned bytes */
1938 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1939 switch (cfi_info->pri_id)
1940 {
1941 /* try block writes (fails without working area) */
1942 case 1:
1943 case 3:
1944 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1945 break;
1946 case 2:
1947 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1948 break;
1949 default:
1950 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1951 retval = ERROR_FLASH_OPERATION_FAILED;
1952 break;
1953 }
1954 if (retval == ERROR_OK)
1955 {
1956 /* Increment pointers and decrease count on succesful block write */
1957 buffer += blk_count;
1958 write_p += blk_count;
1959 count -= blk_count;
1960 }
1961 else
1962 {
1963 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1964 {
1965 //adjust buffersize for chip width
1966 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1967 uint32_t buffermask = buffersize-1;
1968 uint32_t bufferwsize;
1969
1970 switch (bank->chip_width)
1971 {
1972 case 4 : bufferwsize = buffersize / 4; break;
1973 case 2 : bufferwsize = buffersize / 2; break;
1974 case 1 : bufferwsize = buffersize; break;
1975 default:
1976 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1977 return ERROR_FLASH_OPERATION_FAILED;
1978 }
1979
1980 bufferwsize/=(bank->bus_width / bank->chip_width);
1981
1982 /* fall back to memory writes */
1983 while (count >= (uint32_t)bank->bus_width)
1984 {
1985 int fallback;
1986 if ((write_p & 0xff) == 0)
1987 {
1988 LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
1989 }
1990 fallback = 1;
1991 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1992 {
1993 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1994 if (retval == ERROR_OK)
1995 {
1996 buffer += buffersize;
1997 write_p += buffersize;
1998 count -= buffersize;
1999 fallback = 0;
2000 }
2001 }
2002 /* try the slow way? */
2003 if (fallback)
2004 {
2005 for (i = 0; i < bank->bus_width; i++)
2006 current_word[i] = 0;
2007
2008 for (i = 0; i < bank->bus_width; i++)
2009 {
2010 cfi_add_byte(bank, current_word, *buffer++);
2011 }
2012
2013 retval = cfi_write_word(bank, current_word, write_p);
2014 if (retval != ERROR_OK)
2015 return retval;
2016
2017 write_p += bank->bus_width;
2018 count -= bank->bus_width;
2019 }
2020 }
2021 }
2022 else
2023 return retval;
2024 }
2025
2026 /* return to read array mode, so we can read from flash again for padding */
2027 cfi_command(bank, 0xf0, current_word);
2028 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2029 {
2030 return retval;
2031 }
2032 cfi_command(bank, 0xff, current_word);
2033 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2034 {
2035 return retval;
2036 }
2037
2038 /* handle unaligned tail bytes */
2039 if (count > 0)
2040 {
2041 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2042
2043 copy_p = write_p;
2044 for (i = 0; i < bank->bus_width; i++)
2045 current_word[i] = 0;
2046
2047 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2048 {
2049 cfi_add_byte(bank, current_word, *buffer++);
2050 count--;
2051 }
2052 for (; i < bank->bus_width; ++i, ++copy_p)
2053 {
2054 uint8_t byte;
2055 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2056 {
2057 return retval;
2058 }
2059 cfi_add_byte(bank, current_word, byte);
2060 }
2061 retval = cfi_write_word(bank, current_word, write_p);
2062 if (retval != ERROR_OK)
2063 return retval;
2064 }
2065
2066 /* return to read array mode */
2067 cfi_command(bank, 0xf0, current_word);
2068 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2069 {
2070 return retval;
2071 }
2072 cfi_command(bank, 0xff, current_word);
2073 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2074 }
2075
2076 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2077 {
2078 (void) param;
2079 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2080 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2081
2082 pri_ext->_reversed_geometry = 1;
2083 }
2084
2085 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2086 {
2087 int i;
2088 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2089 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2090 (void) param;
2091
2092 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2093 {
2094 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2095
2096 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2097 {
2098 int j = (cfi_info->num_erase_regions - 1) - i;
2099 uint32_t swap;
2100
2101 swap = cfi_info->erase_region_info[i];
2102 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2103 cfi_info->erase_region_info[j] = swap;
2104 }
2105 }
2106 }
2107
2108 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2109 {
2110 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2111 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2112 struct cfi_unlock_addresses *unlock_addresses = param;
2113
2114 pri_ext->_unlock1 = unlock_addresses->unlock1;
2115 pri_ext->_unlock2 = unlock_addresses->unlock2;
2116 }
2117
2118
2119 static int cfi_query_string(struct flash_bank *bank, int address)
2120 {
2121 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2122 struct target *target = bank->target;
2123 int retval;
2124 uint8_t command[8];
2125
2126 cfi_command(bank, 0x98, command);
2127 if ((retval = target_write_memory(target, flash_address(bank, 0, address), bank->bus_width, 1, command)) != ERROR_OK)
2128 {
2129 return retval;
2130 }
2131
2132 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2133 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2134 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2135
2136 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2137
2138 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2139 {
2140 cfi_command(bank, 0xf0, command);
2141 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2142 {
2143 return retval;
2144 }
2145 cfi_command(bank, 0xff, command);
2146 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2147 {
2148 return retval;
2149 }
2150 LOG_ERROR("Could not probe bank: no QRY");
2151 return ERROR_FLASH_BANK_INVALID;
2152 }
2153
2154 return ERROR_OK;
2155 }
2156
2157 static int cfi_probe(struct flash_bank *bank)
2158 {
2159 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2160 struct target *target = bank->target;
2161 uint8_t command[8];
2162 int num_sectors = 0;
2163 int i;
2164 int sector = 0;
2165 uint32_t unlock1 = 0x555;
2166 uint32_t unlock2 = 0x2aa;
2167 int retval;
2168
2169 if (bank->target->state != TARGET_HALTED)
2170 {
2171 LOG_ERROR("Target not halted");
2172 return ERROR_TARGET_NOT_HALTED;
2173 }
2174
2175 cfi_info->probed = 0;
2176
2177 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2178 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2179 */
2180 if (cfi_info->jedec_probe)
2181 {
2182 unlock1 = 0x5555;
2183 unlock2 = 0x2aaa;
2184 }
2185
2186 /* switch to read identifier codes mode ("AUTOSELECT") */
2187 cfi_command(bank, 0xaa, command);
2188 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2189 {
2190 return retval;
2191 }
2192 cfi_command(bank, 0x55, command);
2193 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2194 {
2195 return retval;
2196 }
2197 cfi_command(bank, 0x90, command);
2198 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2199 {
2200 return retval;
2201 }
2202
2203 if (bank->chip_width == 1)
2204 {
2205 uint8_t manufacturer, device_id;
2206 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2207 {
2208 return retval;
2209 }
2210 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2211 {
2212 return retval;
2213 }
2214 cfi_info->manufacturer = manufacturer;
2215 cfi_info->device_id = device_id;
2216 }
2217 else if (bank->chip_width == 2)
2218 {
2219 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2220 {
2221 return retval;
2222 }
2223 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
2224 {
2225 return retval;
2226 }
2227 }
2228
2229 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2230 /* switch back to read array mode */
2231 cfi_command(bank, 0xf0, command);
2232 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2233 {
2234 return retval;
2235 }
2236 cfi_command(bank, 0xff, command);
2237 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2238 {
2239 return retval;
2240 }
2241
2242 /* check device/manufacturer ID for known non-CFI flashes. */
2243 cfi_fixup_non_cfi(bank);
2244
2245 /* query only if this is a CFI compatible flash,
2246 * otherwise the relevant info has already been filled in
2247 */
2248 if (cfi_info->not_cfi == 0)
2249 {
2250 int retval;
2251
2252 /* enter CFI query mode
2253 * according to JEDEC Standard No. 68.01,
2254 * a single bus sequence with address = 0x55, data = 0x98 should put
2255 * the device into CFI query mode.
2256 *
2257 * SST flashes clearly violate this, and we will consider them incompatbile for now
2258 */
2259
2260 retval = cfi_query_string(bank, 0x55);
2261 if (retval != ERROR_OK)
2262 {
2263 /*
2264 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2265 * be harmless enough:
2266 *
2267 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2268 */
2269 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2270 retval = cfi_query_string(bank, 0x555);
2271 }
2272 if (retval != ERROR_OK)
2273 return retval;
2274
2275 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2276 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2277 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2278 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2279
2280 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2281
2282 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2283 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2284 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2285 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2286 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2287 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2288 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2289 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2290 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2291 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2292 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2293 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2294
2295 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2296 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2297 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2298 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2299 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2300 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2301 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2302 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2303 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2304 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2305 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2306
2307 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2308 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2309 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2310 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2311
2312 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2313
2314 if (cfi_info->num_erase_regions)
2315 {
2316 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2317 for (i = 0; i < cfi_info->num_erase_regions; i++)
2318 {
2319 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2320 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2321 i,
2322 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2323 (cfi_info->erase_region_info[i] >> 16) * 256);
2324 }
2325 }
2326 else
2327 {
2328 cfi_info->erase_region_info = NULL;
2329 }
2330
2331 /* We need to read the primary algorithm extended query table before calculating
2332 * the sector layout to be able to apply fixups
2333 */
2334 switch (cfi_info->pri_id)
2335 {
2336 /* Intel command set (standard and extended) */
2337 case 0x0001:
2338 case 0x0003:
2339 cfi_read_intel_pri_ext(bank);
2340 break;
2341 /* AMD/Spansion, Atmel, ... command set */
2342 case 0x0002:
2343 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2344 cfi_read_0002_pri_ext(bank);
2345 break;
2346 default:
2347 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2348 break;
2349 }
2350
2351 /* return to read array mode
2352 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2353 */
2354 cfi_command(bank, 0xf0, command);
2355 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2356 {
2357 return retval;
2358 }
2359 cfi_command(bank, 0xff, command);
2360 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2361 {
2362 return retval;
2363 }
2364 } /* end CFI case */
2365
2366 /* apply fixups depending on the primary command set */
2367 switch (cfi_info->pri_id)
2368 {
2369 /* Intel command set (standard and extended) */
2370 case 0x0001:
2371 case 0x0003:
2372 cfi_fixup(bank, cfi_0001_fixups);
2373 break;
2374 /* AMD/Spansion, Atmel, ... command set */
2375 case 0x0002:
2376 cfi_fixup(bank, cfi_0002_fixups);
2377 break;
2378 default:
2379 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2380 break;
2381 }
2382
2383 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2384 {
2385 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2386 }
2387
2388 if (cfi_info->num_erase_regions == 0)
2389 {
2390 /* a device might have only one erase block, spanning the whole device */
2391 bank->num_sectors = 1;
2392 bank->sectors = malloc(sizeof(struct flash_sector));
2393
2394 bank->sectors[sector].offset = 0x0;
2395 bank->sectors[sector].size = bank->size;
2396 bank->sectors[sector].is_erased = -1;
2397 bank->sectors[sector].is_protected = -1;
2398 }
2399 else
2400 {
2401 uint32_t offset = 0;
2402
2403 for (i = 0; i < cfi_info->num_erase_regions; i++)
2404 {
2405 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2406 }
2407
2408 bank->num_sectors = num_sectors;
2409 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2410
2411 for (i = 0; i < cfi_info->num_erase_regions; i++)
2412 {
2413 uint32_t j;
2414 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2415 {
2416 bank->sectors[sector].offset = offset;
2417 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2418 offset += bank->sectors[sector].size;
2419 bank->sectors[sector].is_erased = -1;
2420 bank->sectors[sector].is_protected = -1;
2421 sector++;
2422 }
2423 }
2424 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2425 {
2426 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2427 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2428 }
2429 }
2430
2431 cfi_info->probed = 1;
2432
2433 return ERROR_OK;
2434 }
2435
2436 static int cfi_auto_probe(struct flash_bank *bank)
2437 {
2438 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2439 if (cfi_info->probed)
2440 return ERROR_OK;
2441 return cfi_probe(bank);
2442 }
2443
2444
2445 static int cfi_intel_protect_check(struct flash_bank *bank)
2446 {
2447 int retval;
2448 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2449 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2450 struct target *target = bank->target;
2451 uint8_t command[CFI_MAX_BUS_WIDTH];
2452 int i;
2453
2454 /* check if block lock bits are supported on this device */
2455 if (!(pri_ext->blk_status_reg_mask & 0x1))
2456 return ERROR_FLASH_OPERATION_FAILED;
2457
2458 cfi_command(bank, 0x90, command);
2459 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2460 {
2461 return retval;
2462 }
2463
2464 for (i = 0; i < bank->num_sectors; i++)
2465 {
2466 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2467
2468 if (block_status & 1)
2469 bank->sectors[i].is_protected = 1;
2470 else
2471 bank->sectors[i].is_protected = 0;
2472 }
2473
2474 cfi_command(bank, 0xff, command);
2475 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2476 }
2477
2478 static int cfi_spansion_protect_check(struct flash_bank *bank)
2479 {
2480 int retval;
2481 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2482 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2483 struct target *target = bank->target;
2484 uint8_t command[8];
2485 int i;
2486
2487 cfi_command(bank, 0xaa, command);
2488 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2489 {
2490 return retval;
2491 }
2492
2493 cfi_command(bank, 0x55, command);
2494 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2495 {
2496 return retval;
2497 }
2498
2499 cfi_command(bank, 0x90, command);
2500 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2501 {
2502 return retval;
2503 }
2504
2505 for (i = 0; i < bank->num_sectors; i++)
2506 {
2507 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2508
2509 if (block_status & 1)
2510 bank->sectors[i].is_protected = 1;
2511 else
2512 bank->sectors[i].is_protected = 0;
2513 }
2514
2515 cfi_command(bank, 0xf0, command);
2516 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2517 }
2518
2519 static int cfi_protect_check(struct flash_bank *bank)
2520 {
2521 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2522
2523 if (bank->target->state != TARGET_HALTED)
2524 {
2525 LOG_ERROR("Target not halted");
2526 return ERROR_TARGET_NOT_HALTED;
2527 }
2528
2529 if (cfi_info->qry[0] != 'Q')
2530 return ERROR_FLASH_BANK_NOT_PROBED;
2531
2532 switch (cfi_info->pri_id)
2533 {
2534 case 1:
2535 case 3:
2536 return cfi_intel_protect_check(bank);
2537 break;
2538 case 2:
2539 return cfi_spansion_protect_check(bank);
2540 break;
2541 default:
2542 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2543 break;
2544 }
2545
2546 return ERROR_OK;
2547 }
2548
2549 static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2550 {
2551 int printed;
2552 struct cfi_flash_bank *cfi_info = cfi_bank_data(bank);
2553
2554 if (cfi_info->qry[0] == (char)-1)
2555 {
2556 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2557 return ERROR_OK;
2558 }
2559
2560 if (cfi_info->not_cfi == 0)
2561 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2562 else
2563 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2564 buf += printed;
2565 buf_size -= printed;
2566
2567 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2568 cfi_info->manufacturer, cfi_info->device_id);
2569 buf += printed;
2570 buf_size -= printed;
2571
2572 if (cfi_info->not_cfi == 0)
2573 {
2574 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2575 buf += printed;
2576 buf_size -= printed;
2577
2578 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2579 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2580 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2581 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2582 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2583 buf += printed;
2584 buf_size -= printed;
2585
2586 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2587 1 << cfi_info->word_write_timeout_typ,
2588 1 << cfi_info->buf_write_timeout_typ,
2589 1 << cfi_info->block_erase_timeout_typ,
2590 1 << cfi_info->chip_erase_timeout_typ);
2591 buf += printed;
2592 buf_size -= printed;
2593
2594 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2595 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2596 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2597 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2598 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2599 buf += printed;
2600 buf_size -= printed;
2601
2602 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2603 cfi_info->dev_size,
2604 cfi_info->interface_desc,
2605 1 << cfi_info->max_buf_write_size);
2606 buf += printed;
2607 buf_size -= printed;
2608
2609 switch (cfi_info->pri_id)
2610 {
2611 case 1:
2612 case 3:
2613 cfi_intel_info(bank, buf, buf_size);
2614 break;
2615 case 2:
2616 cfi_spansion_info(bank, buf, buf_size);
2617 break;
2618 default:
2619 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2620 break;
2621 }
2622 }
2623
2624 return ERROR_OK;
2625 }
2626
2627 FLASH_DRIVER(cfi, &cfi_flash_bank_command, NULL,
2628 .erase = &cfi_erase,
2629 .protect = &cfi_protect,
2630 .write = &cfi_write,
2631 .probe = &cfi_probe,
2632 .auto_probe = &cfi_auto_probe,
2633 .erase_check = &default_flash_blank_check,
2634 .protect_check = &cfi_protect_check,
2635 .info = &cfi_info,
2636 );
Zach's Unofficial Testing Repository