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nor: use common flash driver
[openocd/ztw.git] / src / flash / nor / tms470.c
blobc6edd9a690d2b391f5504d8c4378b0ab8f1f8c1e
1 /***************************************************************************
2 * Copyright (C) 2007,2008 by Christopher Kilgour *
3 * techie |_at_| whiterocker |_dot_| com *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "tms470.h"
25 #include "imp.h"
26
27
28 /* ----------------------------------------------------------------------
29 Internal Support, Helpers
30 ---------------------------------------------------------------------- */
31
32 const struct flash_sector TMS470R1A256_SECTORS[] = {
33 {0x00000000, 0x00002000, -1, -1},
34 {0x00002000, 0x00002000, -1, -1},
35 {0x00004000, 0x00002000, -1, -1},
36 {0x00006000, 0x00002000, -1, -1},
37 {0x00008000, 0x00008000, -1, -1},
38 {0x00010000, 0x00008000, -1, -1},
39 {0x00018000, 0x00008000, -1, -1},
40 {0x00020000, 0x00008000, -1, -1},
41 {0x00028000, 0x00008000, -1, -1},
42 {0x00030000, 0x00008000, -1, -1},
43 {0x00038000, 0x00002000, -1, -1},
44 {0x0003A000, 0x00002000, -1, -1},
45 {0x0003C000, 0x00002000, -1, -1},
46 {0x0003E000, 0x00002000, -1, -1},
47 };
48
49 #define TMS470R1A256_NUM_SECTORS \
50 ARRAY_SIZE(TMS470R1A256_SECTORS)
51
52 const struct flash_sector TMS470R1A288_BANK0_SECTORS[] = {
53 {0x00000000, 0x00002000, -1, -1},
54 {0x00002000, 0x00002000, -1, -1},
55 {0x00004000, 0x00002000, -1, -1},
56 {0x00006000, 0x00002000, -1, -1},
57 };
58
59 #define TMS470R1A288_BANK0_NUM_SECTORS \
60 ARRAY_SIZE(TMS470R1A288_BANK0_SECTORS)
61
62 const struct flash_sector TMS470R1A288_BANK1_SECTORS[] = {
63 {0x00040000, 0x00010000, -1, -1},
64 {0x00050000, 0x00010000, -1, -1},
65 {0x00060000, 0x00010000, -1, -1},
66 {0x00070000, 0x00010000, -1, -1},
67 };
68
69 #define TMS470R1A288_BANK1_NUM_SECTORS \
70 ARRAY_SIZE(TMS470R1A288_BANK1_SECTORS)
71
72 const struct flash_sector TMS470R1A384_BANK0_SECTORS[] = {
73 {0x00000000, 0x00002000, -1, -1},
74 {0x00002000, 0x00002000, -1, -1},
75 {0x00004000, 0x00004000, -1, -1},
76 {0x00008000, 0x00004000, -1, -1},
77 {0x0000C000, 0x00004000, -1, -1},
78 {0x00010000, 0x00004000, -1, -1},
79 {0x00014000, 0x00004000, -1, -1},
80 {0x00018000, 0x00002000, -1, -1},
81 {0x0001C000, 0x00002000, -1, -1},
82 {0x0001E000, 0x00002000, -1, -1},
83 };
84
85 #define TMS470R1A384_BANK0_NUM_SECTORS \
86 ARRAY_SIZE(TMS470R1A384_BANK0_SECTORS)
87
88 const struct flash_sector TMS470R1A384_BANK1_SECTORS[] = {
89 {0x00020000, 0x00008000, -1, -1},
90 {0x00028000, 0x00008000, -1, -1},
91 {0x00030000, 0x00008000, -1, -1},
92 {0x00038000, 0x00008000, -1, -1},
93 };
94
95 #define TMS470R1A384_BANK1_NUM_SECTORS \
96 ARRAY_SIZE(TMS470R1A384_BANK1_SECTORS)
97
98 const struct flash_sector TMS470R1A384_BANK2_SECTORS[] = {
99 {0x00040000, 0x00008000, -1, -1},
100 {0x00048000, 0x00008000, -1, -1},
101 {0x00050000, 0x00008000, -1, -1},
102 {0x00058000, 0x00008000, -1, -1},
103 };
104
105 #define TMS470R1A384_BANK2_NUM_SECTORS \
106 ARRAY_SIZE(TMS470R1A384_BANK2_SECTORS)
107
108 /* ---------------------------------------------------------------------- */
109
110 static struct tms470_flash_bank *tms470_bank_data(struct flash_bank *bank)
111 {
112 return (struct tms470_flash_bank *)flash_bank_data(bank);
113 }
114
115 static int tms470_read_part_info(struct flash_bank *bank)
116 {
117 struct tms470_flash_bank *tms470_info = tms470_bank_data(bank);
118 struct target *target = bank->target;
119 uint32_t device_ident_reg;
120 uint32_t silicon_version;
121 uint32_t technology_family;
122 uint32_t rom_flash;
123 uint32_t part_number;
124 char *part_name;
125
126 /* we shall not rely on the caller in this test, this function allocates memory,
127 thus and executing the code more than once may cause memory leak */
128 if (tms470_info->device_ident_reg)
129 return ERROR_OK;
130
131 /* read and parse the device identification register */
132 target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
133
134 LOG_INFO("device_ident_reg = 0x%08" PRIx32 "", device_ident_reg);
135
136 if ((device_ident_reg & 7) == 0)
137 {
138 LOG_WARNING("Cannot identify target as a TMS470 family.");
139 return ERROR_FLASH_OPERATION_FAILED;
140 }
141
142 silicon_version = (device_ident_reg >> 12) & 0xF;
143 technology_family = (device_ident_reg >> 11) & 1;
144 rom_flash = (device_ident_reg >> 10) & 1;
145 part_number = (device_ident_reg >> 3) & 0x7f;
146
147 /*
148 * If the part number is known, determine if the flash bank is valid
149 * based on the base address being within the known flash bank
150 * ranges. Then fixup/complete the remaining fields of the flash
151 * bank structure.
152 */
153 switch (part_number)
154 {
155 case 0x0a:
156 part_name = "TMS470R1A256";
157
158 if (bank->base >= 0x00040000)
159 {
160 LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".", part_name, bank->base);
161 return ERROR_FLASH_OPERATION_FAILED;
162 }
163 tms470_info->ordinal = 0;
164 bank->base = 0x00000000;
165 bank->size = 256 * 1024;
166 bank->num_sectors = TMS470R1A256_NUM_SECTORS;
167 bank->sectors = malloc(sizeof(TMS470R1A256_SECTORS));
168 if (!bank->sectors)
169 {
170 return ERROR_FLASH_OPERATION_FAILED;
171 }
172 (void)memcpy(bank->sectors, TMS470R1A256_SECTORS, sizeof(TMS470R1A256_SECTORS));
173 break;
174
175 case 0x2b:
176 part_name = "TMS470R1A288";
177
178 if (bank->base < 0x00008000)
179 {
180 tms470_info->ordinal = 0;
181 bank->base = 0x00000000;
182 bank->size = 32 * 1024;
183 bank->num_sectors = TMS470R1A288_BANK0_NUM_SECTORS;
184 bank->sectors = malloc(sizeof(TMS470R1A288_BANK0_SECTORS));
185 if (!bank->sectors)
186 {
187 return ERROR_FLASH_OPERATION_FAILED;
188 }
189 (void)memcpy(bank->sectors, TMS470R1A288_BANK0_SECTORS, sizeof(TMS470R1A288_BANK0_SECTORS));
190 }
191 else if ((bank->base >= 0x00040000) && (bank->base < 0x00080000))
192 {
193 tms470_info->ordinal = 1;
194 bank->base = 0x00040000;
195 bank->size = 256 * 1024;
196 bank->num_sectors = TMS470R1A288_BANK1_NUM_SECTORS;
197 bank->sectors = malloc(sizeof(TMS470R1A288_BANK1_SECTORS));
198 if (!bank->sectors)
199 {
200 return ERROR_FLASH_OPERATION_FAILED;
201 }
202 (void)memcpy(bank->sectors, TMS470R1A288_BANK1_SECTORS, sizeof(TMS470R1A288_BANK1_SECTORS));
203 }
204 else
205 {
206 LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".", part_name, bank->base);
207 return ERROR_FLASH_OPERATION_FAILED;
208 }
209 break;
210
211 case 0x2d:
212 part_name = "TMS470R1A384";
213
214 if (bank->base < 0x00020000)
215 {
216 tms470_info->ordinal = 0;
217 bank->base = 0x00000000;
218 bank->size = 128 * 1024;
219 bank->num_sectors = TMS470R1A384_BANK0_NUM_SECTORS;
220 bank->sectors = malloc(sizeof(TMS470R1A384_BANK0_SECTORS));
221 if (!bank->sectors)
222 {
223 return ERROR_FLASH_OPERATION_FAILED;
224 }
225 (void)memcpy(bank->sectors, TMS470R1A384_BANK0_SECTORS, sizeof(TMS470R1A384_BANK0_SECTORS));
226 }
227 else if ((bank->base >= 0x00020000) && (bank->base < 0x00040000))
228 {
229 tms470_info->ordinal = 1;
230 bank->base = 0x00020000;
231 bank->size = 128 * 1024;
232 bank->num_sectors = TMS470R1A384_BANK1_NUM_SECTORS;
233 bank->sectors = malloc(sizeof(TMS470R1A384_BANK1_SECTORS));
234 if (!bank->sectors)
235 {
236 return ERROR_FLASH_OPERATION_FAILED;
237 }
238 (void)memcpy(bank->sectors, TMS470R1A384_BANK1_SECTORS, sizeof(TMS470R1A384_BANK1_SECTORS));
239 }
240 else if ((bank->base >= 0x00040000) && (bank->base < 0x00060000))
241 {
242 tms470_info->ordinal = 2;
243 bank->base = 0x00040000;
244 bank->size = 128 * 1024;
245 bank->num_sectors = TMS470R1A384_BANK2_NUM_SECTORS;
246 bank->sectors = malloc(sizeof(TMS470R1A384_BANK2_SECTORS));
247 if (!bank->sectors)
248 {
249 return ERROR_FLASH_OPERATION_FAILED;
250 }
251 (void)memcpy(bank->sectors, TMS470R1A384_BANK2_SECTORS, sizeof(TMS470R1A384_BANK2_SECTORS));
252 }
253 else
254 {
255 LOG_ERROR("No %s flash bank contains base address 0x%08" PRIx32 ".", part_name, bank->base);
256 return ERROR_FLASH_OPERATION_FAILED;
257 }
258 break;
259
260 default:
261 LOG_WARNING("Could not identify part 0x%02x as a member of the TMS470 family.", (unsigned)part_number);
262 return ERROR_FLASH_OPERATION_FAILED;
263 }
264
265 /* turn off memory selects */
266 target_write_u32(target, 0xFFFFFFE4, 0x00000000);
267 target_write_u32(target, 0xFFFFFFE0, 0x00000000);
268
269 bank->chip_width = 32;
270 bank->bus_width = 32;
271
272 LOG_INFO("Identified %s, ver=%d, core=%s, nvmem=%s.",
273 part_name,
274 (int)(silicon_version),
275 (technology_family ? "1.8v" : "3.3v"),
276 (rom_flash ? "rom" : "flash"));
277
278 tms470_info->device_ident_reg = device_ident_reg;
279 tms470_info->silicon_version = silicon_version;
280 tms470_info->technology_family = technology_family;
281 tms470_info->rom_flash = rom_flash;
282 tms470_info->part_number = part_number;
283 tms470_info->part_name = part_name;
284
285 /*
286 * Disable reset on address access violation.
287 */
288 target_write_u32(target, 0xFFFFFFE0, 0x00004007);
289
290 return ERROR_OK;
291 }
292
293 /* ---------------------------------------------------------------------- */
294
295 static uint32_t keysSet = 0;
296 static uint32_t flashKeys[4];
297
298 COMMAND_HANDLER(tms470_handle_flash_keyset_command)
299 {
300 if (CMD_ARGC > 4)
301 {
302 command_print(CMD_CTX, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
303 return ERROR_INVALID_ARGUMENTS;
304 }
305 else if (CMD_ARGC == 4)
306 {
307 int i;
308
309 for (i = 0; i < 4; i++)
310 {
311 int start = (0 == strncmp(CMD_ARGV[i], "0x", 2)) ? 2 : 0;
312
313 if (1 != sscanf(&CMD_ARGV[i][start], "%" SCNx32 "", &flashKeys[i]))
314 {
315 command_print(CMD_CTX, "could not process flash key %s", CMD_ARGV[i]);
316 LOG_ERROR("could not process flash key %s", CMD_ARGV[i]);
317 return ERROR_INVALID_ARGUMENTS;
318 }
319 }
320
321 keysSet = 1;
322 }
323 else if (CMD_ARGC != 0)
324 {
325 command_print(CMD_CTX, "tms470 flash_keyset <key0> <key1> <key2> <key3>");
326 return ERROR_INVALID_ARGUMENTS;
327 }
328
329 if (keysSet)
330 {
331 command_print(CMD_CTX, "using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
332 flashKeys[0], flashKeys[1], flashKeys[2], flashKeys[3]);
333 }
334 else
335 {
336 command_print(CMD_CTX, "flash keys not set");
337 }
338
339 return ERROR_OK;
340 }
341
342 static const uint32_t FLASH_KEYS_ALL_ONES[] = { 0xFFFFFFFF, 0xFFFFFFFF,
343 0xFFFFFFFF, 0xFFFFFFFF,
344 };
345
346 static const uint32_t FLASH_KEYS_ALL_ZEROS[] = { 0x00000000, 0x00000000,
347 0x00000000, 0x00000000,
348 };
349
350 static const uint32_t FLASH_KEYS_MIX1[] = { 0xf0fff0ff, 0xf0fff0ff,
351 0xf0fff0ff, 0xf0fff0ff
352 };
353
354 static const uint32_t FLASH_KEYS_MIX2[] = { 0x0000ffff, 0x0000ffff,
355 0x0000ffff, 0x0000ffff
356 };
357
358 /* ---------------------------------------------------------------------- */
359
360 static int oscMHz = 12;
361
362 COMMAND_HANDLER(tms470_handle_osc_megahertz_command)
363 {
364 if (CMD_ARGC > 1)
365 {
366 command_print(CMD_CTX, "tms470 osc_megahertz <MHz>");
367 return ERROR_INVALID_ARGUMENTS;
368 }
369 else if (CMD_ARGC == 1)
370 {
371 sscanf(CMD_ARGV[0], "%d", &oscMHz);
372 }
373
374 if (oscMHz <= 0)
375 {
376 LOG_ERROR("osc_megahertz must be positive and non-zero!");
377 command_print(CMD_CTX, "osc_megahertz must be positive and non-zero!");
378 oscMHz = 12;
379 return ERROR_INVALID_ARGUMENTS;
380 }
381
382 command_print(CMD_CTX, "osc_megahertz=%d", oscMHz);
383
384 return ERROR_OK;
385 }
386
387 /* ---------------------------------------------------------------------- */
388
389 static int plldis = 0;
390
391 COMMAND_HANDLER(tms470_handle_plldis_command)
392 {
393 if (CMD_ARGC > 1)
394 {
395 command_print(CMD_CTX, "tms470 plldis <0 | 1>");
396 return ERROR_INVALID_ARGUMENTS;
397 }
398 else if (CMD_ARGC == 1)
399 {
400 sscanf(CMD_ARGV[0], "%d", &plldis);
401 plldis = plldis ? 1 : 0;
402 }
403
404 command_print(CMD_CTX, "plldis=%d", plldis);
405
406 return ERROR_OK;
407 }
408
409 /* ---------------------------------------------------------------------- */
410
411 static int tms470_check_flash_unlocked(struct target * target)
412 {
413 uint32_t fmbbusy;
414
415 target_read_u32(target, 0xFFE89C08, &fmbbusy);
416 LOG_INFO("tms470 fmbbusy = 0x%08" PRIx32 " -> %s", fmbbusy, fmbbusy & 0x8000 ? "unlocked" : "LOCKED");
417 return fmbbusy & 0x8000 ? ERROR_OK : ERROR_FLASH_OPERATION_FAILED;
418 }
419
420 /* ---------------------------------------------------------------------- */
421
422 static int tms470_try_flash_keys(struct target * target, const uint32_t * key_set)
423 {
424 uint32_t glbctrl, fmmstat;
425 int retval = ERROR_FLASH_OPERATION_FAILED;
426
427 /* set GLBCTRL.4 */
428 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
429 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
430
431 /* only perform the key match when 3VSTAT is clear */
432 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
433 if (!(fmmstat & 0x08))
434 {
435 unsigned i;
436 uint32_t fmbptr, fmbac2, orig_fmregopt;
437
438 target_write_u32(target, 0xFFE8BC04, fmmstat & ~0x07);
439
440 /* wait for pump ready */
441 do
442 {
443 target_read_u32(target, 0xFFE8A814, &fmbptr);
444 alive_sleep(1);
445 }
446 while (!(fmbptr & 0x0200));
447
448 /* force max wait states */
449 target_read_u32(target, 0xFFE88004, &fmbac2);
450 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
451
452 /* save current access mode, force normal read mode */
453 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
454 target_write_u32(target, 0xFFE89C00, 0x00);
455
456 for (i = 0; i < 4; i++)
457 {
458 uint32_t tmp;
459
460 /* There is no point displaying the value of tmp, it is
461 * filtered by the chip. The purpose of this read is to
462 * prime the unlocking logic rather than read out the value.
463 */
464 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
465
466 LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32 "", key_set[i]);
467 target_write_u32(target, 0xFFE89C0C, key_set[i]);
468 }
469
470 if (ERROR_OK == tms470_check_flash_unlocked(target))
471 {
472 /*
473 * There seems to be a side-effect of reading the FMPKEY
474 * register in that it re-enables the protection. So we
475 * re-enable it.
476 */
477 for (i = 0; i < 4; i++)
478 {
479 uint32_t tmp;
480
481 target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
482 target_write_u32(target, 0xFFE89C0C, key_set[i]);
483 }
484 retval = ERROR_OK;
485 }
486
487 /* restore settings */
488 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
489 target_write_u32(target, 0xFFE88004, fmbac2);
490 }
491
492 /* clear config bit */
493 target_write_u32(target, 0xFFFFFFDC, glbctrl);
494
495 return retval;
496 }
497
498 /* ---------------------------------------------------------------------- */
499
500 static int tms470_unlock_flash(struct flash_bank *bank)
501 {
502 struct target *target = bank->target;
503 const uint32_t *p_key_sets[5];
504 unsigned i, key_set_count;
505
506 if (keysSet)
507 {
508 key_set_count = 5;
509 p_key_sets[0] = flashKeys;
510 p_key_sets[1] = FLASH_KEYS_ALL_ONES;
511 p_key_sets[2] = FLASH_KEYS_ALL_ZEROS;
512 p_key_sets[3] = FLASH_KEYS_MIX1;
513 p_key_sets[4] = FLASH_KEYS_MIX2;
514 }
515 else
516 {
517 key_set_count = 4;
518 p_key_sets[0] = FLASH_KEYS_ALL_ONES;
519 p_key_sets[1] = FLASH_KEYS_ALL_ZEROS;
520 p_key_sets[2] = FLASH_KEYS_MIX1;
521 p_key_sets[3] = FLASH_KEYS_MIX2;
522 }
523
524 for (i = 0; i < key_set_count; i++)
525 {
526 if (tms470_try_flash_keys(target, p_key_sets[i]) == ERROR_OK)
527 {
528 LOG_INFO("tms470 flash is unlocked");
529 return ERROR_OK;
530 }
531 }
532
533 LOG_WARNING("tms470 could not unlock flash memory protection level 2");
534 return ERROR_FLASH_OPERATION_FAILED;
535 }
536
537 /* ---------------------------------------------------------------------- */
538
539 static int tms470_flash_initialize_internal_state_machine(struct flash_bank *bank)
540 {
541 uint32_t fmmac2, fmmac1, fmmaxep, k, delay, glbctrl, sysclk;
542 struct target *target = bank->target;
543 struct tms470_flash_bank *tms470_info = tms470_bank_data(bank);
544 int result = ERROR_OK;
545
546 /*
547 * Select the desired bank to be programmed by writing BANK[2:0] of
548 * FMMAC2.
549 */
550 target_read_u32(target, 0xFFE8BC04, &fmmac2);
551 fmmac2 &= ~0x0007;
552 fmmac2 |= (tms470_info->ordinal & 7);
553 target_write_u32(target, 0xFFE8BC04, fmmac2);
554 LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
555
556 /*
557 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
558 */
559 target_read_u32(target, 0xFFE8BC00, &fmmac1);
560 fmmac1 |= 0x8000;
561 target_write_u32(target, 0xFFE8BC00, fmmac1);
562 LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
563
564 /*
565 * FMTCREG = 0x2fc0;
566 */
567 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
568 LOG_DEBUG("set fmtcreg = 0x2fc0");
569
570 /*
571 * MAXPP = 50
572 */
573 target_write_u32(target, 0xFFE8A07C, 50);
574 LOG_DEBUG("set fmmaxpp = 50");
575
576 /*
577 * MAXCP = 0xf000 + 2000
578 */
579 target_write_u32(target, 0xFFE8A084, 0xf000 + 2000);
580 LOG_DEBUG("set fmmaxcp = 0x%04x", 0xf000 + 2000);
581
582 /*
583 * configure VHV
584 */
585 target_read_u32(target, 0xFFE8A080, &fmmaxep);
586 if (fmmaxep == 0xf000)
587 {
588 fmmaxep = 0xf000 + 4095;
589 target_write_u32(target, 0xFFE8A80C, 0x9964);
590 LOG_DEBUG("set fmptr3 = 0x9964");
591 }
592 else
593 {
594 fmmaxep = 0xa000 + 4095;
595 target_write_u32(target, 0xFFE8A80C, 0x9b64);
596 LOG_DEBUG("set fmptr3 = 0x9b64");
597 }
598 target_write_u32(target, 0xFFE8A080, fmmaxep);
599 LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
600
601 /*
602 * FMPTR4 = 0xa000
603 */
604 target_write_u32(target, 0xFFE8A810, 0xa000);
605 LOG_DEBUG("set fmptr4 = 0xa000");
606
607 /*
608 * FMPESETUP, delay parameter selected based on clock frequency.
609 *
610 * According to the TI App Note SPNU257 and flashing code, delay is
611 * int((sysclk(MHz) + 1) / 2), with a minimum of 5. The system
612 * clock is usually derived from the ZPLL module, and selected by
613 * the plldis global.
614 */
615 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
616 sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * oscMHz / (1 + (glbctrl & 7));
617 delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
618 target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
619 LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
620
621 /*
622 * FMPVEVACCESS, based on delay.
623 */
624 k = delay | (delay << 8);
625 target_write_u32(target, 0xFFE8A05C, k);
626 LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
627
628 /*
629 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
630 */
631 k <<= 1;
632 target_write_u32(target, 0xFFE8A034, k);
633 LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
634 target_write_u32(target, 0xFFE8A040, k);
635 LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
636 target_write_u32(target, 0xFFE8A024, k);
637 LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
638
639 /*
640 * FMCVACCESS, based on delay.
641 */
642 k = delay * 16;
643 target_write_u32(target, 0xFFE8A060, k);
644 LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
645
646 /*
647 * FMCSETUP, based on delay.
648 */
649 k = 0x3000 | delay * 20;
650 target_write_u32(target, 0xFFE8A020, k);
651 LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
652
653 /*
654 * FMEHOLD, based on delay.
655 */
656 k = (delay * 20) << 2;
657 target_write_u32(target, 0xFFE8A038, k);
658 LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
659
660 /*
661 * PWIDTH, CWIDTH, EWIDTH, based on delay.
662 */
663 target_write_u32(target, 0xFFE8A050, delay * 8);
664 LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
665 target_write_u32(target, 0xFFE8A058, delay * 1000);
666 LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
667 target_write_u32(target, 0xFFE8A054, delay * 5400);
668 LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
669
670 return result;
671 }
672
673 /* ---------------------------------------------------------------------- */
674
675 int tms470_flash_status(struct flash_bank *bank)
676 {
677 struct target *target = bank->target;
678 int result = ERROR_OK;
679 uint32_t fmmstat;
680
681 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
682 LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
683
684 if (fmmstat & 0x0080)
685 {
686 LOG_WARNING("tms470 flash command: erase still active after busy clear.");
687 result = ERROR_FLASH_OPERATION_FAILED;
688 }
689
690 if (fmmstat & 0x0040)
691 {
692 LOG_WARNING("tms470 flash command: program still active after busy clear.");
693 result = ERROR_FLASH_OPERATION_FAILED;
694 }
695
696 if (fmmstat & 0x0020)
697 {
698 LOG_WARNING("tms470 flash command: invalid data command.");
699 result = ERROR_FLASH_OPERATION_FAILED;
700 }
701
702 if (fmmstat & 0x0010)
703 {
704 LOG_WARNING("tms470 flash command: program, erase or validate sector failed.");
705 result = ERROR_FLASH_OPERATION_FAILED;
706 }
707
708 if (fmmstat & 0x0008)
709 {
710 LOG_WARNING("tms470 flash command: voltage instability detected.");
711 result = ERROR_FLASH_OPERATION_FAILED;
712 }
713
714 if (fmmstat & 0x0006)
715 {
716 LOG_WARNING("tms470 flash command: command suspend detected.");
717 result = ERROR_FLASH_OPERATION_FAILED;
718 }
719
720 if (fmmstat & 0x0001)
721 {
722 LOG_WARNING("tms470 flash command: sector was locked.");
723 result = ERROR_FLASH_OPERATION_FAILED;
724 }
725
726 return result;
727 }
728
729 /* ---------------------------------------------------------------------- */
730
731 static int tms470_erase_sector(struct flash_bank *bank, int sector)
732 {
733 uint32_t glbctrl, orig_fmregopt, fmbsea, fmbseb, fmmstat;
734 struct target *target = bank->target;
735 uint32_t flashAddr = bank->base + bank->sectors[sector].offset;
736 int result = ERROR_OK;
737
738 /*
739 * Set the bit GLBCTRL4 of the GLBCTRL register (in the System
740 * module) to enable writing to the flash registers }.
741 */
742 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
743 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
744 LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
745
746 /* Force normal read mode. */
747 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
748 target_write_u32(target, 0xFFE89C00, 0);
749 LOG_DEBUG("set fmregopt = 0x%08x", 0);
750
751 (void)tms470_flash_initialize_internal_state_machine(bank);
752
753 /*
754 * Select one or more bits in FMBSEA or FMBSEB to disable Level 1
755 * protection for the particular sector to be erased/written.
756 */
757 if (sector < 16)
758 {
759 target_read_u32(target, 0xFFE88008, &fmbsea);
760 target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
761 LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
762 }
763 else
764 {
765 target_read_u32(target, 0xFFE8800C, &fmbseb);
766 target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
767 LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
768 }
769 bank->sectors[sector].is_protected = 0;
770
771 /*
772 * clear status regiser, sent erase command, kickoff erase
773 */
774 target_write_u16(target, flashAddr, 0x0040);
775 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
776 target_write_u16(target, flashAddr, 0x0020);
777 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0020", flashAddr);
778 target_write_u16(target, flashAddr, 0xffff);
779 LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0xffff", flashAddr);
780
781 /*
782 * Monitor FMMSTAT, busy until clear, then check and other flags for
783 * ultimate result of the operation.
784 */
785 do
786 {
787 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
788 if (fmmstat & 0x0100)
789 {
790 alive_sleep(1);
791 }
792 }
793 while (fmmstat & 0x0100);
794
795 result = tms470_flash_status(bank);
796
797 if (sector < 16)
798 {
799 target_write_u32(target, 0xFFE88008, fmbsea);
800 LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
801 bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
802 }
803 else
804 {
805 target_write_u32(target, 0xFFE8800C, fmbseb);
806 LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
807 bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
808 }
809 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
810 LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
811 target_write_u32(target, 0xFFFFFFDC, glbctrl);
812 LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
813
814 if (result == ERROR_OK)
815 {
816 bank->sectors[sector].is_erased = 1;
817 }
818
819 return result;
820 }
821
822 /* ----------------------------------------------------------------------
823 Implementation of Flash Driver Interfaces
824 ---------------------------------------------------------------------- */
825
826 static const struct command_registration tms470_any_command_handlers[] = {
827 {
828 .name = "flash_keyset",
829 .handler = &tms470_handle_flash_keyset_command,
830 .mode = COMMAND_ANY,
831 .help = "tms470 flash_keyset <key0> <key1> <key2> <key3>",
832 },
833 {
834 .name = "osc_megahertz",
835 .handler = &tms470_handle_osc_megahertz_command,
836 .mode = COMMAND_ANY,
837 .help = "tms470 osc_megahertz <MHz>",
838 },
839 {
840 .name = "plldis",
841 .handler = &tms470_handle_plldis_command,
842 .mode = COMMAND_ANY,
843 .help = "tms470 plldis <0/1>",
844 },
845 COMMAND_REGISTRATION_DONE
846 };
847 static const struct command_registration tms470_command_handlers[] = {
848 {
849 .name = "tms470",
850 .mode = COMMAND_ANY,
851 .help = "TI tms470 flash command group",
852 .chain = tms470_any_command_handlers,
853 },
854 COMMAND_REGISTRATION_DONE
855 };
856
857 /* ---------------------------------------------------------------------- */
858
859 static int tms470_erase(struct flash_bank *bank, int first, int last)
860 {
861 struct tms470_flash_bank *tms470_info = tms470_bank_data(bank);
862 int sector, result = ERROR_OK;
863
864 if (bank->target->state != TARGET_HALTED)
865 {
866 LOG_ERROR("Target not halted");
867 return ERROR_TARGET_NOT_HALTED;
868 }
869
870 tms470_read_part_info(bank);
871
872 if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
873 {
874 LOG_ERROR("Sector range %d to %d invalid.", first, last);
875 return ERROR_FLASH_SECTOR_INVALID;
876 }
877
878 result = tms470_unlock_flash(bank);
879 if (result != ERROR_OK)
880 {
881 return result;
882 }
883
884 for (sector = first; sector <= last; sector++)
885 {
886 LOG_INFO("Erasing tms470 bank %d sector %d...", tms470_info->ordinal, sector);
887
888 result = tms470_erase_sector(bank, sector);
889
890 if (result != ERROR_OK)
891 {
892 LOG_ERROR("tms470 could not erase flash sector.");
893 break;
894 }
895 else
896 {
897 LOG_INFO("sector erased successfully.");
898 }
899 }
900
901 return result;
902 }
903
904 /* ---------------------------------------------------------------------- */
905
906 static int tms470_protect(struct flash_bank *bank, int set, int first, int last)
907 {
908 struct tms470_flash_bank *tms470_info = tms470_bank_data(bank);
909 struct target *target = bank->target;
910 uint32_t fmmac2, fmbsea, fmbseb;
911 int sector;
912
913 if (target->state != TARGET_HALTED)
914 {
915 LOG_ERROR("Target not halted");
916 return ERROR_TARGET_NOT_HALTED;
917 }
918
919 tms470_read_part_info(bank);
920
921 if ((first < 0) || (first >= bank->num_sectors) || (last < 0) || (last >= bank->num_sectors) || (first > last))
922 {
923 LOG_ERROR("Sector range %d to %d invalid.", first, last);
924 return ERROR_FLASH_SECTOR_INVALID;
925 }
926
927 /* enable the appropriate bank */
928 target_read_u32(target, 0xFFE8BC04, &fmmac2);
929 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
930
931 /* get the original sector proection flags for this bank */
932 target_read_u32(target, 0xFFE88008, &fmbsea);
933 target_read_u32(target, 0xFFE8800C, &fmbseb);
934
935 for (sector = 0; sector < bank->num_sectors; sector++)
936 {
937 if (sector < 16)
938 {
939 fmbsea = set ? fmbsea & ~(1 << sector) : fmbsea | (1 << sector);
940 bank->sectors[sector].is_protected = set ? 1 : 0;
941 }
942 else
943 {
944 fmbseb = set ? fmbseb & ~(1 << (sector - 16)) : fmbseb | (1 << (sector - 16));
945 bank->sectors[sector].is_protected = set ? 1 : 0;
946 }
947 }
948
949 /* update the protection bits */
950 target_write_u32(target, 0xFFE88008, fmbsea);
951 target_write_u32(target, 0xFFE8800C, fmbseb);
952
953 return ERROR_OK;
954 }
955
956 /* ---------------------------------------------------------------------- */
957
958 static int tms470_write(struct flash_bank *bank, uint8_t * buffer, uint32_t offset, uint32_t count)
959 {
960 struct target *target = bank->target;
961 uint32_t glbctrl, fmbac2, orig_fmregopt, fmbsea, fmbseb, fmmaxpp, fmmstat;
962 int result = ERROR_OK;
963 uint32_t i;
964
965 if (target->state != TARGET_HALTED)
966 {
967 LOG_ERROR("Target not halted");
968 return ERROR_TARGET_NOT_HALTED;
969 }
970
971 tms470_read_part_info(bank);
972
973 LOG_INFO("Writing %" PRId32 " bytes starting at 0x%08" PRIx32 "", count, bank->base + offset);
974
975 /* set GLBCTRL.4 */
976 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
977 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
978
979 (void)tms470_flash_initialize_internal_state_machine(bank);
980
981 /* force max wait states */
982 target_read_u32(target, 0xFFE88004, &fmbac2);
983 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
984
985 /* save current access mode, force normal read mode */
986 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
987 target_write_u32(target, 0xFFE89C00, 0x00);
988
989 /*
990 * Disable Level 1 protection for all sectors to be erased/written.
991 */
992 target_read_u32(target, 0xFFE88008, &fmbsea);
993 target_write_u32(target, 0xFFE88008, 0xffff);
994 target_read_u32(target, 0xFFE8800C, &fmbseb);
995 target_write_u32(target, 0xFFE8800C, 0xffff);
996
997 /* read MAXPP */
998 target_read_u32(target, 0xFFE8A07C, &fmmaxpp);
999
1000 for (i = 0; i < count; i += 2)
1001 {
1002 uint32_t addr = bank->base + offset + i;
1003 uint16_t word = (((uint16_t) buffer[i]) << 8) | (uint16_t) buffer[i + 1];
1004
1005 if (word != 0xffff)
1006 {
1007 LOG_INFO("writing 0x%04x at 0x%08" PRIx32 "", word, addr);
1008
1009 /* clear status register */
1010 target_write_u16(target, addr, 0x0040);
1011 /* program flash command */
1012 target_write_u16(target, addr, 0x0010);
1013 /* burn the 16-bit word (big-endian) */
1014 target_write_u16(target, addr, word);
1015
1016 /*
1017 * Monitor FMMSTAT, busy until clear, then check and other flags
1018 * for ultimate result of the operation.
1019 */
1020 do
1021 {
1022 target_read_u32(target, 0xFFE8BC0C, &fmmstat);
1023 if (fmmstat & 0x0100)
1024 {
1025 alive_sleep(1);
1026 }
1027 }
1028 while (fmmstat & 0x0100);
1029
1030 if (fmmstat & 0x3ff)
1031 {
1032 LOG_ERROR("fmstat = 0x%04" PRIx32 "", fmmstat);
1033 LOG_ERROR("Could not program word 0x%04x at address 0x%08" PRIx32 ".", word, addr);
1034 result = ERROR_FLASH_OPERATION_FAILED;
1035 break;
1036 }
1037 }
1038 else
1039 {
1040 LOG_INFO("skipping 0xffff at 0x%08" PRIx32 "", addr);
1041 }
1042 }
1043
1044 /* restore */
1045 target_write_u32(target, 0xFFE88008, fmbsea);
1046 target_write_u32(target, 0xFFE8800C, fmbseb);
1047 target_write_u32(target, 0xFFE88004, fmbac2);
1048 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
1049 target_write_u32(target, 0xFFFFFFDC, glbctrl);
1050
1051 return result;
1052 }
1053
1054 /* ---------------------------------------------------------------------- */
1055
1056 static int tms470_probe(struct flash_bank *bank)
1057 {
1058 if (bank->target->state != TARGET_HALTED)
1059 {
1060 LOG_WARNING("Cannot communicate... target not halted.");
1061 return ERROR_TARGET_NOT_HALTED;
1062 }
1063
1064 return tms470_read_part_info(bank);
1065 }
1066
1067 static int tms470_auto_probe(struct flash_bank *bank)
1068 {
1069 struct tms470_flash_bank *tms470_info = tms470_bank_data(bank);
1070
1071 if (tms470_info->device_ident_reg)
1072 return ERROR_OK;
1073 return tms470_probe(bank);
1074 }
1075
1076 /* ---------------------------------------------------------------------- */
1077
1078 static int tms470_erase_check(struct flash_bank *bank)
1079 {
1080 struct target *target = bank->target;
1081 struct tms470_flash_bank *tms470_info = tms470_bank_data(bank);
1082 int sector, result = ERROR_OK;
1083 uint32_t fmmac2, fmbac2, glbctrl, orig_fmregopt;
1084 static uint8_t buffer[64 * 1024];
1085
1086 if (target->state != TARGET_HALTED)
1087 {
1088 LOG_ERROR("Target not halted");
1089 return ERROR_TARGET_NOT_HALTED;
1090 }
1091
1092 if (!tms470_info->device_ident_reg)
1093 {
1094 tms470_read_part_info(bank);
1095 }
1096
1097 /* set GLBCTRL.4 */
1098 target_read_u32(target, 0xFFFFFFDC, &glbctrl);
1099 target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
1100
1101 /* save current access mode, force normal read mode */
1102 target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
1103 target_write_u32(target, 0xFFE89C00, 0x00);
1104
1105 /* enable the appropriate bank */
1106 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1107 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1108
1109 /* TCR = 0 */
1110 target_write_u32(target, 0xFFE8BC10, 0x2fc0);
1111
1112 /* clear TEZ in fmbrdy */
1113 target_write_u32(target, 0xFFE88010, 0x0b);
1114
1115 /* save current wait states, force max */
1116 target_read_u32(target, 0xFFE88004, &fmbac2);
1117 target_write_u32(target, 0xFFE88004, fmbac2 | 0xff);
1118
1119 /*
1120 * The TI primitives inspect the flash memory by reading one 32-bit
1121 * word at a time. Here we read an entire sector and inspect it in
1122 * an attempt to reduce the JTAG overhead.
1123 */
1124 for (sector = 0; sector < bank->num_sectors; sector++)
1125 {
1126 if (bank->sectors[sector].is_erased != 1)
1127 {
1128 uint32_t i, addr = bank->base + bank->sectors[sector].offset;
1129
1130 LOG_INFO("checking flash bank %d sector %d", tms470_info->ordinal, sector);
1131
1132 target_read_buffer(target, addr, bank->sectors[sector].size, buffer);
1133
1134 bank->sectors[sector].is_erased = 1;
1135 for (i = 0; i < bank->sectors[sector].size; i++)
1136 {
1137 if (buffer[i] != 0xff)
1138 {
1139 LOG_WARNING("tms470 bank %d, sector %d, not erased.", tms470_info->ordinal, sector);
1140 LOG_WARNING("at location 0x%08" PRIx32 ": flash data is 0x%02x.", addr + i, buffer[i]);
1141
1142 bank->sectors[sector].is_erased = 0;
1143 break;
1144 }
1145 }
1146 }
1147 if (bank->sectors[sector].is_erased != 1)
1148 {
1149 result = ERROR_FLASH_SECTOR_NOT_ERASED;
1150 break;
1151 }
1152 else
1153 {
1154 LOG_INFO("sector erased");
1155 }
1156 }
1157
1158 /* reset TEZ, wait states, read mode, GLBCTRL.4 */
1159 target_write_u32(target, 0xFFE88010, 0x0f);
1160 target_write_u32(target, 0xFFE88004, fmbac2);
1161 target_write_u32(target, 0xFFE89C00, orig_fmregopt);
1162 target_write_u32(target, 0xFFFFFFDC, glbctrl);
1163
1164 return result;
1165 }
1166
1167 /* ---------------------------------------------------------------------- */
1168
1169 static int tms470_protect_check(struct flash_bank *bank)
1170 {
1171 struct target *target = bank->target;
1172 struct tms470_flash_bank *tms470_info = tms470_bank_data(bank);
1173 int sector, result = ERROR_OK;
1174 uint32_t fmmac2, fmbsea, fmbseb;
1175
1176 if (target->state != TARGET_HALTED)
1177 {
1178 LOG_ERROR("Target not halted");
1179 return ERROR_TARGET_NOT_HALTED;
1180 }
1181
1182 if (!tms470_info->device_ident_reg)
1183 {
1184 tms470_read_part_info(bank);
1185 }
1186
1187 /* enable the appropriate bank */
1188 target_read_u32(target, 0xFFE8BC04, &fmmac2);
1189 target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
1190
1191 target_read_u32(target, 0xFFE88008, &fmbsea);
1192 target_read_u32(target, 0xFFE8800C, &fmbseb);
1193
1194 for (sector = 0; sector < bank->num_sectors; sector++)
1195 {
1196 int protected;
1197
1198 if (sector < 16)
1199 {
1200 protected = fmbsea & (1 << sector) ? 0 : 1;
1201 bank->sectors[sector].is_protected = protected;
1202 }
1203 else
1204 {
1205 protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
1206 bank->sectors[sector].is_protected = protected;
1207 }
1208
1209 LOG_DEBUG("bank %d sector %d is %s", tms470_info->ordinal, sector, protected ? "protected" : "not protected");
1210 }
1211
1212 return result;
1213 }
1214
1215 /* ---------------------------------------------------------------------- */
1216
1217 static int tms470_info(struct flash_bank *bank, char *buf, int buf_size)
1218 {
1219 int used = 0;
1220 struct tms470_flash_bank *tms470_info = tms470_bank_data(bank);
1221
1222 if (!tms470_info->device_ident_reg)
1223 {
1224 tms470_read_part_info(bank);
1225 }
1226
1227 if (!tms470_info->device_ident_reg)
1228 {
1229 (void)snprintf(buf, buf_size, "Cannot identify target as a TMS470\n");
1230 return ERROR_FLASH_OPERATION_FAILED;
1231 }
1232
1233 used += snprintf(buf, buf_size, "\ntms470 information: Chip is %s\n", tms470_info->part_name);
1234 buf += used;
1235 buf_size -= used;
1236
1237 used += snprintf(buf, buf_size, "Flash protection level 2 is %s\n", tms470_check_flash_unlocked(bank->target) == ERROR_OK ? "disabled" : "enabled");
1238 buf += used;
1239 buf_size -= used;
1240
1241 return ERROR_OK;
1242 }
1243
1244 /* ---------------------------------------------------------------------- */
1245
1246 /*
1247 * flash bank tms470 <base> <size> <chip_width> <bus_width> <target>
1248 * [options...]
1249 */
1250
1251 FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command)
1252 {
1253 struct flash_bank *bank = flash_bank_from_object(object);
1254 void *data = calloc(1, sizeof(struct tms470_flash_bank));
1255 if (NULL == data)
1256 return ERROR_FLASH_OPERATION_FAILED;
1257
1258 set_flash_bank_data(bank, data);
1259 return ERROR_OK;
1260 }
1261
1262 FLASH_DRIVER(tms470, &tms470_flash_bank_command, tms470_command_handlers,
1263 .erase = &tms470_erase,
1264 .protect = &tms470_protect,
1265 .write = &tms470_write,
1266 .probe = &tms470_probe,
1267 .auto_probe = &tms470_auto_probe,
1268 .erase_check = &tms470_erase_check,
1269 .protect_check = &tms470_protect_check,
1270 .info = &tms470_info,
1271 );
Zach's Unofficial Testing Repository