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nor: use common flash driver
[openocd/ztw.git] / src / flash / nor / str9x.c
blobc46c02d1eaf6768124c89d7f038a4fe8fed2c5ec
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "imp.h"
31 #include "str9x.h"
32 #include <target/arm966e.h>
33 #include <target/algorithm.h>
34
35
36 static uint32_t bank1start = 0x00080000;
37
38 static struct str9x_flash_bank *str9x_bank_data(struct flash_bank *bank)
39 {
40 return (struct str9x_flash_bank *)flash_bank_data(bank);
41 }
42
43 static int str9x_build_block_list(struct flash_bank *bank)
44 {
45 struct str9x_flash_bank *str9x_info = str9x_bank_data(bank);
46
47 int i;
48 int num_sectors;
49 int b0_sectors = 0, b1_sectors = 0;
50 uint32_t offset = 0;
51
52 /* set if we have large flash str9 */
53 str9x_info->variant = 0;
54 str9x_info->bank1 = 0;
55
56 switch (bank->size)
57 {
58 case (256 * 1024):
59 b0_sectors = 4;
60 break;
61 case (512 * 1024):
62 b0_sectors = 8;
63 break;
64 case (1024 * 1024):
65 bank1start = 0x00100000;
66 str9x_info->variant = 1;
67 b0_sectors = 16;
68 break;
69 case (2048 * 1024):
70 bank1start = 0x00200000;
71 str9x_info->variant = 1;
72 b0_sectors = 32;
73 break;
74 case (128 * 1024):
75 str9x_info->variant = 1;
76 str9x_info->bank1 = 1;
77 b1_sectors = 8;
78 bank1start = bank->base;
79 break;
80 case (32 * 1024):
81 str9x_info->bank1 = 1;
82 b1_sectors = 4;
83 bank1start = bank->base;
84 break;
85 default:
86 LOG_ERROR("BUG: unknown bank->size encountered");
87 exit(-1);
88 }
89
90 num_sectors = b0_sectors + b1_sectors;
91
92 bank->num_sectors = num_sectors;
93 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
94 str9x_info->sector_bits = malloc(sizeof(uint32_t) * num_sectors);
95
96 num_sectors = 0;
97
98 for (i = 0; i < b0_sectors; i++)
99 {
100 bank->sectors[num_sectors].offset = offset;
101 bank->sectors[num_sectors].size = 0x10000;
102 offset += bank->sectors[i].size;
103 bank->sectors[num_sectors].is_erased = -1;
104 bank->sectors[num_sectors].is_protected = 1;
105 str9x_info->sector_bits[num_sectors++] = (1 << i);
106 }
107
108 for (i = 0; i < b1_sectors; i++)
109 {
110 bank->sectors[num_sectors].offset = offset;
111 bank->sectors[num_sectors].size = str9x_info->variant == 0 ? 0x2000 : 0x4000;
112 offset += bank->sectors[i].size;
113 bank->sectors[num_sectors].is_erased = -1;
114 bank->sectors[num_sectors].is_protected = 1;
115 if (str9x_info->variant)
116 str9x_info->sector_bits[num_sectors++] = (1 << i);
117 else
118 str9x_info->sector_bits[num_sectors++] = (1 << (i + 8));
119 }
120
121 return ERROR_OK;
122 }
123
124 /* flash bank str9x <base> <size> 0 0 <target#>
125 */
126 FLASH_BANK_COMMAND_HANDLER(str9x_flash_bank_command)
127 {
128 struct str9x_flash_bank *str9x_info;
129
130 if (CMD_ARGC < 6)
131 {
132 LOG_WARNING("incomplete flash_bank str9x configuration");
133 return ERROR_FLASH_BANK_INVALID;
134 }
135
136 str9x_info = malloc(sizeof(struct str9x_flash_bank));
137 struct flash_bank *bank = flash_bank_from_object(object);
138 set_flash_bank_data(bank, str9x_info);
139
140 str9x_build_block_list(bank);
141
142 str9x_info->write_algorithm = NULL;
143
144 return ERROR_OK;
145 }
146
147 static int str9x_protect_check(struct flash_bank *bank)
148 {
149 int retval;
150 struct str9x_flash_bank *str9x_info = str9x_bank_data(bank);
151 struct target *target = bank->target;
152
153 int i;
154 uint32_t adr;
155 uint32_t status = 0;
156 uint16_t hstatus = 0;
157
158 if (bank->target->state != TARGET_HALTED)
159 {
160 LOG_ERROR("Target not halted");
161 return ERROR_TARGET_NOT_HALTED;
162 }
163
164 /* read level one protection */
165
166 if (str9x_info->variant)
167 {
168 if (str9x_info->bank1)
169 {
170 adr = bank1start + 0x18;
171 if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
172 {
173 return retval;
174 }
175 if ((retval = target_read_u16(target, adr, &hstatus)) != ERROR_OK)
176 {
177 return retval;
178 }
179 status = hstatus;
180 }
181 else
182 {
183 adr = bank1start + 0x14;
184 if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
185 {
186 return retval;
187 }
188 if ((retval = target_read_u32(target, adr, &status)) != ERROR_OK)
189 {
190 return retval;
191 }
192 }
193 }
194 else
195 {
196 adr = bank1start + 0x10;
197 if ((retval = target_write_u16(target, adr, 0x90)) != ERROR_OK)
198 {
199 return retval;
200 }
201 if ((retval = target_read_u16(target, adr, &hstatus)) != ERROR_OK)
202 {
203 return retval;
204 }
205 status = hstatus;
206 }
207
208 /* read array command */
209 if ((retval = target_write_u16(target, adr, 0xFF)) != ERROR_OK)
210 {
211 return retval;
212 }
213
214 for (i = 0; i < bank->num_sectors; i++)
215 {
216 if (status & str9x_info->sector_bits[i])
217 bank->sectors[i].is_protected = 1;
218 else
219 bank->sectors[i].is_protected = 0;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int str9x_erase(struct flash_bank *bank, int first, int last)
226 {
227 struct target *target = bank->target;
228 int i;
229 uint32_t adr;
230 uint8_t status;
231 uint8_t erase_cmd;
232
233 if (bank->target->state != TARGET_HALTED)
234 {
235 LOG_ERROR("Target not halted");
236 return ERROR_TARGET_NOT_HALTED;
237 }
238
239 /* Check if we erase whole bank */
240 if ((first == 0) && (last == (bank->num_sectors - 1)))
241 {
242 /* Optimize to run erase bank command instead of sector */
243 erase_cmd = 0x80;
244 }
245 else
246 {
247 /* Erase sector command */
248 erase_cmd = 0x20;
249 }
250
251 for (i = first; i <= last; i++)
252 {
253 int retval;
254 adr = bank->base + bank->sectors[i].offset;
255
256 /* erase sectors */
257 if ((retval = target_write_u16(target, adr, erase_cmd)) != ERROR_OK)
258 {
259 return retval;
260 }
261 if ((retval = target_write_u16(target, adr, 0xD0)) != ERROR_OK)
262 {
263 return retval;
264 }
265
266 /* get status */
267 if ((retval = target_write_u16(target, adr, 0x70)) != ERROR_OK)
268 {
269 return retval;
270 }
271
272 int timeout;
273 for (timeout = 0; timeout < 1000; timeout++) {
274 if ((retval = target_read_u8(target, adr, &status)) != ERROR_OK)
275 {
276 return retval;
277 }
278 if (status & 0x80)
279 break;
280 alive_sleep(1);
281 }
282 if (timeout == 1000)
283 {
284 LOG_ERROR("erase timed out");
285 return ERROR_FAIL;
286 }
287
288 /* clear status, also clear read array */
289 if ((retval = target_write_u16(target, adr, 0x50)) != ERROR_OK)
290 {
291 return retval;
292 }
293
294 /* read array command */
295 if ((retval = target_write_u16(target, adr, 0xFF)) != ERROR_OK)
296 {
297 return retval;
298 }
299
300 if (status & 0x22)
301 {
302 LOG_ERROR("error erasing flash bank, status: 0x%x", status);
303 return ERROR_FLASH_OPERATION_FAILED;
304 }
305
306 /* If we ran erase bank command, we are finished */
307 if (erase_cmd == 0x80)
308 break;
309 }
310
311 for (i = first; i <= last; i++)
312 bank->sectors[i].is_erased = 1;
313
314 return ERROR_OK;
315 }
316
317 static int str9x_protect(struct flash_bank *bank,
318 int set, int first, int last)
319 {
320 struct target *target = bank->target;
321 int i;
322 uint32_t adr;
323 uint8_t status;
324
325 if (bank->target->state != TARGET_HALTED)
326 {
327 LOG_ERROR("Target not halted");
328 return ERROR_TARGET_NOT_HALTED;
329 }
330
331 for (i = first; i <= last; i++)
332 {
333 /* Level One Protection */
334
335 adr = bank->base + bank->sectors[i].offset;
336
337 target_write_u16(target, adr, 0x60);
338 if (set)
339 target_write_u16(target, adr, 0x01);
340 else
341 target_write_u16(target, adr, 0xD0);
342
343 /* query status */
344 target_read_u8(target, adr, &status);
345
346 /* clear status, also clear read array */
347 target_write_u16(target, adr, 0x50);
348
349 /* read array command */
350 target_write_u16(target, adr, 0xFF);
351 }
352
353 return ERROR_OK;
354 }
355
356 static int str9x_write_block(struct flash_bank *bank,
357 uint8_t *buffer, uint32_t offset, uint32_t count)
358 {
359 struct str9x_flash_bank *str9x_info = str9x_bank_data(bank);
360 struct target *target = bank->target;
361 uint32_t buffer_size = 8192;
362 struct working_area *source;
363 uint32_t address = bank->base + offset;
364 struct reg_param reg_params[4];
365 struct arm_algorithm armv4_5_info;
366 int retval = ERROR_OK;
367
368 uint32_t str9x_flash_write_code[] = {
369 /* write: */
370 0xe3c14003, /* bic r4, r1, #3 */
371 0xe3a03040, /* mov r3, #0x40 */
372 0xe1c430b0, /* strh r3, [r4, #0] */
373 0xe0d030b2, /* ldrh r3, [r0], #2 */
374 0xe0c130b2, /* strh r3, [r1], #2 */
375 0xe3a03070, /* mov r3, #0x70 */
376 0xe1c430b0, /* strh r3, [r4, #0] */
377 /* busy: */
378 0xe5d43000, /* ldrb r3, [r4, #0] */
379 0xe3130080, /* tst r3, #0x80 */
380 0x0afffffc, /* beq busy */
381 0xe3a05050, /* mov r5, #0x50 */
382 0xe1c450b0, /* strh r5, [r4, #0] */
383 0xe3a050ff, /* mov r5, #0xFF */
384 0xe1c450b0, /* strh r5, [r4, #0] */
385 0xe3130012, /* tst r3, #0x12 */
386 0x1a000001, /* bne exit */
387 0xe2522001, /* subs r2, r2, #1 */
388 0x1affffed, /* bne write */
389 /* exit: */
390 0xeafffffe, /* b exit */
391 };
392
393 /* flash write code */
394 if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)
395 {
396 LOG_WARNING("no working area available, can't do block memory writes");
397 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
398 };
399
400 target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (uint8_t*)str9x_flash_write_code);
401
402 /* memory buffer */
403 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
404 {
405 buffer_size /= 2;
406 if (buffer_size <= 256)
407 {
408 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
409 if (str9x_info->write_algorithm)
410 target_free_working_area(target, str9x_info->write_algorithm);
411
412 LOG_WARNING("no large enough working area available, can't do block memory writes");
413 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
414 }
415 }
416
417 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
418 armv4_5_info.core_mode = ARM_MODE_SVC;
419 armv4_5_info.core_state = ARM_STATE_ARM;
420
421 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
422 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
423 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
424 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
425
426 while (count > 0)
427 {
428 uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
429
430 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
431
432 buf_set_u32(reg_params[0].value, 0, 32, source->address);
433 buf_set_u32(reg_params[1].value, 0, 32, address);
434 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
435
436 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
437 {
438 LOG_ERROR("error executing str9x flash write algorithm");
439 retval = ERROR_FLASH_OPERATION_FAILED;
440 break;
441 }
442
443 if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
444 {
445 retval = ERROR_FLASH_OPERATION_FAILED;
446 break;
447 }
448
449 buffer += thisrun_count * 2;
450 address += thisrun_count * 2;
451 count -= thisrun_count;
452 }
453
454 target_free_working_area(target, source);
455 target_free_working_area(target, str9x_info->write_algorithm);
456
457 destroy_reg_param(&reg_params[0]);
458 destroy_reg_param(&reg_params[1]);
459 destroy_reg_param(&reg_params[2]);
460 destroy_reg_param(&reg_params[3]);
461
462 return retval;
463 }
464
465 static int str9x_write(struct flash_bank *bank,
466 uint8_t *buffer, uint32_t offset, uint32_t count)
467 {
468 struct target *target = bank->target;
469 uint32_t words_remaining = (count / 2);
470 uint32_t bytes_remaining = (count & 0x00000001);
471 uint32_t address = bank->base + offset;
472 uint32_t bytes_written = 0;
473 uint8_t status;
474 int retval;
475 uint32_t check_address = offset;
476 uint32_t bank_adr;
477 int i;
478
479 if (bank->target->state != TARGET_HALTED)
480 {
481 LOG_ERROR("Target not halted");
482 return ERROR_TARGET_NOT_HALTED;
483 }
484
485 if (offset & 0x1)
486 {
487 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
488 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
489 }
490
491 for (i = 0; i < bank->num_sectors; i++)
492 {
493 uint32_t sec_start = bank->sectors[i].offset;
494 uint32_t sec_end = sec_start + bank->sectors[i].size;
495
496 /* check if destination falls within the current sector */
497 if ((check_address >= sec_start) && (check_address < sec_end))
498 {
499 /* check if destination ends in the current sector */
500 if (offset + count < sec_end)
501 check_address = offset + count;
502 else
503 check_address = sec_end;
504 }
505 }
506
507 if (check_address != offset + count)
508 return ERROR_FLASH_DST_OUT_OF_BANK;
509
510 /* multiple half words (2-byte) to be programmed? */
511 if (words_remaining > 0)
512 {
513 /* try using a block write */
514 if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
515 {
516 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
517 {
518 /* if block write failed (no sufficient working area),
519 * we use normal (slow) single dword accesses */
520 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
521 }
522 else if (retval == ERROR_FLASH_OPERATION_FAILED)
523 {
524 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
525 return ERROR_FLASH_OPERATION_FAILED;
526 }
527 }
528 else
529 {
530 buffer += words_remaining * 2;
531 address += words_remaining * 2;
532 words_remaining = 0;
533 }
534 }
535
536 while (words_remaining > 0)
537 {
538 bank_adr = address & ~0x03;
539
540 /* write data command */
541 target_write_u16(target, bank_adr, 0x40);
542 target_write_memory(target, address, 2, 1, buffer + bytes_written);
543
544 /* get status command */
545 target_write_u16(target, bank_adr, 0x70);
546
547 int timeout;
548 for (timeout = 0; timeout < 1000; timeout++)
549 {
550 target_read_u8(target, bank_adr, &status);
551 if (status & 0x80)
552 break;
553 alive_sleep(1);
554 }
555 if (timeout == 1000)
556 {
557 LOG_ERROR("write timed out");
558 return ERROR_FAIL;
559 }
560
561 /* clear status reg and read array */
562 target_write_u16(target, bank_adr, 0x50);
563 target_write_u16(target, bank_adr, 0xFF);
564
565 if (status & 0x10)
566 return ERROR_FLASH_OPERATION_FAILED;
567 else if (status & 0x02)
568 return ERROR_FLASH_OPERATION_FAILED;
569
570 bytes_written += 2;
571 words_remaining--;
572 address += 2;
573 }
574
575 if (bytes_remaining)
576 {
577 uint8_t last_halfword[2] = {0xff, 0xff};
578 int i = 0;
579
580 while (bytes_remaining > 0)
581 {
582 last_halfword[i++] = *(buffer + bytes_written);
583 bytes_remaining--;
584 bytes_written++;
585 }
586
587 bank_adr = address & ~0x03;
588
589 /* write data command */
590 target_write_u16(target, bank_adr, 0x40);
591 target_write_memory(target, address, 2, 1, last_halfword);
592
593 /* query status command */
594 target_write_u16(target, bank_adr, 0x70);
595
596 int timeout;
597 for (timeout = 0; timeout < 1000; timeout++)
598 {
599 target_read_u8(target, bank_adr, &status);
600 if (status & 0x80)
601 break;
602 alive_sleep(1);
603 }
604 if (timeout == 1000)
605 {
606 LOG_ERROR("write timed out");
607 return ERROR_FAIL;
608 }
609
610 /* clear status reg and read array */
611 target_write_u16(target, bank_adr, 0x50);
612 target_write_u16(target, bank_adr, 0xFF);
613
614 if (status & 0x10)
615 return ERROR_FLASH_OPERATION_FAILED;
616 else if (status & 0x02)
617 return ERROR_FLASH_OPERATION_FAILED;
618 }
619
620 return ERROR_OK;
621 }
622
623 static int str9x_probe(struct flash_bank *bank)
624 {
625 return ERROR_OK;
626 }
627
628 #if 0
629 COMMAND_HANDLER(str9x_handle_part_id_command)
630 {
631 return ERROR_OK;
632 }
633 #endif
634
635 static int str9x_info(struct flash_bank *bank, char *buf, int buf_size)
636 {
637 snprintf(buf, buf_size, "str9x flash driver info");
638 return ERROR_OK;
639 }
640
641 COMMAND_HANDLER(str9x_handle_flash_config_command)
642 {
643 struct str9x_flash_bank *str9x_info;
644 struct target *target = NULL;
645
646 if (CMD_ARGC < 5)
647 {
648 return ERROR_COMMAND_SYNTAX_ERROR;
649 }
650
651 struct flash_bank *bank;
652 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
653 if (ERROR_OK != retval)
654 return retval;
655
656 uint32_t bbsr, nbbsr, bbadr, nbbadr;
657 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], bbsr);
658 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], nbbsr);
659 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], bbadr);
660 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], nbbadr);
661
662 str9x_info = str9x_bank_data(bank);
663
664 target = bank->target;
665
666 if (bank->target->state != TARGET_HALTED)
667 {
668 LOG_ERROR("Target not halted");
669 return ERROR_TARGET_NOT_HALTED;
670 }
671
672 /* config flash controller */
673 target_write_u32(target, FLASH_BBSR, bbsr);
674 target_write_u32(target, FLASH_NBBSR, nbbsr);
675 target_write_u32(target, FLASH_BBADR, bbadr >> 2);
676 target_write_u32(target, FLASH_NBBADR, nbbadr >> 2);
677
678 /* set bit 18 instruction TCM order as per flash programming manual */
679 arm966e_write_cp15(target, 62, 0x40000);
680
681 /* enable flash bank 1 */
682 target_write_u32(target, FLASH_CR, 0x18);
683 return ERROR_OK;
684 }
685
686 static const struct command_registration str9x_config_command_handlers[] = {
687 {
688 .name = "disable_jtag",
689 .handler = &str9x_handle_flash_config_command,
690 .mode = COMMAND_EXEC,
691 .help = "configure str9x flash controller",
692 .usage = "<bank_id> <BBSR> <NBBSR> <BBADR> <NBBADR>",
693 },
694 COMMAND_REGISTRATION_DONE
695 };
696 static const struct command_registration str9x_command_handlers[] = {
697 {
698 .name = "str9x",
699 .mode = COMMAND_ANY,
700 .help = "str9x flash command group",
701 .chain = str9x_config_command_handlers,
702 },
703 COMMAND_REGISTRATION_DONE
704 };
705
706 FLASH_DRIVER(str9x, &str9x_flash_bank_command, str9x_command_handlers,
707 .erase = &str9x_erase,
708 .protect = &str9x_protect,
709 .write = &str9x_write,
710 .probe = &str9x_probe,
711 .auto_probe = &str9x_probe,
712 .erase_check = &default_flash_blank_check,
713 .protect_check = &str9x_protect_check,
714 .info = &str9x_info,
715 );
Zach's Unofficial Testing Repository