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nor: use common flash driver
[openocd/ztw.git] / src / flash / nor / stm32x.c
blob636d161a3df36d64509cc1de4e5a4c483e7b001e
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "imp.h"
28 #include "stm32x.h"
29 #include <helper/binarybuffer.h>
30 #include <target/algorithm.h>
31 #include <target/armv7m.h>
32
33
34 static int stm32x_mass_erase(struct flash_bank *bank);
35
36 /* flash bank stm32x <base> <size> 0 0 <target#>
37 */
38 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
39 {
40 struct stm32x_flash_bank *stm32x_info;
41
42 if (CMD_ARGC < 6)
43 {
44 LOG_WARNING("incomplete flash_bank stm32x configuration");
45 return ERROR_FLASH_BANK_INVALID;
46 }
47
48 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
49
50 struct flash_bank *bank = flash_bank_from_object(object);
51 set_flash_bank_data(bank, stm32x_info);
52
53 stm32x_info->write_algorithm = NULL;
54 stm32x_info->probed = 0;
55
56 return ERROR_OK;
57 }
58
59 static struct stm32x_flash_bank *stm32x_bank_data(struct flash_bank *bank)
60 {
61 return (struct stm32x_flash_bank *)flash_bank_data(bank);
62 }
63
64 static uint32_t stm32x_get_flash_status(struct flash_bank *bank)
65 {
66 struct target *target = bank->target;
67 uint32_t status;
68
69 target_read_u32(target, STM32_FLASH_SR, &status);
70
71 return status;
72 }
73
74 static uint32_t stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
75 {
76 struct target *target = bank->target;
77 uint32_t status;
78
79 /* wait for busy to clear */
80 while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
81 {
82 LOG_DEBUG("status: 0x%" PRIx32 "", status);
83 alive_sleep(1);
84 }
85 /* Clear but report errors */
86 if (status & (FLASH_WRPRTERR | FLASH_PGERR))
87 {
88 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
89 }
90 return status;
91 }
92
93 static int stm32x_read_options(struct flash_bank *bank)
94 {
95 uint32_t optiondata;
96 struct stm32x_flash_bank *stm32x_info = NULL;
97 struct target *target = bank->target;
98
99 stm32x_info = stm32x_bank_data(bank);
100
101 /* read current option bytes */
102 target_read_u32(target, STM32_FLASH_OBR, &optiondata);
103
104 stm32x_info->option_bytes.user_options = (uint16_t)0xFFF8 | ((optiondata >> 2) & 0x07);
105 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
106
107 if (optiondata & (1 << OPT_READOUT))
108 LOG_INFO("Device Security Bit Set");
109
110 /* each bit refers to a 4bank protection */
111 target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
112
113 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
114 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
115 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
116 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
117
118 return ERROR_OK;
119 }
120
121 static int stm32x_erase_options(struct flash_bank *bank)
122 {
123 struct stm32x_flash_bank *stm32x_info = NULL;
124 struct target *target = bank->target;
125 uint32_t status;
126
127 stm32x_info = stm32x_bank_data(bank);
128
129 /* read current options */
130 stm32x_read_options(bank);
131
132 /* unlock flash registers */
133 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
134 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
135
136 /* unlock option flash registers */
137 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
138 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
139
140 /* erase option bytes */
141 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
142 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
143
144 status = stm32x_wait_status_busy(bank, 10);
145
146 if (status & FLASH_WRPRTERR)
147 return ERROR_FLASH_OPERATION_FAILED;
148 if (status & FLASH_PGERR)
149 return ERROR_FLASH_OPERATION_FAILED;
150
151 /* clear readout protection and complementary option bytes
152 * this will also force a device unlock if set */
153 stm32x_info->option_bytes.RDP = 0x5AA5;
154
155 return ERROR_OK;
156 }
157
158 static int stm32x_write_options(struct flash_bank *bank)
159 {
160 struct stm32x_flash_bank *stm32x_info = NULL;
161 struct target *target = bank->target;
162 uint32_t status;
163
164 stm32x_info = stm32x_bank_data(bank);
165
166 /* unlock flash registers */
167 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
168 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
169
170 /* unlock option flash registers */
171 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
172 target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
173
174 /* program option bytes */
175 target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
176
177 /* write user option byte */
178 target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
179
180 status = stm32x_wait_status_busy(bank, 10);
181
182 if (status & FLASH_WRPRTERR)
183 return ERROR_FLASH_OPERATION_FAILED;
184 if (status & FLASH_PGERR)
185 return ERROR_FLASH_OPERATION_FAILED;
186
187 /* write protection byte 1 */
188 target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
189
190 status = stm32x_wait_status_busy(bank, 10);
191
192 if (status & FLASH_WRPRTERR)
193 return ERROR_FLASH_OPERATION_FAILED;
194 if (status & FLASH_PGERR)
195 return ERROR_FLASH_OPERATION_FAILED;
196
197 /* write protection byte 2 */
198 target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
199
200 status = stm32x_wait_status_busy(bank, 10);
201
202 if (status & FLASH_WRPRTERR)
203 return ERROR_FLASH_OPERATION_FAILED;
204 if (status & FLASH_PGERR)
205 return ERROR_FLASH_OPERATION_FAILED;
206
207 /* write protection byte 3 */
208 target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
209
210 status = stm32x_wait_status_busy(bank, 10);
211
212 if (status & FLASH_WRPRTERR)
213 return ERROR_FLASH_OPERATION_FAILED;
214 if (status & FLASH_PGERR)
215 return ERROR_FLASH_OPERATION_FAILED;
216
217 /* write protection byte 4 */
218 target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
219
220 status = stm32x_wait_status_busy(bank, 10);
221
222 if (status & FLASH_WRPRTERR)
223 return ERROR_FLASH_OPERATION_FAILED;
224 if (status & FLASH_PGERR)
225 return ERROR_FLASH_OPERATION_FAILED;
226
227 /* write readout protection bit */
228 target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
229
230 status = stm32x_wait_status_busy(bank, 10);
231
232 if (status & FLASH_WRPRTERR)
233 return ERROR_FLASH_OPERATION_FAILED;
234 if (status & FLASH_PGERR)
235 return ERROR_FLASH_OPERATION_FAILED;
236
237 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
238
239 return ERROR_OK;
240 }
241
242 static int stm32x_protect_check(struct flash_bank *bank)
243 {
244 struct target *target = bank->target;
245 struct stm32x_flash_bank *stm32x_info = stm32x_bank_data(bank);
246
247 uint32_t protection;
248 int i, s;
249 int num_bits;
250 int set;
251
252 if (target->state != TARGET_HALTED)
253 {
254 LOG_ERROR("Target not halted");
255 return ERROR_TARGET_NOT_HALTED;
256 }
257
258 /* medium density - each bit refers to a 4bank protection
259 * high density - each bit refers to a 2bank protection */
260 target_read_u32(target, STM32_FLASH_WRPR, &protection);
261
262 /* medium density - each protection bit is for 4 * 1K pages
263 * high density - each protection bit is for 2 * 2K pages */
264 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
265
266 if (stm32x_info->ppage_size == 2)
267 {
268 /* high density flash/connectivity line protection */
269
270 set = 1;
271
272 if (protection & (1 << 31))
273 set = 0;
274
275 /* bit 31 controls sector 62 - 255 protection for high density
276 * bit 31 controls sector 62 - 127 protection for connectivity line */
277 for (s = 62; s < bank->num_sectors; s++)
278 {
279 bank->sectors[s].is_protected = set;
280 }
281
282 if (bank->num_sectors > 61)
283 num_bits = 31;
284
285 for (i = 0; i < num_bits; i++)
286 {
287 set = 1;
288
289 if (protection & (1 << i))
290 set = 0;
291
292 for (s = 0; s < stm32x_info->ppage_size; s++)
293 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
294 }
295 }
296 else
297 {
298 /* low/medium density flash protection */
299 for (i = 0; i < num_bits; i++)
300 {
301 set = 1;
302
303 if (protection & (1 << i))
304 set = 0;
305
306 for (s = 0; s < stm32x_info->ppage_size; s++)
307 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
308 }
309 }
310
311 return ERROR_OK;
312 }
313
314 static int stm32x_erase(struct flash_bank *bank, int first, int last)
315 {
316 struct target *target = bank->target;
317 int i;
318 uint32_t status;
319
320 if (bank->target->state != TARGET_HALTED)
321 {
322 LOG_ERROR("Target not halted");
323 return ERROR_TARGET_NOT_HALTED;
324 }
325
326 if ((first == 0) && (last == (bank->num_sectors - 1)))
327 {
328 return stm32x_mass_erase(bank);
329 }
330
331 /* unlock flash registers */
332 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
333 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
334
335 for (i = first; i <= last; i++)
336 {
337 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
338 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
339 target_write_u32(target, STM32_FLASH_CR, FLASH_PER | FLASH_STRT);
340
341 status = stm32x_wait_status_busy(bank, 10);
342
343 if (status & FLASH_WRPRTERR)
344 return ERROR_FLASH_OPERATION_FAILED;
345 if (status & FLASH_PGERR)
346 return ERROR_FLASH_OPERATION_FAILED;
347 bank->sectors[i].is_erased = 1;
348 }
349
350 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
351
352 return ERROR_OK;
353 }
354
355 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
356 {
357 struct stm32x_flash_bank *stm32x_info = NULL;
358 struct target *target = bank->target;
359 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
360 int i, reg, bit;
361 int status;
362 uint32_t protection;
363
364 stm32x_info = stm32x_bank_data(bank);
365
366 if (target->state != TARGET_HALTED)
367 {
368 LOG_ERROR("Target not halted");
369 return ERROR_TARGET_NOT_HALTED;
370 }
371
372 if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
373 {
374 LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", stm32x_info->ppage_size);
375 return ERROR_FLASH_SECTOR_INVALID;
376 }
377
378 /* medium density - each bit refers to a 4bank protection
379 * high density - each bit refers to a 2bank protection */
380 target_read_u32(target, STM32_FLASH_WRPR, &protection);
381
382 prot_reg[0] = (uint16_t)protection;
383 prot_reg[1] = (uint16_t)(protection >> 8);
384 prot_reg[2] = (uint16_t)(protection >> 16);
385 prot_reg[3] = (uint16_t)(protection >> 24);
386
387 if (stm32x_info->ppage_size == 2)
388 {
389 /* high density flash */
390
391 /* bit 7 controls sector 62 - 255 protection */
392 if (last > 61)
393 {
394 if (set)
395 prot_reg[3] &= ~(1 << 7);
396 else
397 prot_reg[3] |= (1 << 7);
398 }
399
400 if (first > 61)
401 first = 62;
402 if (last > 61)
403 last = 61;
404
405 for (i = first; i <= last; i++)
406 {
407 reg = (i / stm32x_info->ppage_size) / 8;
408 bit = (i / stm32x_info->ppage_size) - (reg * 8);
409
410 if (set)
411 prot_reg[reg] &= ~(1 << bit);
412 else
413 prot_reg[reg] |= (1 << bit);
414 }
415 }
416 else
417 {
418 /* medium density flash */
419 for (i = first; i <= last; i++)
420 {
421 reg = (i / stm32x_info->ppage_size) / 8;
422 bit = (i / stm32x_info->ppage_size) - (reg * 8);
423
424 if (set)
425 prot_reg[reg] &= ~(1 << bit);
426 else
427 prot_reg[reg] |= (1 << bit);
428 }
429 }
430
431 if ((status = stm32x_erase_options(bank)) != ERROR_OK)
432 return status;
433
434 stm32x_info->option_bytes.protection[0] = prot_reg[0];
435 stm32x_info->option_bytes.protection[1] = prot_reg[1];
436 stm32x_info->option_bytes.protection[2] = prot_reg[2];
437 stm32x_info->option_bytes.protection[3] = prot_reg[3];
438
439 return stm32x_write_options(bank);
440 }
441
442 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
443 {
444 struct stm32x_flash_bank *stm32x_info = stm32x_bank_data(bank);
445 struct target *target = bank->target;
446 uint32_t buffer_size = 16384;
447 struct working_area *source;
448 uint32_t address = bank->base + offset;
449 struct reg_param reg_params[4];
450 struct armv7m_algorithm armv7m_info;
451 int retval = ERROR_OK;
452
453 uint8_t stm32x_flash_write_code[] = {
454 /* write: */
455 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, STM32_FLASH_CR */
456 0x09, 0x4D, /* ldr r5, STM32_FLASH_SR */
457 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
458 0x23, 0x60, /* str r3, [r4, #0] */
459 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
460 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
461 /* busy: */
462 0x2B, 0x68, /* ldr r3, [r5, #0] */
463 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
464 0xFB, 0xD0, /* beq busy */
465 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
466 0x01, 0xD1, /* bne exit */
467 0x01, 0x3A, /* subs r2, r2, #1 */
468 0xED, 0xD1, /* bne write */
469 /* exit: */
470 0xFE, 0xE7, /* b exit */
471 0x10, 0x20, 0x02, 0x40, /* STM32_FLASH_CR: .word 0x40022010 */
472 0x0C, 0x20, 0x02, 0x40 /* STM32_FLASH_SR: .word 0x4002200C */
473 };
474
475 /* flash write code */
476 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
477 {
478 LOG_WARNING("no working area available, can't do block memory writes");
479 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
480 };
481
482 if ((retval = target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code)) != ERROR_OK)
483 return retval;
484
485 /* memory buffer */
486 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
487 {
488 buffer_size /= 2;
489 if (buffer_size <= 256)
490 {
491 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
492 if (stm32x_info->write_algorithm)
493 target_free_working_area(target, stm32x_info->write_algorithm);
494
495 LOG_WARNING("no large enough working area available, can't do block memory writes");
496 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
497 }
498 };
499
500 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
501 armv7m_info.core_mode = ARMV7M_MODE_ANY;
502
503 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
504 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
505 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
506 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
507
508 while (count > 0)
509 {
510 uint32_t thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
511
512 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer)) != ERROR_OK)
513 break;
514
515 buf_set_u32(reg_params[0].value, 0, 32, source->address);
516 buf_set_u32(reg_params[1].value, 0, 32, address);
517 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
518
519 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
520 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
521 {
522 LOG_ERROR("error executing stm32x flash write algorithm");
523 retval = ERROR_FLASH_OPERATION_FAILED;
524 break;
525 }
526
527 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
528 {
529 LOG_ERROR("flash memory not erased before writing");
530 /* Clear but report errors */
531 target_write_u32(target, STM32_FLASH_SR, FLASH_PGERR);
532 retval = ERROR_FLASH_OPERATION_FAILED;
533 break;
534 }
535
536 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
537 {
538 LOG_ERROR("flash memory write protected");
539 /* Clear but report errors */
540 target_write_u32(target, STM32_FLASH_SR, FLASH_WRPRTERR);
541 retval = ERROR_FLASH_OPERATION_FAILED;
542 break;
543 }
544
545 buffer += thisrun_count * 2;
546 address += thisrun_count * 2;
547 count -= thisrun_count;
548 }
549
550 target_free_working_area(target, source);
551 target_free_working_area(target, stm32x_info->write_algorithm);
552
553 destroy_reg_param(&reg_params[0]);
554 destroy_reg_param(&reg_params[1]);
555 destroy_reg_param(&reg_params[2]);
556 destroy_reg_param(&reg_params[3]);
557
558 return retval;
559 }
560
561 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
562 {
563 struct target *target = bank->target;
564 uint32_t words_remaining = (count / 2);
565 uint32_t bytes_remaining = (count & 0x00000001);
566 uint32_t address = bank->base + offset;
567 uint32_t bytes_written = 0;
568 uint8_t status;
569 int retval;
570
571 if (bank->target->state != TARGET_HALTED)
572 {
573 LOG_ERROR("Target not halted");
574 return ERROR_TARGET_NOT_HALTED;
575 }
576
577 if (offset & 0x1)
578 {
579 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
580 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
581 }
582
583 /* unlock flash registers */
584 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
585 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
586
587 /* multiple half words (2-byte) to be programmed? */
588 if (words_remaining > 0)
589 {
590 /* try using a block write */
591 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
592 {
593 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
594 {
595 /* if block write failed (no sufficient working area),
596 * we use normal (slow) single dword accesses */
597 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
598 }
599 else if (retval == ERROR_FLASH_OPERATION_FAILED)
600 {
601 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
602 return ERROR_FLASH_OPERATION_FAILED;
603 }
604 }
605 else
606 {
607 buffer += words_remaining * 2;
608 address += words_remaining * 2;
609 words_remaining = 0;
610 }
611 }
612
613 while (words_remaining > 0)
614 {
615 uint16_t value;
616 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
617
618 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
619 target_write_u16(target, address, value);
620
621 status = stm32x_wait_status_busy(bank, 5);
622
623 if (status & FLASH_WRPRTERR)
624 {
625 LOG_ERROR("flash memory not erased before writing");
626 return ERROR_FLASH_OPERATION_FAILED;
627 }
628 if (status & FLASH_PGERR)
629 {
630 LOG_ERROR("flash memory write protected");
631 return ERROR_FLASH_OPERATION_FAILED;
632 }
633
634 bytes_written += 2;
635 words_remaining--;
636 address += 2;
637 }
638
639 if (bytes_remaining)
640 {
641 uint16_t value = 0xffff;
642 memcpy(&value, buffer + bytes_written, bytes_remaining);
643
644 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
645 target_write_u16(target, address, value);
646
647 status = stm32x_wait_status_busy(bank, 5);
648
649 if (status & FLASH_WRPRTERR)
650 {
651 LOG_ERROR("flash memory not erased before writing");
652 return ERROR_FLASH_OPERATION_FAILED;
653 }
654 if (status & FLASH_PGERR)
655 {
656 LOG_ERROR("flash memory write protected");
657 return ERROR_FLASH_OPERATION_FAILED;
658 }
659 }
660
661 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
662
663 return ERROR_OK;
664 }
665
666 static int stm32x_probe(struct flash_bank *bank)
667 {
668 struct target *target = bank->target;
669 struct stm32x_flash_bank *stm32x_info = stm32x_bank_data(bank);
670 int i;
671 uint16_t num_pages;
672 uint32_t device_id;
673 int page_size;
674
675 if (bank->target->state != TARGET_HALTED)
676 {
677 LOG_ERROR("Target not halted");
678 return ERROR_TARGET_NOT_HALTED;
679 }
680
681 stm32x_info->probed = 0;
682
683 /* read stm32 device id register */
684 target_read_u32(target, 0xE0042000, &device_id);
685 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
686
687 /* get flash size from target */
688 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
689 {
690 /* failed reading flash size, default to max target family */
691 num_pages = 0xffff;
692 }
693
694 if ((device_id & 0x7ff) == 0x410)
695 {
696 /* medium density - we have 1k pages
697 * 4 pages for a protection area */
698 page_size = 1024;
699 stm32x_info->ppage_size = 4;
700
701 /* check for early silicon */
702 if (num_pages == 0xffff)
703 {
704 /* number of sectors incorrect on revA */
705 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 128k flash");
706 num_pages = 128;
707 }
708 }
709 else if ((device_id & 0x7ff) == 0x412)
710 {
711 /* low density - we have 1k pages
712 * 4 pages for a protection area */
713 page_size = 1024;
714 stm32x_info->ppage_size = 4;
715
716 /* check for early silicon */
717 if (num_pages == 0xffff)
718 {
719 /* number of sectors incorrect on revA */
720 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 32k flash");
721 num_pages = 32;
722 }
723 }
724 else if ((device_id & 0x7ff) == 0x414)
725 {
726 /* high density - we have 2k pages
727 * 2 pages for a protection area */
728 page_size = 2048;
729 stm32x_info->ppage_size = 2;
730
731 /* check for early silicon */
732 if (num_pages == 0xffff)
733 {
734 /* number of sectors incorrect on revZ */
735 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 512k flash");
736 num_pages = 512;
737 }
738 }
739 else if ((device_id & 0x7ff) == 0x418)
740 {
741 /* connectivity line density - we have 2k pages
742 * 2 pages for a protection area */
743 page_size = 2048;
744 stm32x_info->ppage_size = 2;
745
746 /* check for early silicon */
747 if (num_pages == 0xffff)
748 {
749 /* number of sectors incorrect on revZ */
750 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 256k flash");
751 num_pages = 256;
752 }
753 }
754 else
755 {
756 LOG_WARNING("Cannot identify target as a STM32 family.");
757 return ERROR_FLASH_OPERATION_FAILED;
758 }
759
760 LOG_INFO("flash size = %dkbytes", num_pages);
761
762 /* calculate numbers of pages */
763 num_pages /= (page_size / 1024);
764
765 bank->base = 0x08000000;
766 bank->size = (num_pages * page_size);
767 bank->num_sectors = num_pages;
768 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
769
770 for (i = 0; i < num_pages; i++)
771 {
772 bank->sectors[i].offset = i * page_size;
773 bank->sectors[i].size = page_size;
774 bank->sectors[i].is_erased = -1;
775 bank->sectors[i].is_protected = 1;
776 }
777
778 stm32x_info->probed = 1;
779
780 return ERROR_OK;
781 }
782
783 static int stm32x_auto_probe(struct flash_bank *bank)
784 {
785 struct stm32x_flash_bank *stm32x_info = stm32x_bank_data(bank);
786 if (stm32x_info->probed)
787 return ERROR_OK;
788 return stm32x_probe(bank);
789 }
790
791 #if 0
792 COMMAND_HANDLER(stm32x_handle_part_id_command)
793 {
794 return ERROR_OK;
795 }
796 #endif
797
798 static int stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
799 {
800 struct target *target = bank->target;
801 uint32_t device_id;
802 int printed;
803
804 /* read stm32 device id register */
805 target_read_u32(target, 0xE0042000, &device_id);
806
807 if ((device_id & 0x7ff) == 0x410)
808 {
809 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
810 buf += printed;
811 buf_size -= printed;
812
813 switch (device_id >> 16)
814 {
815 case 0x0000:
816 snprintf(buf, buf_size, "A");
817 break;
818
819 case 0x2000:
820 snprintf(buf, buf_size, "B");
821 break;
822
823 case 0x2001:
824 snprintf(buf, buf_size, "Z");
825 break;
826
827 case 0x2003:
828 snprintf(buf, buf_size, "Y");
829 break;
830
831 default:
832 snprintf(buf, buf_size, "unknown");
833 break;
834 }
835 }
836 else if ((device_id & 0x7ff) == 0x412)
837 {
838 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
839 buf += printed;
840 buf_size -= printed;
841
842 switch (device_id >> 16)
843 {
844 case 0x1000:
845 snprintf(buf, buf_size, "A");
846 break;
847
848 default:
849 snprintf(buf, buf_size, "unknown");
850 break;
851 }
852 }
853 else if ((device_id & 0x7ff) == 0x414)
854 {
855 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
856 buf += printed;
857 buf_size -= printed;
858
859 switch (device_id >> 16)
860 {
861 case 0x1000:
862 snprintf(buf, buf_size, "A");
863 break;
864
865 case 0x1001:
866 snprintf(buf, buf_size, "Z");
867 break;
868
869 default:
870 snprintf(buf, buf_size, "unknown");
871 break;
872 }
873 }
874 else if ((device_id & 0x7ff) == 0x418)
875 {
876 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
877 buf += printed;
878 buf_size -= printed;
879
880 switch (device_id >> 16)
881 {
882 case 0x1000:
883 snprintf(buf, buf_size, "A");
884 break;
885
886 case 0x1001:
887 snprintf(buf, buf_size, "Z");
888 break;
889
890 default:
891 snprintf(buf, buf_size, "unknown");
892 break;
893 }
894 }
895 else
896 {
897 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
898 return ERROR_FLASH_OPERATION_FAILED;
899 }
900
901 return ERROR_OK;
902 }
903
904 COMMAND_HANDLER(stm32x_handle_lock_command)
905 {
906 struct target *target = NULL;
907 struct stm32x_flash_bank *stm32x_info = NULL;
908
909 if (CMD_ARGC < 1)
910 {
911 command_print(CMD_CTX, "stm32x lock <bank>");
912 return ERROR_OK;
913 }
914
915 struct flash_bank *bank;
916 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
917 if (ERROR_OK != retval)
918 return retval;
919
920 stm32x_info = stm32x_bank_data(bank);
921
922 target = bank->target;
923
924 if (target->state != TARGET_HALTED)
925 {
926 LOG_ERROR("Target not halted");
927 return ERROR_TARGET_NOT_HALTED;
928 }
929
930 if (stm32x_erase_options(bank) != ERROR_OK)
931 {
932 command_print(CMD_CTX, "stm32x failed to erase options");
933 return ERROR_OK;
934 }
935
936 /* set readout protection */
937 stm32x_info->option_bytes.RDP = 0;
938
939 if (stm32x_write_options(bank) != ERROR_OK)
940 {
941 command_print(CMD_CTX, "stm32x failed to lock device");
942 return ERROR_OK;
943 }
944
945 command_print(CMD_CTX, "stm32x locked");
946
947 return ERROR_OK;
948 }
949
950 COMMAND_HANDLER(stm32x_handle_unlock_command)
951 {
952 struct target *target = NULL;
953 struct stm32x_flash_bank *stm32x_info = NULL;
954
955 if (CMD_ARGC < 1)
956 {
957 command_print(CMD_CTX, "stm32x unlock <bank>");
958 return ERROR_OK;
959 }
960
961 struct flash_bank *bank;
962 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
963 if (ERROR_OK != retval)
964 return retval;
965
966 stm32x_info = stm32x_bank_data(bank);
967
968 target = bank->target;
969
970 if (target->state != TARGET_HALTED)
971 {
972 LOG_ERROR("Target not halted");
973 return ERROR_TARGET_NOT_HALTED;
974 }
975
976 if (stm32x_erase_options(bank) != ERROR_OK)
977 {
978 command_print(CMD_CTX, "stm32x failed to unlock device");
979 return ERROR_OK;
980 }
981
982 if (stm32x_write_options(bank) != ERROR_OK)
983 {
984 command_print(CMD_CTX, "stm32x failed to lock device");
985 return ERROR_OK;
986 }
987
988 command_print(CMD_CTX, "stm32x unlocked");
989
990 return ERROR_OK;
991 }
992
993 COMMAND_HANDLER(stm32x_handle_options_read_command)
994 {
995 uint32_t optionbyte;
996 struct target *target = NULL;
997 struct stm32x_flash_bank *stm32x_info = NULL;
998
999 if (CMD_ARGC < 1)
1000 {
1001 command_print(CMD_CTX, "stm32x options_read <bank>");
1002 return ERROR_OK;
1003 }
1004
1005 struct flash_bank *bank;
1006 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1007 if (ERROR_OK != retval)
1008 return retval;
1009
1010 stm32x_info = stm32x_bank_data(bank);
1011
1012 target = bank->target;
1013
1014 if (target->state != TARGET_HALTED)
1015 {
1016 LOG_ERROR("Target not halted");
1017 return ERROR_TARGET_NOT_HALTED;
1018 }
1019
1020 target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1021 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1022
1023 if (buf_get_u32((uint8_t*)&optionbyte, OPT_ERROR, 1))
1024 command_print(CMD_CTX, "Option Byte Complement Error");
1025
1026 if (buf_get_u32((uint8_t*)&optionbyte, OPT_READOUT, 1))
1027 command_print(CMD_CTX, "Readout Protection On");
1028 else
1029 command_print(CMD_CTX, "Readout Protection Off");
1030
1031 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDWDGSW, 1))
1032 command_print(CMD_CTX, "Software Watchdog");
1033 else
1034 command_print(CMD_CTX, "Hardware Watchdog");
1035
1036 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTOP, 1))
1037 command_print(CMD_CTX, "Stop: No reset generated");
1038 else
1039 command_print(CMD_CTX, "Stop: Reset generated");
1040
1041 if (buf_get_u32((uint8_t*)&optionbyte, OPT_RDRSTSTDBY, 1))
1042 command_print(CMD_CTX, "Standby: No reset generated");
1043 else
1044 command_print(CMD_CTX, "Standby: Reset generated");
1045
1046 return ERROR_OK;
1047 }
1048
1049 COMMAND_HANDLER(stm32x_handle_options_write_command)
1050 {
1051 struct target *target = NULL;
1052 struct stm32x_flash_bank *stm32x_info = NULL;
1053 uint16_t optionbyte = 0xF8;
1054
1055 if (CMD_ARGC < 4)
1056 {
1057 command_print(CMD_CTX, "stm32x options_write <bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>");
1058 return ERROR_OK;
1059 }
1060
1061 struct flash_bank *bank;
1062 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1063 if (ERROR_OK != retval)
1064 return retval;
1065
1066 stm32x_info = stm32x_bank_data(bank);
1067
1068 target = bank->target;
1069
1070 if (target->state != TARGET_HALTED)
1071 {
1072 LOG_ERROR("Target not halted");
1073 return ERROR_TARGET_NOT_HALTED;
1074 }
1075
1076 if (strcmp(CMD_ARGV[1], "SWWDG") == 0)
1077 {
1078 optionbyte |= (1 << 0);
1079 }
1080 else
1081 {
1082 optionbyte &= ~(1 << 0);
1083 }
1084
1085 if (strcmp(CMD_ARGV[2], "NORSTSTNDBY") == 0)
1086 {
1087 optionbyte |= (1 << 1);
1088 }
1089 else
1090 {
1091 optionbyte &= ~(1 << 1);
1092 }
1093
1094 if (strcmp(CMD_ARGV[3], "NORSTSTOP") == 0)
1095 {
1096 optionbyte |= (1 << 2);
1097 }
1098 else
1099 {
1100 optionbyte &= ~(1 << 2);
1101 }
1102
1103 if (stm32x_erase_options(bank) != ERROR_OK)
1104 {
1105 command_print(CMD_CTX, "stm32x failed to erase options");
1106 return ERROR_OK;
1107 }
1108
1109 stm32x_info->option_bytes.user_options = optionbyte;
1110
1111 if (stm32x_write_options(bank) != ERROR_OK)
1112 {
1113 command_print(CMD_CTX, "stm32x failed to write options");
1114 return ERROR_OK;
1115 }
1116
1117 command_print(CMD_CTX, "stm32x write options complete");
1118
1119 return ERROR_OK;
1120 }
1121
1122 static int stm32x_mass_erase(struct flash_bank *bank)
1123 {
1124 struct target *target = bank->target;
1125 uint32_t status;
1126
1127 if (target->state != TARGET_HALTED)
1128 {
1129 LOG_ERROR("Target not halted");
1130 return ERROR_TARGET_NOT_HALTED;
1131 }
1132
1133 /* unlock option flash registers */
1134 target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1135 target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1136
1137 /* mass erase flash memory */
1138 target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1139 target_write_u32(target, STM32_FLASH_CR, FLASH_MER | FLASH_STRT);
1140
1141 status = stm32x_wait_status_busy(bank, 10);
1142
1143 target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1144
1145 if (status & FLASH_WRPRTERR)
1146 {
1147 LOG_ERROR("stm32x device protected");
1148 return ERROR_OK;
1149 }
1150
1151 if (status & FLASH_PGERR)
1152 {
1153 LOG_ERROR("stm32x device programming failed");
1154 return ERROR_OK;
1155 }
1156
1157 return ERROR_OK;
1158 }
1159
1160 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1161 {
1162 int i;
1163
1164 if (CMD_ARGC < 1)
1165 {
1166 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1167 return ERROR_OK;
1168 }
1169
1170 struct flash_bank *bank;
1171 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1172 if (ERROR_OK != retval)
1173 return retval;
1174
1175 if (stm32x_mass_erase(bank) == ERROR_OK)
1176 {
1177 /* set all sectors as erased */
1178 for (i = 0; i < bank->num_sectors; i++)
1179 {
1180 bank->sectors[i].is_erased = 1;
1181 }
1182
1183 command_print(CMD_CTX, "stm32x mass erase complete");
1184 }
1185 else
1186 {
1187 command_print(CMD_CTX, "stm32x mass erase failed");
1188 }
1189
1190 return ERROR_OK;
1191 }
1192
1193 static const struct command_registration stm32x_exec_command_handlers[] = {
1194 {
1195 .name = "lock",
1196 .handler = &stm32x_handle_lock_command,
1197 .mode = COMMAND_EXEC,
1198 .help = "lock device",
1199 },
1200 {
1201 .name = "unlock",
1202 .handler = &stm32x_handle_unlock_command,
1203 .mode = COMMAND_EXEC,
1204 .help = "unlock protected device",
1205 },
1206 {
1207 .name = "mass_erase",
1208 .handler = &stm32x_handle_mass_erase_command,
1209 .mode = COMMAND_EXEC,
1210 .help = "mass erase device",
1211 },
1212 {
1213 .name = "options_read",
1214 .handler = &stm32x_handle_options_read_command,
1215 .mode = COMMAND_EXEC,
1216 .help = "read device option bytes",
1217 },
1218 {
1219 .name = "options_write",
1220 .handler = &stm32x_handle_options_write_command,
1221 .mode = COMMAND_EXEC,
1222 .help = "write device option bytes",
1223 },
1224 COMMAND_REGISTRATION_DONE
1225 };
1226 static const struct command_registration stm32x_command_handlers[] = {
1227 {
1228 .name = "stm32x",
1229 .mode = COMMAND_ANY,
1230 .help = "stm32x flash command group",
1231 .chain = stm32x_exec_command_handlers,
1232 },
1233 COMMAND_REGISTRATION_DONE
1234 };
1235
1236 FLASH_DRIVER(stm32x, &stm32x_flash_bank_command, stm32x_command_handlers,
1237 .erase = &stm32x_erase,
1238 .protect = &stm32x_protect,
1239 .write = &stm32x_write,
1240 .probe = &stm32x_probe,
1241 .auto_probe = &stm32x_auto_probe,
1242 .erase_check = &default_flash_mem_blank_check,
1243 .protect_check = &stm32x_protect_check,
1244 .info = &stm32x_info,
1245 );
Zach's Unofficial Testing Repository