src/flash/nor/stellaris.c

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23
  24 /***************************************************************************
  25 * STELLARIS is tested on LM3S811, LM3S6965
  26 ***************************************************************************/
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "imp.h"
  32 #include "stellaris.h"
  33 #include <helper/binarybuffer.h>
  34 #include <target/algorithm.h>
  35 #include <target/armv7m.h>
  36
  37
  38 #define DID0_VER(did0) ((did0 >> 28)&0x07)
  39
  40 static int stellaris_read_part_info(struct flash_bank *bank);
  41 static uint32_t stellaris_get_flash_status(struct flash_bank *bank);
  42 static void stellaris_set_flash_mode(struct flash_bank *bank,int mode);
  43 //static uint32_t stellaris_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout);
  44
  45 static int stellaris_mass_erase(struct flash_bank *bank);
  46
  47 static struct {
  48         uint32_t partno;
  49         char *partname;
  50 }       StellarisParts[] =
  51 {
  52         {0x01,"LM3S101"},
  53         {0x02,"LM3S102"},
  54         {0x03,"LM3S1625"},
  55         {0x04,"LM3S1626"},
  56         {0x05,"LM3S1627"},
  57         {0x06,"LM3S1607"},
  58         {0x10,"LM3S1776"},
  59         {0x19,"LM3S300"},
  60         {0x11,"LM3S301"},
  61         {0x12,"LM3S310"},
  62         {0x1A,"LM3S308"},
  63         {0x13,"LM3S315"},
  64         {0x14,"LM3S316"},
  65         {0x17,"LM3S317"},
  66         {0x18,"LM3S318"},
  67         {0x15,"LM3S328"},
  68         {0x2A,"LM3S600"},
  69         {0x21,"LM3S601"},
  70         {0x2B,"LM3S608"},
  71         {0x22,"LM3S610"},
  72         {0x23,"LM3S611"},
  73         {0x24,"LM3S612"},
  74         {0x25,"LM3S613"},
  75         {0x26,"LM3S615"},
  76         {0x28,"LM3S617"},
  77         {0x29,"LM3S618"},
  78         {0x27,"LM3S628"},
  79         {0x38,"LM3S800"},
  80         {0x31,"LM3S801"},
  81         {0x39,"LM3S808"},
  82         {0x32,"LM3S811"},
  83         {0x33,"LM3S812"},
  84         /*{0x33,"LM3S2616"},*/
  85         {0x34,"LM3S815"},
  86         {0x36,"LM3S817"},
  87         {0x37,"LM3S818"},
  88         {0x35,"LM3S828"},
  89         {0x39,"LM3S2276"},
  90         {0x3A,"LM3S2776"},
  91         {0x43,"LM3S3651"},
  92         {0x44,"LM3S3739"},
  93         {0x45,"LM3S3749"},
  94         {0x46,"LM3S3759"},
  95         {0x48,"LM3S3768"},
  96         {0x49,"LM3S3748"},
  97         {0x50,"LM3S2678"},
  98         {0x51,"LM3S2110"},
  99         {0x52,"LM3S2739"},
 100         {0x53,"LM3S2651"},
 101         {0x54,"LM3S2939"},
 102         {0x55,"LM3S2965"},
 103         {0x56,"LM3S2432"},
 104         {0x57,"LM3S2620"},
 105         {0x58,"LM3S2950"},
 106         {0x59,"LM3S2412"},
 107         {0x5A,"LM3S2533"},
 108         {0x61,"LM3S8630"},
 109         {0x62,"LM3S8970"},
 110         {0x63,"LM3S8730"},
 111         {0x64,"LM3S8530"},
 112         {0x65,"LM3S8930"},
 113         {0x71,"LM3S6610"},
 114         {0x72,"LM3S6950"},
 115         {0x73,"LM3S6965"},
 116         {0x74,"LM3S6110"},
 117         {0x75,"LM3S6432"},
 118         {0x76,"LM3S6537"},
 119         {0x77,"LM3S6753"},
 120         {0x78,"LM3S6952"},
 121         {0x80,"LM3S2671"},
 122         {0x81,"LM3S5632"},
 123         {0x82,"LM3S6422"},
 124         {0x83,"LM3S6633"},
 125         {0x84,"LM3S2139"},
 126         {0x85,"LM3S2637"},
 127         {0x86,"LM3S8738"},
 128         {0x88,"LM3S8938"},
 129         {0x89,"LM3S6938"},
 130         {0x8A,"LM3S5652"},
 131         {0x8B,"LM3S6637"},
 132         {0x8C,"LM3S8933"},
 133         {0x8D,"LM3S8733"},
 134         {0x8E,"LM3S8538"},
 135         {0x8F,"LM3S2948"},
 136         {0x91,"LM3S5662"},
 137         {0x96,"LM3S5732"},
 138         {0x97,"LM3S5737"},
 139         {0x99,"LM3S5747"},
 140         {0x9A,"LM3S5752"},
 141         {0x9B,"LM3S5757"},
 142         {0x9C,"LM3S5762"},
 143         {0x9D,"LM3S5767"},
 144         {0xA0,"LM3S5739"},
 145         {0xA1,"LM3S6100"},
 146         {0xA2,"LM3S2410"},
 147         {0xA3,"LM3S6730"},
 148         {0xA4,"LM3S2730"},
 149         {0xA5,"LM3S6420"},
 150         {0xA6,"LM3S8962"},
 151         {0xA7,"LM3S5749"},
 152         {0xA8,"LM3S5769"},
 153         {0xA9,"LM3S5768"},
 154         {0xB3,"LM3S1635"},
 155         {0xB4,"LM3S1850"},
 156         {0xB5,"LM3S1960"},
 157         {0xB7,"LM3S1937"},
 158         {0xB8,"LM3S1968"},
 159         {0xB9,"LM3S1751"},
 160         {0xBA,"LM3S1439"},
 161         {0xBB,"LM3S1512"},
 162         {0xBC,"LM3S1435"},
 163         {0xBD,"LM3S1637"},
 164         {0xBE,"LM3S1958"},
 165         {0xBF,"LM3S1110"},
 166         {0xC0,"LM3S1620"},
 167         {0xC1,"LM3S1150"},
 168         {0xC2,"LM3S1165"},
 169         {0xC3,"LM3S1133"},
 170         {0xC4,"LM3S1162"},
 171         {0xC5,"LM3S1138"},
 172         {0xC6,"LM3S1332"},
 173         {0xC7,"LM3S1538"},
 174         {0xD0,"LM3S6815"},
 175         {0xD1,"LM3S6816"},
 176         {0xD2,"LM3S6915"},
 177         {0xD3,"LM3S6916"},
 178         {0xD4,"LM3S2016"},
 179         {0xD5,"LM3S1615"},
 180         {0xD6,"LM3S1616"},
 181         {0xD7,"LM3S8971"},
 182         {0xD8,"LM3S1108"},
 183         {0xD9,"LM3S1101"},
 184         {0xDA,"LM3S1608"},
 185         {0xDB,"LM3S1601"},
 186         {0xDC,"LM3S1918"},
 187         {0xDD,"LM3S1911"},
 188         {0xDE,"LM3S2108"},
 189         {0xDF,"LM3S2101"},
 190         {0xE0,"LM3S2608"},
 191         {0xE1,"LM3S2601"},
 192         {0xE2,"LM3S2918"},
 193         {0xE3,"LM3S2911"},
 194         {0xE4,"LM3S6118"},
 195         {0xE5,"LM3S6111"},
 196         {0xE6,"LM3S6618"},
 197         {0xE7,"LM3S6611"},
 198         {0xE8,"LM3S6918"},
 199         {0xE9,"LM3S6911"},
 200         {0,"Unknown part"}
 201 };
 202
 203 static char * StellarisClassname[5] =
 204 {
 205         "Sandstorm",
 206         "Fury",
 207         "Unknown",
 208         "DustDevil",
 209         "Tempest"
 210 };
 211
 212 /***************************************************************************
 213 *       openocd command interface                                              *
 214 ***************************************************************************/
 215
 216 /* flash_bank stellaris <base> <size> 0 0 <target#>
 217  */
 218 FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command)
 219 {
 220         struct stellaris_flash_bank *stellaris_info;
 221
 222         if (CMD_ARGC < 6)
 223         {
 224                 LOG_WARNING("incomplete flash_bank stellaris configuration");
 225                 return ERROR_FLASH_BANK_INVALID;
 226         }
 227
 228         stellaris_info = calloc(sizeof(struct stellaris_flash_bank), 1);
 229
 230         struct flash_bank *bank = flash_bank_from_object(object);
 231         bank->base = 0x0;
 232         set_flash_bank_data(bank, stellaris_info);
 233
 234         stellaris_info->target_name = "Unknown target";
 235
 236         /* part wasn't probed for info yet */
 237         stellaris_info->did1 = 0;
 238
 239         /* TODO Specify the main crystal speed in kHz using an optional
 240          * argument; ditto, the speed of an external oscillator used
 241          * instead of a crystal.  Avoid programming flash using IOSC.
 242          */
 243         return ERROR_OK;
 244 }
 245
 246 static struct stellaris_flash_bank *stellaris_bank_data(struct flash_bank *bank)
 247 {
 248         return (struct stellaris_flash_bank *)flash_bank_data(bank);
 249 }
 250
 251 static int stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
 252 {
 253         int printed, device_class;
 254         struct stellaris_flash_bank *stellaris_info = stellaris_bank_data(bank);
 255
 256         stellaris_read_part_info(bank);
 257
 258         if (stellaris_info->did1 == 0)
 259         {
 260                 printed = snprintf(buf, buf_size, "Cannot identify target as a Stellaris\n");
 261                 buf += printed;
 262                 buf_size -= printed;
 263                 return ERROR_FLASH_OPERATION_FAILED;
 264         }
 265
 266         if (DID0_VER(stellaris_info->did0) > 0)
 267         {
 268                 device_class = (stellaris_info->did0 >> 16) & 0xFF;
 269         }
 270         else
 271         {
 272                 device_class = 0;
 273         }
 274         printed = snprintf(buf,
 275                            buf_size,
 276                            "\nTI/LMI Stellaris information: Chip is "
 277                            "class %i (%s) %s rev %c%i\n",
 278                            device_class,
 279                            StellarisClassname[device_class],
 280                            stellaris_info->target_name,
 281                            (int)('A' + ((stellaris_info->did0 >> 8) & 0xFF)),
 282                            (int)((stellaris_info->did0) & 0xFF));
 283         buf += printed;
 284         buf_size -= printed;
 285
 286         printed = snprintf(buf,
 287                            buf_size,
 288                            "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
 289                            ", eproc: %s, ramsize: %ik, flashsize: %ik\n",
 290                            stellaris_info->did1,
 291                            stellaris_info->did1,
 292                            "ARMv7M",
 293                            (int)((1 + ((stellaris_info->dc0 >> 16) & 0xFFFF))/4),
 294                            (int)((1 + (stellaris_info->dc0 & 0xFFFF))*2));
 295         buf += printed;
 296         buf_size -= printed;
 297
 298         printed = snprintf(buf,
 299                            buf_size,
 300                            "master clock: %ikHz%s, "
 301                            "rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 "\n",
 302                            (int)(stellaris_info->mck_freq / 1000),
 303                            stellaris_info->mck_desc,
 304                            stellaris_info->rcc,
 305                            stellaris_info->rcc2);
 306         buf += printed;
 307         buf_size -= printed;
 308
 309         if (stellaris_info->num_lockbits > 0)
 310         {
 311                 printed = snprintf(buf,
 312                                    buf_size,
 313                                    "pagesize: %" PRIi32 ", lockbits: %i 0x%4.4" PRIx32 ", pages in lock region: %i \n",
 314                                    stellaris_info->pagesize,
 315                                    stellaris_info->num_lockbits,
 316                                    stellaris_info->lockbits,
 317                                    (int)(stellaris_info->num_pages/stellaris_info->num_lockbits));
 318                 buf += printed;
 319                 buf_size -= printed;
 320         }
 321         return ERROR_OK;
 322 }
 323
 324 /***************************************************************************
 325 *       chip identification and status                                         *
 326 ***************************************************************************/
 327
 328 static uint32_t stellaris_get_flash_status(struct flash_bank *bank)
 329 {
 330         struct target *target = bank->target;
 331         uint32_t fmc;
 332
 333         target_read_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, &fmc);
 334
 335         return fmc;
 336 }
 337
 338 /** Read clock configuration and set stellaris_info->usec_clocks*/
 339
 340 static const unsigned rcc_xtal[32] = {
 341         [0x00] = 1000000,               /* no pll */
 342         [0x01] = 1843200,               /* no pll */
 343         [0x02] = 2000000,               /* no pll */
 344         [0x03] = 2457600,               /* no pll */
 345
 346         [0x04] = 3579545,
 347         [0x05] = 3686400,
 348         [0x06] = 4000000,               /* usb */
 349         [0x07] = 4096000,
 350
 351         [0x08] = 4915200,
 352         [0x09] = 5000000,               /* usb */
 353         [0x0a] = 5120000,
 354         [0x0b] = 6000000,               /* (reset) usb */
 355
 356         [0x0c] = 6144000,
 357         [0x0d] = 7372800,
 358         [0x0e] = 8000000,               /* usb */
 359         [0x0f] = 8192000,
 360
 361         /* parts before DustDevil use just 4 bits for xtal spec */
 362
 363         [0x10] = 10000000,              /* usb */
 364         [0x11] = 12000000,              /* usb */
 365         [0x12] = 12288000,
 366         [0x13] = 13560000,
 367
 368         [0x14] = 14318180,
 369         [0x15] = 16000000,              /* usb */
 370         [0x16] = 16384000,
 371 };
 372
 373 static void stellaris_read_clock_info(struct flash_bank *bank)
 374 {
 375         struct stellaris_flash_bank *stellaris_info = stellaris_bank_data(bank);
 376         struct target *target = bank->target;
 377         uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
 378         unsigned xtal;
 379         unsigned long mainfreq;
 380
 381         target_read_u32(target, SCB_BASE | RCC, &rcc);
 382         LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
 383
 384         target_read_u32(target, SCB_BASE | RCC2, &rcc2);
 385         LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
 386
 387         target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
 388         LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
 389
 390         stellaris_info->rcc = rcc;
 391         stellaris_info->rcc = rcc2;
 392
 393         sysdiv = (rcc >> 23) & 0xF;
 394         usesysdiv = (rcc >> 22) & 0x1;
 395         bypass = (rcc >> 11) & 0x1;
 396         oscsrc = (rcc >> 4) & 0x3;
 397         xtal = (rcc >> 6) & stellaris_info->xtal_mask;
 398
 399         /* NOTE: post-Sandstorm parts have RCC2 which may override
 400          * parts of RCC ... with more sysdiv options, option for
 401          * 32768 Hz mainfreq, PLL controls.  On Sandstorm it reads
 402          * as zero, so the "use RCC2" flag is always clear.
 403          */
 404         if (rcc2 & (1 << 31)) {
 405                 sysdiv = (rcc2 >> 23) & 0x3F;
 406                 bypass = (rcc2 >> 11) & 0x1;
 407                 oscsrc = (rcc2 >> 4) & 0x7;
 408
 409                 /* FIXME Tempest parts have an additional lsb for
 410                  * fractional sysdiv (200 MHz / 2.5 == 80 MHz)
 411                  */
 412         }
 413
 414         stellaris_info->mck_desc = "";
 415
 416         switch (oscsrc)
 417         {
 418                 case 0:                         /* MOSC */
 419                         mainfreq = rcc_xtal[xtal];
 420                         break;
 421                 case 1:                         /* IOSC */
 422                         mainfreq = stellaris_info->iosc_freq;
 423                         stellaris_info->mck_desc = stellaris_info->iosc_desc;
 424                         break;
 425                 case 2:                         /* IOSC/4 */
 426                         mainfreq = stellaris_info->iosc_freq / 4;
 427                         stellaris_info->mck_desc = stellaris_info->iosc_desc;
 428                         break;
 429                 case 3:                         /* lowspeed */
 430                         /* Sandstorm doesn't have this 30K +/- 30% osc */
 431                         mainfreq = 30000;
 432                         stellaris_info->mck_desc = " (±30%)";
 433                         break;
 434                 case 8:                         /* hibernation osc */
 435                         /* not all parts support hibernation */
 436                         mainfreq = 32768;
 437                         break;
 438
 439                 default: /* NOTREACHED */
 440                         mainfreq = 0;
 441                         break;
 442         }
 443
 444         /* PLL is used if it's not bypassed; its output is 200 MHz
 445          * even when it runs at 400 MHz (adds divide-by-two stage).
 446          */
 447         if (!bypass)
 448                 mainfreq = 200000000;
 449
 450         if (usesysdiv)
 451                 stellaris_info->mck_freq = mainfreq/(1 + sysdiv);
 452         else
 453                 stellaris_info->mck_freq = mainfreq;
 454
 455         /* Forget old flash timing */
 456         stellaris_set_flash_mode(bank, 0);
 457 }
 458
 459 /* Setup the timimg registers */
 460 static void stellaris_set_flash_mode(struct flash_bank *bank,int mode)
 461 {
 462         struct stellaris_flash_bank *stellaris_info = stellaris_bank_data(bank);
 463         struct target *target = bank->target;
 464
 465         uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1);
 466         LOG_DEBUG("usecrl = %i",(int)(usecrl));
 467         target_write_u32(target, SCB_BASE | USECRL, usecrl);
 468 }
 469
 470 #if 0
 471 static uint32_t stellaris_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout)
 472 {
 473         uint32_t status;
 474
 475         /* Stellaris waits for cmdbit to clear */
 476         while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0))
 477         {
 478                 LOG_DEBUG("status: 0x%x", status);
 479                 alive_sleep(1);
 480         }
 481
 482         /* Flash errors are reflected in the FLASH_CRIS register */
 483
 484         return status;
 485 }
 486
 487 /* Send one command to the flash controller */
 488 static int stellaris_flash_command(struct flash_bank *bank,uint8_t cmd,uint16_t pagen)
 489 {
 490         uint32_t fmc;
 491         struct target *target = bank->target;
 492
 493         fmc = FMC_WRKEY | cmd;
 494         target_write_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, fmc);
 495         LOG_DEBUG("Flash command: 0x%x", fmc);
 496
 497         if (stellaris_wait_status_busy(bank, cmd, 100))
 498         {
 499                 return ERROR_FLASH_OPERATION_FAILED;
 500         }
 501
 502         return ERROR_OK;
 503 }
 504 #endif
 505
 506 /* Read device id register, main clock frequency register and fill in driver info structure */
 507 static int stellaris_read_part_info(struct flash_bank *bank)
 508 {
 509         struct stellaris_flash_bank *stellaris_info = stellaris_bank_data(bank);
 510         struct target *target = bank->target;
 511         uint32_t did0, did1, ver, fam, status;
 512         int i;
 513
 514         /* Read and parse chip identification register */
 515         target_read_u32(target, SCB_BASE | DID0, &did0);
 516         target_read_u32(target, SCB_BASE | DID1, &did1);
 517         target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
 518         target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
 519         LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
 520                   did0, did1, stellaris_info->dc0, stellaris_info->dc1);
 521
 522         ver = did0 >> 28;
 523         if ((ver != 0) && (ver != 1))
 524         {
 525                 LOG_WARNING("Unknown did0 version, cannot identify target");
 526                 return ERROR_FLASH_OPERATION_FAILED;
 527         }
 528
 529         if (did1 == 0)
 530         {
 531                 LOG_WARNING("Cannot identify target as a Stellaris");
 532                 return ERROR_FLASH_OPERATION_FAILED;
 533         }
 534
 535         ver = did1 >> 28;
 536         fam = (did1 >> 24) & 0xF;
 537         if (((ver != 0) && (ver != 1)) || (fam != 0))
 538         {
 539                 LOG_WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
 540         }
 541
 542         /* For Sandstorm, Fury, DustDevil:  current data sheets say IOSC
 543          * is 12 MHz, but some older parts have 15 MHz.  A few data sheets
 544          * even give _both_ numbers!  We'll use current numbers; IOSC is
 545          * always approximate.
 546          *
 547          * For Tempest:  IOSC is calibrated, 16 MHz
 548          */
 549         stellaris_info->iosc_freq = 12000000;
 550         stellaris_info->iosc_desc = " (±30%)";
 551         stellaris_info->xtal_mask = 0x0f;
 552
 553         switch ((did0 >> 28) & 0x7) {
 554         case 0:                         /* Sandstorm */
 555                 /*
 556                  * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
 557                  * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
 558                  * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
 559                  */
 560                 if (((did0 >> 8) & 0xff) < 2) {
 561                         stellaris_info->iosc_freq = 15000000;
 562                         stellaris_info->iosc_desc = " (±50%)";
 563                 }
 564                 break;
 565         case 1:
 566                 switch ((did0 >> 16) & 0xff) {
 567                 case 1:                 /* Fury */
 568                         break;
 569                 case 4:                 /* Tempest */
 570                         stellaris_info->iosc_freq = 16000000;   /* +/- 1% */
 571                         stellaris_info->iosc_desc = " (±1%)";
 572                         /* FALL THROUGH */
 573                 case 3:                 /* DustDevil */
 574                         stellaris_info->xtal_mask = 0x1f;
 575                         break;
 576                 default:
 577                         LOG_WARNING("Unknown did0 class");
 578                 }
 579         default:
 580                 break;
 581                 LOG_WARNING("Unknown did0 version");
 582         }
 583
 584         for (i = 0; StellarisParts[i].partno; i++)
 585         {
 586                 if (StellarisParts[i].partno == ((did1 >> 16) & 0xFF))
 587                         break;
 588         }
 589
 590         stellaris_info->target_name = StellarisParts[i].partname;
 591
 592         stellaris_info->did0 = did0;
 593         stellaris_info->did1 = did1;
 594
 595         stellaris_info->num_lockbits = 1 + (stellaris_info->dc0 & 0xFFFF);
 596         stellaris_info->num_pages = 2 *(1 + (stellaris_info->dc0 & 0xFFFF));
 597         stellaris_info->pagesize = 1024;
 598         bank->size = 1024 * stellaris_info->num_pages;
 599         stellaris_info->pages_in_lockregion = 2;
 600         target_read_u32(target, SCB_BASE | FMPPE, &stellaris_info->lockbits);
 601
 602         /* provide this for the benefit of the higher flash driver layers */
 603         bank->num_sectors = stellaris_info->num_pages;
 604         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 605         for (i = 0; i < bank->num_sectors; i++)
 606         {
 607                 bank->sectors[i].offset = i * stellaris_info->pagesize;
 608                 bank->sectors[i].size = stellaris_info->pagesize;
 609                 bank->sectors[i].is_erased = -1;
 610                 bank->sectors[i].is_protected = -1;
 611         }
 612
 613         /* Read main and master clock freqency register */
 614         stellaris_read_clock_info(bank);
 615
 616         status = stellaris_get_flash_status(bank);
 617
 618         return ERROR_OK;
 619 }
 620
 621 /***************************************************************************
 622 *       flash operations                                                       *
 623 ***************************************************************************/
 624
 625 static int stellaris_protect_check(struct flash_bank *bank)
 626 {
 627         uint32_t status;
 628
 629         struct stellaris_flash_bank *stellaris_info = stellaris_bank_data(bank);
 630
 631         if (bank->target->state != TARGET_HALTED)
 632         {
 633                 LOG_ERROR("Target not halted");
 634                 return ERROR_TARGET_NOT_HALTED;
 635         }
 636
 637         if (stellaris_info->did1 == 0)
 638         {
 639                 stellaris_read_part_info(bank);
 640         }
 641
 642         if (stellaris_info->did1 == 0)
 643         {
 644                 LOG_WARNING("Cannot identify target as Stellaris");
 645                 return ERROR_FLASH_OPERATION_FAILED;
 646         }
 647
 648         status = stellaris_get_flash_status(bank);
 649         stellaris_info->lockbits = status >> 16;
 650
 651         return ERROR_OK;
 652 }
 653
 654 static int stellaris_erase(struct flash_bank *bank, int first, int last)
 655 {
 656         int banknr;
 657         uint32_t flash_fmc, flash_cris;
 658         struct stellaris_flash_bank *stellaris_info = stellaris_bank_data(bank);
 659         struct target *target = bank->target;
 660
 661         if (bank->target->state != TARGET_HALTED)
 662         {
 663                 LOG_ERROR("Target not halted");
 664                 return ERROR_TARGET_NOT_HALTED;
 665         }
 666
 667         if (stellaris_info->did1 == 0)
 668         {
 669                 stellaris_read_part_info(bank);
 670         }
 671
 672         if (stellaris_info->did1 == 0)
 673         {
 674                 LOG_WARNING("Cannot identify target as Stellaris");
 675                 return ERROR_FLASH_OPERATION_FAILED;
 676         }
 677
 678         if ((first < 0) || (last < first) || (last >= (int)stellaris_info->num_pages))
 679         {
 680                 return ERROR_FLASH_SECTOR_INVALID;
 681         }
 682
 683         if ((first == 0) && (last == ((int)stellaris_info->num_pages-1)))
 684         {
 685                 return stellaris_mass_erase(bank);
 686         }
 687
 688         /* Configure the flash controller timing */
 689         stellaris_read_clock_info(bank);
 690         stellaris_set_flash_mode(bank,0);
 691
 692         /* Clear and disable flash programming interrupts */
 693         target_write_u32(target, FLASH_CIM, 0);
 694         target_write_u32(target, FLASH_MISC, PMISC | AMISC);
 695
 696         for (banknr = first; banknr <= last; banknr++)
 697         {
 698                 /* Address is first word in page */
 699                 target_write_u32(target, FLASH_FMA, banknr * stellaris_info->pagesize);
 700                 /* Write erase command */
 701                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_ERASE);
 702                 /* Wait until erase complete */
 703                 do
 704                 {
 705                         target_read_u32(target, FLASH_FMC, &flash_fmc);
 706                 }
 707                 while (flash_fmc & FMC_ERASE);
 708
 709                 /* Check acess violations */
 710                 target_read_u32(target, FLASH_CRIS, &flash_cris);
 711                 if (flash_cris & (AMASK))
 712                 {
 713                         LOG_WARNING("Error erasing flash page %i,  flash_cris 0x%" PRIx32 "", banknr, flash_cris);
 714                         target_write_u32(target, FLASH_CRIS, 0);
 715                         return ERROR_FLASH_OPERATION_FAILED;
 716                 }
 717
 718                 bank->sectors[banknr].is_erased = 1;
 719         }
 720
 721         return ERROR_OK;
 722 }
 723
 724 static int stellaris_protect(struct flash_bank *bank, int set, int first, int last)
 725 {
 726         uint32_t fmppe, flash_fmc, flash_cris;
 727         int lockregion;
 728
 729         struct stellaris_flash_bank *stellaris_info = stellaris_bank_data(bank);
 730         struct target *target = bank->target;
 731
 732         if (bank->target->state != TARGET_HALTED)
 733         {
 734                 LOG_ERROR("Target not halted");
 735                 return ERROR_TARGET_NOT_HALTED;
 736         }
 737
 738         if ((first < 0) || (last < first) || (last >= stellaris_info->num_lockbits))
 739         {
 740                 return ERROR_FLASH_SECTOR_INVALID;
 741         }
 742
 743         if (stellaris_info->did1 == 0)
 744         {
 745                 stellaris_read_part_info(bank);
 746         }
 747
 748         if (stellaris_info->did1 == 0)
 749         {
 750                 LOG_WARNING("Cannot identify target as an Stellaris MCU");
 751                 return ERROR_FLASH_OPERATION_FAILED;
 752         }
 753
 754         /* Configure the flash controller timing */
 755         stellaris_read_clock_info(bank);
 756         stellaris_set_flash_mode(bank, 0);
 757
 758         fmppe = stellaris_info->lockbits;
 759         for (lockregion = first; lockregion <= last; lockregion++)
 760         {
 761                 if (set)
 762                         fmppe &= ~(1 << lockregion);
 763                 else
 764                         fmppe |= (1 << lockregion);
 765         }
 766
 767         /* Clear and disable flash programming interrupts */
 768         target_write_u32(target, FLASH_CIM, 0);
 769         target_write_u32(target, FLASH_MISC, PMISC | AMISC);
 770
 771         LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe);
 772         target_write_u32(target, SCB_BASE | FMPPE, fmppe);
 773         /* Commit FMPPE */
 774         target_write_u32(target, FLASH_FMA, 1);
 775         /* Write commit command */
 776         /* TODO safety check, sice this cannot be undone */
 777         LOG_WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
 778         /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
 779         /* Wait until erase complete */
 780         do
 781         {
 782                 target_read_u32(target, FLASH_FMC, &flash_fmc);
 783         }
 784         while (flash_fmc & FMC_COMT);
 785
 786         /* Check acess violations */
 787         target_read_u32(target, FLASH_CRIS, &flash_cris);
 788         if (flash_cris & (AMASK))
 789         {
 790                 LOG_WARNING("Error setting flash page protection,  flash_cris 0x%" PRIx32 "", flash_cris);
 791                 target_write_u32(target, FLASH_CRIS, 0);
 792                 return ERROR_FLASH_OPERATION_FAILED;
 793         }
 794
 795         target_read_u32(target, SCB_BASE | FMPPE, &stellaris_info->lockbits);
 796
 797         return ERROR_OK;
 798 }
 799
 800 static uint8_t stellaris_write_code[] =
 801 {
 802 /*
 803         Call with :
 804         r0 = buffer address
 805         r1 = destination address
 806         r2 = bytecount (in) - endaddr (work)
 807
 808         Used registers:
 809         r3 = pFLASH_CTRL_BASE
 810         r4 = FLASHWRITECMD
 811         r5 = #1
 812         r6 = bytes written
 813         r7 = temp reg
 814 */
 815         0x07,0x4B,                      /* ldr r3,pFLASH_CTRL_BASE */
 816         0x08,0x4C,                      /* ldr r4,FLASHWRITECMD */
 817         0x01,0x25,                      /* movs r5, 1 */
 818         0x00,0x26,                      /* movs r6, #0 */
 819 /* mainloop: */
 820         0x19,0x60,                      /* str  r1, [r3, #0] */
 821         0x87,0x59,                      /* ldr  r7, [r0, r6] */
 822         0x5F,0x60,                      /* str  r7, [r3, #4] */
 823         0x9C,0x60,                      /* str  r4, [r3, #8] */
 824 /* waitloop: */
 825         0x9F,0x68,                      /* ldr  r7, [r3, #8] */
 826         0x2F,0x42,                      /* tst  r7, r5 */
 827         0xFC,0xD1,                      /* bne  waitloop */
 828         0x04,0x31,                      /* adds r1, r1, #4 */
 829         0x04,0x36,                      /* adds r6, r6, #4 */
 830         0x96,0x42,                      /* cmp  r6, r2 */
 831         0xF4,0xD1,                      /* bne  mainloop */
 832                                                 /* exit: */
 833         0xFE,0xE7,                      /* b exit */
 834 /* pFLASH_CTRL_BASE: */
 835         0x00,0xD0,0x0F,0x40,    /* .word        0x400FD000 */
 836 /* FLASHWRITECMD: */
 837         0x01,0x00,0x42,0xA4     /* .word        0xA4420001 */
 838 };
 839
 840 static int stellaris_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t wcount)
 841 {
 842         struct target *target = bank->target;
 843         uint32_t buffer_size = 8192;
 844         struct working_area *source;
 845         struct working_area *write_algorithm;
 846         uint32_t address = bank->base + offset;
 847         struct reg_param reg_params[3];
 848         struct armv7m_algorithm armv7m_info;
 849         int retval = ERROR_OK;
 850
 851         LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
 852                         bank, buffer, offset, wcount);
 853
 854         /* flash write code */
 855         if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
 856         {
 857                 LOG_WARNING("no working area available, can't do block memory writes");
 858                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 859         };
 860
 861         target_write_buffer(target, write_algorithm->address, sizeof(stellaris_write_code), stellaris_write_code);
 862
 863         /* memory buffer */
 864         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
 865         {
 866                 LOG_DEBUG("called target_alloc_working_area(target=%p buffer_size=%08" PRIx32 " source=%p)",
 867                                 target, buffer_size, source);
 868                 buffer_size /= 2;
 869                 if (buffer_size <= 256)
 870                 {
 871                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
 872                         if (write_algorithm)
 873                                 target_free_working_area(target, write_algorithm);
 874
 875                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 876                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 877                 }
 878         };
 879
 880         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 881         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 882
 883         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 884         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 885         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 886
 887         while (wcount > 0)
 888         {
 889                 uint32_t thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
 890
 891                 target_write_buffer(target, source->address, thisrun_count * 4, buffer);
 892
 893                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 894                 buf_set_u32(reg_params[1].value, 0, 32, address);
 895                 buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
 896                 LOG_INFO("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
 897                 LOG_DEBUG("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
 898                 if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
 899                 {
 900                         LOG_ERROR("error executing stellaris flash write algorithm");
 901                         retval = ERROR_FLASH_OPERATION_FAILED;
 902                         break;
 903                 }
 904
 905                 buffer += thisrun_count * 4;
 906                 address += thisrun_count * 4;
 907                 wcount -= thisrun_count;
 908         }
 909
 910         target_free_working_area(target, write_algorithm);
 911         target_free_working_area(target, source);
 912
 913         destroy_reg_param(&reg_params[0]);
 914         destroy_reg_param(&reg_params[1]);
 915         destroy_reg_param(&reg_params[2]);
 916
 917         return retval;
 918 }
 919
 920 static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
 921 {
 922         struct stellaris_flash_bank *stellaris_info = stellaris_bank_data(bank);
 923         struct target *target = bank->target;
 924         uint32_t address = offset;
 925         uint32_t flash_cris, flash_fmc;
 926         uint32_t words_remaining = (count / 4);
 927         uint32_t bytes_remaining = (count & 0x00000003);
 928         uint32_t bytes_written = 0;
 929         int retval;
 930
 931         if (bank->target->state != TARGET_HALTED)
 932         {
 933                 LOG_ERROR("Target not halted");
 934                 return ERROR_TARGET_NOT_HALTED;
 935         }
 936
 937         LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
 938                         bank, buffer, offset, count);
 939
 940         if (stellaris_info->did1 == 0)
 941         {
 942                 stellaris_read_part_info(bank);
 943         }
 944
 945         if (stellaris_info->did1 == 0)
 946         {
 947                 LOG_WARNING("Cannot identify target as a Stellaris processor");
 948                 return ERROR_FLASH_OPERATION_FAILED;
 949         }
 950
 951         if (offset & 0x3)
 952         {
 953                 LOG_WARNING("offset size must be word aligned");
 954                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 955         }
 956
 957         if (offset + count > bank->size)
 958                 return ERROR_FLASH_DST_OUT_OF_BANK;
 959
 960         /* Configure the flash controller timing */
 961         stellaris_read_clock_info(bank);
 962         stellaris_set_flash_mode(bank, 0);
 963
 964         /* Clear and disable flash programming interrupts */
 965         target_write_u32(target, FLASH_CIM, 0);
 966         target_write_u32(target, FLASH_MISC, PMISC | AMISC);
 967
 968         /* multiple words to be programmed? */
 969         if (words_remaining > 0)
 970         {
 971                 /* try using a block write */
 972                 if ((retval = stellaris_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 973                 {
 974                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 975                         {
 976                                 /* if block write failed (no sufficient working area),
 977                                  * we use normal (slow) single dword accesses */
 978                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 979                         }
 980                         else if (retval == ERROR_FLASH_OPERATION_FAILED)
 981                         {
 982                                 /* if an error occured, we examine the reason, and quit */
 983                                 target_read_u32(target, FLASH_CRIS, &flash_cris);
 984
 985                                 LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
 986                                 return ERROR_FLASH_OPERATION_FAILED;
 987                         }
 988                 }
 989                 else
 990                 {
 991                         buffer += words_remaining * 4;
 992                         address += words_remaining * 4;
 993                         words_remaining = 0;
 994                 }
 995         }
 996
 997         while (words_remaining > 0)
 998         {
 999                 if (!(address & 0xff))
1000                         LOG_DEBUG("0x%" PRIx32 "", address);
1001
1002                 /* Program one word */
1003                 target_write_u32(target, FLASH_FMA, address);
1004                 target_write_buffer(target, FLASH_FMD, 4, buffer);
1005                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
1006                 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1007                 /* Wait until write complete */
1008                 do
1009                 {
1010                         target_read_u32(target, FLASH_FMC, &flash_fmc);
1011                 } while (flash_fmc & FMC_WRITE);
1012
1013                 buffer += 4;
1014                 address += 4;
1015                 words_remaining--;
1016         }
1017
1018         if (bytes_remaining)
1019         {
1020                 uint8_t last_word[4] = {0xff, 0xff, 0xff, 0xff};
1021                 int i = 0;
1022
1023                 while (bytes_remaining > 0)
1024                 {
1025                         last_word[i++] = *(buffer + bytes_written);
1026                         bytes_remaining--;
1027                         bytes_written++;
1028                 }
1029
1030                 if (!(address & 0xff))
1031                         LOG_DEBUG("0x%" PRIx32 "", address);
1032
1033                 /* Program one word */
1034                 target_write_u32(target, FLASH_FMA, address);
1035                 target_write_buffer(target, FLASH_FMD, 4, last_word);
1036                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_WRITE);
1037                 /* LOG_DEBUG("0x%x 0x%x 0x%x",address,buf_get_u32(buffer, 0, 32),FMC_WRKEY | FMC_WRITE); */
1038                 /* Wait until write complete */
1039                 do
1040                 {
1041                         target_read_u32(target, FLASH_FMC, &flash_fmc);
1042                 } while (flash_fmc & FMC_WRITE);
1043         }
1044
1045         /* Check access violations */
1046         target_read_u32(target, FLASH_CRIS, &flash_cris);
1047         if (flash_cris & (AMASK))
1048         {
1049                 LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
1050                 return ERROR_FLASH_OPERATION_FAILED;
1051         }
1052         return ERROR_OK;
1053 }
1054
1055 static int stellaris_probe(struct flash_bank *bank)
1056 {
1057         /* we can't probe on an stellaris
1058          * if this is an stellaris, it has the configured flash
1059          */
1060
1061         if (bank->target->state != TARGET_HALTED)
1062         {
1063                 LOG_ERROR("Target not halted");
1064                 return ERROR_TARGET_NOT_HALTED;
1065         }
1066
1067         /* stellaris_read_part_info() already takes care about error checking and reporting */
1068         return stellaris_read_part_info(bank);
1069 }
1070
1071 static int stellaris_auto_probe(struct flash_bank *bank)
1072 {
1073         struct stellaris_flash_bank *stellaris_info = stellaris_bank_data(bank);
1074         if (stellaris_info->did1)
1075                 return ERROR_OK;
1076         return stellaris_probe(bank);
1077 }
1078
1079 static int stellaris_mass_erase(struct flash_bank *bank)
1080 {
1081         struct target *target = NULL;
1082         struct stellaris_flash_bank *stellaris_info = NULL;
1083         uint32_t flash_fmc;
1084
1085         stellaris_info = stellaris_bank_data(bank);
1086         target = bank->target;
1087
1088         if (target->state != TARGET_HALTED)
1089         {
1090                 LOG_ERROR("Target not halted");
1091                 return ERROR_TARGET_NOT_HALTED;
1092         }
1093
1094         if (stellaris_info->did1 == 0)
1095         {
1096                 stellaris_read_part_info(bank);
1097         }
1098
1099         if (stellaris_info->did1 == 0)
1100         {
1101                 LOG_WARNING("Cannot identify target as Stellaris");
1102                 return ERROR_FLASH_OPERATION_FAILED;
1103         }
1104
1105         /* Configure the flash controller timing */
1106         stellaris_read_clock_info(bank);
1107         stellaris_set_flash_mode(bank, 0);
1108
1109         /* Clear and disable flash programming interrupts */
1110         target_write_u32(target, FLASH_CIM, 0);
1111         target_write_u32(target, FLASH_MISC, PMISC | AMISC);
1112
1113         target_write_u32(target, FLASH_FMA, 0);
1114         target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
1115         /* Wait until erase complete */
1116         do
1117         {
1118                 target_read_u32(target, FLASH_FMC, &flash_fmc);
1119         }
1120         while (flash_fmc & FMC_MERASE);
1121
1122         /* if device has > 128k, then second erase cycle is needed
1123          * this is only valid for older devices, but will not hurt */
1124         if (stellaris_info->num_pages * stellaris_info->pagesize > 0x20000)
1125         {
1126                 target_write_u32(target, FLASH_FMA, 0x20000);
1127                 target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE);
1128                 /* Wait until erase complete */
1129                 do
1130                 {
1131                         target_read_u32(target, FLASH_FMC, &flash_fmc);
1132                 }
1133                 while (flash_fmc & FMC_MERASE);
1134         }
1135
1136         return ERROR_OK;
1137 }
1138
1139 COMMAND_HANDLER(stellaris_handle_mass_erase_command)
1140 {
1141         int i;
1142
1143         if (CMD_ARGC < 1)
1144         {
1145                 command_print(CMD_CTX, "stellaris mass_erase <bank>");
1146                 return ERROR_OK;
1147         }
1148
1149         struct flash_bank *bank;
1150         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1151         if (ERROR_OK != retval)
1152                 return retval;
1153
1154         if (stellaris_mass_erase(bank) == ERROR_OK)
1155         {
1156                 /* set all sectors as erased */
1157                 for (i = 0; i < bank->num_sectors; i++)
1158                 {
1159                         bank->sectors[i].is_erased = 1;
1160                 }
1161
1162                 command_print(CMD_CTX, "stellaris mass erase complete");
1163         }
1164         else
1165         {
1166                 command_print(CMD_CTX, "stellaris mass erase failed");
1167         }
1168
1169         return ERROR_OK;
1170 }
1171
1172 static const struct command_registration stellaris_exec_command_handlers[] = {
1173         {
1174                 .name = "mass_erase",
1175                 .handler = &stellaris_handle_mass_erase_command,
1176                 .mode = COMMAND_EXEC,
1177                 .help = "erase entire device",
1178         },
1179         COMMAND_REGISTRATION_DONE
1180 };
1181 static const struct command_registration stellaris_command_handlers[] = {
1182         {
1183                 .name = "stellaris",
1184                 .mode = COMMAND_ANY,
1185                 .help = "Stellaris flash command group",
1186                 .chain = stellaris_exec_command_handlers,
1187         },
1188         COMMAND_REGISTRATION_DONE
1189 };
1190
1191 FLASH_DRIVER(stellaris,
1192                 &stellaris_flash_bank_command, stellaris_command_handlers,
1193                 .erase = &stellaris_erase,
1194                 .protect = &stellaris_protect,
1195                 .write = &stellaris_write,
1196                 .probe = &stellaris_probe,
1197                 .auto_probe = &stellaris_auto_probe,
1198                 .erase_check = &default_flash_mem_blank_check,
1199                 .protect_check = &stellaris_protect_check,
1200                 .info = &stellaris_info,
1201         );