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nor: use common flash driver
[openocd/ztw.git] / src / flash / nor / pic32mx.c
bloba7cebbb79210dbdf77812af15e4d3a9af221f87e
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by John McCarthy *
9 * jgmcc@magma.ca *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26 #ifdef HAVE_CONFIG_H
27 #include "config.h"
28 #endif
29
30 #include "imp.h"
31 #include "pic32mx.h"
32 #include <target/mips32.h>
33
34
35 static
36 struct pic32mx_devs_s {
37 uint8_t devid;
38 char *name;
39 uint32_t pfm_size;
40 } pic32mx_devs[] = {
41 { 0x78, "460F512L USB", 512 },
42 { 0x74, "460F256L USB", 256 },
43 { 0x6D, "440F128L USB", 128 },
44 { 0x56, "440F512H USB", 512 },
45 { 0x52, "440F256H USB", 256 },
46 { 0x4D, "440F128H USB", 128 },
47 { 0x42, "420F032H USB", 32 },
48 { 0x38, "360F512L", 512 },
49 { 0x34, "360F256L", 256 },
50 { 0x2D, "340F128L", 128 },
51 { 0x2A, "320F128L", 128 },
52 { 0x16, "340F512H", 512 },
53 { 0x12, "340F256H", 256 },
54 { 0x0D, "340F128H", 128 },
55 { 0x0A, "320F128H", 128 },
56 { 0x06, "320F064H", 64 },
57 { 0x02, "320F032H", 32 },
58 { 0x00, NULL, 0 }
59 };
60
61 static int pic32mx_write_row(struct flash_bank *bank, uint32_t address, uint32_t srcaddr);
62 static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_t word);
63
64 /* flash bank pic32mx <base> <size> 0 0 <target#>
65 */
66 FLASH_BANK_COMMAND_HANDLER(pic32mx_flash_bank_command)
67 {
68 struct pic32mx_flash_bank *pic32mx_info;
69
70 if (CMD_ARGC < 6)
71 {
72 LOG_WARNING("incomplete flash_bank pic32mx configuration");
73 return ERROR_FLASH_BANK_INVALID;
74 }
75
76 pic32mx_info = malloc(sizeof(struct pic32mx_flash_bank));
77
78 struct flash_bank *bank = flash_bank_from_object(object);
79 set_flash_bank_data(bank, pic32mx_info);
80
81 pic32mx_info->write_algorithm = NULL;
82 pic32mx_info->probed = 0;
83
84 return ERROR_OK;
85 }
86
87 static uint32_t pic32mx_get_flash_status(struct flash_bank *bank)
88 {
89 struct target *target = bank->target;
90 uint32_t status;
91
92 target_read_u32(target, PIC32MX_NVMCON, &status);
93
94 return status;
95 }
96
97 static uint32_t pic32mx_wait_status_busy(struct flash_bank *bank, int timeout)
98 {
99 uint32_t status;
100
101 /* wait for busy to clear */
102 while (((status = pic32mx_get_flash_status(bank)) & NVMCON_NVMWR) && (timeout-- > 0))
103 {
104 LOG_DEBUG("status: 0x%" PRIx32, status);
105 alive_sleep(1);
106 }
107 if (timeout <= 0)
108 LOG_DEBUG("timeout: status: 0x%" PRIx32, status);
109
110 return status;
111 }
112
113 static int pic32mx_nvm_exec(struct flash_bank *bank, uint32_t op, uint32_t timeout)
114 {
115 struct target *target = bank->target;
116 uint32_t status;
117
118 target_write_u32(target, PIC32MX_NVMCON, NVMCON_NVMWREN | op);
119
120 /* unlock flash registers */
121 target_write_u32(target, PIC32MX_NVMKEY, NVMKEY1);
122 target_write_u32(target, PIC32MX_NVMKEY, NVMKEY2);
123
124 /* start operation */
125 target_write_u32(target, PIC32MX_NVMCONSET, NVMCON_NVMWR);
126
127 status = pic32mx_wait_status_busy(bank, timeout);
128
129 /* lock flash registers */
130 target_write_u32(target, PIC32MX_NVMCONCLR, NVMCON_NVMWREN);
131
132 return status;
133 }
134
135 static int pic32mx_protect_check(struct flash_bank *bank)
136 {
137 struct target *target = bank->target;
138
139 uint32_t devcfg0;
140 int s;
141 int num_pages;
142
143 if (target->state != TARGET_HALTED)
144 {
145 LOG_ERROR("Target not halted");
146 return ERROR_TARGET_NOT_HALTED;
147 }
148
149 target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);
150 if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
151 num_pages = 0xffff; /* All pages protected */
152 else if (bank->base == PIC32MX_KSEG1_BOOT_FLASH)
153 {
154 if (devcfg0 & (1 << 24))
155 num_pages = 0; /* All pages unprotected */
156 else
157 num_pages = 0xffff; /* All pages protected */
158 }
159 else /* pgm flash */
160 num_pages = (~devcfg0 >> 12) & 0xff;
161 for (s = 0; s < bank->num_sectors && s < num_pages; s++)
162 bank->sectors[s].is_protected = 1;
163 for (; s < bank->num_sectors; s++)
164 bank->sectors[s].is_protected = 0;
165
166 return ERROR_OK;
167 }
168
169 static int pic32mx_erase(struct flash_bank *bank, int first, int last)
170 {
171 struct target *target = bank->target;
172 int i;
173 uint32_t status;
174
175 if (bank->target->state != TARGET_HALTED)
176 {
177 LOG_ERROR("Target not halted");
178 return ERROR_TARGET_NOT_HALTED;
179 }
180
181 if ((first == 0) && (last == (bank->num_sectors - 1)) && (bank->base == PIC32MX_KSEG0_PGM_FLASH || bank->base == PIC32MX_KSEG1_PGM_FLASH))
182 {
183 LOG_DEBUG("Erasing entire program flash");
184 status = pic32mx_nvm_exec(bank, NVMCON_OP_PFM_ERASE, 50);
185 if (status & NVMCON_NVMERR)
186 return ERROR_FLASH_OPERATION_FAILED;
187 if (status & NVMCON_LVDERR)
188 return ERROR_FLASH_OPERATION_FAILED;
189 return ERROR_OK;
190 }
191
192 for (i = first; i <= last; i++)
193 {
194 if (bank->base >= PIC32MX_KSEG1_PGM_FLASH)
195 target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(bank->base + bank->sectors[i].offset));
196 else
197 target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(bank->base + bank->sectors[i].offset));
198
199 status = pic32mx_nvm_exec(bank, NVMCON_OP_PAGE_ERASE, 10);
200
201 if (status & NVMCON_NVMERR)
202 return ERROR_FLASH_OPERATION_FAILED;
203 if (status & NVMCON_LVDERR)
204 return ERROR_FLASH_OPERATION_FAILED;
205 bank->sectors[i].is_erased = 1;
206 }
207
208 return ERROR_OK;
209 }
210
211 static struct pic32mx_flash_bank *pic32mx_bank_data(struct flash_bank *bank)
212 {
213 return (struct pic32mx_flash_bank *)flash_bank_data(bank);
214 }
215
216 static int pic32mx_protect(struct flash_bank *bank, int set, int first, int last)
217 {
218 struct pic32mx_flash_bank *pic32mx_info = NULL;
219 struct target *target = bank->target;
220 #if 0
221 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
222 int i, reg, bit;
223 int status;
224 uint32_t protection;
225 #endif
226
227 pic32mx_info = pic32mx_bank_data(bank);
228
229 if (target->state != TARGET_HALTED)
230 {
231 LOG_ERROR("Target not halted");
232 return ERROR_TARGET_NOT_HALTED;
233 }
234
235 #if 0
236 if ((first && (first % pic32mx_info->ppage_size)) || ((last + 1) && (last + 1) % pic32mx_info->ppage_size))
237 {
238 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", pic32mx_info->ppage_size);
239 return ERROR_FLASH_SECTOR_INVALID;
240 }
241
242 /* medium density - each bit refers to a 4bank protection
243 * high density - each bit refers to a 2bank protection */
244 target_read_u32(target, PIC32MX_FLASH_WRPR, &protection);
245
246 prot_reg[0] = (uint16_t)protection;
247 prot_reg[1] = (uint16_t)(protection >> 8);
248 prot_reg[2] = (uint16_t)(protection >> 16);
249 prot_reg[3] = (uint16_t)(protection >> 24);
250
251 if (pic32mx_info->ppage_size == 2)
252 {
253 /* high density flash */
254
255 /* bit 7 controls sector 62 - 255 protection */
256 if (last > 61)
257 {
258 if (set)
259 prot_reg[3] &= ~(1 << 7);
260 else
261 prot_reg[3] |= (1 << 7);
262 }
263
264 if (first > 61)
265 first = 62;
266 if (last > 61)
267 last = 61;
268
269 for (i = first; i <= last; i++)
270 {
271 reg = (i / pic32mx_info->ppage_size) / 8;
272 bit = (i / pic32mx_info->ppage_size) - (reg * 8);
273
274 if (set)
275 prot_reg[reg] &= ~(1 << bit);
276 else
277 prot_reg[reg] |= (1 << bit);
278 }
279 }
280 else
281 {
282 /* medium density flash */
283 for (i = first; i <= last; i++)
284 {
285 reg = (i / pic32mx_info->ppage_size) / 8;
286 bit = (i / pic32mx_info->ppage_size) - (reg * 8);
287
288 if (set)
289 prot_reg[reg] &= ~(1 << bit);
290 else
291 prot_reg[reg] |= (1 << bit);
292 }
293 }
294
295 if ((status = pic32mx_erase_options(bank)) != ERROR_OK)
296 return status;
297
298 pic32mx_info->option_bytes.protection[0] = prot_reg[0];
299 pic32mx_info->option_bytes.protection[1] = prot_reg[1];
300 pic32mx_info->option_bytes.protection[2] = prot_reg[2];
301 pic32mx_info->option_bytes.protection[3] = prot_reg[3];
302
303 return pic32mx_write_options(bank);
304 #else
305 return ERROR_OK;
306 #endif
307 }
308
309 static int pic32mx_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
310 {
311 struct target *target = bank->target;
312 uint32_t buffer_size = 512;
313 struct working_area *source;
314 uint32_t address = bank->base + offset;
315 int retval = ERROR_OK;
316 #if 0
317 struct pic32mx_flash_bank *pic32mx_info = pic32mx_bank_data(bank);
318 struct armv7m_algorithm armv7m_info;
319
320 uint8_t pic32mx_flash_write_code[] = {
321 /* write: */
322 0xDF, 0xF8, 0x24, 0x40, /* ldr r4, PIC32MX_FLASH_CR */
323 0x09, 0x4D, /* ldr r5, PIC32MX_FLASH_SR */
324 0x4F, 0xF0, 0x01, 0x03, /* mov r3, #1 */
325 0x23, 0x60, /* str r3, [r4, #0] */
326 0x30, 0xF8, 0x02, 0x3B, /* ldrh r3, [r0], #2 */
327 0x21, 0xF8, 0x02, 0x3B, /* strh r3, [r1], #2 */
328 /* busy: */
329 0x2B, 0x68, /* ldr r3, [r5, #0] */
330 0x13, 0xF0, 0x01, 0x0F, /* tst r3, #0x01 */
331 0xFB, 0xD0, /* beq busy */
332 0x13, 0xF0, 0x14, 0x0F, /* tst r3, #0x14 */
333 0x01, 0xD1, /* bne exit */
334 0x01, 0x3A, /* subs r2, r2, #1 */
335 0xED, 0xD1, /* bne write */
336 /* exit: */
337 0xFE, 0xE7, /* b exit */
338 0x10, 0x20, 0x02, 0x40, /* PIC32MX_FLASH_CR: .word 0x40022010 */
339 0x0C, 0x20, 0x02, 0x40 /* PIC32MX_FLASH_SR: .word 0x4002200C */
340 };
341
342 /* flash write code */
343 if (target_alloc_working_area(target, sizeof(pic32mx_flash_write_code), &pic32mx_info->write_algorithm) != ERROR_OK)
344 {
345 LOG_WARNING("no working area available, can't do block memory writes");
346 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
347 };
348
349 if ((retval = target_write_buffer(target, pic32mx_info->write_algorithm->address, sizeof(pic32mx_flash_write_code), pic32mx_flash_write_code)) != ERROR_OK)
350 return retval;
351 #endif
352
353 /* memory buffer */
354 if (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
355 {
356 #if 0
357 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
358 if (pic32mx_info->write_algorithm)
359 target_free_working_area(target, pic32mx_info->write_algorithm);
360 #endif
361
362 LOG_WARNING("no large enough working area available, can't do block memory writes");
363 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
364 }
365
366 while (count >= buffer_size/4)
367 {
368 uint32_t status;
369
370 if ((retval = target_write_buffer(target, source->address, buffer_size, buffer)) != ERROR_OK) {
371 LOG_ERROR("Failed to write row buffer (%d words) to RAM", (int)(buffer_size/4));
372 break;
373 }
374
375 #if 0
376 buf_set_u32(reg_params[0].value, 0, 32, source->address);
377 buf_set_u32(reg_params[1].value, 0, 32, address);
378 buf_set_u32(reg_params[2].value, 0, 32, buffer_size/4);
379
380 if ((retval = target_run_algorithm(target, 0, NULL, 4, reg_params, pic32mx_info->write_algorithm->address, \
381 pic32mx_info->write_algorithm->address + (sizeof(pic32mx_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
382 {
383 LOG_ERROR("error executing pic32mx flash write algorithm");
384 retval = ERROR_FLASH_OPERATION_FAILED;
385 break;
386 }
387
388 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
389 {
390 retval = ERROR_FLASH_OPERATION_FAILED;
391 break;
392 }
393 #endif
394 status = pic32mx_write_row(bank, address, source->address);
395 if (status & NVMCON_NVMERR) {
396 LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
397 retval = ERROR_FLASH_OPERATION_FAILED;
398 break;
399 }
400 if (status & NVMCON_LVDERR) {
401 LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
402 retval = ERROR_FLASH_OPERATION_FAILED;
403 break;
404 }
405
406 buffer += buffer_size;
407 address += buffer_size;
408 count -= buffer_size/4;
409 }
410
411 target_free_working_area(target, source);
412
413 while (count > 0)
414 {
415 uint32_t value;
416 memcpy(&value, buffer, sizeof(uint32_t));
417
418 uint32_t status = pic32mx_write_word(bank, address, value);
419 if (status & NVMCON_NVMERR) {
420 LOG_ERROR("Flash write error NVMERR (status = 0x%08" PRIx32 ")", status);
421 retval = ERROR_FLASH_OPERATION_FAILED;
422 break;
423 }
424 if (status & NVMCON_LVDERR) {
425 LOG_ERROR("Flash write error LVDERR (status = 0x%08" PRIx32 ")", status);
426 retval = ERROR_FLASH_OPERATION_FAILED;
427 break;
428 }
429
430 buffer += 4;
431 address += 4;
432 count--;
433 }
434
435 return retval;
436 }
437
438 static int pic32mx_write_word(struct flash_bank *bank, uint32_t address, uint32_t word)
439 {
440 struct target *target = bank->target;
441
442 if (bank->base >= PIC32MX_KSEG1_PGM_FLASH)
443 target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
444 else
445 target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(address));
446 target_write_u32(target, PIC32MX_NVMDATA, word);
447
448 return pic32mx_nvm_exec(bank, NVMCON_OP_WORD_PROG, 5);
449 }
450
451 /*
452 * Write a 128 word (512 byte) row to flash address from RAM srcaddr.
453 */
454 static int pic32mx_write_row(struct flash_bank *bank, uint32_t address, uint32_t srcaddr)
455 {
456 struct target *target = bank->target;
457
458 LOG_DEBUG("addr: 0x%08" PRIx32 " srcaddr: 0x%08" PRIx32 "", address, srcaddr);
459
460 if (address >= PIC32MX_KSEG1_PGM_FLASH)
461 target_write_u32(target, PIC32MX_NVMADDR, KS1Virt2Phys(address));
462 else
463 target_write_u32(target, PIC32MX_NVMADDR, KS0Virt2Phys(address));
464 if (srcaddr >= PIC32MX_KSEG1_RAM)
465 target_write_u32(target, PIC32MX_NVMSRCADDR, KS1Virt2Phys(srcaddr));
466 else
467 target_write_u32(target, PIC32MX_NVMSRCADDR, KS0Virt2Phys(srcaddr));
468
469 return pic32mx_nvm_exec(bank, NVMCON_OP_ROW_PROG, 100);
470 }
471
472 static int pic32mx_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
473 {
474 uint32_t words_remaining = (count / 4);
475 uint32_t bytes_remaining = (count & 0x00000003);
476 uint32_t address = bank->base + offset;
477 uint32_t bytes_written = 0;
478 uint32_t status;
479 int retval;
480
481 if (bank->target->state != TARGET_HALTED)
482 {
483 LOG_ERROR("Target not halted");
484 return ERROR_TARGET_NOT_HALTED;
485 }
486
487 if (offset & 0x3)
488 {
489 LOG_WARNING("offset 0x%" PRIx32 "breaks required 4-byte alignment", offset);
490 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
491 }
492
493 /* multiple words (4-byte) to be programmed? */
494 if (words_remaining > 0)
495 {
496 /* try using a block write */
497 if ((retval = pic32mx_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
498 {
499 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
500 {
501 /* if block write failed (no sufficient working area),
502 * we use normal (slow) single dword accesses */
503 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
504 }
505 else if (retval == ERROR_FLASH_OPERATION_FAILED)
506 {
507 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
508 return ERROR_FLASH_OPERATION_FAILED;
509 }
510 }
511 else
512 {
513 buffer += words_remaining * 4;
514 address += words_remaining * 4;
515 words_remaining = 0;
516 }
517 }
518
519 while (words_remaining > 0)
520 {
521 uint32_t value;
522 memcpy(&value, buffer + bytes_written, sizeof(uint32_t));
523
524 status = pic32mx_write_word(bank, address, value);
525 if (status & NVMCON_NVMERR)
526 return ERROR_FLASH_OPERATION_FAILED;
527 if (status & NVMCON_LVDERR)
528 return ERROR_FLASH_OPERATION_FAILED;
529
530 bytes_written += 4;
531 words_remaining--;
532 address += 4;
533 }
534
535 if (bytes_remaining)
536 {
537 uint32_t value = 0xffffffff;
538 memcpy(&value, buffer + bytes_written, bytes_remaining);
539
540 status = pic32mx_write_word(bank, address, value);
541 if (status & NVMCON_NVMERR)
542 return ERROR_FLASH_OPERATION_FAILED;
543 if (status & NVMCON_LVDERR)
544 return ERROR_FLASH_OPERATION_FAILED;
545 }
546
547 return ERROR_OK;
548 }
549
550 static int pic32mx_probe(struct flash_bank *bank)
551 {
552 struct target *target = bank->target;
553 struct pic32mx_flash_bank *pic32mx_info = pic32mx_bank_data(bank);
554 struct mips32_common *mips32 = target->arch_info;
555 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
556 int i;
557 uint16_t num_pages = 0;
558 uint32_t device_id;
559 int page_size;
560
561 pic32mx_info->probed = 0;
562
563 device_id = ejtag_info->idcode;
564 LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%02x, ver 0x%03x)",
565 device_id,
566 (unsigned)((device_id >> 1)&0x7ff),
567 (unsigned)((device_id >> 12)&0xff),
568 (unsigned)((device_id >> 20)&0xfff));
569
570 if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
571 LOG_WARNING("Cannot identify target as a PIC32MX family.");
572 return ERROR_FLASH_OPERATION_FAILED;
573 }
574
575 page_size = 4096;
576 if (bank->base == PIC32MX_KSEG1_BOOT_FLASH || bank->base == 1) {
577 /* 0xBFC00000: Boot flash size fixed at 12k */
578 num_pages = 12;
579 } else {
580 /* 0xBD000000: Program flash size varies with device */
581 for (i = 0; pic32mx_devs[i].name != NULL; i++)
582 if (pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
583 num_pages = pic32mx_devs[i].pfm_size;
584 break;
585 }
586 if (pic32mx_devs[i].name == NULL) {
587 LOG_WARNING("Cannot identify target as a PIC32MX family.");
588 return ERROR_FLASH_OPERATION_FAILED;
589 }
590 }
591
592 #if 0
593 if (bank->target->state != TARGET_HALTED)
594 {
595 LOG_ERROR("Target not halted");
596 return ERROR_TARGET_NOT_HALTED;
597 }
598
599 /* get flash size from target */
600 if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
601 {
602 /* failed reading flash size, default to max target family */
603 num_pages = 0xffff;
604 }
605 #endif
606
607 LOG_INFO("flash size = %dkbytes", num_pages);
608
609 /* calculate numbers of pages */
610 num_pages /= (page_size / 1024);
611
612 if (bank->base == 0) bank->base = PIC32MX_KSEG1_PGM_FLASH;
613 if (bank->base == 1) bank->base = PIC32MX_KSEG1_BOOT_FLASH;
614 bank->size = (num_pages * page_size);
615 bank->num_sectors = num_pages;
616 bank->chip_width = 4;
617 bank->bus_width = 4;
618 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
619
620 for (i = 0; i < num_pages; i++)
621 {
622 bank->sectors[i].offset = i * page_size;
623 bank->sectors[i].size = page_size;
624 bank->sectors[i].is_erased = -1;
625 bank->sectors[i].is_protected = 1;
626 }
627
628 pic32mx_info->probed = 1;
629
630 return ERROR_OK;
631 }
632
633 static int pic32mx_auto_probe(struct flash_bank *bank)
634 {
635 struct pic32mx_flash_bank *pic32mx_info = pic32mx_bank_data(bank);
636 if (pic32mx_info->probed)
637 return ERROR_OK;
638 return pic32mx_probe(bank);
639 }
640
641 #if 0
642 COMMAND_HANDLER(pic32mx_handle_part_id_command)
643 {
644 return ERROR_OK;
645 }
646 #endif
647
648 static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
649 {
650 struct target *target = bank->target;
651 struct mips32_common *mips32 = target->arch_info;
652 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
653 uint32_t device_id;
654 int printed = 0, i;
655
656 device_id = ejtag_info->idcode;
657
658 if (((device_id >> 1)&0x7ff) != PIC32MX_MANUF_ID) {
659 snprintf(buf, buf_size,
660 "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
661 (unsigned)((device_id >> 1)&0x7ff),
662 PIC32MX_MANUF_ID);
663 return ERROR_FLASH_OPERATION_FAILED;
664 }
665 for (i = 0; pic32mx_devs[i].name != NULL; i++)
666 if (pic32mx_devs[i].devid == ((device_id >> 12) & 0xff)) {
667 printed = snprintf(buf, buf_size, "PIC32MX%s", pic32mx_devs[i].name);
668 break;
669 }
670 if (pic32mx_devs[i].name == NULL) {
671 snprintf(buf, buf_size, "Cannot identify target as a PIC32MX family\n");
672 return ERROR_FLASH_OPERATION_FAILED;
673 }
674 buf += printed;
675 buf_size -= printed;
676 printed = snprintf(buf, buf_size, " Ver: 0x%03x",
677 (unsigned)((device_id >> 20)&0xfff));
678
679 return ERROR_OK;
680 }
681
682 #if 0
683 COMMAND_HANDLER(pic32mx_handle_lock_command)
684 {
685 struct target *target = NULL;
686 struct pic32mx_flash_bank *pic32mx_info = NULL;
687
688 if (CMD_ARGC < 1)
689 {
690 command_print(CMD_CTX, "pic32mx lock <bank>");
691 return ERROR_OK;
692 }
693
694 struct flash_bank *bank;
695 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
696 if (ERROR_OK != retval)
697 return retval;
698
699 pic32mx_info = pic32mx_bank_data(bank);
700
701 target = bank->target;
702
703 if (target->state != TARGET_HALTED)
704 {
705 LOG_ERROR("Target not halted");
706 return ERROR_TARGET_NOT_HALTED;
707 }
708
709 if (pic32mx_erase_options(bank) != ERROR_OK)
710 {
711 command_print(CMD_CTX, "pic32mx failed to erase options");
712 return ERROR_OK;
713 }
714
715 /* set readout protection */
716 pic32mx_info->option_bytes.RDP = 0;
717
718 if (pic32mx_write_options(bank) != ERROR_OK)
719 {
720 command_print(CMD_CTX, "pic32mx failed to lock device");
721 return ERROR_OK;
722 }
723
724 command_print(CMD_CTX, "pic32mx locked");
725
726 return ERROR_OK;
727 }
728
729 COMMAND_HANDLER(pic32mx_handle_unlock_command)
730 {
731 struct target *target = NULL;
732 struct pic32mx_flash_bank *pic32mx_info = NULL;
733
734 if (CMD_ARGC < 1)
735 {
736 command_print(CMD_CTX, "pic32mx unlock <bank>");
737 return ERROR_OK;
738 }
739
740 struct flash_bank *bank;
741 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
742 if (ERROR_OK != retval)
743 return retval;
744
745 pic32mx_info = pic32mx_bank_data(bank);
746
747 target = bank->target;
748
749 if (target->state != TARGET_HALTED)
750 {
751 LOG_ERROR("Target not halted");
752 return ERROR_TARGET_NOT_HALTED;
753 }
754
755 if (pic32mx_erase_options(bank) != ERROR_OK)
756 {
757 command_print(CMD_CTX, "pic32mx failed to unlock device");
758 return ERROR_OK;
759 }
760
761 if (pic32mx_write_options(bank) != ERROR_OK)
762 {
763 command_print(CMD_CTX, "pic32mx failed to lock device");
764 return ERROR_OK;
765 }
766
767 command_print(CMD_CTX, "pic32mx unlocked");
768
769 return ERROR_OK;
770 }
771 #endif
772
773 #if 0
774 static int pic32mx_chip_erase(struct flash_bank *bank)
775 {
776 struct target *target = bank->target;
777 #if 0
778 uint32_t status;
779 #endif
780
781 if (target->state != TARGET_HALTED)
782 {
783 LOG_ERROR("Target not halted");
784 return ERROR_TARGET_NOT_HALTED;
785 }
786
787 LOG_INFO("PIC32MX chip erase called");
788
789 #if 0
790 /* unlock option flash registers */
791 target_write_u32(target, PIC32MX_FLASH_KEYR, KEY1);
792 target_write_u32(target, PIC32MX_FLASH_KEYR, KEY2);
793
794 /* chip erase flash memory */
795 target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER);
796 target_write_u32(target, PIC32MX_FLASH_CR, FLASH_MER | FLASH_STRT);
797
798 status = pic32mx_wait_status_busy(bank, 10);
799
800 target_write_u32(target, PIC32MX_FLASH_CR, FLASH_LOCK);
801
802 if (status & FLASH_WRPRTERR)
803 {
804 LOG_ERROR("pic32mx device protected");
805 return ERROR_OK;
806 }
807
808 if (status & FLASH_PGERR)
809 {
810 LOG_ERROR("pic32mx device programming failed");
811 return ERROR_OK;
812 }
813 #endif
814
815 return ERROR_OK;
816 }
817 #endif
818
819 COMMAND_HANDLER(pic32mx_handle_chip_erase_command)
820 {
821 #if 0
822 int i;
823
824 if (CMD_ARGC != 0)
825 {
826 command_print(CMD_CTX, "pic32mx chip_erase");
827 return ERROR_OK;
828 }
829
830 struct flash_bank *bank;
831 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
832 if (ERROR_OK != retval)
833 return retval;
834
835 if (pic32mx_chip_erase(bank) == ERROR_OK)
836 {
837 /* set all sectors as erased */
838 for (i = 0; i < bank->num_sectors; i++)
839 {
840 bank->sectors[i].is_erased = 1;
841 }
842
843 command_print(CMD_CTX, "pic32mx chip erase complete");
844 }
845 else
846 {
847 command_print(CMD_CTX, "pic32mx chip erase failed");
848 }
849 #endif
850
851 return ERROR_OK;
852 }
853
854 COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
855 {
856 uint32_t address, value;
857 int status, res;
858
859 if (CMD_ARGC != 3)
860 {
861 command_print(CMD_CTX, "pic32mx pgm_word <addr> <value> <bank>");
862 return ERROR_OK;
863 }
864
865 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
866 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
867
868 struct flash_bank *bank;
869 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 2, &bank);
870 if (ERROR_OK != retval)
871 return retval;
872
873 if (address < bank->base || address >= (bank->base + bank->size))
874 {
875 command_print(CMD_CTX, "flash address '%s' is out of bounds", CMD_ARGV[0]);
876 return ERROR_OK;
877 }
878
879 res = ERROR_OK;
880 status = pic32mx_write_word(bank, address, value);
881 if (status & NVMCON_NVMERR)
882 res = ERROR_FLASH_OPERATION_FAILED;
883 if (status & NVMCON_LVDERR)
884 res = ERROR_FLASH_OPERATION_FAILED;
885
886 if (res == ERROR_OK)
887 command_print(CMD_CTX, "pic32mx pgm word complete");
888 else
889 command_print(CMD_CTX, "pic32mx pgm word failed (status = 0x%x)", status);
890
891 return ERROR_OK;
892 }
893 static const struct command_registration pic32mx_exec_command_handlers[] = {
894 {
895 .name = "chip_erase",
896 .handler = &pic32mx_handle_chip_erase_command,
897 .mode = COMMAND_EXEC,
898 .help = "erase device",
899 },
900 {
901 .name = "pgm_word",
902 .handler = &pic32mx_handle_pgm_word_command,
903 .mode = COMMAND_EXEC,
904 .help = "program a word",
905 },
906 COMMAND_REGISTRATION_DONE
907 };
908 static const struct command_registration pic32mx_command_handlers[] = {
909 {
910 .name = "pic32mx",
911 .mode = COMMAND_ANY,
912 .help = "pic32mx flash command group",
913 .chain = pic32mx_exec_command_handlers,
914 },
915 COMMAND_REGISTRATION_DONE
916 };
917
918 FLASH_DRIVER(pic32mx, &pic32mx_flash_bank_command, pic32mx_command_handlers,
919 .erase = &pic32mx_erase,
920 .protect = &pic32mx_protect,
921 .write = &pic32mx_write,
922 .probe = &pic32mx_probe,
923 .auto_probe = &pic32mx_auto_probe,
924 .erase_check = &default_flash_mem_blank_check,
925 .protect_check = &pic32mx_protect_check,
926 .info = &pic32mx_info,
927 );
Zach's Unofficial Testing Repository