src/flash/nor/at91sam7.c

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Gheorghe Guran (atlas)                          *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21 ****************************************************************************/
  22
  23 /***************************************************************************
  24 *
  25 * New flash setup command:
  26 *
  27 * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
  28 *       [<chip_type> <banks>
  29 *        <sectors_per_bank> <pages_per_sector>
  30 *        <page_size> <num_nvmbits>
  31 *        <ext_freq_khz>]
  32 *
  33 *   <ext_freq_khz> - MUST be used if clock is from external source,
  34 *                    CAN be used if main oscillator frequency is known (recommended)
  35 * Examples:
  36 * ==== RECOMMENDED (covers clock speed) ============
  37 *  flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
  38 *                       (if auto-detect fails; provides clock spec)
  39 *  flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
  40 *                       (auto-detect everything except the clock)
  41 * ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
  42 *  flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
  43 *                       (if auto-detect fails)
  44 *  flash bank at91sam7 0 0 0 0 $_TARGETNAME
  45 *                       (old style, auto-detect everything)
  46 ****************************************************************************/
  47
  48 #ifdef HAVE_CONFIG_H
  49 #include "config.h"
  50 #endif
  51
  52 #include "imp.h"
  53 #include "at91sam7.h"
  54 #include <helper/binarybuffer.h>
  55
  56 static int at91sam7_protect_check(struct flash_bank *bank);
  57 static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
  58
  59 static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number);
  60 static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode);
  61 static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout);
  62 static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen);
  63
  64 static uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
  65 static uint32_t MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
  66 static uint32_t MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
  67
  68 static char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
  69
  70 #if 0
  71 static long SRAMSIZ[16] = {
  72         -1,
  73         0x0400,         /*  1K */
  74         0x0800,         /*  2K */
  75         -1,
  76         0x1c000,        /* 112K */
  77         0x1000,         /*   4K */
  78         0x14000,        /*  80K */
  79         0x28000,        /* 160K */
  80         0x2000,         /*   8K */
  81         0x4000,         /*  16K */
  82         0x8000,         /*  32K */
  83         0x10000,        /*  64K */
  84         0x20000,        /* 128K */
  85         0x40000,        /* 256K */
  86         0x18000,        /*  96K */
  87         0x80000,        /* 512K */
  88 };
  89 #endif
  90
  91
  92 static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number)
  93 {
  94         uint32_t fsr;
  95         target_read_u32(target, MC_FSR[bank_number], &fsr);
  96
  97         return fsr;
  98 }
  99
 100 static struct at91sam7_flash_bank *at91sam7_bank_data(struct flash_bank *bank)
 101 {
 102         return (struct at91sam7_flash_bank *)flash_bank_data(bank);
 103 }
 104
 105 /* Read clock configuration and set at91sam7_info->mck_freq */
 106 static void at91sam7_read_clock_info(struct flash_bank *bank)
 107 {
 108         struct at91sam7_flash_bank *at91sam7_info = at91sam7_bank_data(bank);
 109         struct target *target = bank->target;
 110         uint32_t mckr, mcfr, pllr, mor;
 111         unsigned long tmp = 0, mainfreq;
 112
 113         /* Read Clock Generator Main Oscillator Register */
 114         target_read_u32(target, CKGR_MOR, &mor);
 115         /* Read Clock Generator Main Clock Frequency Register */
 116         target_read_u32(target, CKGR_MCFR, &mcfr);
 117         /* Read Master Clock Register*/
 118         target_read_u32(target, PMC_MCKR, &mckr);
 119         /* Read Clock Generator PLL Register  */
 120         target_read_u32(target, CKGR_PLLR, &pllr);
 121
 122         at91sam7_info->mck_valid = 0;
 123         at91sam7_info->mck_freq = 0;
 124         switch (mckr & PMC_MCKR_CSS)
 125         {
 126                 case 0:                 /* Slow Clock */
 127                         at91sam7_info->mck_valid = 1;
 128                         tmp = RC_FREQ;
 129                         break;
 130
 131                 case 1:                 /* Main Clock */
 132                         if ((mcfr & CKGR_MCFR_MAINRDY) &&
 133                                 (at91sam7_info->ext_freq == 0))
 134                         {
 135                                 at91sam7_info->mck_valid = 1;
 136                                 tmp = RC_FREQ / 16ul * (mcfr & 0xffff);
 137                         }
 138                         else if (at91sam7_info->ext_freq != 0)
 139                         {
 140                                 at91sam7_info->mck_valid = 1;
 141                                 tmp = at91sam7_info->ext_freq;
 142                         }
 143                         break;
 144
 145                 case 2:                 /* Reserved */
 146                         break;
 147
 148                 case 3:                 /* PLL Clock */
 149                         if ((mcfr & CKGR_MCFR_MAINRDY) &&
 150                                 (at91sam7_info->ext_freq == 0))
 151                         {
 152                                 target_read_u32(target, CKGR_PLLR, &pllr);
 153                                 if (!(pllr & CKGR_PLLR_DIV))
 154                                         break; /* 0 Hz */
 155                                 at91sam7_info->mck_valid = 1;
 156                                 mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
 157                                 /* Integer arithmetic should have sufficient precision
 158                                  * as long as PLL is properly configured. */
 159                                 tmp = mainfreq / (pllr & CKGR_PLLR_DIV)*
 160                                         (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
 161                         }
 162                         else if ((at91sam7_info->ext_freq != 0) &&
 163                                 ((pllr&CKGR_PLLR_DIV) != 0))
 164                         {
 165                                 at91sam7_info->mck_valid = 1;
 166                                 tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)*
 167                                         (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
 168                         }
 169                         break;
 170         }
 171
 172         /* Prescaler adjust */
 173         if ((((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0))
 174         {
 175                 at91sam7_info->mck_valid = 0;
 176                 at91sam7_info->mck_freq = 0;
 177         }
 178         else if (((mckr & PMC_MCKR_PRES) >> 2) != 0)
 179                 at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
 180         else
 181                 at91sam7_info->mck_freq = tmp;
 182 }
 183
 184 /* Setup the timimg registers for nvbits or normal flash */
 185 static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
 186 {
 187         uint32_t fmr, fmcn = 0, fws = 0;
 188         struct at91sam7_flash_bank *at91sam7_info = at91sam7_bank_data(bank);
 189         struct target *target = bank->target;
 190
 191         if (mode && (mode != at91sam7_info->flashmode))
 192         {
 193                 /* Always round up (ceil) */
 194                 if (mode == FMR_TIMING_NVBITS)
 195                 {
 196                         if (at91sam7_info->cidr_arch == 0x60)
 197                         {
 198                                 /* AT91SAM7A3 uses master clocks in 100 ns */
 199                                 fmcn = (at91sam7_info->mck_freq/10000000ul) + 1;
 200                         }
 201                         else
 202                         {
 203                                 /* master clocks in 1uS for ARCH 0x7 types */
 204                                 fmcn = (at91sam7_info->mck_freq/1000000ul) + 1;
 205                         }
 206                 }
 207                 else if (mode == FMR_TIMING_FLASH)
 208                 {
 209                         /* main clocks in 1.5uS */
 210                         fmcn = (at91sam7_info->mck_freq/1000000ul)+
 211                                 (at91sam7_info->mck_freq/2000000ul) + 1;
 212                 }
 213
 214                 /* hard overclocking */
 215                 if (fmcn > 0xFF)
 216                         fmcn = 0xFF;
 217
 218                 /* Only allow fmcn = 0 if clock period is > 30 us = 33kHz. */
 219                 if (at91sam7_info->mck_freq <= 33333ul)
 220                         fmcn = 0;
 221                 /* Only allow fws = 0 if clock frequency is < 30 MHz. */
 222                 if (at91sam7_info->mck_freq > 30000000ul)
 223                         fws = 1;
 224
 225                 LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn));
 226                 fmr = fmcn << 16 | fws << 8;
 227                 target_write_u32(target, MC_FMR[bank->bank_number], fmr);
 228         }
 229
 230         at91sam7_info->flashmode = mode;
 231 }
 232
 233 static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout)
 234 {
 235         uint32_t status;
 236
 237         while ((!((status = at91sam7_get_flash_status(bank->target, bank->bank_number)) & waitbits)) && (timeout-- > 0))
 238         {
 239                 LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
 240                 alive_sleep(1);
 241         }
 242
 243         LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
 244
 245         if (status & 0x0C)
 246         {
 247                 LOG_ERROR("status register: 0x%" PRIx32 "", status);
 248                 if (status & 0x4)
 249                         LOG_ERROR("Lock Error Bit Detected, Operation Abort");
 250                 if (status & 0x8)
 251                         LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
 252                 if (status & 0x10)
 253                         LOG_ERROR("Security Bit Set, Operation Abort");
 254         }
 255
 256         return status;
 257 }
 258
 259 /* Send one command to the AT91SAM flash controller */
 260 static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen)
 261 {
 262         uint32_t fcr;
 263         struct at91sam7_flash_bank *at91sam7_info = at91sam7_bank_data(bank);
 264         struct target *target = bank->target;
 265
 266         fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
 267         target_write_u32(target, MC_FCR[bank->bank_number], fcr);
 268         LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen);
 269
 270         if ((at91sam7_info->cidr_arch == 0x60) && ((cmd == SLB) | (cmd == CLB)))
 271         {
 272                 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
 273                 if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
 274                 {
 275                         return ERROR_FLASH_OPERATION_FAILED;
 276                 }
 277                 return ERROR_OK;
 278         }
 279
 280         if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
 281         {
 282                 return ERROR_FLASH_OPERATION_FAILED;
 283         }
 284
 285         return ERROR_OK;
 286 }
 287
 288 /* Read device id register, main clock frequency register and fill in driver info structure */
 289 static int at91sam7_read_part_info(struct flash_bank *bank)
 290 {
 291         struct flash_bank *t_bank = bank;
 292         struct at91sam7_flash_bank *at91sam7_info;
 293         struct target *target = t_bank->target;
 294
 295         uint16_t bnk, sec;
 296         uint16_t arch;
 297         uint32_t cidr;
 298         uint8_t banks_num = 0;
 299         uint16_t num_nvmbits = 0;
 300         uint16_t sectors_num = 0;
 301         uint16_t pages_per_sector = 0;
 302         uint16_t page_size = 0;
 303         uint32_t ext_freq;
 304         uint32_t bank_size;
 305         uint32_t base_address = 0;
 306         char *target_name = "Unknown";
 307
 308         at91sam7_info = at91sam7_bank_data(t_bank);
 309
 310         if (at91sam7_info->cidr != 0)
 311         {
 312                 /* flash already configured, update clock and check for protected sectors */
 313                 struct flash_bank *fb = bank;
 314                 t_bank = fb;
 315
 316                 while (t_bank)
 317                 {
 318                         /* re-calculate master clock frequency */
 319                         at91sam7_read_clock_info(t_bank);
 320
 321                         /* no timming */
 322                         at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 323
 324                         /* check protect state */
 325                         at91sam7_protect_check(t_bank);
 326
 327                         t_bank = flash_bank_next(fb);
 328                         fb = t_bank;
 329                 }
 330
 331                 return ERROR_OK;
 332         }
 333
 334         /* Read and parse chip identification register */
 335         target_read_u32(target, DBGU_CIDR, &cidr);
 336         if (cidr == 0)
 337         {
 338                 LOG_WARNING("Cannot identify target as an AT91SAM");
 339                 return ERROR_FLASH_OPERATION_FAILED;
 340         }
 341
 342         if (at91sam7_info->flash_autodetection == 0)
 343         {
 344                 /* banks and sectors are already created, based on data from input file */
 345                 struct flash_bank *fb = bank;
 346                 t_bank = fb;
 347                 while (t_bank)
 348                 {
 349                         at91sam7_info = at91sam7_bank_data(t_bank);
 350
 351                         at91sam7_info->cidr = cidr;
 352                         at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
 353                         at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
 354                         at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
 355                         at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
 356                         at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
 357                         at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
 358                         at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
 359                         at91sam7_info->cidr_version = cidr&0x001F;
 360
 361                         /* calculate master clock frequency */
 362                         at91sam7_read_clock_info(t_bank);
 363
 364                         /* no timming */
 365                         at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 366
 367                         /* check protect state */
 368                         at91sam7_protect_check(t_bank);
 369
 370                         t_bank = flash_bank_next(fb);
 371                         fb = t_bank;
 372                 }
 373
 374                 return ERROR_OK;
 375         }
 376
 377         arch = (cidr >> 20)&0x00FF;
 378
 379         /* check flash size */
 380         switch ((cidr >> 8)&0x000F)
 381         {
 382                 case FLASH_SIZE_8KB:
 383                         break;
 384
 385                 case FLASH_SIZE_16KB:
 386                         banks_num = 1;
 387                         sectors_num = 8;
 388                         pages_per_sector = 32;
 389                         page_size  = 64;
 390                         base_address = 0x00100000;
 391                         if (arch == 0x70)
 392                         {
 393                                 num_nvmbits = 2;
 394                                 target_name = "AT91SAM7S161/16";
 395                         }
 396                         break;
 397
 398                 case FLASH_SIZE_32KB:
 399                         banks_num = 1;
 400                         sectors_num = 8;
 401                         pages_per_sector = 32;
 402                         page_size  = 128;
 403                         base_address = 0x00100000;
 404                         if (arch == 0x70)
 405                         {
 406                                 num_nvmbits = 2;
 407                                 target_name = "AT91SAM7S321/32";
 408                         }
 409                         if (arch == 0x72)
 410                         {
 411                                 num_nvmbits = 3;
 412                                 target_name = "AT91SAM7SE32";
 413                         }
 414                         break;
 415
 416                 case FLASH_SIZE_64KB:
 417                         banks_num = 1;
 418                         sectors_num = 16;
 419                         pages_per_sector = 32;
 420                         page_size  = 128;
 421                         base_address = 0x00100000;
 422                         if (arch == 0x70)
 423                         {
 424                                 num_nvmbits = 2;
 425                                 target_name = "AT91SAM7S64";
 426                         }
 427                         break;
 428
 429                 case FLASH_SIZE_128KB:
 430                         banks_num = 1;
 431                         sectors_num = 8;
 432                         pages_per_sector = 64;
 433                         page_size  = 256;
 434                         base_address = 0x00100000;
 435                         if (arch == 0x70)
 436                         {
 437                                 num_nvmbits = 2;
 438                                 target_name = "AT91SAM7S128";
 439                         }
 440                         if (arch == 0x71)
 441                         {
 442                                 num_nvmbits = 3;
 443                                 target_name = "AT91SAM7XC128";
 444                         }
 445                         if (arch == 0x72)
 446                         {
 447                                 num_nvmbits = 3;
 448                                 target_name = "AT91SAM7SE128";
 449                         }
 450                         if (arch == 0x75)
 451                         {
 452                                 num_nvmbits = 3;
 453                                 target_name = "AT91SAM7X128";
 454                         }
 455                         break;
 456
 457                 case FLASH_SIZE_256KB:
 458                         banks_num = 1;
 459                         sectors_num = 16;
 460                         pages_per_sector = 64;
 461                         page_size  = 256;
 462                         base_address = 0x00100000;
 463                         if (arch == 0x60)
 464                         {
 465                                 num_nvmbits = 3;
 466                                 target_name = "AT91SAM7A3";
 467                         }
 468                         if (arch == 0x70)
 469                         {
 470                                 num_nvmbits = 2;
 471                                 target_name = "AT91SAM7S256";
 472                         }
 473                         if (arch == 0x71)
 474                         {
 475                                 num_nvmbits = 3;
 476                                 target_name = "AT91SAM7XC256";
 477                         }
 478                         if (arch == 0x72)
 479                         {
 480                                 num_nvmbits = 3;
 481                                 target_name = "AT91SAM7SE256";
 482                         }
 483                         if (arch == 0x75)
 484                         {
 485                                 num_nvmbits = 3;
 486                                 target_name = "AT91SAM7X256";
 487                         }
 488                         break;
 489
 490                 case FLASH_SIZE_512KB:
 491                         banks_num = 2;
 492                         sectors_num = 16;
 493                         pages_per_sector = 64;
 494                         page_size  = 256;
 495                         base_address = 0x00100000;
 496                         if (arch == 0x70)
 497                         {
 498                                 num_nvmbits = 2;
 499                                 target_name = "AT91SAM7S512";
 500                         }
 501                         if (arch == 0x71)
 502                         {
 503                                 num_nvmbits = 3;
 504                                 target_name = "AT91SAM7XC512";
 505                         }
 506                         if (arch == 0x72)
 507                         {
 508                                 num_nvmbits = 3;
 509                                 target_name = "AT91SAM7SE512";
 510                         }
 511                         if (arch == 0x75)
 512                         {
 513                                 num_nvmbits = 3;
 514                                 target_name = "AT91SAM7X512";
 515                         }
 516                         break;
 517
 518                 case FLASH_SIZE_1024KB:
 519                         break;
 520
 521                 case FLASH_SIZE_2048KB:
 522                         break;
 523         }
 524
 525         if (strcmp(target_name, "Unknown") == 0)
 526         {
 527                 LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
 528                 return ERROR_FLASH_OPERATION_FAILED;
 529         }
 530
 531         ext_freq = at91sam7_info->ext_freq;
 532
 533         /* calculate bank size  */
 534         bank_size = sectors_num * pages_per_sector * page_size;
 535
 536         for (bnk = 0; bnk < banks_num; bnk++)
 537         {
 538                 if (bnk > 0)
 539                 {
 540                         /* create a new flash bank element */
 541                         struct flash_bank *fb = malloc(sizeof(struct flash_bank));
 542                         fb->target = target;
 543                         fb->object.driver = bank->object.driver;
 544                         void *data = malloc(sizeof(struct at91sam7_flash_bank));
 545                         fb->object.driver_priv = data;
 546                         fb->object.next = NULL;
 547
 548                         /* link created bank in 'flash_banks' list and redirect t_bank */
 549                         t_bank->object.next = &fb->object;
 550                         t_bank = fb;
 551                 }
 552
 553                 t_bank->bank_number = bnk;
 554                 t_bank->base = base_address + bnk * bank_size;
 555                 t_bank->size = bank_size;
 556                 t_bank->chip_width = 0;
 557                 t_bank->bus_width = 4;
 558                 t_bank->num_sectors = sectors_num;
 559
 560                 /* allocate sectors */
 561                 t_bank->sectors = malloc(sectors_num * sizeof(struct flash_sector));
 562                 for (sec = 0; sec < sectors_num; sec++)
 563                 {
 564                         t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
 565                         t_bank->sectors[sec].size = pages_per_sector * page_size;
 566                         t_bank->sectors[sec].is_erased = -1;
 567                         t_bank->sectors[sec].is_protected = -1;
 568                 }
 569
 570                 at91sam7_info = at91sam7_bank_data(t_bank);
 571
 572                 at91sam7_info->cidr = cidr;
 573                 at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
 574                 at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
 575                 at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
 576                 at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
 577                 at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
 578                 at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
 579                 at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
 580                 at91sam7_info->cidr_version = cidr&0x001F;
 581
 582                 at91sam7_info->target_name  = target_name;
 583                 at91sam7_info->flashmode = 0;
 584                 at91sam7_info->ext_freq = ext_freq;
 585                 at91sam7_info->num_nvmbits = num_nvmbits;
 586                 at91sam7_info->num_nvmbits_on = 0;
 587                 at91sam7_info->pagesize = page_size;
 588                 at91sam7_info->pages_per_sector = pages_per_sector;
 589
 590                 /* calculate master clock frequency */
 591                 at91sam7_read_clock_info(t_bank);
 592
 593                 /* no timming */
 594                 at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 595
 596                 /* check protect state */
 597                 at91sam7_protect_check(t_bank);
 598         }
 599
 600         LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch);
 601
 602         return ERROR_OK;
 603 }
 604
 605 static int at91sam7_erase_check(struct flash_bank *bank)
 606 {
 607         struct target *target = bank->target;
 608         uint16_t retval;
 609         uint32_t blank;
 610         uint16_t fast_check;
 611         uint8_t *buffer;
 612         uint16_t nSector;
 613         uint16_t nByte;
 614
 615         if (bank->target->state != TARGET_HALTED)
 616         {
 617                 LOG_ERROR("Target not halted");
 618                 return ERROR_TARGET_NOT_HALTED;
 619         }
 620
 621         /* Configure the flash controller timing */
 622         at91sam7_read_clock_info(bank);
 623         at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
 624
 625         fast_check = 1;
 626         for (nSector = 0; nSector < bank->num_sectors; nSector++)
 627         {
 628                 retval = target_blank_check_memory(target, bank->base + bank->sectors[nSector].offset,
 629                         bank->sectors[nSector].size, &blank);
 630                 if (retval != ERROR_OK)
 631                 {
 632                         fast_check = 0;
 633                         break;
 634                 }
 635                 if (blank == 0xFF)
 636                         bank->sectors[nSector].is_erased = 1;
 637                 else
 638                         bank->sectors[nSector].is_erased = 0;
 639         }
 640
 641         if (fast_check)
 642         {
 643                 return ERROR_OK;
 644         }
 645
 646         LOG_USER("Running slow fallback erase check - add working memory");
 647
 648         buffer = malloc(bank->sectors[0].size);
 649         for (nSector = 0; nSector < bank->num_sectors; nSector++)
 650         {
 651                 bank->sectors[nSector].is_erased = 1;
 652                 retval = target_read_memory(target, bank->base + bank->sectors[nSector].offset, 4,
 653                         bank->sectors[nSector].size/4, buffer);
 654                 if (retval != ERROR_OK)
 655                         return retval;
 656
 657                 for (nByte = 0; nByte < bank->sectors[nSector].size; nByte++)
 658                 {
 659                         if (buffer[nByte] != 0xFF)
 660                         {
 661                                 bank->sectors[nSector].is_erased = 0;
 662                                 break;
 663                         }
 664                 }
 665         }
 666         free(buffer);
 667
 668         return ERROR_OK;
 669 }
 670
 671 static int at91sam7_protect_check(struct flash_bank *bank)
 672 {
 673         uint8_t lock_pos, gpnvm_pos;
 674         uint32_t status;
 675
 676         struct at91sam7_flash_bank *at91sam7_info = at91sam7_bank_data(bank);
 677
 678         if (at91sam7_info->cidr == 0)
 679         {
 680                 return ERROR_FLASH_BANK_NOT_PROBED;
 681         }
 682         if (bank->target->state != TARGET_HALTED)
 683         {
 684                 LOG_ERROR("Target not halted");
 685                 return ERROR_TARGET_NOT_HALTED;
 686         }
 687
 688         status = at91sam7_get_flash_status(bank->target, bank->bank_number);
 689         at91sam7_info->lockbits = (status >> 16);
 690
 691         at91sam7_info->num_lockbits_on = 0;
 692         for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++)
 693         {
 694                 if (((status >> (16 + lock_pos))&(0x0001)) == 1)
 695                 {
 696                         at91sam7_info->num_lockbits_on++;
 697                         bank->sectors[lock_pos].is_protected = 1;
 698                 }
 699                 else
 700                         bank->sectors[lock_pos].is_protected = 0;
 701         }
 702
 703         /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
 704         status = at91sam7_get_flash_status(bank->target, 0);
 705
 706         at91sam7_info->securitybit = (status >> 4)&0x01;
 707         at91sam7_info->nvmbits = (status >> 8)&0xFF;
 708
 709         at91sam7_info->num_nvmbits_on = 0;
 710         for (gpnvm_pos = 0; gpnvm_pos < at91sam7_info->num_nvmbits; gpnvm_pos++)
 711         {
 712                 if (((status >> (8 + gpnvm_pos))&(0x01)) == 1)
 713                 {
 714                         at91sam7_info->num_nvmbits_on++;
 715                 }
 716         }
 717
 718         return ERROR_OK;
 719 }
 720
 721 FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
 722 {
 723         struct flash_bank *bank = flash_bank_from_object(object);
 724         struct flash_bank *t_bank = bank;
 725         struct at91sam7_flash_bank *at91sam7_info;
 726         struct target *target = t_bank->target;
 727
 728         uint32_t base_address;
 729         uint32_t bank_size;
 730         uint32_t ext_freq = 0;
 731
 732         int chip_width;
 733         int bus_width;
 734         int banks_num;
 735         int num_sectors;
 736
 737         uint16_t pages_per_sector;
 738         uint16_t page_size;
 739         uint16_t num_nvmbits;
 740
 741         char *target_name;
 742
 743         int bnk, sec;
 744
 745         at91sam7_info = malloc(sizeof(struct at91sam7_flash_bank));
 746         set_flash_bank_data(t_bank, at91sam7_info);
 747
 748         /* part wasn't probed for info yet */
 749         at91sam7_info->cidr = 0;
 750         at91sam7_info->flashmode = 0;
 751         at91sam7_info->ext_freq = 0;
 752         at91sam7_info->flash_autodetection = 0;
 753
 754         if (CMD_ARGC < 13)
 755         {
 756                 at91sam7_info->flash_autodetection = 1;
 757                 return ERROR_OK;
 758         }
 759
 760         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], base_address);
 761
 762         COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], chip_width);
 763         COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], bus_width);
 764
 765         COMMAND_PARSE_NUMBER(int, CMD_ARGV[8], banks_num);
 766         COMMAND_PARSE_NUMBER(int, CMD_ARGV[9], num_sectors);
 767         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[10], pages_per_sector);
 768         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[11], page_size);
 769         COMMAND_PARSE_NUMBER(u16, CMD_ARGV[12], num_nvmbits);
 770
 771         if (CMD_ARGC == 14) {
 772                 unsigned long freq;
 773                 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[13], freq);
 774                 ext_freq = freq * 1000;
 775                 at91sam7_info->ext_freq = ext_freq;
 776         }
 777
 778         if ((bus_width == 0) || (banks_num == 0) || (num_sectors == 0) ||
 779                 (pages_per_sector == 0) || (page_size == 0) || (num_nvmbits == 0))
 780         {
 781                 at91sam7_info->flash_autodetection = 1;
 782                 return ERROR_OK;
 783         }
 784
 785         target_name = calloc(strlen(CMD_ARGV[7]) + 1, sizeof(char));
 786         strcpy(target_name, CMD_ARGV[7]);
 787
 788         /* calculate bank size  */
 789         bank_size = num_sectors * pages_per_sector * page_size;
 790
 791         for (bnk = 0; bnk < banks_num; bnk++)
 792         {
 793                 if (bnk > 0)
 794                 {
 795                         /* create a new bank element */
 796                         struct flash_bank *fb = malloc(sizeof(struct flash_bank));
 797                         fb->target = target;
 798                         fb->object.driver = bank->object.driver;
 799                         fb->object.driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
 800                         fb->object.next = NULL;
 801
 802                         /* link created bank in 'flash_banks' list and redirect t_bank */
 803                         t_bank->object.next = &fb->object;
 804                         t_bank = fb;
 805                 }
 806
 807                 t_bank->bank_number = bnk;
 808                 t_bank->base = base_address + bnk * bank_size;
 809                 t_bank->size = bank_size;
 810                 t_bank->chip_width = chip_width;
 811                 t_bank->bus_width = bus_width;
 812                 t_bank->num_sectors = num_sectors;
 813
 814                 /* allocate sectors */
 815                 t_bank->sectors = malloc(num_sectors * sizeof(struct flash_sector));
 816                 for (sec = 0; sec < num_sectors; sec++)
 817                 {
 818                         t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
 819                         t_bank->sectors[sec].size = pages_per_sector * page_size;
 820                         t_bank->sectors[sec].is_erased = -1;
 821                         t_bank->sectors[sec].is_protected = -1;
 822                 }
 823
 824                 at91sam7_info = at91sam7_bank_data(t_bank);
 825
 826                 at91sam7_info->target_name  = target_name;
 827                 at91sam7_info->flashmode = 0;
 828                 at91sam7_info->ext_freq  = ext_freq;
 829                 at91sam7_info->num_nvmbits = num_nvmbits;
 830                 at91sam7_info->num_nvmbits_on = 0;
 831                 at91sam7_info->pagesize = page_size;
 832                 at91sam7_info->pages_per_sector = pages_per_sector;
 833         }
 834
 835         return ERROR_OK;
 836 }
 837
 838 static int at91sam7_erase(struct flash_bank *bank, int first, int last)
 839 {
 840         struct at91sam7_flash_bank *at91sam7_info = at91sam7_bank_data(bank);
 841         int sec;
 842         uint32_t nbytes, pos;
 843         uint8_t *buffer;
 844         uint8_t erase_all;
 845
 846         if (at91sam7_info->cidr == 0)
 847         {
 848                 return ERROR_FLASH_BANK_NOT_PROBED;
 849         }
 850
 851         if (bank->target->state != TARGET_HALTED)
 852         {
 853                 LOG_ERROR("Target not halted");
 854                 return ERROR_TARGET_NOT_HALTED;
 855         }
 856
 857         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 858         {
 859                 return ERROR_FLASH_SECTOR_INVALID;
 860         }
 861
 862         erase_all = 0;
 863         if ((first == 0) && (last == (bank->num_sectors-1)))
 864         {
 865                 erase_all = 1;
 866         }
 867
 868         /* Configure the flash controller timing */
 869         at91sam7_read_clock_info(bank);
 870         at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
 871
 872         if (erase_all)
 873         {
 874                 if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
 875                 {
 876                         return ERROR_FLASH_OPERATION_FAILED;
 877                 }
 878         }
 879         else
 880         {
 881                 /* allocate and clean buffer  */
 882                 nbytes = (last - first + 1) * bank->sectors[first].size;
 883                 buffer = malloc(nbytes * sizeof(uint8_t));
 884                 for (pos = 0; pos < nbytes; pos++)
 885                 {
 886                         buffer[pos] = 0xFF;
 887                 }
 888
 889                 if (at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
 890                 {
 891                         return ERROR_FLASH_OPERATION_FAILED;
 892                 }
 893
 894                 free(buffer);
 895         }
 896
 897         /* mark erased sectors */
 898         for (sec = first; sec <= last; sec++)
 899         {
 900                 bank->sectors[sec].is_erased = 1;
 901         }
 902
 903         return ERROR_OK;
 904 }
 905
 906 static int at91sam7_protect(struct flash_bank *bank, int set, int first, int last)
 907 {
 908         uint32_t cmd;
 909         int sector;
 910         uint32_t pagen;
 911
 912         struct at91sam7_flash_bank *at91sam7_info = at91sam7_bank_data(bank);
 913
 914         if (at91sam7_info->cidr == 0)
 915         {
 916                 return ERROR_FLASH_BANK_NOT_PROBED;
 917         }
 918
 919         if (bank->target->state != TARGET_HALTED)
 920         {
 921                 LOG_ERROR("Target not halted");
 922                 return ERROR_TARGET_NOT_HALTED;
 923         }
 924
 925         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 926         {
 927                 return ERROR_FLASH_SECTOR_INVALID;
 928         }
 929
 930         /* Configure the flash controller timing */
 931         at91sam7_read_clock_info(bank);
 932         at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
 933
 934         for (sector = first; sector <= last; sector++)
 935         {
 936                 if (set)
 937                         cmd = SLB;
 938                 else
 939                         cmd = CLB;
 940
 941                 /* if we lock a page from one sector then entire sector will be locked, also,
 942                  * if we unlock a page from a locked sector, entire sector will be unlocked   */
 943                 pagen = sector * at91sam7_info->pages_per_sector;
 944
 945                 if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
 946                 {
 947                         return ERROR_FLASH_OPERATION_FAILED;
 948                 }
 949         }
 950
 951         at91sam7_protect_check(bank);
 952
 953         return ERROR_OK;
 954 }
 955
 956 static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
 957 {
 958         int retval;
 959         struct at91sam7_flash_bank *at91sam7_info = at91sam7_bank_data(bank);
 960         struct target *target = bank->target;
 961         uint32_t dst_min_alignment, wcount, bytes_remaining = count;
 962         uint32_t first_page, last_page, pagen, buffer_pos;
 963
 964         if (at91sam7_info->cidr == 0)
 965         {
 966                 return ERROR_FLASH_BANK_NOT_PROBED;
 967         }
 968
 969         if (bank->target->state != TARGET_HALTED)
 970         {
 971                 LOG_ERROR("Target not halted");
 972                 return ERROR_TARGET_NOT_HALTED;
 973         }
 974
 975         if (offset + count > bank->size)
 976                 return ERROR_FLASH_DST_OUT_OF_BANK;
 977
 978         dst_min_alignment = at91sam7_info->pagesize;
 979
 980         if (offset % dst_min_alignment)
 981         {
 982                 LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "", offset, dst_min_alignment);
 983                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 984         }
 985
 986         if (at91sam7_info->cidr_arch == 0)
 987                 return ERROR_FLASH_BANK_NOT_PROBED;
 988
 989         first_page = offset/dst_min_alignment;
 990         last_page = DIV_ROUND_UP(offset + count, dst_min_alignment);
 991
 992         LOG_DEBUG("first_page: %i, last_page: %i, count %i", (int)first_page, (int)last_page, (int)count);
 993
 994         /* Configure the flash controller timing */
 995         at91sam7_read_clock_info(bank);
 996         at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
 997
 998         for (pagen = first_page; pagen < last_page; pagen++)
 999         {
1000                 if (bytes_remaining < dst_min_alignment)
1001                         count = bytes_remaining;
1002                 else
1003                         count = dst_min_alignment;
1004                 bytes_remaining -= count;
1005
1006                 /* Write one block to the PageWriteBuffer */
1007                 buffer_pos = (pagen-first_page)*dst_min_alignment;
1008                 wcount = DIV_ROUND_UP(count,4);
1009                 if ((retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4, wcount, buffer + buffer_pos)) != ERROR_OK)
1010                 {
1011                         return retval;
1012                 }
1013
1014                 /* Send Write Page command to Flash Controller */
1015                 if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
1016                 {
1017                         return ERROR_FLASH_OPERATION_FAILED;
1018                 }
1019                 LOG_DEBUG("Write flash bank:%i page number:%" PRIi32 "", bank->bank_number, pagen);
1020         }
1021
1022         return ERROR_OK;
1023 }
1024
1025 static int at91sam7_probe(struct flash_bank *bank)
1026 {
1027         /* we can't probe on an at91sam7
1028          * if this is an at91sam7, it has the configured flash */
1029         int retval;
1030
1031         if (bank->target->state != TARGET_HALTED)
1032         {
1033                 LOG_ERROR("Target not halted");
1034                 return ERROR_TARGET_NOT_HALTED;
1035         }
1036
1037         retval = at91sam7_read_part_info(bank);
1038         if (retval != ERROR_OK)
1039                 return retval;
1040
1041         return ERROR_OK;
1042 }
1043
1044 static int at91sam7_info(struct flash_bank *bank, char *buf, int buf_size)
1045 {
1046         int printed;
1047         struct at91sam7_flash_bank *at91sam7_info = at91sam7_bank_data(bank);
1048
1049         if (at91sam7_info->cidr == 0)
1050         {
1051                 return ERROR_FLASH_BANK_NOT_PROBED;
1052         }
1053
1054         printed = snprintf(buf, buf_size,
1055                 "\n at91sam7 driver information: Chip is %s\n",
1056                 at91sam7_info->target_name);
1057
1058         buf += printed;
1059         buf_size -= printed;
1060
1061         printed = snprintf(buf,
1062                            buf_size,
1063                            " Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32 "\n",
1064                            at91sam7_info->cidr,
1065                            at91sam7_info->cidr_arch,
1066                            EPROC[at91sam7_info->cidr_eproc],
1067                            at91sam7_info->cidr_version,
1068                            bank->size);
1069
1070         buf += printed;
1071         buf_size -= printed;
1072
1073         printed = snprintf(buf, buf_size,
1074                 " Master clock (estimated): %u KHz | External clock: %u KHz\n",
1075                 (unsigned)(at91sam7_info->mck_freq / 1000), (unsigned)(at91sam7_info->ext_freq / 1000));
1076
1077         buf += printed;
1078         buf_size -= printed;
1079
1080         printed = snprintf(buf, buf_size,
1081                 " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
1082                 at91sam7_info->pagesize, bank->num_sectors, at91sam7_info->num_lockbits_on,
1083                 at91sam7_info->lockbits, at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
1084
1085         buf += printed;
1086         buf_size -= printed;
1087
1088         printed = snprintf(buf, buf_size,
1089                 " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
1090                 at91sam7_info->securitybit, at91sam7_info->num_nvmbits,
1091                 at91sam7_info->num_nvmbits_on, at91sam7_info->nvmbits);
1092
1093         buf += printed;
1094         buf_size -= printed;
1095
1096         return ERROR_OK;
1097 }
1098
1099 /*
1100 * On AT91SAM7S: When the gpnvm bits are set with
1101 * > at91sam7 gpnvm bitnr set
1102 * the changes are not visible in the flash controller status register MC_FSR
1103 * until the processor has been reset.
1104 * On the Olimex board this requires a power cycle.
1105 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
1106 *   The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
1107 *   Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
1108 */
1109 COMMAND_HANDLER(at91sam7_handle_gpnvm_command)
1110 {
1111         struct flash_bank *bank;
1112         int bit;
1113         uint8_t  flashcmd;
1114         uint32_t status;
1115         struct at91sam7_flash_bank *at91sam7_info;
1116         int retval;
1117
1118         if (CMD_ARGC != 2)
1119         {
1120                 command_print(CMD_CTX, "at91sam7 gpnvm <bit> <set | clear>");
1121                 return ERROR_OK;
1122         }
1123
1124         bank = get_flash_bank_by_num_noprobe(0);
1125         if (bank ==  NULL)
1126         {
1127                 return ERROR_FLASH_BANK_INVALID;
1128         }
1129         if (strcmp(flash_driver_name(flash_bank_driver(bank)), "at91sam7"))
1130         {
1131                 command_print(CMD_CTX, "not an at91sam7 flash bank '%s'", CMD_ARGV[0]);
1132                 return ERROR_FLASH_BANK_INVALID;
1133         }
1134         if (bank->target->state != TARGET_HALTED)
1135         {
1136                 LOG_ERROR("target has to be halted to perform flash operation");
1137                 return ERROR_TARGET_NOT_HALTED;
1138         }
1139
1140         if (strcmp(CMD_ARGV[1], "set") == 0)
1141         {
1142                 flashcmd = SGPB;
1143         }
1144         else if (strcmp(CMD_ARGV[1], "clear") == 0)
1145         {
1146                 flashcmd = CGPB;
1147         }
1148         else
1149         {
1150                 return ERROR_COMMAND_SYNTAX_ERROR;
1151         }
1152
1153         at91sam7_info = at91sam7_bank_data(bank);
1154         if (at91sam7_info->cidr == 0)
1155         {
1156                 retval = at91sam7_read_part_info(bank);
1157                 if (retval != ERROR_OK)
1158                 {
1159                         return retval;
1160                 }
1161         }
1162
1163         COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], bit);
1164         if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits))
1165         {
1166                 command_print(CMD_CTX, "gpnvm bit '#%s' is out of bounds for target %s", CMD_ARGV[0], at91sam7_info->target_name);
1167                 return ERROR_OK;
1168         }
1169
1170         /* Configure the flash controller timing */
1171         at91sam7_read_clock_info(bank);
1172         at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
1173
1174         if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
1175         {
1176                 return ERROR_FLASH_OPERATION_FAILED;
1177         }
1178
1179         /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
1180         status = at91sam7_get_flash_status(bank->target, 0);
1181         LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32 " \n", flashcmd, bit, status);
1182
1183         /* check protect state */
1184         at91sam7_protect_check(bank);
1185
1186         return ERROR_OK;
1187 }
1188
1189 static const struct command_registration at91sam7_exec_command_handlers[] = {
1190         {
1191                 .name = "gpnvm",
1192                 .handler = &at91sam7_handle_gpnvm_command,
1193                 .mode = COMMAND_EXEC,
1194                 .usage = "gpnvm <bit> set | clear, "
1195                         "set or clear one gpnvm bit",
1196         },
1197         COMMAND_REGISTRATION_DONE
1198 };
1199 static const struct command_registration at91sam7_command_handlers[] = {
1200         {
1201                 .name = "at91sam7",
1202                 .mode = COMMAND_ANY,
1203                 .help = "at91sam7 flash command group",
1204                 .chain = at91sam7_exec_command_handlers,
1205         },
1206         COMMAND_REGISTRATION_DONE
1207 };
1208
1209 FLASH_DRIVER(at91sam7,
1210                 &at91sam7_flash_bank_command,
1211                 at91sam7_command_handlers,
1212                 .erase = &at91sam7_erase,
1213                 .protect = &at91sam7_protect,
1214                 .write = &at91sam7_write,
1215                 .probe = &at91sam7_probe,
1216                 .auto_probe = &at91sam7_probe,
1217                 .erase_check = &at91sam7_erase_check,
1218                 .protect_check = &at91sam7_protect_check,
1219                 .info = &at91sam7_info,
1220         );